Migen flipflop test

flipflop.py

"""
Flip Flop
"""
from random import randrange
from migen.fhdl.module import Module
from migen.fhdl.structure import Signal
from migen.fhdl import verilog
from migen import run_simulation


class Dflipflop(Module):  # pylint: disable=too-few-public-methods
    """
    D Type Flip Flop
    """
    def __init__(self, d_flag, q_flag, qi_flag):
        self.q_flag = q_flag
        self.qi_flag = qi_flag

        self.sync += q_flag.eq(d_flag)
        self.comb += qi_flag.eq(~q_flag)


def _test(d_flag, dut):
    """
    Test the flipflop
    """
    def zero():
        yield from send(0)
        assert (yield dut.q_flag) == 0
        assert (yield dut.qi_flag) == 1

    def one():
        yield from send(1)
        assert (yield dut.q_flag) == 1
        assert (yield dut.qi_flag) == 0

    def send(bit):
        yield d_flag.eq(bit)
        yield
        yield

    for i in range(20):
        if randrange(2):
            yield from zero()
        else:
            yield from one()
        yield


if __name__ == "__main__":
    D = Signal()
    Q = Signal()
    Qi = Signal()

    dut = Dflipflop(D, Q, Qi)
    run_simulation(dut, _test(D, dut), vcd_name="test.vcd")

    print(
        verilog.convert(
            Dflipflop(D, Q, Qi),
            ios={D, Q, Qi}
        )
    )

/* Machine-generated using Migen */
module top(
	input D,
	output reg Q,
	output Qi,
	input sys_clk,
	input sys_rst
);



// Adding a dummy event (using a dummy signal 'dummy_s') to get the simulator
// to run the combinatorial process once at the beginning.
// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on

assign Qi = (~Q);

always @(posedge sys_clk) begin
	Q <= D;
	if (sys_rst) begin
		Q <= 1'd0;
	end
end

endmodule