6502 32-Bit Vector Extension

v32.txt

# 6502 32-bit vector extension
This extension is based on [16-bit vector extension)[https://gist.github.com/alex-s168/4affe0004397688aeb88fbd6e194bdc0].
All instructions and registers from the "old" extension are assumed to be present here.

## Registers
This extension adds one single SIMD register:

### W
A 32-bit single instruction multiple data (SIMD) register.
The low word of this register overlaps with the full `V` reigster.

## Instructions
This extension adds numerous instructions related to the `W` and `V` register:

### SWW
Swaps the high and low word in `W`

Addressing modes:
- `i`    implied                      0x2B    3   cycles

### SW2
Swaps the high and low word in `W`, and then swaps the high and low byte in `V` (low word of `W`).

Addressing modes:
- `i`    implied                      0x3B    3   cycles

### SUV
Sums all bytes in the `V` register together into `A`. Ignores carry and does not set carry.

Addressing modes:
- `i`    implied                      0x4B    3   cycles

### ZHW
Zeros out the high word in the `W` register.

Addressing modes:
- `i`    implied                      0x5B    2   cycles

### ZHW
Zeros out the high byte in the high word in the `W` register.

Addressing modes:
- `i`    implied                      0x5C    2   cycles

### HAD
Adds both bytes in the low word of the `W` register into the low byte of the `V` (= `W`) register and adds both bytes in the high word of the `W` register into the high byte of the `V` (= `W`) register. Ignores carry.

Addressing modes:
- `i`    implied                      0x6B    3   cycles