Icebreaker FPGA blink example with simulation

blink.py

from nmigen import *
from nmigen_boards.icebreaker import *
from nmigen.back import rtlil, verilog, pysim

class Blinker(Elaboratable):
    def __init__(self, maxperiod):
        self.maxperiod = maxperiod
        self.led = Signal()
        self.counter = Signal(max=self.maxperiod+1)
    
    def set_period(self, maxperiod):
        self.maxperiod = maxperiod

    def elaborate(self, platform):
        m = Module()

        if type(platform) is not pysim._SimulatorPlatform:
            clk12 = platform.request("clk12")
            self.led = plat.request("user_ledr")

            m.domains.sync = ClockDomain()
            m.d.comb += ClockSignal().eq(clk12)
        
        period = Signal(max=self.maxperiod+1)
        m.d.comb += period.eq(self.maxperiod)
        
        with m.If(self.counter == 0):
            m.d.sync += [
                self.led.eq(~self.led),
                self.counter.eq(period)
            ]
        with m.Else():
            m.d.sync += [
                self.counter.eq(self.counter - 1)
            ]

        return m

if __name__ == "__main__":

    period = 10000000

    blink = Blinker(period)
    ports = [
        blink.led, blink.counter
    ]

    import argparse

    parser = argparse.ArgumentParser()
    p_action = parser.add_subparsers(dest="action")
    p_action.add_parser("simulate")

    args = parser.parse_args()
    if args.action == "simulate":
        period = 1000
        blink.set_period(period)
        with pysim.Simulator(blink,
                vcd_file=open("blink.vcd", "w"),
                gtkw_file=open("blink.gtkw", "w"),
                traces=ports) as sim:
            sim.add_clock(1e-6)
            def blink_proc():
                yield; yield; yield
            sim.add_sync_process(blink_proc())
            sim.run_until(period * 1e-6 * 4, run_passive=True)
    else:
        plat = ICEBreakerPlatform()
        plat.build(blink, do_program=True)