VHDL-FPGA-model

-- Automatically generated VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.all;
use work.types.all;

entity switchBoxBlock_1 is
  port(sram_i1     : in std_logic_vector(48 downto 0);
       inputs_i2   : in array_of_std_logic_vector_2(3 downto 0);
       clk1000     : in std_logic;
       clk1000_rst : in std_logic;
       outputs_o   : out array_of_std_logic_vector_2(3 downto 0));
end;

architecture structural of switchBoxBlock_1 is
  signal outputs_o_sig : array_of_std_logic_vector_2(3 downto 0);
  signal repANF_0      : std_logic;
  signal repANF_1      : std_logic_vector(31 downto 0);
  signal x_2           : std_logic_vector(16 downto 0);
  signal x_3           : std_logic_vector(3 downto 0);
  signal repANF_4      : std_logic_vector(1 downto 0);
  signal repANF_5      : std_logic_vector(1 downto 0);
  signal sram_swb_6    : std_logic_vector(31 downto 0);
  signal x_7           : product0;
  signal sram_lb_8     : std_logic_vector(16 downto 0);
  signal tmp_9         : product0;
begin
  outputs_o_sig_comp_inst : entity swbMuxs_2
    port map
      (topLet_o  => outputs_o_sig
      ,lout_i1   => repANF_0
      ,inputs_i2 => inputs_i2
      ,sram_i3   => repANF_1);
  
  repANF_0_comp_inst : entity logicBlock_5
    port map
      (bodyVar_o   => repANF_0
      ,clk1000     => clk1000
      ,clk1000_rst => clk1000_rst
      ,sram_i1     => x_2
      ,args_i2     => x_3);
  
  repANF_1 <= sram_swb_6;
  
  x_2 <= sram_lb_8;
  
  x_3 <= std_logic_vector'(repANF_4) & std_logic_vector'(repANF_5);
  
  repANF_4_comp_inst : entity zk_16
    port map
      (topLet_o => repANF_4
      ,pTS_i1   => inputs_i2);
  
  repANF_5_comp_inst : entity zk_16
    port map
      (topLet_o => repANF_5
      ,pTS_i1   => outputs_o_sig);
  
  sram_swb_6 <= x_7.product0_sel1;
  
  n_11_vsplit : block
    signal n_12 : std_logic_vector(48 downto 0);
  begin
    n_12 <= sram_i1;
    tmp_9 <= (n_12(n_12'high downto (17)),n_12((17)-1 downto 0));
  end block;
  
  x_7 <= tmp_9;
  
  sram_lb_8 <= x_7.product0_sel0;
  
  outputs_o <= outputs_o_sig;
end;