gistfile1.vhdl

--testbench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all ;

entity tb_shift_dev is
	generic(
		clk_time: time:= 10 ns;
		capacity: integer:= 15);
end entity;

architecture tb_shift_dev of tb_shift_dev is
-- 	component shift_dev is
-- 		generic(capacity: integer:= 15);
-- 		port(
-- 			D: in std_logic_vector(capacity downto 0);
-- 			sd: in std_logic_vector(3 downto 0);--shift depth
-- 			Q: out std_logic_vector(capacity downto 0));
-- 	end component;

signal tb_input, tb_Q: std_logic_vector(capacity downto 0);
signal tb_sd: std_logic_vector(3 downto 0);
signal tb_clk: std_logic;
begin
	test_shifter: WORK.shift_dev port map(D=>tb_input, sd=>tb_sd, Q=>tb_Q);

	process(tb_clk)
		variable counter:integer:=0;
	begin
		if rising_edge(tb_clk) then
			case counter is
				when 0 =>
					tb_input<=std_logic_vector(to_signed(-2, 16));
					tb_sd<=std_logic_vector(to_signed(4, 4));
				when 1 =>
					tb_input<=std_logic_vector(to_signed(78, 16));
					tb_sd<=std_logic_vector(to_signed(3, 4));
				when 2 =>
					tb_input<=std_logic_vector(to_signed(144, 16));
					tb_sd<=std_logic_vector(to_signed(5, 4));
				when 3 =>
					tb_input<=std_logic_vector(to_signed(2000, 16));
					tb_sd<=std_logic_vector(to_signed(2, 4));
				when 4 =>
					tb_input<=std_logic_vector(to_signed(30, 16));
					tb_sd<=std_logic_vector(to_signed(1, 4));
				when 5 =>
					tb_input<=std_logic_vector(to_signed(15, 16));
					tb_sd<=std_logic_vector(to_signed(0, 4));
				when others =>null;
			end case;
			counter:=counter+1;
			if counter=6 then counter:=0;
			end if;
		end if;
	end process;

	process is
	begin
		while true loop
			tb_clk<='0'; wait for clk_time;
			tb_clk<='1'; wait for clk_time;
		end loop;
	end process;
end architecture;