aljazmedic/chal.sv

## chal.sv
module top();
    reg eo3,nF3;
    wire [11:0] D1q7APfd;
    wire [7:0] Dy,HZ4cC8Gwm7YlmW,XIzbggF,XvqVFhCAiK8ZU,eCzsnH;
    wire n35s92a4h;
    string flag;
    integer z;

    initial forever begin
        eo3 = 0; #5;
        eo3 = 1; #5;
    end

    initial begin
        #1;
        flag = "maple{testflag}";
        for (z=0; z< flag.len(); z++)
            TSdB.fgS[z+140] = flag[z];
        nF3 = 1;
        #10;
        nF3 = 0;
        #500000;
        if (TSdB.fgS[135] == 2)
            $display("You are winner!");
        else
            $display("Try again.");
        $finish();
    end

    ioJ xft(eo3,nF3,
        D1q7APfd,Dy,
        HZ4cC8Gwm7YlmW,XIzbggF,n35s92a4h,
        XvqVFhCAiK8ZU,eCzsnH);

    WsR #(8,8,"data.txt") TSdB(eo3,XvqVFhCAiK8ZU,HZ4cC8Gwm7YlmW,n35s92a4h,XIzbggF,eCzsnH);
    WsR #(12,8,"prog.txt") njg4YL52AkHJ(eo3,Dy,8'b0,1'b0,12'b0,D1q7APfd);
endmodule

module WsR(eo3,OaPYNLCWZ,FTkstjTLci,rIefx,eqJ,zhRu);
    parameter V2akbDl5qY = 32;
    parameter ulTe71D35n = 4;
    parameter Yj4Y6kAS = "data.txt";

    input eo3;
    input [ulTe71D35n-1:0] OaPYNLCWZ, FTkstjTLci;
    input rIefx;
    input [V2akbDl5qY-1:0] eqJ;
    output logic [V2akbDl5qY-1:0] zhRu;

    reg [V2akbDl5qY-1:0] fgS [2**ulTe71D35n-1:0];

    initial $readmemh(Yj4Y6kAS, fgS);

    always @ (posedge eo3) begin
        if (rIefx)
        fgS[FTkstjTLci] <= eqJ;
        zhRu <= fgS[OaPYNLCWZ];
    end
endmodule

module ioJ(eo3,nF3,
        D1q7APfd,Dy,
        HZ4cC8Gwm7YlmW,eCzsnH,n35s92a4h,
        XvqVFhCAiK8ZU,XIzbggF);

    input eo3, nF3;
    input [11:0] D1q7APfd;
    input [7:0] XIzbggF;
    output logic [7:0] Dy;
    output wire [7:0] HZ4cC8Gwm7YlmW,XvqVFhCAiK8ZU,eCzsnH;
    output logic n35s92a4h;

    wire [7:0] wgb7SWQCojbM0z,t14sshQ2kVxklOx;

    logic XTy0gvT0Bt1zmDLV008,EyZChyzXuhgMsgovFC;
    logic [2:0] QD2p2rf6jj5o9,ZamHFiK7It0a;
    logic [2:0] b4ivvC;

    wire [3:0] rSRUKV;
    wire [7:0] HySaIQf,BGtF9jPA,eRl31tlw1,yPs51RDPPUv,ulW9ociVdXXbW;
    logic C2y,R7O7txm93M,d6FZwCaz4mM,BXNS,WsNZ9Zbv;
    logic [7:0] nYKQupS;

    typedef enum {EKQMvI6y,jiZAPV,CSdThODUs,zAdA} LpZvRPGZ;
    LpZvRPGZ nWFEYy;

    enum {vJwNE,VEIImw4} nvuDF;

    wBlFnCyLj AI(eo3,nF3,
                d6FZwCaz4mM,
                yPs51RDPPUv,
                b4ivvC,lMwuHWy,
                XTy0gvT0Bt1zmDLV008,EyZChyzXuhgMsgovFC,
                QD2p2rf6jj5o9,ZamHFiK7It0a,
                eRl31tlw1,ulW9ociVdXXbW,
                wgb7SWQCojbM0z,t14sshQ2kVxklOx);

    assign rSRUKV = D1q7APfd[11:8];
    assign HySaIQf = D1q7APfd[7:0];
    assign BGtF9jPA = C2y == 0 ? HySaIQf : yPs51RDPPUv;
    assign HZ4cC8Gwm7YlmW = t14sshQ2kVxklOx;
    assign XvqVFhCAiK8ZU = wgb7SWQCojbM0z;
    assign eRl31tlw1 = R7O7txm93M == 1 ? HySaIQf : XIzbggF;

    assign eCzsnH = wgb7SWQCojbM0z;
    assign ulW9ociVdXXbW = Dy + 1;

    always_comb begin
        d6FZwCaz4mM = 1'b0;
        XTy0gvT0Bt1zmDLV008 = 1'b0;
        EyZChyzXuhgMsgovFC = 1'b0;
        QD2p2rf6jj5o9 = 3'b0;
        ZamHFiK7It0a = 3'b0;
        nWFEYy = CSdThODUs;
        C2y = 1'b0;
        R7O7txm93M = 1'b1;
        n35s92a4h = 1'b0;
        WsNZ9Zbv = 1'b0;
        if (nvuDF == VEIImw4) begin
        casez(rSRUKV)
            4'b0???: begin
                    if (rSRUKV != 7) begin
                        d6FZwCaz4mM = 1'b1;
                        b4ivvC = rSRUKV[2:0];
                        XTy0gvT0Bt1zmDLV008 = 1'b1;
                        QD2p2rf6jj5o9 = 3'd3;
                        WsNZ9Zbv = 1'b1;
                    end else begin
                        XTy0gvT0Bt1zmDLV008 = 1'b1;
                        QD2p2rf6jj5o9 = 3'd4;
                        end
                    end
            4'd8: begin
                    nWFEYy = jiZAPV;
                    C2y = 1'b0;
                    end
            4'd9: begin
                    nWFEYy = jiZAPV;
                    EyZChyzXuhgMsgovFC = 1'b1;
                    ZamHFiK7It0a = 3'd0;
                    C2y = 1'b0;
                    end
            4'd10: begin
                    nWFEYy = jiZAPV;
                    EyZChyzXuhgMsgovFC = 1'b1;
                    ZamHFiK7It0a = 3'd4;
                    C2y = 1'b1;
                    end
            4'd11: begin
                    C2y = 1'b0;
                    if(BXNS)
                        nWFEYy = jiZAPV;
                    else
                        nWFEYy = CSdThODUs;
                    end
            4'd12: begin
                    d6FZwCaz4mM = 1'b0;
                    XTy0gvT0Bt1zmDLV008 = 1'b1;
                    QD2p2rf6jj5o9 = 3'b0;
                    end
            4'd13: begin
                    QD2p2rf6jj5o9 = 3'd1;
                    d6FZwCaz4mM = 1'b0;
                    R7O7txm93M = 1'b0;
                    XTy0gvT0Bt1zmDLV008 = 1'b1;
                    end
            4'd14: begin
                    n35s92a4h = 1'b1;
                    QD2p2rf6jj5o9 = 3'd2;
                    XTy0gvT0Bt1zmDLV008 = 1'b1;
            end
            4'd15: nWFEYy = zAdA;
        endcase
        end
    end


    always_comb begin
        case(nWFEYy)
            EKQMvI6y: nYKQupS = 8'b0;
            jiZAPV: nYKQupS = BGtF9jPA;
            CSdThODUs: nYKQupS = Dy + 1;
            zAdA: nYKQupS = Dy;
            default: nYKQupS = 8'bz;
        endcase
    end

    always_ff @(posedge eo3) begin
        if (nF3) begin
            Dy <= 8'b0;
        end
        else begin
            if (nvuDF == VEIImw4)
                Dy <= nYKQupS;
            if (WsNZ9Zbv == 1)
                BXNS = lMwuHWy;
        end
    end

    always_ff @(posedge eo3) begin
        if (nF3)
            nvuDF <= vJwNE;
        else begin
            case(nvuDF)
                vJwNE: nvuDF <= VEIImw4;
                VEIImw4: nvuDF <= vJwNE;
            endcase
        end
    end
endmodule

module wBlFnCyLj(eo3,nF3,
                d6FZwCaz4mM,
                WnBJU6Eefj,
                b4ivvC,f,
                XTy0gvT0Bt1zmDLV008,EyZChyzXuhgMsgovFC,
                QD2p2rf6jj5o9,ZamHFiK7It0a,
                eRl31tlw1,ulW9ociVdXXbW,
                wgb7SWQCojbM0z,t14sshQ2kVxklOx);
    input eo3,nF3,d6FZwCaz4mM,XTy0gvT0Bt1zmDLV008,EyZChyzXuhgMsgovFC;
    input [7:0] eRl31tlw1,ulW9ociVdXXbW;
    input [2:0] QD2p2rf6jj5o9,ZamHFiK7It0a;
    output logic [7:0] WnBJU6Eefj,wgb7SWQCojbM0z,t14sshQ2kVxklOx;
    input [2:0] b4ivvC;
    output wire f;

    wire [7:0] QU6cTlk, yceR1D2,ZuqqtM7t, HgY3ljXJn, CMFdSku6Yj7;

    assign QU6cTlk = d6FZwCaz4mM == 0 ? eRl31tlw1 : yceR1D2;
    assign wgb7SWQCojbM0z = ZuqqtM7t;
    assign t14sshQ2kVxklOx = HgY3ljXJn;

    Ol8vW #(10) sIctJNEm0A(.eo3(eo3),.nF3(nF3),
                        .QU6cTlk(QU6cTlk),
                        .Jpup6gEow(ZuqqtM7t),.nFOoEI7Dnl(HgY3ljXJn),
                        .QV(QD2p2rf6jj5o9),.pb(XTy0gvT0Bt1zmDLV008));

    Ol8vW #(10) ek6j3imqGFx6(.eo3(eo3),.nF3(nF3),
                            .QU6cTlk(ulW9ociVdXXbW),
                            .Jpup6gEow(WnBJU6Eefj),.nFOoEI7Dnl(CMFdSku6Yj7),
                            .QV(ZamHFiK7It0a),.pb(EyZChyzXuhgMsgovFC));

    Ltc Ltc(ZuqqtM7t,HgY3ljXJn,b4ivvC,yceR1D2,f);


endmodule

module Ol8vW(eo3,nF3,QU6cTlk,Jpup6gEow,nFOoEI7Dnl,QV,pb);
    input eo3,nF3,pb;

    input [7:0] QU6cTlk;
    output [7:0] Jpup6gEow,nFOoEI7Dnl;
    input [2:0] QV;

    parameter WXifi4fqUy9NY = 16;
    logic [7:0] fgS [2**WXifi4fqUy9NY-1:0];
    logic [WXifi4fqUy9NY-1:0] gPrDVGD;


    always_ff @(posedge eo3) begin
        if (nF3 == 1) begin
            gPrDVGD <= 0;
        end else if (pb ==1) begin
            case (QV)
                3'd0: begin
                        fgS[gPrDVGD+1] <= QU6cTlk;
                        gPrDVGD <= gPrDVGD + 1;
                end
                3'd1: fgS[gPrDVGD]<=QU6cTlk;
                3'd2: gPrDVGD <= gPrDVGD - 2;
                3'd3: begin
                        gPrDVGD <= gPrDVGD - 1;
                        fgS[gPrDVGD-1] <= QU6cTlk;
                end
                3'd4: gPrDVGD <= gPrDVGD - 1;
            endcase
        end
    end

    assign {Jpup6gEow,nFOoEI7Dnl} = {fgS[gPrDVGD],fgS[gPrDVGD-1]};

endmodule

module Ltc(Z,o,QV,mtc,f);
    input [7:0] Z,o;
    output logic [7:0] mtc;
    input [2:0] QV;
    output f;

    assign f = mtc == 0 ? 1'b1 : 1'b0;

    always_comb begin
        case (QV)
            3'd0: mtc = Z + o;
            3'd1: mtc = Z - o;
            3'd2: mtc = Z ^ o;
            3'd3: mtc = Z & o;
            3'd4: mtc = Z | o;
            3'd5: mtc = Z << o;
            3'd6: mtc = Z >> o;
            default: mtc = 8'bz;
        endcase
    end
endmodule

## data.txt
bb
4d
00
80
cb
15
9c
ef
90
b9
1f
8b
41
30
07
e1
76
64
eb
44
eb
11
d0
4c
ea
1c
f5
96
6a
ea
6c
2f
04
27
e6
d4
56
80
52
38
59
59
c5
aa
82
94
df
ab
da
a3
41
47
c4
53
b3
d5
83
fc
56
a1
43
30
97
0d
48
ea
49
d2
5b
77
0e
26
ab
d9
f4
e6
61
49
e5
6e
33
d4
bb
42
ef
e4
fd
4c
93
56
0c
81
2a
63
84
be
d9
9f
5f
a8
f7
ee
b8
77
39
b9
db
4e
27
73
a8
89
75
89
c5
d8
c5
95
3a
1d
bc
24
83
50
07
1e
74
12
fa
7f
04
1f
72
87
33
ac
ae
8a
85
1b
6d
61
70
6c
65
7b
76
69
72
74
75
61
6c
5f
6d
61
63
68
69
6e
65
5f
6d
6f
72
65
5f
6c
69
6b
65
5f
76
65
72
69
6c
6f
67
5f
6d
61
63
68
69
6e
65
7d
01
32
1b
67
6a
4e
63
24
65
44
2a
42
24
36
78
6f
0a
64
32
69
7d
57
5f
18
21
50
1a
15
3e
3f
66
46
2f
42
22
56
2e
03
5e
51
61
26
1d
00
1d
6a
35
61
3a
b2
4e
bd
7b
9d
70
65
75
60
d8
2b
0b
08
d9
11
9c
b4
44
57

## data2.txt
a4
f4
61
9b
1f
28
81
9a
99
74
11
a9
67
cf
1a
47
4c
c6
48
b2
e0
d8
d6
86
0f
e5
68
96
03
14
b9
9d
a2
c9
83
fe
a3
74
df
2f
51
cb
21
0b
53
c8
8c
69
1e
38
c8
c7
1e
f2
cd
ec
2b
0a
5a
80
97
ea
94
f5
9e
ae
70
2f
31
b1
b0
42
e6
a8
a3
5a
97
9b
31
9c
c5
73
06
a1
86
3b
b0
c9
a2
5c
99
e0
24
af
e6
d6
bb
99
46
c1
42
c3
9f
66
8c
4a
88
ac
dd
05
73
29
8a
18
b0
e3
d5
a5
a3
6b
76
95
b0
e5
10
2a
d7
a1
33
55
51
53
a7
59
84
eb
e1
45
63
05
b6
bb
60
60
6f
fe
7b
4f
da
dd
12
93
6c
10
dc
56
1a
6d
6f
0c
3f
bb
49
00
34
1e
17
81
69
ce
04
70
a5
ad
b9
76
23
e7
a8
f4
05
a5
7a
4b
a1
0f
7f
a3
6a
5a
30
6e
03
71
6e
3f
7e
75
79
72
24
50
57
6e
17
3a
11
1b
73
2a
26
23
4a
57
4e
2c
20
0a
28
28
6c
21
20
47
71
0c
22
30
1c
70
6d
3b
6c
73
57
2a
ad
2a
85
bf
35
34
0d
d9
19
67
7c
51
2a
7e
3e
2c
bc
41
67
c0

## prog.txt
C80 C7f E00 C80 D00 C80 D00 E00 C00 C80 D00 100 B15 C80 C01 C80 D00 100 E00 700 803 C80 C00 E00 C81 C00 E00 C81 C81 D00 C80 D00 D00 000 C80 D00 C07 300 Cf8 000 D00 000 C7f 300 E00 97d C80 C80 D00 C01 000 E00 C80 D00 C80 200 B3b 700 81b C80 C00 E00 C81 C00 E00 C80 C80 D00 C01 000 E00 C81 C81 D00 C80 D00 D00 000 C7f 300 E00 97d C80 D00 D00 C81 D00 D00 000 C7f 300 D00 C01 C8c C80 D00 000 100 D00 200 C01 Cbc C80 D00 000 100 D00 200 700 B72 C87 C01 E00 F00 C80 D00 C30 200 B79 700 841 C87 C02 E00 F00 C81 D00 C80 D00 D00 C80 D00 C81 D00 D00 E00 E00 A00

## renamed_chal.sv
module top();
    reg clock, RST_flag;
    wire [11:0] prog_value;
    wire [7:0] prog_ptr, dataWrite_ptr, dataWrite_value, data_ptr, data_value;
    wire dataWrite_flag;
    string flag;
    integer z;

    initial forever begin
        clock = 0; #5;
        clock = 1; #5;
    end

    initial begin
        #1;
        flag = "maple{moj_poskus}";
        for (z=0; z< flag.len(); z++)
            DataMemorySpace.memorySpace[z+140] = flag[z];
        RST_flag = 1;
        #10;
        RST_flag = 0;
        #500000;
        if (DataMemorySpace.memorySpace[135] == 2)
            $display("You are winner!");
        else
            $display("Try again.");
        $finish();
    end

    Procesor TheProcessor(clock,
        RST_flag,
        prog_value, prog_ptr,
        dataWrite_ptr, dataWrite_value, dataWrite_flag,
        data_ptr, data_value);

    MemorySpace #(8,8,"data.txt") DataMemorySpace(clock, data_ptr, dataWrite_ptr, dataWrite_flag, dataWrite_value, data_value);
    MemorySpace #(12,8,"prog.txt") ProgMemorySpace(clock, prog_ptr, 8'b0, 1'b0, 12'b0, prog_value);
endmodule

module MemorySpace(clock, read_ptr, write_ptr, writeEnable_flag, write_value, read_value);
    parameter wordSize = 32;
    parameter addressBits = 4;
    parameter data_filename = "data.txt";

    input clock;
    input [addressBits-1:0] read_ptr, write_ptr;
    input writeEnable_flag;
    input [wordSize-1:0] write_value;
    output logic [wordSize-1:0] read_value;

    reg [wordSize-1:0] memorySpace [2**addressBits-1:0];

    initial $readmemh(data_filename, memorySpace);

    always @ (posedge clock) begin
        if (writeEnable_flag)
            memorySpace[write_ptr] <= write_value;
        read_value <= memorySpace[read_ptr];
    end
endmodule

module Procesor(clock, RST_flag,
        prog_value, prog_ptr,
        dataWrite_ptr,dataWrite_value,dataWrite_flag,
        data_ptr,data_value);

    input clock, RST_flag;
    input [11:0] prog_value;
    input [7:0] data_value;
    output logic [7:0] prog_ptr;
    output wire [7:0] dataWrite_ptr,data_ptr,dataWrite_value;
    output logic dataWrite_flag;

    wire [7:0] aluInput1,aluInput2;

    logic alustackEnable_flag, callstackEnable_flag;
    logic [2:0] aluStack_op,callStack_op;
    logic [2:0] op_subcode_3;

    wire [3:0] op_code;
    wire [7:0] immediate_value,nextProgJumpActive_ptr,aluStackIn_value,callstack2topval_value,prog_ptr_plus1;
    logic progAddr_callstack1_imm0_flag,alustackIn_1imm_0dataResult_flag,alustackIn_1aluResult_0given_flag,isZero_flag,arithmeticEnable_flag;
    logic [7:0] nextProg_ptr;

    typedef enum {STATE1_RESET, STATE2_JUMP, STATE3_NEXT_PTR, STATE4_HALT} PossibleStates;
    PossibleStates nextInstructionResolve;

    enum {TICK_OFF, TICK_ON} tickState;

    ArithmeticLogicUnit TheALU(clock, RST_flag,
                alustackIn_1aluResult_0given_flag,
                callstack2topval_value,
                op_subcode_3, arithmeticZero_flag,
                alustackEnable_flag, callstackEnable_flag,
                aluStack_op, callStack_op,
                aluStackIn_value,prog_ptr_plus1,
                aluInput1, aluInput2);

    // destructure
    assign op_code = prog_value[11:8];
    assign immediate_value = prog_value[7:0];

    assign nextProgJumpActive_ptr = progAddr_callstack1_imm0_flag == 0 ? immediate_value : callstack2topval_value;
    assign dataWrite_value = aluInput1;// alustack_top
    assign dataWrite_ptr = aluInput2; // alustack_top2
    assign data_ptr = aluInput1; // alustack_top
    assign aluStackIn_value = alustackIn_1imm_0dataResult_flag == 1 ? immediate_value : data_value;

    assign prog_ptr_plus1 = prog_ptr + 1;

    always_comb begin
        alustackIn_1aluResult_0given_flag = 1'b0;
        alustackEnable_flag = 1'b0;
        callstackEnable_flag = 1'b0;
        aluStack_op = 3'b0;
        callStack_op = 3'b0;
        nextInstructionResolve = STATE3_NEXT_PTR;
        progAddr_callstack1_imm0_flag = 1'b0;
        alustackIn_1imm_0dataResult_flag = 1'b1;
        dataWrite_flag = 1'b0;
        arithmeticEnable_flag = 1'b0;
        if (tickState == TICK_ON) begin
        casez(op_code)
            4'b0???: begin // CALC
                    if (op_code != 7) begin
                        // ALU result feedback to alu stack
                        alustackIn_1aluResult_0given_flag = 1'b1;
                        arithmeticEnable_flag = 1'b1;
                        op_subcode_3 = op_code[2:0];

                        // alu stack op removes top two elements and pushes on the result
                        alustackEnable_flag = 1'b1;
                        aluStack_op = 3'd3;

                    end else begin
                        // alu opcode for pop (remove)
                        alustackEnable_flag = 1'b1;
                        aluStack_op = 3'd4;
                        end
                    end
            4'd8: begin // JMP <low8>
                    nextInstructionResolve = STATE2_JUMP;
                    // Use immediate_value address
                    progAddr_callstack1_imm0_flag = 1'b0;
                    end
            4'd9: begin // CALL <low8>
                    nextInstructionResolve = STATE2_JUMP;

                    // Push prog_ptr+1 onto callstack
                    callstackEnable_flag = 1'b1;
                    callStack_op = 3'd0;

                    // Use immediate_value address
                    progAddr_callstack1_imm0_flag = 1'b0;
                    end
            4'd10: begin // RET
                    nextInstructionResolve = STATE2_JUMP;

                    // Removes from callstack
                    callstackEnable_flag = 1'b1;
                    callStack_op = 3'd4;

                    // Use callstack top item
                    progAddr_callstack1_imm0_flag = 1'b1;
                    end
            4'd11: begin // JZ AAAAAAAA
                    // Use imm value for jmp
                    progAddr_callstack1_imm0_flag = 1'b0;

                    if(isZero_flag)
                        nextInstructionResolve = STATE2_JUMP;
                    else
                        nextInstructionResolve = STATE3_NEXT_PTR;
                    end
            4'd12: begin // ALU_PUSH immediate_value
                    // alu input from given data
                    alustackIn_1aluResult_0given_flag = 1'b0;

                    // aluStack_op push
                    alustackEnable_flag = 1'b1;
                    aluStack_op = 3'b0;
                    end
            4'd13: begin // ALU_READ data_value

                    //aluStack_op overwrite top
                    aluStack_op = 3'd1;

                    // alustack input <- data.txt read
                    alustackIn_1aluResult_0given_flag = 1'b0;
                    alustackIn_1imm_0dataResult_flag = 1'b0;
                    alustackEnable_flag = 1'b1;
                    end
            4'd14: begin // ALU_WRITE
                    // enable write for this cycle
                    dataWrite_flag = 1'b1;

                    // aluStack_op remove top 2
                    aluStack_op = 3'd2;
                    alustackEnable_flag = 1'b1;
            end
            4'd15: nextInstructionResolve = STATE4_HALT;
        endcase
        end
    end


    always_comb begin
        // Update program pointer, based on current state
        case(nextInstructionResolve)
            STATE1_RESET: nextProg_ptr = 8'b0;
            STATE2_JUMP: nextProg_ptr = nextProgJumpActive_ptr;
            STATE3_NEXT_PTR: nextProg_ptr = prog_ptr + 1;
            STATE4_HALT: nextProg_ptr = prog_ptr;
            default: nextProg_ptr = 8'bz;
        endcase
    end

    always_ff @(posedge clock) begin
        if (RST_flag) begin
            prog_ptr <= 8'b0;
        end
        else begin
            if (tickState == TICK_ON)
                prog_ptr <= nextProg_ptr;
            if (arithmeticEnable_flag == 1)
                isZero_flag = arithmeticZero_flag;
        end
    end

    always_ff @(posedge clock) begin
        if (RST_flag)
            tickState <= TICK_OFF;
        else begin
            case(tickState)
                TICK_OFF: tickState <= TICK_ON;
                TICK_ON: tickState <= TICK_OFF;
            endcase
        end
    end
endmodule

module ArithmeticLogicUnit(clock,RST_flag,
                alustackIn_1aluResult_0given_flag,
                callstack2topval_value,
                op_subcode_3,arithmeticZero_flag,
                alustackEnable_flag,callstackEnable_flag,
                aluStack_op,callStack_op,
                aluStackIn_value,prog_ptr_plus1,
                aluInput1,aluInput2);

    input clock, RST_flag, alustackIn_1aluResult_0given_flag, alustackEnable_flag, callstackEnable_flag;
    input [7:0] aluStackIn_value, prog_ptr_plus1;
    input [2:0] aluStack_op, callStack_op;
    output logic [7:0] callstack2topval_value,aluInput1,aluInput2;
    input [2:0] op_subcode_3;
    output wire arithmeticZero_flag;

    wire [7:0] alustackInActive_value, aluResult, input1, input2, ram2memBefore_value;

    assign alustackInActive_value = alustackIn_1aluResult_0given_flag == 0 ? aluStackIn_value : aluResult;
    assign aluInput1 = input1;
    assign aluInput2 = input2;

    StackUnit #(10) ALUStack(.clock(clock),.RST_flag(RST_flag),
                        .memSet_value(alustackInActive_value),
                        .stackOp1_out(input1),.stackOp2_out(input2),
                        .unit_opcode(aluStack_op),.isActive(alustackEnable_flag));

    StackUnit #(10) CallStack(.clock(clock),.RST_flag(RST_flag),
                            .memSet_value(prog_ptr_plus1),
                            .stackOp1_out(callstack2topval_value),.stackOp2_out(ram2memBefore_value),
                            .unit_opcode(callStack_op),.isActive(callstackEnable_flag));

    ArithmeticUnit ArithmeticUnit(input1, input2, op_subcode_3, aluResult, arithmeticZero_flag);
endmodule

module StackUnit(clock,RST_flag,memSet_value,stackOp1_out,stackOp2_out,unit_opcode,isActive);
    input clock,RST_flag,isActive;

    input [7:0] memSet_value;
    output [7:0] stackOp1_out,stackOp2_out;
    input [2:0] unit_opcode;

    parameter addressLength = 16;
    logic [7:0] memorySpace [2**addressLength-1:0];
    logic [addressLength-1:0] addr_ptr;


    always_ff @(posedge clock) begin
        if (RST_flag == 1) begin
            addr_ptr <= 0;
        end else if (isActive ==1) begin
            case (unit_opcode)
                3'd0: begin // push
                        memorySpace[addr_ptr+1] <= memSet_value;
                        addr_ptr <= addr_ptr + 1;
                end
                3'd1: memorySpace[addr_ptr]<=memSet_value; //set top item
                3'd2: addr_ptr <= addr_ptr - 2; // pop 2
                3'd3: begin
                        addr_ptr <= addr_ptr - 1; // pop 2, push
                        memorySpace[addr_ptr-1] <= memSet_value;
                end
                3'd4: addr_ptr <= addr_ptr - 1; // pop 1
            endcase
        end
    end

    assign { stackOp1_out, stackOp2_out } = { memorySpace[addr_ptr], memorySpace[addr_ptr-1] };
endmodule

module ArithmeticUnit(input1, input2, unit_opcode, arithmeticResult, arithmeticZero_flag);
    input [7:0] input1, input2;
    output logic [7:0] arithmeticResult;
    input [2:0] unit_opcode;
    output arithmeticZero_flag;

    assign arithmeticZero_flag = arithmeticResult == 0 ? 1'b1 : 1'b0;

    always_comb begin
        case (unit_opcode)
            3'd0: arithmeticResult = input1 + input2;
            3'd1: arithmeticResult = input1 - input2;
            3'd2: arithmeticResult = input1 ^ input2;
            3'd3: arithmeticResult = input1 & input2;
            3'd4: arithmeticResult = input1 | input2;
            3'd5: arithmeticResult = input1 << input2;
            3'd6: arithmeticResult = input1 >> input2;
            default: arithmeticResult = 8'bz;
        endcase
    end
endmodule
	module top();
	reg eo3,nF3;
	wire [11:0] D1q7APfd;
	wire [7:0] Dy,HZ4cC8Gwm7YlmW,XIzbggF,XvqVFhCAiK8ZU,eCzsnH;
	wire n35s92a4h;
	string flag;
	integer z;

	initial forever begin
	eo3 = 0; #5;
	eo3 = 1; #5;
	end

	initial begin
	#1;
	flag = "maple{testflag}";
	for (z=0; z< flag.len(); z++)
	TSdB.fgS[z+140] = flag[z];
	nF3 = 1;
	#10;
	nF3 = 0;
	#500000;
	if (TSdB.fgS[135] == 2)
	$display("You are winner!");
	else
	$display("Try again.");
	$finish();
	end

	ioJ xft(eo3,nF3,
	D1q7APfd,Dy,
	HZ4cC8Gwm7YlmW,XIzbggF,n35s92a4h,
	XvqVFhCAiK8ZU,eCzsnH);

	WsR #(8,8,"data.txt") TSdB(eo3,XvqVFhCAiK8ZU,HZ4cC8Gwm7YlmW,n35s92a4h,XIzbggF,eCzsnH);
	WsR #(12,8,"prog.txt") njg4YL52AkHJ(eo3,Dy,8'b0,1'b0,12'b0,D1q7APfd);
	endmodule

	module WsR(eo3,OaPYNLCWZ,FTkstjTLci,rIefx,eqJ,zhRu);
	parameter V2akbDl5qY = 32;
	parameter ulTe71D35n = 4;
	parameter Yj4Y6kAS = "data.txt";

	input eo3;
	input [ulTe71D35n-1:0] OaPYNLCWZ, FTkstjTLci;
	input rIefx;
	input [V2akbDl5qY-1:0] eqJ;
	output logic [V2akbDl5qY-1:0] zhRu;

	reg [V2akbDl5qY-1:0] fgS [2**ulTe71D35n-1:0];

	initial $readmemh(Yj4Y6kAS, fgS);

	always @ (posedge eo3) begin
	if (rIefx)
	fgS[FTkstjTLci] <= eqJ;
	zhRu <= fgS[OaPYNLCWZ];
	end
	endmodule

	module ioJ(eo3,nF3,
	D1q7APfd,Dy,
	HZ4cC8Gwm7YlmW,eCzsnH,n35s92a4h,
	XvqVFhCAiK8ZU,XIzbggF);

	input eo3, nF3;
	input [11:0] D1q7APfd;
	input [7:0] XIzbggF;
	output logic [7:0] Dy;
	output wire [7:0] HZ4cC8Gwm7YlmW,XvqVFhCAiK8ZU,eCzsnH;
	output logic n35s92a4h;

	wire [7:0] wgb7SWQCojbM0z,t14sshQ2kVxklOx;

	logic XTy0gvT0Bt1zmDLV008,EyZChyzXuhgMsgovFC;
	logic [2:0] QD2p2rf6jj5o9,ZamHFiK7It0a;
	logic [2:0] b4ivvC;

	wire [3:0] rSRUKV;
	wire [7:0] HySaIQf,BGtF9jPA,eRl31tlw1,yPs51RDPPUv,ulW9ociVdXXbW;
	logic C2y,R7O7txm93M,d6FZwCaz4mM,BXNS,WsNZ9Zbv;
	logic [7:0] nYKQupS;

	typedef enum {EKQMvI6y,jiZAPV,CSdThODUs,zAdA} LpZvRPGZ;
	LpZvRPGZ nWFEYy;

	enum {vJwNE,VEIImw4} nvuDF;

	wBlFnCyLj AI(eo3,nF3,
	d6FZwCaz4mM,
	yPs51RDPPUv,
	b4ivvC,lMwuHWy,
	XTy0gvT0Bt1zmDLV008,EyZChyzXuhgMsgovFC,
	QD2p2rf6jj5o9,ZamHFiK7It0a,
	eRl31tlw1,ulW9ociVdXXbW,
	wgb7SWQCojbM0z,t14sshQ2kVxklOx);

	assign rSRUKV = D1q7APfd[11:8];
	assign HySaIQf = D1q7APfd[7:0];
	assign BGtF9jPA = C2y == 0 ? HySaIQf : yPs51RDPPUv;
	assign HZ4cC8Gwm7YlmW = t14sshQ2kVxklOx;
	assign XvqVFhCAiK8ZU = wgb7SWQCojbM0z;
	assign eRl31tlw1 = R7O7txm93M == 1 ? HySaIQf : XIzbggF;

	assign eCzsnH = wgb7SWQCojbM0z;
	assign ulW9ociVdXXbW = Dy + 1;

	always_comb begin
	d6FZwCaz4mM = 1'b0;
	XTy0gvT0Bt1zmDLV008 = 1'b0;
	EyZChyzXuhgMsgovFC = 1'b0;
	QD2p2rf6jj5o9 = 3'b0;
	ZamHFiK7It0a = 3'b0;
	nWFEYy = CSdThODUs;
	C2y = 1'b0;
	R7O7txm93M = 1'b1;
	n35s92a4h = 1'b0;
	WsNZ9Zbv = 1'b0;
	if (nvuDF == VEIImw4) begin
	casez(rSRUKV)
	4'b0???: begin
	if (rSRUKV != 7) begin
	d6FZwCaz4mM = 1'b1;
	b4ivvC = rSRUKV[2:0];
	XTy0gvT0Bt1zmDLV008 = 1'b1;
	QD2p2rf6jj5o9 = 3'd3;
	WsNZ9Zbv = 1'b1;
	end else begin
	XTy0gvT0Bt1zmDLV008 = 1'b1;
	QD2p2rf6jj5o9 = 3'd4;
	end
	end
	4'd8: begin
	nWFEYy = jiZAPV;
	C2y = 1'b0;
	end
	4'd9: begin
	nWFEYy = jiZAPV;
	EyZChyzXuhgMsgovFC = 1'b1;
	ZamHFiK7It0a = 3'd0;
	C2y = 1'b0;
	end
	4'd10: begin
	nWFEYy = jiZAPV;
	EyZChyzXuhgMsgovFC = 1'b1;
	ZamHFiK7It0a = 3'd4;
	C2y = 1'b1;
	end
	4'd11: begin
	C2y = 1'b0;
	if(BXNS)
	nWFEYy = jiZAPV;
	else
	nWFEYy = CSdThODUs;
	end
	4'd12: begin
	d6FZwCaz4mM = 1'b0;
	XTy0gvT0Bt1zmDLV008 = 1'b1;
	QD2p2rf6jj5o9 = 3'b0;
	end
	4'd13: begin
	QD2p2rf6jj5o9 = 3'd1;
	d6FZwCaz4mM = 1'b0;
	R7O7txm93M = 1'b0;
	XTy0gvT0Bt1zmDLV008 = 1'b1;
	end
	4'd14: begin
	n35s92a4h = 1'b1;
	QD2p2rf6jj5o9 = 3'd2;
	XTy0gvT0Bt1zmDLV008 = 1'b1;
	end
	4'd15: nWFEYy = zAdA;
	endcase
	end
	end


	always_comb begin
	case(nWFEYy)
	EKQMvI6y: nYKQupS = 8'b0;
	jiZAPV: nYKQupS = BGtF9jPA;
	CSdThODUs: nYKQupS = Dy + 1;
	zAdA: nYKQupS = Dy;
	default: nYKQupS = 8'bz;
	endcase
	end

	always_ff @(posedge eo3) begin
	if (nF3) begin
	Dy <= 8'b0;
	end
	else begin
	if (nvuDF == VEIImw4)
	Dy <= nYKQupS;
	if (WsNZ9Zbv == 1)
	BXNS = lMwuHWy;
	end
	end

	always_ff @(posedge eo3) begin
	if (nF3)
	nvuDF <= vJwNE;
	else begin
	case(nvuDF)
	vJwNE: nvuDF <= VEIImw4;
	VEIImw4: nvuDF <= vJwNE;
	endcase
	end
	end
	endmodule

	module wBlFnCyLj(eo3,nF3,
	d6FZwCaz4mM,
	WnBJU6Eefj,
	b4ivvC,f,
	XTy0gvT0Bt1zmDLV008,EyZChyzXuhgMsgovFC,
	QD2p2rf6jj5o9,ZamHFiK7It0a,
	eRl31tlw1,ulW9ociVdXXbW,
	wgb7SWQCojbM0z,t14sshQ2kVxklOx);
	input eo3,nF3,d6FZwCaz4mM,XTy0gvT0Bt1zmDLV008,EyZChyzXuhgMsgovFC;
	input [7:0] eRl31tlw1,ulW9ociVdXXbW;
	input [2:0] QD2p2rf6jj5o9,ZamHFiK7It0a;
	output logic [7:0] WnBJU6Eefj,wgb7SWQCojbM0z,t14sshQ2kVxklOx;
	input [2:0] b4ivvC;
	output wire f;

	wire [7:0] QU6cTlk, yceR1D2,ZuqqtM7t, HgY3ljXJn, CMFdSku6Yj7;

	assign QU6cTlk = d6FZwCaz4mM == 0 ? eRl31tlw1 : yceR1D2;
	assign wgb7SWQCojbM0z = ZuqqtM7t;
	assign t14sshQ2kVxklOx = HgY3ljXJn;

	Ol8vW #(10) sIctJNEm0A(.eo3(eo3),.nF3(nF3),
	.QU6cTlk(QU6cTlk),
	.Jpup6gEow(ZuqqtM7t),.nFOoEI7Dnl(HgY3ljXJn),
	.QV(QD2p2rf6jj5o9),.pb(XTy0gvT0Bt1zmDLV008));

	Ol8vW #(10) ek6j3imqGFx6(.eo3(eo3),.nF3(nF3),
	.QU6cTlk(ulW9ociVdXXbW),
	.Jpup6gEow(WnBJU6Eefj),.nFOoEI7Dnl(CMFdSku6Yj7),
	.QV(ZamHFiK7It0a),.pb(EyZChyzXuhgMsgovFC));

	Ltc Ltc(ZuqqtM7t,HgY3ljXJn,b4ivvC,yceR1D2,f);




	endmodule

	module Ol8vW(eo3,nF3,QU6cTlk,Jpup6gEow,nFOoEI7Dnl,QV,pb);
	input eo3,nF3,pb;

	input [7:0] QU6cTlk;
	output [7:0] Jpup6gEow,nFOoEI7Dnl;
	input [2:0] QV;

	parameter WXifi4fqUy9NY = 16;
	logic [7:0] fgS [2**WXifi4fqUy9NY-1:0];
	logic [WXifi4fqUy9NY-1:0] gPrDVGD;


	always_ff @(posedge eo3) begin
	if (nF3 == 1) begin
	gPrDVGD <= 0;
	end else if (pb ==1) begin
	case (QV)
	3'd0: begin
	fgS[gPrDVGD+1] <= QU6cTlk;
	gPrDVGD <= gPrDVGD + 1;
	end
	3'd1: fgS[gPrDVGD]<=QU6cTlk;
	3'd2: gPrDVGD <= gPrDVGD - 2;
	3'd3: begin
	gPrDVGD <= gPrDVGD - 1;
	fgS[gPrDVGD-1] <= QU6cTlk;
	end
	3'd4: gPrDVGD <= gPrDVGD - 1;
	endcase
	end
	end

	assign {Jpup6gEow,nFOoEI7Dnl} = {fgS[gPrDVGD],fgS[gPrDVGD-1]};

	endmodule

	module Ltc(Z,o,QV,mtc,f);
	input [7:0] Z,o;
	output logic [7:0] mtc;
	input [2:0] QV;
	output f;

	assign f = mtc == 0 ? 1'b1 : 1'b0;

	always_comb begin
	case (QV)
	3'd0: mtc = Z + o;
	3'd1: mtc = Z - o;
	3'd2: mtc = Z ^ o;
	3'd3: mtc = Z & o;
	3'd4: mtc = Z \| o;
	3'd5: mtc = Z << o;
	3'd6: mtc = Z >> o;
	default: mtc = 8'bz;
	endcase
	end
	endmodule
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	c0
	module top();
	reg clock, RST_flag;
	wire [11:0] prog_value;
	wire [7:0] prog_ptr, dataWrite_ptr, dataWrite_value, data_ptr, data_value;
	wire dataWrite_flag;
	string flag;
	integer z;

	initial forever begin
	clock = 0; #5;
	clock = 1; #5;
	end

	initial begin
	#1;
	flag = "maple{moj_poskus}";
	for (z=0; z< flag.len(); z++)
	DataMemorySpace.memorySpace[z+140] = flag[z];
	RST_flag = 1;
	#10;
	RST_flag = 0;
	#500000;
	if (DataMemorySpace.memorySpace[135] == 2)
	$display("You are winner!");
	else
	$display("Try again.");
	$finish();
	end

	Procesor TheProcessor(clock,
	RST_flag,
	prog_value, prog_ptr,
	dataWrite_ptr, dataWrite_value, dataWrite_flag,
	data_ptr, data_value);

	MemorySpace #(8,8,"data.txt") DataMemorySpace(clock, data_ptr, dataWrite_ptr, dataWrite_flag, dataWrite_value, data_value);
	MemorySpace #(12,8,"prog.txt") ProgMemorySpace(clock, prog_ptr, 8'b0, 1'b0, 12'b0, prog_value);
	endmodule

	module MemorySpace(clock, read_ptr, write_ptr, writeEnable_flag, write_value, read_value);
	parameter wordSize = 32;
	parameter addressBits = 4;
	parameter data_filename = "data.txt";

	input clock;
	input [addressBits-1:0] read_ptr, write_ptr;
	input writeEnable_flag;
	input [wordSize-1:0] write_value;
	output logic [wordSize-1:0] read_value;

	reg [wordSize-1:0] memorySpace [2**addressBits-1:0];

	initial $readmemh(data_filename, memorySpace);

	always @ (posedge clock) begin
	if (writeEnable_flag)
	memorySpace[write_ptr] <= write_value;
	read_value <= memorySpace[read_ptr];
	end
	endmodule

	module Procesor(clock, RST_flag,
	prog_value, prog_ptr,
	dataWrite_ptr,dataWrite_value,dataWrite_flag,
	data_ptr,data_value);

	input clock, RST_flag;
	input [11:0] prog_value;
	input [7:0] data_value;
	output logic [7:0] prog_ptr;
	output wire [7:0] dataWrite_ptr,data_ptr,dataWrite_value;
	output logic dataWrite_flag;

	wire [7:0] aluInput1,aluInput2;

	logic alustackEnable_flag, callstackEnable_flag;
	logic [2:0] aluStack_op,callStack_op;
	logic [2:0] op_subcode_3;

	wire [3:0] op_code;
	wire [7:0] immediate_value,nextProgJumpActive_ptr,aluStackIn_value,callstack2topval_value,prog_ptr_plus1;
	logic progAddr_callstack1_imm0_flag,alustackIn_1imm_0dataResult_flag,alustackIn_1aluResult_0given_flag,isZero_flag,arithmeticEnable_flag;
	logic [7:0] nextProg_ptr;

	typedef enum {STATE1_RESET, STATE2_JUMP, STATE3_NEXT_PTR, STATE4_HALT} PossibleStates;
	PossibleStates nextInstructionResolve;

	enum {TICK_OFF, TICK_ON} tickState;

	ArithmeticLogicUnit TheALU(clock, RST_flag,
	alustackIn_1aluResult_0given_flag,
	callstack2topval_value,
	op_subcode_3, arithmeticZero_flag,
	alustackEnable_flag, callstackEnable_flag,
	aluStack_op, callStack_op,
	aluStackIn_value,prog_ptr_plus1,
	aluInput1, aluInput2);

	// destructure
	assign op_code = prog_value[11:8];
	assign immediate_value = prog_value[7:0];

	assign nextProgJumpActive_ptr = progAddr_callstack1_imm0_flag == 0 ? immediate_value : callstack2topval_value;
	assign dataWrite_value = aluInput1;// alustack_top
	assign dataWrite_ptr = aluInput2; // alustack_top2
	assign data_ptr = aluInput1; // alustack_top
	assign aluStackIn_value = alustackIn_1imm_0dataResult_flag == 1 ? immediate_value : data_value;

	assign prog_ptr_plus1 = prog_ptr + 1;

	always_comb begin
	alustackIn_1aluResult_0given_flag = 1'b0;
	alustackEnable_flag = 1'b0;
	callstackEnable_flag = 1'b0;
	aluStack_op = 3'b0;
	callStack_op = 3'b0;
	nextInstructionResolve = STATE3_NEXT_PTR;
	progAddr_callstack1_imm0_flag = 1'b0;
	alustackIn_1imm_0dataResult_flag = 1'b1;
	dataWrite_flag = 1'b0;
	arithmeticEnable_flag = 1'b0;
	if (tickState == TICK_ON) begin
	casez(op_code)
	4'b0???: begin // CALC
	if (op_code != 7) begin
	// ALU result feedback to alu stack
	alustackIn_1aluResult_0given_flag = 1'b1;
	arithmeticEnable_flag = 1'b1;
	op_subcode_3 = op_code[2:0];

	// alu stack op removes top two elements and pushes on the result
	alustackEnable_flag = 1'b1;
	aluStack_op = 3'd3;

	end else begin
	// alu opcode for pop (remove)
	alustackEnable_flag = 1'b1;
	aluStack_op = 3'd4;
	end
	end
	4'd8: begin // JMP <low8>
	nextInstructionResolve = STATE2_JUMP;
	// Use immediate_value address
	progAddr_callstack1_imm0_flag = 1'b0;
	end
	4'd9: begin // CALL <low8>
	nextInstructionResolve = STATE2_JUMP;

	// Push prog_ptr+1 onto callstack
	callstackEnable_flag = 1'b1;
	callStack_op = 3'd0;

	// Use immediate_value address
	progAddr_callstack1_imm0_flag = 1'b0;
	end
	4'd10: begin // RET
	nextInstructionResolve = STATE2_JUMP;

	// Removes from callstack
	callstackEnable_flag = 1'b1;
	callStack_op = 3'd4;

	// Use callstack top item
	progAddr_callstack1_imm0_flag = 1'b1;
	end
	4'd11: begin // JZ AAAAAAAA
	// Use imm value for jmp
	progAddr_callstack1_imm0_flag = 1'b0;

	if(isZero_flag)
	nextInstructionResolve = STATE2_JUMP;
	else
	nextInstructionResolve = STATE3_NEXT_PTR;
	end
	4'd12: begin // ALU_PUSH immediate_value
	// alu input from given data
	alustackIn_1aluResult_0given_flag = 1'b0;

	// aluStack_op push
	alustackEnable_flag = 1'b1;
	aluStack_op = 3'b0;
	end
	4'd13: begin // ALU_READ data_value

	//aluStack_op overwrite top
	aluStack_op = 3'd1;

	// alustack input <- data.txt read
	alustackIn_1aluResult_0given_flag = 1'b0;
	alustackIn_1imm_0dataResult_flag = 1'b0;
	alustackEnable_flag = 1'b1;
	end
	4'd14: begin // ALU_WRITE
	// enable write for this cycle
	dataWrite_flag = 1'b1;

	// aluStack_op remove top 2
	aluStack_op = 3'd2;
	alustackEnable_flag = 1'b1;
	end
	4'd15: nextInstructionResolve = STATE4_HALT;
	endcase
	end
	end


	always_comb begin
	// Update program pointer, based on current state
	case(nextInstructionResolve)
	STATE1_RESET: nextProg_ptr = 8'b0;
	STATE2_JUMP: nextProg_ptr = nextProgJumpActive_ptr;
	STATE3_NEXT_PTR: nextProg_ptr = prog_ptr + 1;
	STATE4_HALT: nextProg_ptr = prog_ptr;
	default: nextProg_ptr = 8'bz;
	endcase
	end

	always_ff @(posedge clock) begin
	if (RST_flag) begin
	prog_ptr <= 8'b0;
	end
	else begin
	if (tickState == TICK_ON)
	prog_ptr <= nextProg_ptr;
	if (arithmeticEnable_flag == 1)
	isZero_flag = arithmeticZero_flag;
	end
	end

	always_ff @(posedge clock) begin
	if (RST_flag)
	tickState <= TICK_OFF;
	else begin
	case(tickState)
	TICK_OFF: tickState <= TICK_ON;
	TICK_ON: tickState <= TICK_OFF;
	endcase
	end
	end
	endmodule

	module ArithmeticLogicUnit(clock,RST_flag,
	alustackIn_1aluResult_0given_flag,
	callstack2topval_value,
	op_subcode_3,arithmeticZero_flag,
	alustackEnable_flag,callstackEnable_flag,
	aluStack_op,callStack_op,
	aluStackIn_value,prog_ptr_plus1,
	aluInput1,aluInput2);

	input clock, RST_flag, alustackIn_1aluResult_0given_flag, alustackEnable_flag, callstackEnable_flag;
	input [7:0] aluStackIn_value, prog_ptr_plus1;
	input [2:0] aluStack_op, callStack_op;
	output logic [7:0] callstack2topval_value,aluInput1,aluInput2;
	input [2:0] op_subcode_3;
	output wire arithmeticZero_flag;

	wire [7:0] alustackInActive_value, aluResult, input1, input2, ram2memBefore_value;

	assign alustackInActive_value = alustackIn_1aluResult_0given_flag == 0 ? aluStackIn_value : aluResult;
	assign aluInput1 = input1;
	assign aluInput2 = input2;

	StackUnit #(10) ALUStack(.clock(clock),.RST_flag(RST_flag),
	.memSet_value(alustackInActive_value),
	.stackOp1_out(input1),.stackOp2_out(input2),
	.unit_opcode(aluStack_op),.isActive(alustackEnable_flag));

	StackUnit #(10) CallStack(.clock(clock),.RST_flag(RST_flag),
	.memSet_value(prog_ptr_plus1),
	.stackOp1_out(callstack2topval_value),.stackOp2_out(ram2memBefore_value),
	.unit_opcode(callStack_op),.isActive(callstackEnable_flag));

	ArithmeticUnit ArithmeticUnit(input1, input2, op_subcode_3, aluResult, arithmeticZero_flag);
	endmodule

	module StackUnit(clock,RST_flag,memSet_value,stackOp1_out,stackOp2_out,unit_opcode,isActive);
	input clock,RST_flag,isActive;

	input [7:0] memSet_value;
	output [7:0] stackOp1_out,stackOp2_out;
	input [2:0] unit_opcode;

	parameter addressLength = 16;
	logic [7:0] memorySpace [2**addressLength-1:0];
	logic [addressLength-1:0] addr_ptr;


	always_ff @(posedge clock) begin
	if (RST_flag == 1) begin
	addr_ptr <= 0;
	end else if (isActive ==1) begin
	case (unit_opcode)
	3'd0: begin // push
	memorySpace[addr_ptr+1] <= memSet_value;
	addr_ptr <= addr_ptr + 1;
	end
	3'd1: memorySpace[addr_ptr]<=memSet_value; //set top item
	3'd2: addr_ptr <= addr_ptr - 2; // pop 2
	3'd3: begin
	addr_ptr <= addr_ptr - 1; // pop 2, push
	memorySpace[addr_ptr-1] <= memSet_value;
	end
	3'd4: addr_ptr <= addr_ptr - 1; // pop 1
	endcase
	end
	end

	assign { stackOp1_out, stackOp2_out } = { memorySpace[addr_ptr], memorySpace[addr_ptr-1] };
	endmodule

	module ArithmeticUnit(input1, input2, unit_opcode, arithmeticResult, arithmeticZero_flag);
	input [7:0] input1, input2;
	output logic [7:0] arithmeticResult;
	input [2:0] unit_opcode;
	output arithmeticZero_flag;

	assign arithmeticZero_flag = arithmeticResult == 0 ? 1'b1 : 1'b0;

	always_comb begin
	case (unit_opcode)
	3'd0: arithmeticResult = input1 + input2;
	3'd1: arithmeticResult = input1 - input2;
	3'd2: arithmeticResult = input1 ^ input2;
	3'd3: arithmeticResult = input1 & input2;
	3'd4: arithmeticResult = input1 \| input2;
	3'd5: arithmeticResult = input1 << input2;
	3'd6: arithmeticResult = input1 >> input2;
	default: arithmeticResult = 8'bz;
	endcase
	end
	endmodule