lpc845.svd_orig

<?xml version="1.0" encoding="UTF-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
  <vendor>NXP Semiconductors</vendor>
  <vendorID>NXP</vendorID>
  <name>LPC845</name>
  <series>LPC</series>
  <version>1.6</version>
  <description>LPC845 NXP Microcontroller</description>
  <licenseText>Copyright 2016-2020 NXP\n All rights reserved.\n SPDX-License-Identifier: BSD-3-Clause</licenseText>
  <cpu>
    <name>CM0PLUS</name>
    <revision>r0p0</revision>
    <endian>little</endian>
    <mpuPresent>false</mpuPresent>
    <fpuPresent>false</fpuPresent>
    <vtorPresent>true</vtorPresent>
    <nvicPrioBits>2</nvicPrioBits>
    <vendorSystickConfig>false</vendorSystickConfig>
  </cpu>
  <addressUnitBits>8</addressUnitBits>
  <width>32</width>
  <peripherals>
    <peripheral>
      <name>WWDT</name>
      <description>LPC84x Windowed Watchdog Timer (WWDT)</description>
      <baseAddress>0x40000000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x1C</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>WDT</name>
        <value>12</value>
      </interrupt>
      <registers>
        <register>
          <name>MOD</name>
          <description>Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3F</resetMask>
          <fields>
            <field>
              <name>WDEN</name>
              <description>Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Stop. The watchdog timer is stopped.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Run. The watchdog timer is running.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>WDRESET</name>
              <description>Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Interrupt. A watchdog time-out will not cause a chip reset.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Reset. A watchdog time-out will cause a chip reset.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>WDTOF</name>
              <description>Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDINT</name>
              <description>Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDPROTECT</name>
              <description>Watchdog update mode. This bit can be set once by software and is only cleared by a reset.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Flexible. The watchdog time-out value (TC) can be changed at any time.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>LOCK</name>
              <description>Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TC</name>
          <description>Watchdog timer constant register. This 24-bit register determines the time-out value.</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFF</resetValue>
          <resetMask>0xFFFFFF</resetMask>
          <fields>
            <field>
              <name>COUNT</name>
              <description>Watchdog time-out value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>24</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FEED</name>
          <description>Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC.</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>FEED</name>
              <description>Feed value should be 0xAA followed by 0x55.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TV</name>
          <description>Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFF</resetValue>
          <resetMask>0xFFFFFF</resetMask>
          <fields>
            <field>
              <name>COUNT</name>
              <description>Counter timer value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>24</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WARNINT</name>
          <description>Watchdog Warning Interrupt compare value.</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3FF</resetMask>
          <fields>
            <field>
              <name>WARNINT</name>
              <description>Watchdog warning interrupt compare value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WINDOW</name>
          <description>Watchdog Window compare value.</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFF</resetValue>
          <resetMask>0xFFFFFF</resetMask>
          <fields>
            <field>
              <name>WINDOW</name>
              <description>Watchdog window value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>24</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>MRT0</name>
      <description>LPC84x Multi-Rate Timer (MRT)</description>
      <baseAddress>0x40004000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0xFC</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>MRT0</name>
        <value>10</value>
      </interrupt>
      <registers>
        <register>
          <name>INTVAL0</name>
          <description>MRT Time interval value register. This value is loaded into the TIMER register.</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>IVALUE</name>
              <description>Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>31</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LOAD</name>
              <description>Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMER0</name>
          <description>MRT Timer register. This register reads the value of the down-counter.</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFFFFFF</resetValue>
          <resetMask>0x7FFFFFFF</resetMask>
          <fields>
            <field>
              <name>VALUE</name>
              <description>Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>31</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL0</name>
          <description>MRT Control register. This register controls the MRT modes.</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x7</resetMask>
          <fields>
            <field>
              <name>INTEN</name>
              <description>Enable the TIMERn interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. TIMERn interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. TIMERn interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MODE</name>
              <description>Selects timer mode.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Repeat interrupt mode.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>One-shot interrupt mode.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>One-shot stall mode.</description>
                  <value>#10</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT0</name>
          <description>MRT Status register.</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3</resetMask>
          <fields>
            <field>
              <name>INTFLAG</name>
              <description>Monitors the interrupt flag.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RUN</name>
              <description>Indicates the state of TIMERn. This bit is read-only.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Idle state. TIMERn is stopped.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Running. TIMERn is running.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTVAL1</name>
          <description>MRT Time interval value register. This value is loaded into the TIMER register.</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>IVALUE</name>
              <description>Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>31</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LOAD</name>
              <description>Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMER1</name>
          <description>MRT Timer register. This register reads the value of the down-counter.</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFFFFFF</resetValue>
          <resetMask>0x7FFFFFFF</resetMask>
          <fields>
            <field>
              <name>VALUE</name>
              <description>Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>31</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL1</name>
          <description>MRT Control register. This register controls the MRT modes.</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x7</resetMask>
          <fields>
            <field>
              <name>INTEN</name>
              <description>Enable the TIMERn interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. TIMERn interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. TIMERn interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MODE</name>
              <description>Selects timer mode.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Repeat interrupt mode.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>One-shot interrupt mode.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>One-shot stall mode.</description>
                  <value>#10</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT1</name>
          <description>MRT Status register.</description>
          <addressOffset>0x1C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3</resetMask>
          <fields>
            <field>
              <name>INTFLAG</name>
              <description>Monitors the interrupt flag.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RUN</name>
              <description>Indicates the state of TIMERn. This bit is read-only.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Idle state. TIMERn is stopped.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Running. TIMERn is running.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTVAL2</name>
          <description>MRT Time interval value register. This value is loaded into the TIMER register.</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>IVALUE</name>
              <description>Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>31</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LOAD</name>
              <description>Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMER2</name>
          <description>MRT Timer register. This register reads the value of the down-counter.</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFFFFFF</resetValue>
          <resetMask>0x7FFFFFFF</resetMask>
          <fields>
            <field>
              <name>VALUE</name>
              <description>Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>31</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL2</name>
          <description>MRT Control register. This register controls the MRT modes.</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x7</resetMask>
          <fields>
            <field>
              <name>INTEN</name>
              <description>Enable the TIMERn interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. TIMERn interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. TIMERn interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MODE</name>
              <description>Selects timer mode.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Repeat interrupt mode.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>One-shot interrupt mode.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>One-shot stall mode.</description>
                  <value>#10</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT2</name>
          <description>MRT Status register.</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3</resetMask>
          <fields>
            <field>
              <name>INTFLAG</name>
              <description>Monitors the interrupt flag.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RUN</name>
              <description>Indicates the state of TIMERn. This bit is read-only.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Idle state. TIMERn is stopped.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Running. TIMERn is running.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTVAL3</name>
          <description>MRT Time interval value register. This value is loaded into the TIMER register.</description>
          <addressOffset>0x30</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>IVALUE</name>
              <description>Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>31</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LOAD</name>
              <description>Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMER3</name>
          <description>MRT Timer register. This register reads the value of the down-counter.</description>
          <addressOffset>0x34</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFFFFFF</resetValue>
          <resetMask>0x7FFFFFFF</resetMask>
          <fields>
            <field>
              <name>VALUE</name>
              <description>Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>31</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL3</name>
          <description>MRT Control register. This register controls the MRT modes.</description>
          <addressOffset>0x38</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x7</resetMask>
          <fields>
            <field>
              <name>INTEN</name>
              <description>Enable the TIMERn interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. TIMERn interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. TIMERn interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MODE</name>
              <description>Selects timer mode.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Repeat interrupt mode.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>One-shot interrupt mode.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>One-shot stall mode.</description>
                  <value>#10</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT3</name>
          <description>MRT Status register.</description>
          <addressOffset>0x3C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3</resetMask>
          <fields>
            <field>
              <name>INTFLAG</name>
              <description>Monitors the interrupt flag.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RUN</name>
              <description>Indicates the state of TIMERn. This bit is read-only.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Idle state. TIMERn is stopped.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Running. TIMERn is running.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>IDLE_CH</name>
          <description>Idle channel register. This register returns the number of the first idle channel.</description>
          <addressOffset>0xF4</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xF0</resetMask>
          <fields>
            <field>
              <name>CHAN</name>
              <description>Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IRQ_FLAG</name>
          <description>Global interrupt flag register</description>
          <addressOffset>0xF8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>GFLAG0</name>
              <description>Monitors the interrupt flag of TIMER0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>GFLAG1</name>
              <description>Monitors the interrupt flag of TIMER1. See description of channel 0.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GFLAG2</name>
              <description>Monitors the interrupt flag of TIMER2. See description of channel 0.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GFLAG3</name>
              <description>Monitors the interrupt flag of TIMER3. See description of channel 0.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>WKT</name>
      <description>LPC84x Wake Up Timer(WKT)</description>
      <baseAddress>0x40008000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x10</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>WKT</name>
        <value>15</value>
      </interrupt>
      <registers>
        <register>
          <name>CTRL</name>
          <description>Self wake-up timer control register.</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>CLKSEL</name>
              <description>Select the self wake-up timer clock source. Remark: This bit only has an effect if the SEL_EXTCLK bit is not set.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Divided FRO clock. This clock runs at 750 kHz and provides time-out periods of up to approximately 95 minutes in 1.33 us increments. Remark: This clock is not available in not available in Deep-sleep, power-down, deep power-down modes. Do not select this option if the timer is to be used to wake up from one of these modes.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>This is the (nominally) 10 kHz clock and provides time-out periods of up to approximately 119 hours in 100 us increments. The accuracy of this clock is limited to +/- 40 % over temperature and processing. Remark: This clock is available in all power modes. Prior to use, the low-power oscillator must be enabled. The oscillator must also be set to remain active in Deep power-down if needed.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ALARMFLAG</name>
              <description>Wake-up or alarm timer flag.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No time-out. The self wake-up timer has not timed out. Writing a 0 to has no effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Time-out. The self wake-up timer has timed out. This flag generates an interrupt request which can wake up the part from any reduced power mode including Deep power-down if the clock source is the low power oscillator. Writing a 1 clears this status bit.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLEARCTR</name>
              <description>Clears the self wake-up timer.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect. Reading this bit always returns 0.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Clear the counter. Counting is halted until a new count value is loaded.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SEL_EXTCLK</name>
              <description>Select external or internal clock source for the self wake-up timer. The internal clock source is selected by the CLKSEL bit in this register if SET_EXTCLK is set to internal.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Internal. The clock source is the internal clock selected by the CLKSEL bit.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>External. The self wake-up timer uses the external WKTCLKIN pin.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>COUNT</name>
          <description>Counter register.</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>VALUE</name>
              <description>A write to this register pre-loads start count value into the timer and starts the count-down sequence. A read reflects the current value of the timer.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>SWM0</name>
      <description>LPC84x SWM</description>
      <baseAddress>0x4000C000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x1C8</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>PINASSIGN0</name>
          <description>Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS.</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>U0_TXD_O</name>
              <description>U0_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35) .</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>U0_RXD_I</name>
              <description>U0_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>U0_RTS_O</name>
              <description>U0_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>U0_CTS_I</name>
              <description>U0_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA0</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN1</name>
          <description>Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_RTS.</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>U0_SCLK_IO</name>
              <description>U0_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>U1_TXD_O</name>
              <description>U1_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>U1_RXD_I</name>
              <description>U1_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>U1_RTS_O</name>
              <description>U1_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA1</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN2</name>
          <description>Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, U2_TXD, U2_RXD.</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>U1_CTS_I</name>
              <description>U1_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>U1_SCLK_IO</name>
              <description>U1_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>U2_TXD_O</name>
              <description>U2_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>U2_RXD_I</name>
              <description>U2_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA2</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN3</name>
          <description>Pin assign register 3. Assign movable function U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK.</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>U2_RTS_O</name>
              <description>U2_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>U2_CTS_I</name>
              <description>U2_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>U2_SCLK_IO</name>
              <description>U2_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SPI0_SCK_IO</name>
              <description>SPI0_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA3</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN4</name>
          <description>Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1.</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>SPI0_MOSI_IO</name>
              <description>SPI0_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SPI0_MISO_IO</name>
              <description>SPI0_MISIO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SPI0_SSEL0_IO</name>
              <description>SPI0_SSEL0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SPI0_SSEL1_IO</name>
              <description>SPI0_SSEL1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA4</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN5</name>
          <description>Pin assign register 5. Assign movable functions SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>SPI0_SSEL2_IO</name>
              <description>SPI0_SSEL2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SPI0_SSEL3_IO</name>
              <description>SPI0_SSEL3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SPI1_SCK_IO</name>
              <description>SPI1_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SPI1_MOSI_IO</name>
              <description>SPI1_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA5</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN6</name>
          <description>Pin assign register 6. Assign movable functions SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0.</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>SPI1_MISO_IO</name>
              <description>SPI1_MISO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SPI1_SSEL0_IO</name>
              <description>SPI1_SSEL0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SPI1_SSEL1_IO</name>
              <description>SPI1_SSEL1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCT0_GPIO_IN_A_I</name>
              <description>SCT0_GPIO_IN_A function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA6</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN7</name>
          <description>Pin assign register 7. Assign movable functions SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0.</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x1C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>SCT0_GPIO_IN_B_I</name>
              <description>SCT0_GPIO_IN_B function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCT0_GPIO_IN_C_I</name>
              <description>SCT0_GPIO_IN_C function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCT0_GPIO_IN_D_I</name>
              <description>SCT0_GPIO_IN_D function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCT_OUT0_O</name>
              <description>SCT_OUT0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA7</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x1C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN8</name>
          <description>Pin assign register 8. Assign movable functions SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4.</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>SCT_OUT1_O</name>
              <description>SCT_OUT1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCT_OUT2_O</name>
              <description>SCT_OUT2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCT_OUT3_O</name>
              <description>SCT_OUT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCT_OUT4_O</name>
              <description>SCT_OUT4 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA8</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN9</name>
          <description>Pin assign register 9. Assign movable functions SCT_OUT5, SCT_OUT6, I2C1_SDA, I2C1_SCL.</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>SCT_OUT5_O</name>
              <description>SCT_OUT5 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCT_OUT6_O</name>
              <description>SCT_OUT6 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>I2C1_SDA_IO</name>
              <description>I2C1_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>I2C1_SCL_IO</name>
              <description>I2C1_SCL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA9</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN10</name>
          <description>Pin assign register 10. Assign movable functions I2C2_SDA, I2C2_SCL, I2C3_SDA, I2C3_SCL.</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>I2C2_SDA_IO</name>
              <description>I2C1_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>I2C2_SCL_IO</name>
              <description>I2C1_SCL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>I2C3_SDA_IO</name>
              <description>I2C3_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>I2C3_SCL_IO</name>
              <description>I2C3_SCL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA10</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN11</name>
          <description>Pin assign register 11. Assign movable functions COMP0_OUT, CLKOUT, GPIOINT_BMATCH, UART3_TXD</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>COMP0_OUT_O</name>
              <description>COMP0_OUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLKOUT_O</name>
              <description>CLKOUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_INT_BMAT_O</name>
              <description>GPIO_INT_BMAT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UART3_TXD</name>
              <description>UART3_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA11</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN12</name>
          <description>Pin assign register 12. Assign movable functions UART3_RXD, UART3_SCLK, UART4_TXD, UART4_RXD.</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x30</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>UART3_RXD</name>
              <description>UART3_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UART3_SCLK</name>
              <description>UART3_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UART4_TXD</name>
              <description>UART4_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UART4_RXD</name>
              <description>UART4_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA12</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x30</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN13</name>
          <description>Pin assign register 13. Assign movable functions UART4_SCLK, T0_MAT0, T0_MAT1, T0_MAT2.</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x34</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>UART4_SCLK</name>
              <description>UART4_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>T0_MAT0</name>
              <description>T0_MAT0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>T0_MAT1</name>
              <description>T0_MAT1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>T0_MAT2</name>
              <description>T0_MAT2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA13</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x34</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN14</name>
          <description>Pin assign register 14. Assign movable functions T0_MAT3, T0_CAP0, T0_CAP1, T0_CAP2.</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x38</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>T0_MAT3</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>T0_CAP0</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>T0_CAP1</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>T0_CAP2</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINASSIGN_DATA14</name>
          <description>Pin assign register</description>
          <alternateGroup>SWM0</alternateGroup>
          <addressOffset>0x38</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA0</name>
              <description>T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA1</name>
              <description>T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA2</name>
              <description>T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA3</name>
              <description>T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PINENABLE0</name>
          <description>Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP and so on.</description>
          <addressOffset>0x1C0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFD9F</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>ACMP_I1</name>
              <description>ACMP_I1 function select.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ACMP_I1 enabled on pin PIO0_00.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ACMP_I1 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ACMP_I2</name>
              <description>ACMP_I2 function select.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ACMP_I2 enabled on pin PIO0_1.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ACMP_I2 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ACMP_I3</name>
              <description>ACMP_I3 function select.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ACMP_I3 enabled on pin PIO0_14.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ACMP_I3 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ACMP_I4</name>
              <description>ACMP_I4 function select.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ACMP_I4 enabled on pin PIO0_23.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ACMP_I4 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ACMP_I5</name>
              <description>ACMP_I5 function select.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ACMP_I5 enabled on pin PIO0_30.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ACMP_I5 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SWCLK</name>
              <description>SWCLK function select.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>SWCLK enabled on pin PIO0_3.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>SWCLK disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SWDIO</name>
              <description>SWDIO function select.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>SWDIO enabled on pin PIO0_2.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>SWDIO disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>XTALIN</name>
              <description>XTALIN function select.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>XTALIN enabled on pin PIO0_8.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>XTALIN disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>XTALOUT</name>
              <description>XTALOUT function select.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>XTALOUT enabled on pin PIO0_9.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>XTALOUT disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RESETN</name>
              <description>RESETN function select.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>RESETN enabled on pin PIO0_5.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>RESETN disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLKIN</name>
              <description>CLKIN function select.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>CLKIN enabled on pin PIO0_1.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>CLKIN disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>VDDCMP</name>
              <description>VDDCMP function select.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>VDDCMP enabled on pin PIO0_6.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>VDDCMP disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>I2C0_SDA</name>
              <description>I2C0_SDA function select.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>I2C0_SDA enabled on pin PIO0_11.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>I2C0_SDA disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>I2C0_SCL</name>
              <description>I2C0_SCL function select.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>I2C0_SCL enabled on pin PIO0_10.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>I2C0_SCL disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_0</name>
              <description>ADC_0 function select.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ADC_0 enabled on pin PIO0_7.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ADC_0 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_1</name>
              <description>ADC_1 function select.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ADC_1 enabled on pin PIO0_6.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ADC_1 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_2</name>
              <description>ADC_2 function select.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ADC_2 enabled on pin PIO0_14.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ADC_2 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_3</name>
              <description>ADC_3 function select.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ADC_3 enabled on pin PIO0_23.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ADC_3 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_4</name>
              <description>ADC_4 function select.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ADC_4 enabled on pin PIO0_22.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ADC_4 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_5</name>
              <description>ADC_5 function select.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ADC_5 enabled on pin PIO0_21.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ADC_5 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_6</name>
              <description>ADC_6 function select.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ADC_6 enabled on pin PIO0_20.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ADC_6 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_7</name>
              <description>ADC_7 function select.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ADC_7 enabled on pin PIO0_19.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ADC_7 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_8</name>
              <description>ADC_8 function select.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ADC_8 enabled on pin PIO0_18.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ADC_8 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_9</name>
              <description>ADC_9 function select.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ADC_9 enabled on pin PIO0_17.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ADC_9 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_10</name>
              <description>ADC_10 function select.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ADC_10 enabled on pin PIO0_13.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ADC_10 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_11</name>
              <description>ADC_11 function select.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>ADC_11 enabled on pin PIO0_4.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>ADC_11 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DACOUT0</name>
              <description>DACOUT0 function select.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>DACOUT0 enabled on pin PIO0_17.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>DACOUT0 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DACOUT1</name>
              <description>DACOUT1 function select.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>DACOUT1 enabled on pin PIO0_29.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>DACOUT1 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CAPT_X0</name>
              <description>CAPT_X0 function select.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>CAPT_X0 enabled on pin PIO0_31.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>CAPT_X0 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CAPT_X1</name>
              <description>CAPT_X1 function select.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>CAPT_X1 enabled on pin PIO1_0.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>CAPT_X1 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CAPT_X2</name>
              <description>CAPT_X2 function select.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>CAPT_X2 enabled on pin PIO1_1.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>CAPT_X2 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CAPT_X3</name>
              <description>CAPT_X3 function select.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>CAPT_X3 enabled on pin PIO1_2.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>CAPT_X3 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PINENABLE1</name>
          <description>Pin enable register 1. Enables fixed-pin functions CAPT_X4, CAPT_X5, CAPT_X6, CAPT_X7, CAPT_X8, CAPT_X4, CAPT_YL and CAPT_YH.</description>
          <addressOffset>0x1C4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1F</resetValue>
          <resetMask>0x7F</resetMask>
          <fields>
            <field>
              <name>CAPT_X4</name>
              <description>CAPT_X4 function select.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>CAPT_X4 enabled on pin PIO1_3.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>CAPT_X4 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CAPT_X5</name>
              <description>CAPT_X5 function select.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>CAPT_X5 enabled on pin PIO1_4.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>CAPT_X5 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CAPT_X6</name>
              <description>CAPT_X6 function select.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>CAPT_X6 enabled on pin PIO1_5.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>CAPT_X6 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CAPT_X7</name>
              <description>CAPT_X7 function select.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>CAPT_X7 enabled on pin PIO1_6.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>CAPT_X7 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CAPT_X8</name>
              <description>CAPT_X8 function select.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>CAPT_X8 enabled on pin PIO1_7.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>CAPT_X8 disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CAPT_YL</name>
              <description>CAPT_YL function select.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>CAPT_YL enabled on pin PIO1_8.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>CAPT_YL disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CAPT_YH</name>
              <description>CAPT_YH function select.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>CAPT_YH enabled on pin PIO1_9.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>CAPT_YH disabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>DAC0</name>
      <description>LPC84x 10-bit DAC controller (DAC)</description>
      <groupName>DAC</groupName>
      <baseAddress>0x40014000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0xC</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>DAC0</name>
        <value>2</value>
      </interrupt>
      <registers>
        <register>
          <name>CR</name>
          <description>D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit.</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFC0</resetMask>
          <fields>
            <field>
              <name>VALUE</name>
              <description>After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE (VREFP - VREFN)/1024 + VREFN.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BIAS</name>
              <description>The settling time of the DAC</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL</name>
          <description>DAC Control register. This register controls DMA and timer operation.</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INT_DMA_REQ</name>
              <description>DMA request</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>This bit is cleared on any write to the DACR register.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>This bit is set by hardware when the timer times out.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DBLBUF_ENA</name>
              <description>dacr double buffer</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>DACR double-buffering is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CNT_ENA</name>
              <description>time-out counter operation</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Time-out counter operation is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Time-out counter operation is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DMA_ENA</name>
              <description>DMA access</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>DMA access is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>DMA Burst Request Input 7 is enabled for the DAC</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>CNTVAL</name>
          <description>DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer.</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>VALUE</name>
              <description>16-bit reload value for the DAC interrupt/DMA timer.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>DAC1</name>
      <description>LPC84x 10-bit DAC controller (DAC)</description>
      <groupName>DAC</groupName>
      <baseAddress>0x40018000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0xC</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>PIN_INT5_DAC1</name>
        <value>29</value>
      </interrupt>
      <registers>
        <register>
          <name>CR</name>
          <description>D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit.</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFC0</resetMask>
          <fields>
            <field>
              <name>VALUE</name>
              <description>After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE (VREFP - VREFN)/1024 + VREFN.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BIAS</name>
              <description>The settling time of the DAC</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL</name>
          <description>DAC Control register. This register controls DMA and timer operation.</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INT_DMA_REQ</name>
              <description>DMA request</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>This bit is cleared on any write to the DACR register.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>This bit is set by hardware when the timer times out.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DBLBUF_ENA</name>
              <description>dacr double buffer</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>DACR double-buffering is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CNT_ENA</name>
              <description>time-out counter operation</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Time-out counter operation is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Time-out counter operation is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DMA_ENA</name>
              <description>DMA access</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>DMA access is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>DMA Burst Request Input 7 is enabled for the DAC</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>CNTVAL</name>
          <description>DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer.</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>VALUE</name>
              <description>16-bit reload value for the DAC interrupt/DMA timer.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>ADC0</name>
      <description>LPC84x 12-bit ADC controller (ADC)</description>
      <baseAddress>0x4001C000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x70</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>ADC0_SEQA</name>
        <value>16</value>
      </interrupt>
      <interrupt>
        <name>ADC0_SEQB</name>
        <value>17</value>
      </interrupt>
      <interrupt>
        <name>ADC0_THCMP</name>
        <value>18</value>
      </interrupt>
      <interrupt>
        <name>ADC0_OVR</name>
        <value>19</value>
      </interrupt>
      <registers>
        <register>
          <name>CTRL</name>
          <description>ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls.</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x400005FF</resetMask>
          <fields>
            <field>
              <name>CLKDIV</name>
              <description>In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ASYNMODE</name>
              <description>Select clock mode.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger pulse.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>LPWRMODE</name>
              <description>The low-power ADC mode</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the ADC_ENA bit is low.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CALMODE</name>
              <description>Writing a &apos;1&apos; to this bit will initiate a sef-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted unitl the full calibration cycle has ended.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SEQ_CTRLA</name>
          <description>ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFFF</resetMask>
          <fields>
            <field>
              <name>CHANNELS</name>
              <description>Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRIGGER</name>
              <description>Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRIGPOL</name>
              <description>Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Negative edge. A negative edge launches the conversion sequence on the selected trigger input.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Positive edge. A positive edge launches the conversion sequence on the selected trigger input.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SYNCBYPASS</name>
              <description>Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enable trigger synchronization. The hardware trigger bypass is not enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Bypass trigger synchronization. The hardware trigger bypass is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>START</name>
              <description>Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BURST</name>
              <description>Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SINGLESTEP</name>
              <description>When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LOWPRIO</name>
              <description>Set priority for sequence A.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it&apos;s place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MODE</name>
              <description>Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SEQ_ENA</name>
              <description>Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. Sequence n is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SEQ_CTRLB</name>
          <description>ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFFF</resetMask>
          <fields>
            <field>
              <name>CHANNELS</name>
              <description>Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRIGGER</name>
              <description>Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRIGPOL</name>
              <description>Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Negative edge. A negative edge launches the conversion sequence on the selected trigger input.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Positive edge. A positive edge launches the conversion sequence on the selected trigger input.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SYNCBYPASS</name>
              <description>Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enable trigger synchronization. The hardware trigger bypass is not enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Bypass trigger synchronization. The hardware trigger bypass is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>START</name>
              <description>Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BURST</name>
              <description>Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SINGLESTEP</name>
              <description>When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LOWPRIO</name>
              <description>Set priority for sequence A.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it&apos;s place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MODE</name>
              <description>Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SEQ_ENA</name>
              <description>Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. Sequence n is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SEQ_GDATA</name>
          <description>ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n.</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFF0</resetMask>
          <fields>
            <field>
              <name>RESULT</name>
              <description>This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPRANGE</name>
              <description>Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPCROSS</name>
              <description>Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHN</name>
              <description>These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.).</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN</name>
              <description>This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to &apos;0&apos; (and if the overrun interrupt is enabled).</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATAVALID</name>
              <description>This bit is set to &apos;1&apos; at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled).</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SEQ_GDATB</name>
          <description>ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n.</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFF0</resetMask>
          <fields>
            <field>
              <name>RESULT</name>
              <description>This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPRANGE</name>
              <description>Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPCROSS</name>
              <description>Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHN</name>
              <description>These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.).</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN</name>
              <description>This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to &apos;0&apos; (and if the overrun interrupt is enabled).</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATAVALID</name>
              <description>This bit is set to &apos;1&apos; at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled).</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DAT0</name>
          <description>ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFF0</resetMask>
          <fields>
            <field>
              <name>RESULT</name>
              <description>This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPRANGE</name>
              <description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPCROSS</name>
              <description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHANNEL</name>
              <description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN</name>
              <description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATAVALID</name>
              <description>This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DAT1</name>
          <description>ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFF0</resetMask>
          <fields>
            <field>
              <name>RESULT</name>
              <description>This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPRANGE</name>
              <description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPCROSS</name>
              <description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHANNEL</name>
              <description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN</name>
              <description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATAVALID</name>
              <description>This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DAT2</name>
          <description>ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFF0</resetMask>
          <fields>
            <field>
              <name>RESULT</name>
              <description>This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPRANGE</name>
              <description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPCROSS</name>
              <description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHANNEL</name>
              <description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN</name>
              <description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATAVALID</name>
              <description>This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DAT3</name>
          <description>ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFF0</resetMask>
          <fields>
            <field>
              <name>RESULT</name>
              <description>This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPRANGE</name>
              <description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPCROSS</name>
              <description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHANNEL</name>
              <description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN</name>
              <description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATAVALID</name>
              <description>This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DAT4</name>
          <description>ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.</description>
          <addressOffset>0x30</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFF0</resetMask>
          <fields>
            <field>
              <name>RESULT</name>
              <description>This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPRANGE</name>
              <description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPCROSS</name>
              <description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHANNEL</name>
              <description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN</name>
              <description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATAVALID</name>
              <description>This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DAT5</name>
          <description>ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.</description>
          <addressOffset>0x34</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFF0</resetMask>
          <fields>
            <field>
              <name>RESULT</name>
              <description>This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPRANGE</name>
              <description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPCROSS</name>
              <description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHANNEL</name>
              <description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN</name>
              <description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATAVALID</name>
              <description>This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DAT6</name>
          <description>ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.</description>
          <addressOffset>0x38</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFF0</resetMask>
          <fields>
            <field>
              <name>RESULT</name>
              <description>This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPRANGE</name>
              <description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPCROSS</name>
              <description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHANNEL</name>
              <description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN</name>
              <description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATAVALID</name>
              <description>This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DAT7</name>
          <description>ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.</description>
          <addressOffset>0x3C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFF0</resetMask>
          <fields>
            <field>
              <name>RESULT</name>
              <description>This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPRANGE</name>
              <description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPCROSS</name>
              <description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHANNEL</name>
              <description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN</name>
              <description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATAVALID</name>
              <description>This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DAT8</name>
          <description>ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.</description>
          <addressOffset>0x40</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFF0</resetMask>
          <fields>
            <field>
              <name>RESULT</name>
              <description>This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPRANGE</name>
              <description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPCROSS</name>
              <description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHANNEL</name>
              <description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN</name>
              <description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATAVALID</name>
              <description>This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DAT9</name>
          <description>ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.</description>
          <addressOffset>0x44</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFF0</resetMask>
          <fields>
            <field>
              <name>RESULT</name>
              <description>This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPRANGE</name>
              <description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPCROSS</name>
              <description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHANNEL</name>
              <description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN</name>
              <description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATAVALID</name>
              <description>This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DAT10</name>
          <description>ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.</description>
          <addressOffset>0x48</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFF0</resetMask>
          <fields>
            <field>
              <name>RESULT</name>
              <description>This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPRANGE</name>
              <description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPCROSS</name>
              <description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHANNEL</name>
              <description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN</name>
              <description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATAVALID</name>
              <description>This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DAT11</name>
          <description>ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.</description>
          <addressOffset>0x4C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFC0FFFF0</resetMask>
          <fields>
            <field>
              <name>RESULT</name>
              <description>This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPRANGE</name>
              <description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMPCROSS</name>
              <description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CHANNEL</name>
              <description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN</name>
              <description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATAVALID</name>
              <description>This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>THR0_LOW</name>
          <description>ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0.</description>
          <addressOffset>0x50</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFF0</resetMask>
          <fields>
            <field>
              <name>THRLOW</name>
              <description>Low threshold value against which ADC results will be compared</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>THR1_LOW</name>
          <description>ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1.</description>
          <addressOffset>0x54</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFF0</resetMask>
          <fields>
            <field>
              <name>THRLOW</name>
              <description>Low threshold value against which ADC results will be compared</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>THR0_HIGH</name>
          <description>ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0.</description>
          <addressOffset>0x58</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFF0</resetMask>
          <fields>
            <field>
              <name>THRHIGH</name>
              <description>High threshold value against which ADC results will be compared</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>THR1_HIGH</name>
          <description>ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1.</description>
          <addressOffset>0x5C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFF0</resetMask>
          <fields>
            <field>
              <name>THRHIGH</name>
              <description>High threshold value against which ADC results will be compared</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CHAN_THRSEL</name>
          <description>ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel</description>
          <addressOffset>0x60</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFF</resetMask>
          <fields>
            <field>
              <name>CH0_THRSEL</name>
              <description>Threshold select for channel 0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CH1_THRSEL</name>
              <description>Threshold select for channel 1. See description for channel 0.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CH2_THRSEL</name>
              <description>Threshold select for channel 2. See description for channel 0.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CH3_THRSEL</name>
              <description>Threshold select for channel 3. See description for channel 0.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CH4_THRSEL</name>
              <description>Threshold select for channel 4. See description for channel 0.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CH5_THRSEL</name>
              <description>Threshold select for channel 5. See description for channel 0.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CH6_THRSEL</name>
              <description>Threshold select for channel 6. See description for channel 0.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CH7_THRSEL</name>
              <description>Threshold select for channel 7. See description for channel 0.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CH8_THRSEL</name>
              <description>Threshold select for channel 8. See description for channel 0.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CH9_THRSEL</name>
              <description>Threshold select for channel 9. See description for channel 0.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CH10_THRSEL</name>
              <description>Threshold select for channel 10. See description for channel 0.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CH11_THRSEL</name>
              <description>Threshold select for channel 11. See description for channel 0.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTEN</name>
          <description>ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.</description>
          <addressOffset>0x64</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x7FFFFFF</resetMask>
          <fields>
            <field>
              <name>SEQA_INTEN</name>
              <description>Sequence A interrupt enable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The sequence A interrupt/DMA trigger is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SEQB_INTEN</name>
              <description>Sequence B interrupt enable.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The sequence B interrupt/DMA trigger is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OVR_INTEN</name>
              <description>Overrun interrupt enable.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The overrun interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADCMPINTEN0</name>
              <description>Threshold comparison interrupt enable for channel 0.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Disabled.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Outside threshold.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Crossing threshold.</description>
                  <value>#10</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADCMPINTEN1</name>
              <description>Channel 1 threshold comparison interrupt enable. See description for channel 0.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADCMPINTEN2</name>
              <description>Channel 2 threshold comparison interrupt enable. See description for channel 0.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADCMPINTEN3</name>
              <description>Channel 3 threshold comparison interrupt enable. See description for channel 0.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADCMPINTEN4</name>
              <description>Channel 4 threshold comparison interrupt enable. See description for channel 0.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADCMPINTEN5</name>
              <description>Channel 5 threshold comparison interrupt enable. See description for channel 0.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADCMPINTEN6</name>
              <description>Channel 6 threshold comparison interrupt enable. See description for channel 0.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADCMPINTEN7</name>
              <description>Channel 7 threshold comparison interrupt enable. See description for channel 0.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADCMPINTEN8</name>
              <description>Channel 8 threshold comparison interrupt enable. See description for channel 0.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADCMPINTEN9</name>
              <description>Channel 9 threshold comparison interrupt enable. See description for channel 0.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADCMPINTEN10</name>
              <description>Channel 10 threshold comparison interrupt enable. See description for channel 0.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADCMPINTEN11</name>
              <description>Channel 21 threshold comparison interrupt enable. See description for channel 0.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLAGS</name>
          <description>ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers).</description>
          <addressOffset>0x68</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF3FFFFFF</resetMask>
          <fields>
            <field>
              <name>THCMP0</name>
              <description>Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THCMP1</name>
              <description>Threshold comparison event on Channel 1. See description for channel 0.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THCMP2</name>
              <description>Threshold comparison event on Channel 2. See description for channel 0.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THCMP3</name>
              <description>Threshold comparison event on Channel 3. See description for channel 0.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THCMP4</name>
              <description>Threshold comparison event on Channel 4. See description for channel 0.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THCMP5</name>
              <description>Threshold comparison event on Channel 5. See description for channel 0.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THCMP6</name>
              <description>Threshold comparison event on Channel 6. See description for channel 0.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THCMP7</name>
              <description>Threshold comparison event on Channel 7. See description for channel 0.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THCMP8</name>
              <description>Threshold comparison event on Channel 8. See description for channel 0.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THCMP9</name>
              <description>Threshold comparison event on Channel 9. See description for channel 0.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THCMP10</name>
              <description>Threshold comparison event on Channel 10. See description for channel 0.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THCMP11</name>
              <description>Threshold comparison event on Channel 11. See description for channel 0.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OVERRUN0</name>
              <description>Mirrors the OVERRRUN status flag from the result register for ADC channel 0</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN1</name>
              <description>Mirrors the OVERRRUN status flag from the result register for ADC channel 1</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN2</name>
              <description>Mirrors the OVERRRUN status flag from the result register for ADC channel 2</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN3</name>
              <description>Mirrors the OVERRRUN status flag from the result register for ADC channel 3</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN4</name>
              <description>Mirrors the OVERRRUN status flag from the result register for ADC channel 4</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN5</name>
              <description>Mirrors the OVERRRUN status flag from the result register for ADC channel 5</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN6</name>
              <description>Mirrors the OVERRRUN status flag from the result register for ADC channel 6</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN7</name>
              <description>Mirrors the OVERRRUN status flag from the result register for ADC channel 7</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN8</name>
              <description>Mirrors the OVERRRUN status flag from the result register for ADC channel 8</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN9</name>
              <description>Mirrors the OVERRRUN status flag from the result register for ADC channel 9</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN10</name>
              <description>Mirrors the OVERRRUN status flag from the result register for ADC channel 10</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVERRUN11</name>
              <description>Mirrors the OVERRRUN status flag from the result register for ADC channel 11</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SEQA_OVR</name>
              <description>Mirrors the global OVERRUN status flag in the SEQA_GDAT register</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SEQB_OVR</name>
              <description>Mirrors the global OVERRUN status flag in the SEQB_GDAT register</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SEQA_INT</name>
              <description>Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SEQB_INT</name>
              <description>Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every ADC conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THCMP_INT</name>
              <description>Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the individual threshold flags are cleared via writing 1s to those bits.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVR_INT</name>
              <description>Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TRM</name>
          <description>ADC Startup register.</description>
          <addressOffset>0x6C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x20</resetMask>
          <fields>
            <field>
              <name>VRANGE</name>
              <description>1.8V to 3.6V Vdd range: This bit MUST be set to &apos;1&apos; if operation below 2.7V is to be used. Failure to set this bit will result in invalid ADC results. Note: This bit will not be spec&apos;d on parts that do not support operation below 2.7V</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>PMU</name>
      <description>LPC84x PMU</description>
      <baseAddress>0x40020000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x18</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>PCON</name>
          <description>Power control register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x90F</resetMask>
          <fields>
            <field>
              <name>PM</name>
              <description>Power mode</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Default. The part is in active or sleep mode.</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Deep-sleep mode. ARM WFI will enter Deep-sleep mode.</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Power-down mode. ARM WFI will enter Power-down mode.</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Deep power-down mode. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down).</description>
                  <value>#011</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>NODPD</name>
              <description>A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLEEPFLAG</name>
              <description>Sleep mode flag</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Low power mode. Read: Sleep, Deep-sleep or Power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DPDFLAG</name>
              <description>Deep power-down flag</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>GPREG0</name>
          <description>General purpose register N</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>GPDATA</name>
              <description>Data retained during Deep power-down mode.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>GPREG1</name>
          <description>General purpose register N</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>GPDATA</name>
              <description>Data retained during Deep power-down mode.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>GPREG2</name>
          <description>General purpose register N</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>GPDATA</name>
              <description>Data retained during Deep power-down mode.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>GPREG3</name>
          <description>General purpose register N</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>GPDATA</name>
              <description>Data retained during Deep power-down mode.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DPDCTRL</name>
          <description>Deep power-down control register. Also includes bits for general purpose storage.</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>WAKEUPHYS</name>
              <description>WAKEUP pin hysteresis enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. Hysteresis for WAKEUP pin disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. Hysteresis for WAKEUP pin enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>WAKEPAD_DISABLE</name>
              <description>WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Remark: Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer is enabled and configured. Remark: Setting this bit is not necessary if Deep power-down mode is not used.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. The wake-up function is enabled on pin PIO0_4.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Disabled. Setting this bit disables the wake-up function on pin PIO0_4.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>LPOSCEN</name>
              <description>Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable the low-power oscillator if the self wake-up timer is clocked by the divided IRC or the external clock input.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>LPOSCDPDEN</name>
              <description>causes the low-power oscillator to remain running during Deep power-down mode provided that bit 2 in this register is set as well. You must set this bit for the self wake-up timer to be able to wake up the part from Deep power-down mode. Remark: Do not set this bit unless you use the self wake-up timer with the low-power oscillator clock source to wake up from Deep power-down mode.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>WAKEUPCLKHYS</name>
              <description>External clock input for the self wake-up timer WKTCLKIN hysteresis enable.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. Hysteresis for WAKEUP clock pin disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. Hysteresis for WAKEUP clock pin enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>WAKECLKPAD_DISABLE</name>
              <description>Disable the external clock input for the self-wake-up timer. Setting this bit enables the self-wake-up timer clock pin WKTCLKLIN. To minimize power consumption, especially in deep power-down mode, disable this clock input when not using the external clock option for the self-wake-up timer.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. Setting this bit disables external clock input on pin PIO0_28.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The external clock input for the self wake-up timer is enabled on pin PIO0_28.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RESETHYS</name>
              <description>RESET pin hysteresis enable.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. Hysteresis for RESET pin disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. Hysteresis for RESET pin enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RESET_DISABLE</name>
              <description>RESET pin disable. Setting this bit disables the reset wake-up function, so the pin can be used for other purposes. Remark: Setting this bit is not necessary if deep power-down mode is not used.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. The reset wake-up function is enabled on pin PIO0_5.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Disabled. Setting this bit disables the wake-up function on pin PIO0_5.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>GPDATA</name>
              <description>Data retained during Deep power-down mode.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>24</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>ACOMP</name>
      <description>LPC84x analog comparator</description>
      <baseAddress>0x40024000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x8</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>CMP_CAPT</name>
        <value>11</value>
      </interrupt>
      <registers>
        <register>
          <name>CTRL</name>
          <description>Comparator control register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x6C03F58</resetMask>
          <fields>
            <field>
              <name>EDGESEL</name>
              <description>This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Falling edges</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Rising edges</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Both edges</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Both edges</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>COMPSA</name>
              <description>Comparator output control</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Comparator output is used directly.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Comparator output is synchronized to the bus clock for output to other modules.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>COMP_VP_SEL</name>
              <description>Selects positive voltage input</description>
              <bitOffset>8</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>VOLTAGE_LADDER_OUTPUT</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>ACMP_I1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>ACMP_I2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>ACMP_I3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>ACMP_I4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>ACMP_I5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>Band gap. Internal reference voltage.</description>
                  <value>#110</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>111</name>
                  <description>DAC0 output</description>
                  <value>#111</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>COMP_VM_SEL</name>
              <description>Selects negative voltage input</description>
              <bitOffset>11</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>VOLTAGE_LADDER_OUTPUT</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>ACMP_I1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>ACMP_I2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>ACMP_I3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>ACMP_I4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>ACMP_I5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>Band gap. Internal reference voltage.</description>
                  <value>#110</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>111</name>
                  <description>DAC0 output</description>
                  <value>#111</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EDGECLR</name>
              <description>Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COMPSTAT</name>
              <description>Comparator status. This bit reflects the state of the comparator output.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COMPEDGE</name>
              <description>Comparator edge-detect status.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INTENA</name>
              <description>Must be set to generate interrupts.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HYS</name>
              <description>Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>None (the output will switch as the voltages cross)</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>5 mv</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>10 mv</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>20 mv</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>LAD</name>
          <description>Voltage ladder register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>LADEN</name>
              <description>Voltage ladder enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LADSEL</name>
              <description>Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref</description>
              <bitOffset>1</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LADREF</name>
              <description>Selects the reference voltage Vref for the voltage ladder.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Supply pin VDD</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>VDDCMP pin</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>INPUTMUX</name>
      <description>LPC84x Input multiplexing (INPUT MUX)</description>
      <baseAddress>0x4002C000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0xA4</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>DMA_INMUX_INMUX0</name>
          <description>DMA output trigger selection to become DMA trigger</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1F</resetValue>
          <resetMask>0x1F</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>DMA trigger output number (decimal value) for DMA channel n (n = 0 to 24).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_INMUX_INMUX1</name>
          <description>DMA output trigger selection to become DMA trigger</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1F</resetValue>
          <resetMask>0x1F</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>DMA trigger output number (decimal value) for DMA channel n (n = 0 to 24).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SCT_INMUX0</name>
          <description>input select register for SCT</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP_N</name>
              <description>Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct input 2 3= sct gpio input 3 4= adc_thcmp_irq 5 = comparator out 6 = timer ct32b0 match2 7=gpio_int_bmatch 8=arm_txev 9=debug_halted</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SCT_INMUX1</name>
          <description>input select register for SCT</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP_N</name>
              <description>Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct input 2 3= sct gpio input 3 4= adc_thcmp_irq 5 = comparator out 6 = timer ct32b0 match2 7=gpio_int_bmatch 8=arm_txev 9=debug_halted</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SCT_INMUX2</name>
          <description>input select register for SCT</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP_N</name>
              <description>Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct input 2 3= sct gpio input 3 4= adc_thcmp_irq 5 = comparator out 6 = timer ct32b0 match2 7=gpio_int_bmatch 8=arm_txev 9=debug_halted</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SCT_INMUX3</name>
          <description>input select register for SCT</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP_N</name>
              <description>Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct input 2 3= sct gpio input 3 4= adc_thcmp_irq 5 = comparator out 6 = timer ct32b0 match2 7=gpio_int_bmatch 8=arm_txev 9=debug_halted</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX0</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x40</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX1</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x44</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX2</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x48</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX3</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x4C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX4</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x50</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX5</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x54</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX6</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x58</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX7</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x5C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX8</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x60</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX9</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x64</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX10</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x68</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX11</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x6C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX12</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x70</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX13</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x74</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX14</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x78</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX15</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x7C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX16</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x80</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX17</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x84</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX18</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x88</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX19</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x8C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX20</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x90</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX21</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x94</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX22</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x98</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX23</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x9C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_ITRIG_INMUX24</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0xA0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>I2C2</name>
      <description>LPC84x I2C-bus interfaces</description>
      <groupName>I2C</groupName>
      <baseAddress>0x40030000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x84</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>I2C2</name>
        <value>21</value>
      </interrupt>
      <registers>
        <register>
          <name>CFG</name>
          <description>Configuration for shared functions.</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3F</resetMask>
          <fields>
            <field>
              <name>MSTEN</name>
              <description>Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The I2C Master function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The I2C Master function is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVEN</name>
              <description>Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The I2C slave function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The I2C slave function is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONEN</name>
              <description>Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The I2C Monitor function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The I2C Monitor function is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TIMEOUTEN</name>
              <description>I2C bus Time-out Enable. When disabled, the time-out function is internally reset.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. Time-out function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONCLKSTR</name>
              <description>Monitor function Clock Stretching.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT</name>
          <description>Status register for Master, Slave, and Monitor functions.</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x801</resetValue>
          <resetMask>0x30FFF5F</resetMask>
          <fields>
            <field>
              <name>MSTPENDING</name>
              <description>Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTATE</name>
              <description>Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>Idle. The Master function is available to be used for a new transaction.</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>NACK Address. Slave NACKed address.</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>NACK Data. Slave NACKed transmitted data.</description>
                  <value>#100</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTARBLOSS</name>
              <description>Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No Arbitration Loss has occurred.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTSTPERR</name>
              <description>Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No Start/Stop Error has occurred.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVPENDING</name>
              <description>Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>In progress. The Slave function does not currently need service.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVSTATE</name>
              <description>Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Slave receive. Received data is available (Slave Receiver mode).</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Slave transmit. Data can be transmitted (Slave Transmitter mode).</description>
                  <value>#10</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNOTSTR</name>
              <description>Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVIDX</name>
              <description>Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Address 0. Slave address 0 was matched.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Address 1. Slave address 1 was matched.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Address 2. Slave address 2 was matched.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Address 3. Slave address 3 was matched.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVSEL</name>
              <description>Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Not selected. The Slave function is not currently selected.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Selected. The Slave function is currently selected.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDESEL</name>
              <description>Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRDY</name>
              <description>Monitor Ready. This flag is cleared when the MONRXDAT register is read.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No data. The Monitor function does not currently have data available.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Data waiting. The Monitor function has data waiting to be read.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONOV</name>
              <description>Monitor Overflow flag.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No overrun. Monitor data has not overrun.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONACTIVE</name>
              <description>Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Inactive. The Monitor function considers the I2C bus to be inactive.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Active. The Monitor function considers the I2C bus to be active.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONIDLE</name>
              <description>Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Not idle. The I2C bus is not idle, or this flag has been cleared by software.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EVENTTIMEOUT</name>
              <description>Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No time-out. I2C bus events have not caused a time-out.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SCLTIMEOUT</name>
              <description>SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No time-out. SCL low time has not caused a time-out.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Time-out. SCL low time has caused a time-out.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENSET</name>
          <description>Interrupt Enable Set and read register.</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x30B8951</resetMask>
          <fields>
            <field>
              <name>MSTPENDINGEN</name>
              <description>Master Pending interrupt Enable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MstPending interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MstPending interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTARBLOSSEN</name>
              <description>Master Arbitration Loss interrupt Enable.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MstArbLoss interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MstArbLoss interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTSTPERREN</name>
              <description>Master Start/Stop Error interrupt Enable.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MstStStpErr interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MstStStpErr interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVPENDINGEN</name>
              <description>Slave Pending interrupt Enable.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SlvPending interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SlvPending interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNOTSTREN</name>
              <description>Slave Not Stretching interrupt Enable.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SlvNotStr interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SlvNotStr interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDESELEN</name>
              <description>Slave Deselect interrupt Enable.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SlvDeSel interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SlvDeSel interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRDYEN</name>
              <description>Monitor data Ready interrupt Enable.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MonRdy interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MonRdy interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONOVEN</name>
              <description>Monitor Overrun interrupt Enable.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MonOv interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MonOv interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONIDLEEN</name>
              <description>Monitor Idle interrupt Enable.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MonIdle interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MonIdle interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EVENTTIMEOUTEN</name>
              <description>Event time-out interrupt Enable.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The Event time-out interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The Event time-out interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SCLTIMEOUTEN</name>
              <description>SCL time-out interrupt Enable.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SCL time-out interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SCL time-out interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENCLR</name>
          <description>Interrupt Enable Clear register.</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>MSTPENDINGCLR</name>
              <description>Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MSTARBLOSSCLR</name>
              <description>Master Arbitration Loss interrupt clear.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MSTSTSTPERRCLR</name>
              <description>Master Start/Stop Error interrupt clear.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVPENDINGCLR</name>
              <description>Slave Pending interrupt clear.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVNOTSTRCLR</name>
              <description>Slave Not Stretching interrupt clear.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVDESELCLR</name>
              <description>Slave Deselect interrupt clear.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONRDYCLR</name>
              <description>Monitor data Ready interrupt clear.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONOVCLR</name>
              <description>Monitor Overrun interrupt clear.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONIDLECLR</name>
              <description>Monitor Idle interrupt clear.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>EVENTTIMEOUTCLR</name>
              <description>Event time-out interrupt clear.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SCLTIMEOUTCLR</name>
              <description>SCL time-out interrupt clear.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMEOUT</name>
          <description>Time-out value register.</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFF</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>TOMIN</name>
              <description>Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TO</name>
              <description>Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLKDIV</name>
          <description>Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>DIVVAL</name>
              <description>This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTSTAT</name>
          <description>Interrupt Status register for Master, Slave, and Monitor functions.</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x801</resetValue>
          <resetMask>0x30FFF5F</resetMask>
          <fields>
            <field>
              <name>MSTPENDING</name>
              <description>Master Pending.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MSTARBLOSS</name>
              <description>Master Arbitration Loss flag.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MSTSTSTPERR</name>
              <description>Master Start/Stop Error flag.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVPENDING</name>
              <description>Slave Pending.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVNOTSTR</name>
              <description>Slave Not Stretching status.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVDESEL</name>
              <description>Slave Deselected flag.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONRDY</name>
              <description>Monitor Ready.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONOV</name>
              <description>Monitor Overflow flag.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONIDLE</name>
              <description>Monitor Idle flag.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>EVENTTIMEOUT</name>
              <description>Event time-out Interrupt flag.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SCLTIMEOUT</name>
              <description>SCL time-out Interrupt flag.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTCTL</name>
          <description>Master control register.</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>MSTCONTINUE</name>
              <description>Master Continue.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Informs the Master function to continue to the next operation.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTART</name>
              <description>Master Start control.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Start. A Start will be generated on the I2C bus at the next allowed time.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTOP</name>
              <description>Master Stop control.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTDMA</name>
              <description>Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable. No DMA requests are generated for master operation.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTTIME</name>
          <description>Master timing configuration.</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x77</resetValue>
          <resetMask>0x77</resetMask>
          <fields>
            <field>
              <name>MSTSCLLOW</name>
              <description>Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.</description>
                  <value>#110</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>111</name>
                  <description>9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.</description>
                  <value>#111</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSCLHIGH</name>
              <description>Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.</description>
                  <value>#110</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>111</name>
                  <description>9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.</description>
                  <value>#111</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTDAT</name>
          <description>Combined Master receiver and transmitter data register.</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVCTL</name>
          <description>Slave control register.</description>
          <addressOffset>0x40</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xB</resetMask>
          <fields>
            <field>
              <name>SLVCONTINUE</name>
              <description>Slave Continue.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Informs the Slave function to continue to the next operation.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNACK</name>
              <description>Slave NACK.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDMA</name>
              <description>Slave DMA enable.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. No DMA requests are issued for Slave mode operation.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. DMA requests are issued for I2C slave data transmission and reception.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVDAT</name>
          <description>Combined Slave receiver and transmitter data register.</description>
          <addressOffset>0x44</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR0</name>
          <description>Slave address register.</description>
          <addressOffset>0x48</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR1</name>
          <description>Slave address register.</description>
          <addressOffset>0x4C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR2</name>
          <description>Slave address register.</description>
          <addressOffset>0x50</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR3</name>
          <description>Slave address register.</description>
          <addressOffset>0x54</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVQUAL0</name>
          <description>Slave Qualification for address 0.</description>
          <addressOffset>0x58</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>QUALMODE0</name>
              <description>Qualify mode for slave address 0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVQUAL0</name>
              <description>Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] &lt;= received address &lt;= SLVQUAL0[7:1]).</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MONRXDAT</name>
          <description>Monitor receiver data register.</description>
          <addressOffset>0x80</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x7FF</resetMask>
          <fields>
            <field>
              <name>MONRXDAT</name>
              <description>Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONSTART</name>
              <description>Monitor Received Start.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No start detected. The Monitor function has not detected a Start event on the I2C bus.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Start detected. The Monitor function has detected a Start event on the I2C bus.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRESTART</name>
              <description>Monitor Received Repeated Start.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONNACK</name>
              <description>Monitor Received NACK.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>I2C3</name>
      <description>LPC84x I2C-bus interfaces</description>
      <groupName>I2C</groupName>
      <baseAddress>0x40034000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x84</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>I2C3</name>
        <value>22</value>
      </interrupt>
      <registers>
        <register>
          <name>CFG</name>
          <description>Configuration for shared functions.</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3F</resetMask>
          <fields>
            <field>
              <name>MSTEN</name>
              <description>Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The I2C Master function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The I2C Master function is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVEN</name>
              <description>Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The I2C slave function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The I2C slave function is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONEN</name>
              <description>Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The I2C Monitor function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The I2C Monitor function is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TIMEOUTEN</name>
              <description>I2C bus Time-out Enable. When disabled, the time-out function is internally reset.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. Time-out function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONCLKSTR</name>
              <description>Monitor function Clock Stretching.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT</name>
          <description>Status register for Master, Slave, and Monitor functions.</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x801</resetValue>
          <resetMask>0x30FFF5F</resetMask>
          <fields>
            <field>
              <name>MSTPENDING</name>
              <description>Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTATE</name>
              <description>Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>Idle. The Master function is available to be used for a new transaction.</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>NACK Address. Slave NACKed address.</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>NACK Data. Slave NACKed transmitted data.</description>
                  <value>#100</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTARBLOSS</name>
              <description>Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No Arbitration Loss has occurred.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTSTPERR</name>
              <description>Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No Start/Stop Error has occurred.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVPENDING</name>
              <description>Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>In progress. The Slave function does not currently need service.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVSTATE</name>
              <description>Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Slave receive. Received data is available (Slave Receiver mode).</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Slave transmit. Data can be transmitted (Slave Transmitter mode).</description>
                  <value>#10</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNOTSTR</name>
              <description>Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVIDX</name>
              <description>Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Address 0. Slave address 0 was matched.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Address 1. Slave address 1 was matched.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Address 2. Slave address 2 was matched.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Address 3. Slave address 3 was matched.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVSEL</name>
              <description>Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Not selected. The Slave function is not currently selected.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Selected. The Slave function is currently selected.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDESEL</name>
              <description>Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRDY</name>
              <description>Monitor Ready. This flag is cleared when the MONRXDAT register is read.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No data. The Monitor function does not currently have data available.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Data waiting. The Monitor function has data waiting to be read.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONOV</name>
              <description>Monitor Overflow flag.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No overrun. Monitor data has not overrun.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONACTIVE</name>
              <description>Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Inactive. The Monitor function considers the I2C bus to be inactive.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Active. The Monitor function considers the I2C bus to be active.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONIDLE</name>
              <description>Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Not idle. The I2C bus is not idle, or this flag has been cleared by software.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EVENTTIMEOUT</name>
              <description>Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No time-out. I2C bus events have not caused a time-out.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SCLTIMEOUT</name>
              <description>SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No time-out. SCL low time has not caused a time-out.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Time-out. SCL low time has caused a time-out.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENSET</name>
          <description>Interrupt Enable Set and read register.</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x30B8951</resetMask>
          <fields>
            <field>
              <name>MSTPENDINGEN</name>
              <description>Master Pending interrupt Enable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MstPending interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MstPending interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTARBLOSSEN</name>
              <description>Master Arbitration Loss interrupt Enable.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MstArbLoss interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MstArbLoss interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTSTPERREN</name>
              <description>Master Start/Stop Error interrupt Enable.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MstStStpErr interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MstStStpErr interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVPENDINGEN</name>
              <description>Slave Pending interrupt Enable.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SlvPending interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SlvPending interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNOTSTREN</name>
              <description>Slave Not Stretching interrupt Enable.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SlvNotStr interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SlvNotStr interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDESELEN</name>
              <description>Slave Deselect interrupt Enable.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SlvDeSel interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SlvDeSel interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRDYEN</name>
              <description>Monitor data Ready interrupt Enable.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MonRdy interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MonRdy interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONOVEN</name>
              <description>Monitor Overrun interrupt Enable.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MonOv interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MonOv interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONIDLEEN</name>
              <description>Monitor Idle interrupt Enable.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MonIdle interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MonIdle interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EVENTTIMEOUTEN</name>
              <description>Event time-out interrupt Enable.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The Event time-out interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The Event time-out interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SCLTIMEOUTEN</name>
              <description>SCL time-out interrupt Enable.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SCL time-out interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SCL time-out interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENCLR</name>
          <description>Interrupt Enable Clear register.</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>MSTPENDINGCLR</name>
              <description>Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MSTARBLOSSCLR</name>
              <description>Master Arbitration Loss interrupt clear.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MSTSTSTPERRCLR</name>
              <description>Master Start/Stop Error interrupt clear.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVPENDINGCLR</name>
              <description>Slave Pending interrupt clear.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVNOTSTRCLR</name>
              <description>Slave Not Stretching interrupt clear.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVDESELCLR</name>
              <description>Slave Deselect interrupt clear.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONRDYCLR</name>
              <description>Monitor data Ready interrupt clear.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONOVCLR</name>
              <description>Monitor Overrun interrupt clear.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONIDLECLR</name>
              <description>Monitor Idle interrupt clear.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>EVENTTIMEOUTCLR</name>
              <description>Event time-out interrupt clear.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SCLTIMEOUTCLR</name>
              <description>SCL time-out interrupt clear.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMEOUT</name>
          <description>Time-out value register.</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFF</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>TOMIN</name>
              <description>Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TO</name>
              <description>Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLKDIV</name>
          <description>Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>DIVVAL</name>
              <description>This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTSTAT</name>
          <description>Interrupt Status register for Master, Slave, and Monitor functions.</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x801</resetValue>
          <resetMask>0x30FFF5F</resetMask>
          <fields>
            <field>
              <name>MSTPENDING</name>
              <description>Master Pending.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MSTARBLOSS</name>
              <description>Master Arbitration Loss flag.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MSTSTSTPERR</name>
              <description>Master Start/Stop Error flag.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVPENDING</name>
              <description>Slave Pending.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVNOTSTR</name>
              <description>Slave Not Stretching status.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVDESEL</name>
              <description>Slave Deselected flag.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONRDY</name>
              <description>Monitor Ready.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONOV</name>
              <description>Monitor Overflow flag.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONIDLE</name>
              <description>Monitor Idle flag.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>EVENTTIMEOUT</name>
              <description>Event time-out Interrupt flag.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SCLTIMEOUT</name>
              <description>SCL time-out Interrupt flag.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTCTL</name>
          <description>Master control register.</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>MSTCONTINUE</name>
              <description>Master Continue.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Informs the Master function to continue to the next operation.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTART</name>
              <description>Master Start control.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Start. A Start will be generated on the I2C bus at the next allowed time.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTOP</name>
              <description>Master Stop control.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTDMA</name>
              <description>Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable. No DMA requests are generated for master operation.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTTIME</name>
          <description>Master timing configuration.</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x77</resetValue>
          <resetMask>0x77</resetMask>
          <fields>
            <field>
              <name>MSTSCLLOW</name>
              <description>Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.</description>
                  <value>#110</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>111</name>
                  <description>9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.</description>
                  <value>#111</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSCLHIGH</name>
              <description>Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.</description>
                  <value>#110</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>111</name>
                  <description>9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.</description>
                  <value>#111</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTDAT</name>
          <description>Combined Master receiver and transmitter data register.</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVCTL</name>
          <description>Slave control register.</description>
          <addressOffset>0x40</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xB</resetMask>
          <fields>
            <field>
              <name>SLVCONTINUE</name>
              <description>Slave Continue.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Informs the Slave function to continue to the next operation.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNACK</name>
              <description>Slave NACK.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDMA</name>
              <description>Slave DMA enable.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. No DMA requests are issued for Slave mode operation.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. DMA requests are issued for I2C slave data transmission and reception.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVDAT</name>
          <description>Combined Slave receiver and transmitter data register.</description>
          <addressOffset>0x44</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR0</name>
          <description>Slave address register.</description>
          <addressOffset>0x48</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR1</name>
          <description>Slave address register.</description>
          <addressOffset>0x4C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR2</name>
          <description>Slave address register.</description>
          <addressOffset>0x50</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR3</name>
          <description>Slave address register.</description>
          <addressOffset>0x54</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVQUAL0</name>
          <description>Slave Qualification for address 0.</description>
          <addressOffset>0x58</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>QUALMODE0</name>
              <description>Qualify mode for slave address 0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVQUAL0</name>
              <description>Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] &lt;= received address &lt;= SLVQUAL0[7:1]).</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MONRXDAT</name>
          <description>Monitor receiver data register.</description>
          <addressOffset>0x80</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x7FF</resetMask>
          <fields>
            <field>
              <name>MONRXDAT</name>
              <description>Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONSTART</name>
              <description>Monitor Received Start.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No start detected. The Monitor function has not detected a Start event on the I2C bus.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Start detected. The Monitor function has detected a Start event on the I2C bus.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRESTART</name>
              <description>Monitor Received Repeated Start.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONNACK</name>
              <description>Monitor Received NACK.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>I2C0</name>
      <description>LPC84x I2C-bus interfaces</description>
      <groupName>I2C</groupName>
      <baseAddress>0x40050000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x84</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>I2C0</name>
        <value>8</value>
      </interrupt>
      <registers>
        <register>
          <name>CFG</name>
          <description>Configuration for shared functions.</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3F</resetMask>
          <fields>
            <field>
              <name>MSTEN</name>
              <description>Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The I2C Master function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The I2C Master function is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVEN</name>
              <description>Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The I2C slave function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The I2C slave function is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONEN</name>
              <description>Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The I2C Monitor function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The I2C Monitor function is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TIMEOUTEN</name>
              <description>I2C bus Time-out Enable. When disabled, the time-out function is internally reset.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. Time-out function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONCLKSTR</name>
              <description>Monitor function Clock Stretching.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT</name>
          <description>Status register for Master, Slave, and Monitor functions.</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x801</resetValue>
          <resetMask>0x30FFF5F</resetMask>
          <fields>
            <field>
              <name>MSTPENDING</name>
              <description>Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTATE</name>
              <description>Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>Idle. The Master function is available to be used for a new transaction.</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>NACK Address. Slave NACKed address.</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>NACK Data. Slave NACKed transmitted data.</description>
                  <value>#100</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTARBLOSS</name>
              <description>Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No Arbitration Loss has occurred.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTSTPERR</name>
              <description>Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No Start/Stop Error has occurred.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVPENDING</name>
              <description>Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>In progress. The Slave function does not currently need service.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVSTATE</name>
              <description>Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Slave receive. Received data is available (Slave Receiver mode).</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Slave transmit. Data can be transmitted (Slave Transmitter mode).</description>
                  <value>#10</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNOTSTR</name>
              <description>Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVIDX</name>
              <description>Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Address 0. Slave address 0 was matched.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Address 1. Slave address 1 was matched.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Address 2. Slave address 2 was matched.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Address 3. Slave address 3 was matched.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVSEL</name>
              <description>Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Not selected. The Slave function is not currently selected.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Selected. The Slave function is currently selected.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDESEL</name>
              <description>Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRDY</name>
              <description>Monitor Ready. This flag is cleared when the MONRXDAT register is read.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No data. The Monitor function does not currently have data available.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Data waiting. The Monitor function has data waiting to be read.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONOV</name>
              <description>Monitor Overflow flag.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No overrun. Monitor data has not overrun.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONACTIVE</name>
              <description>Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Inactive. The Monitor function considers the I2C bus to be inactive.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Active. The Monitor function considers the I2C bus to be active.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONIDLE</name>
              <description>Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Not idle. The I2C bus is not idle, or this flag has been cleared by software.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EVENTTIMEOUT</name>
              <description>Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No time-out. I2C bus events have not caused a time-out.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SCLTIMEOUT</name>
              <description>SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No time-out. SCL low time has not caused a time-out.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Time-out. SCL low time has caused a time-out.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENSET</name>
          <description>Interrupt Enable Set and read register.</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x30B8951</resetMask>
          <fields>
            <field>
              <name>MSTPENDINGEN</name>
              <description>Master Pending interrupt Enable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MstPending interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MstPending interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTARBLOSSEN</name>
              <description>Master Arbitration Loss interrupt Enable.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MstArbLoss interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MstArbLoss interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTSTPERREN</name>
              <description>Master Start/Stop Error interrupt Enable.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MstStStpErr interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MstStStpErr interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVPENDINGEN</name>
              <description>Slave Pending interrupt Enable.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SlvPending interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SlvPending interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNOTSTREN</name>
              <description>Slave Not Stretching interrupt Enable.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SlvNotStr interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SlvNotStr interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDESELEN</name>
              <description>Slave Deselect interrupt Enable.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SlvDeSel interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SlvDeSel interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRDYEN</name>
              <description>Monitor data Ready interrupt Enable.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MonRdy interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MonRdy interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONOVEN</name>
              <description>Monitor Overrun interrupt Enable.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MonOv interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MonOv interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONIDLEEN</name>
              <description>Monitor Idle interrupt Enable.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MonIdle interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MonIdle interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EVENTTIMEOUTEN</name>
              <description>Event time-out interrupt Enable.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The Event time-out interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The Event time-out interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SCLTIMEOUTEN</name>
              <description>SCL time-out interrupt Enable.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SCL time-out interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SCL time-out interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENCLR</name>
          <description>Interrupt Enable Clear register.</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>MSTPENDINGCLR</name>
              <description>Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MSTARBLOSSCLR</name>
              <description>Master Arbitration Loss interrupt clear.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MSTSTSTPERRCLR</name>
              <description>Master Start/Stop Error interrupt clear.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVPENDINGCLR</name>
              <description>Slave Pending interrupt clear.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVNOTSTRCLR</name>
              <description>Slave Not Stretching interrupt clear.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVDESELCLR</name>
              <description>Slave Deselect interrupt clear.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONRDYCLR</name>
              <description>Monitor data Ready interrupt clear.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONOVCLR</name>
              <description>Monitor Overrun interrupt clear.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONIDLECLR</name>
              <description>Monitor Idle interrupt clear.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>EVENTTIMEOUTCLR</name>
              <description>Event time-out interrupt clear.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SCLTIMEOUTCLR</name>
              <description>SCL time-out interrupt clear.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMEOUT</name>
          <description>Time-out value register.</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFF</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>TOMIN</name>
              <description>Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TO</name>
              <description>Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLKDIV</name>
          <description>Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>DIVVAL</name>
              <description>This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTSTAT</name>
          <description>Interrupt Status register for Master, Slave, and Monitor functions.</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x801</resetValue>
          <resetMask>0x30FFF5F</resetMask>
          <fields>
            <field>
              <name>MSTPENDING</name>
              <description>Master Pending.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MSTARBLOSS</name>
              <description>Master Arbitration Loss flag.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MSTSTSTPERR</name>
              <description>Master Start/Stop Error flag.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVPENDING</name>
              <description>Slave Pending.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVNOTSTR</name>
              <description>Slave Not Stretching status.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVDESEL</name>
              <description>Slave Deselected flag.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONRDY</name>
              <description>Monitor Ready.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONOV</name>
              <description>Monitor Overflow flag.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONIDLE</name>
              <description>Monitor Idle flag.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>EVENTTIMEOUT</name>
              <description>Event time-out Interrupt flag.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SCLTIMEOUT</name>
              <description>SCL time-out Interrupt flag.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTCTL</name>
          <description>Master control register.</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>MSTCONTINUE</name>
              <description>Master Continue.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Informs the Master function to continue to the next operation.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTART</name>
              <description>Master Start control.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Start. A Start will be generated on the I2C bus at the next allowed time.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTOP</name>
              <description>Master Stop control.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTDMA</name>
              <description>Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable. No DMA requests are generated for master operation.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTTIME</name>
          <description>Master timing configuration.</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x77</resetValue>
          <resetMask>0x77</resetMask>
          <fields>
            <field>
              <name>MSTSCLLOW</name>
              <description>Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.</description>
                  <value>#110</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>111</name>
                  <description>9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.</description>
                  <value>#111</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSCLHIGH</name>
              <description>Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.</description>
                  <value>#110</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>111</name>
                  <description>9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.</description>
                  <value>#111</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTDAT</name>
          <description>Combined Master receiver and transmitter data register.</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVCTL</name>
          <description>Slave control register.</description>
          <addressOffset>0x40</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xB</resetMask>
          <fields>
            <field>
              <name>SLVCONTINUE</name>
              <description>Slave Continue.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Informs the Slave function to continue to the next operation.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNACK</name>
              <description>Slave NACK.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDMA</name>
              <description>Slave DMA enable.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. No DMA requests are issued for Slave mode operation.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. DMA requests are issued for I2C slave data transmission and reception.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVDAT</name>
          <description>Combined Slave receiver and transmitter data register.</description>
          <addressOffset>0x44</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR0</name>
          <description>Slave address register.</description>
          <addressOffset>0x48</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR1</name>
          <description>Slave address register.</description>
          <addressOffset>0x4C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR2</name>
          <description>Slave address register.</description>
          <addressOffset>0x50</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR3</name>
          <description>Slave address register.</description>
          <addressOffset>0x54</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVQUAL0</name>
          <description>Slave Qualification for address 0.</description>
          <addressOffset>0x58</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>QUALMODE0</name>
              <description>Qualify mode for slave address 0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVQUAL0</name>
              <description>Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] &lt;= received address &lt;= SLVQUAL0[7:1]).</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MONRXDAT</name>
          <description>Monitor receiver data register.</description>
          <addressOffset>0x80</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x7FF</resetMask>
          <fields>
            <field>
              <name>MONRXDAT</name>
              <description>Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONSTART</name>
              <description>Monitor Received Start.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No start detected. The Monitor function has not detected a Start event on the I2C bus.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Start detected. The Monitor function has detected a Start event on the I2C bus.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRESTART</name>
              <description>Monitor Received Repeated Start.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONNACK</name>
              <description>Monitor Received NACK.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>I2C1</name>
      <description>LPC84x I2C-bus interfaces</description>
      <groupName>I2C</groupName>
      <baseAddress>0x40054000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x84</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>I2C1</name>
        <value>7</value>
      </interrupt>
      <registers>
        <register>
          <name>CFG</name>
          <description>Configuration for shared functions.</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3F</resetMask>
          <fields>
            <field>
              <name>MSTEN</name>
              <description>Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The I2C Master function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The I2C Master function is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVEN</name>
              <description>Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The I2C slave function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The I2C slave function is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONEN</name>
              <description>Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The I2C Monitor function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The I2C Monitor function is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TIMEOUTEN</name>
              <description>I2C bus Time-out Enable. When disabled, the time-out function is internally reset.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. Time-out function is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONCLKSTR</name>
              <description>Monitor function Clock Stretching.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT</name>
          <description>Status register for Master, Slave, and Monitor functions.</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x801</resetValue>
          <resetMask>0x30FFF5F</resetMask>
          <fields>
            <field>
              <name>MSTPENDING</name>
              <description>Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTATE</name>
              <description>Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>Idle. The Master function is available to be used for a new transaction.</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>NACK Address. Slave NACKed address.</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>NACK Data. Slave NACKed transmitted data.</description>
                  <value>#100</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTARBLOSS</name>
              <description>Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No Arbitration Loss has occurred.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTSTPERR</name>
              <description>Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No Start/Stop Error has occurred.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVPENDING</name>
              <description>Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>In progress. The Slave function does not currently need service.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVSTATE</name>
              <description>Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Slave receive. Received data is available (Slave Receiver mode).</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Slave transmit. Data can be transmitted (Slave Transmitter mode).</description>
                  <value>#10</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNOTSTR</name>
              <description>Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVIDX</name>
              <description>Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Address 0. Slave address 0 was matched.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Address 1. Slave address 1 was matched.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Address 2. Slave address 2 was matched.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Address 3. Slave address 3 was matched.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVSEL</name>
              <description>Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Not selected. The Slave function is not currently selected.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Selected. The Slave function is currently selected.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDESEL</name>
              <description>Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRDY</name>
              <description>Monitor Ready. This flag is cleared when the MONRXDAT register is read.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No data. The Monitor function does not currently have data available.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Data waiting. The Monitor function has data waiting to be read.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONOV</name>
              <description>Monitor Overflow flag.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No overrun. Monitor data has not overrun.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONACTIVE</name>
              <description>Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Inactive. The Monitor function considers the I2C bus to be inactive.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Active. The Monitor function considers the I2C bus to be active.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONIDLE</name>
              <description>Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Not idle. The I2C bus is not idle, or this flag has been cleared by software.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EVENTTIMEOUT</name>
              <description>Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No time-out. I2C bus events have not caused a time-out.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SCLTIMEOUT</name>
              <description>SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No time-out. SCL low time has not caused a time-out.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Time-out. SCL low time has caused a time-out.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENSET</name>
          <description>Interrupt Enable Set and read register.</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x30B8951</resetMask>
          <fields>
            <field>
              <name>MSTPENDINGEN</name>
              <description>Master Pending interrupt Enable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MstPending interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MstPending interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTARBLOSSEN</name>
              <description>Master Arbitration Loss interrupt Enable.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MstArbLoss interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MstArbLoss interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTSTPERREN</name>
              <description>Master Start/Stop Error interrupt Enable.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MstStStpErr interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MstStStpErr interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVPENDINGEN</name>
              <description>Slave Pending interrupt Enable.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SlvPending interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SlvPending interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNOTSTREN</name>
              <description>Slave Not Stretching interrupt Enable.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SlvNotStr interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SlvNotStr interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDESELEN</name>
              <description>Slave Deselect interrupt Enable.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SlvDeSel interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SlvDeSel interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRDYEN</name>
              <description>Monitor data Ready interrupt Enable.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MonRdy interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MonRdy interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONOVEN</name>
              <description>Monitor Overrun interrupt Enable.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MonOv interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MonOv interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONIDLEEN</name>
              <description>Monitor Idle interrupt Enable.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The MonIdle interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The MonIdle interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EVENTTIMEOUTEN</name>
              <description>Event time-out interrupt Enable.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The Event time-out interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The Event time-out interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SCLTIMEOUTEN</name>
              <description>SCL time-out interrupt Enable.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. The SCL time-out interrupt is disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The SCL time-out interrupt is enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENCLR</name>
          <description>Interrupt Enable Clear register.</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>MSTPENDINGCLR</name>
              <description>Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MSTARBLOSSCLR</name>
              <description>Master Arbitration Loss interrupt clear.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MSTSTSTPERRCLR</name>
              <description>Master Start/Stop Error interrupt clear.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVPENDINGCLR</name>
              <description>Slave Pending interrupt clear.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVNOTSTRCLR</name>
              <description>Slave Not Stretching interrupt clear.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVDESELCLR</name>
              <description>Slave Deselect interrupt clear.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONRDYCLR</name>
              <description>Monitor data Ready interrupt clear.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONOVCLR</name>
              <description>Monitor Overrun interrupt clear.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONIDLECLR</name>
              <description>Monitor Idle interrupt clear.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>EVENTTIMEOUTCLR</name>
              <description>Event time-out interrupt clear.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SCLTIMEOUTCLR</name>
              <description>SCL time-out interrupt clear.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMEOUT</name>
          <description>Time-out value register.</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFF</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>TOMIN</name>
              <description>Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TO</name>
              <description>Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLKDIV</name>
          <description>Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>DIVVAL</name>
              <description>This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTSTAT</name>
          <description>Interrupt Status register for Master, Slave, and Monitor functions.</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x801</resetValue>
          <resetMask>0x30FFF5F</resetMask>
          <fields>
            <field>
              <name>MSTPENDING</name>
              <description>Master Pending.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MSTARBLOSS</name>
              <description>Master Arbitration Loss flag.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MSTSTSTPERR</name>
              <description>Master Start/Stop Error flag.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVPENDING</name>
              <description>Slave Pending.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVNOTSTR</name>
              <description>Slave Not Stretching status.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVDESEL</name>
              <description>Slave Deselected flag.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONRDY</name>
              <description>Monitor Ready.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONOV</name>
              <description>Monitor Overflow flag.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONIDLE</name>
              <description>Monitor Idle flag.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>EVENTTIMEOUT</name>
              <description>Event time-out Interrupt flag.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SCLTIMEOUT</name>
              <description>SCL time-out Interrupt flag.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTCTL</name>
          <description>Master control register.</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>MSTCONTINUE</name>
              <description>Master Continue.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Informs the Master function to continue to the next operation.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTART</name>
              <description>Master Start control.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Start. A Start will be generated on the I2C bus at the next allowed time.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTOP</name>
              <description>Master Stop control.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTDMA</name>
              <description>Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable. No DMA requests are generated for master operation.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTTIME</name>
          <description>Master timing configuration.</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x77</resetValue>
          <resetMask>0x77</resetMask>
          <fields>
            <field>
              <name>MSTSCLLOW</name>
              <description>Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.</description>
                  <value>#110</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>111</name>
                  <description>9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.</description>
                  <value>#111</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSCLHIGH</name>
              <description>Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.</description>
                  <value>#110</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>111</name>
                  <description>9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.</description>
                  <value>#111</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTDAT</name>
          <description>Combined Master receiver and transmitter data register.</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVCTL</name>
          <description>Slave control register.</description>
          <addressOffset>0x40</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xB</resetMask>
          <fields>
            <field>
              <name>SLVCONTINUE</name>
              <description>Slave Continue.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Informs the Slave function to continue to the next operation.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNACK</name>
              <description>Slave NACK.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No effect.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDMA</name>
              <description>Slave DMA enable.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. No DMA requests are issued for Slave mode operation.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. DMA requests are issued for I2C slave data transmission and reception.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVDAT</name>
          <description>Combined Slave receiver and transmitter data register.</description>
          <addressOffset>0x44</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR0</name>
          <description>Slave address register.</description>
          <addressOffset>0x48</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR1</name>
          <description>Slave address register.</description>
          <addressOffset>0x4C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR2</name>
          <description>Slave address register.</description>
          <addressOffset>0x50</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVADR3</name>
          <description>Slave address register.</description>
          <addressOffset>0x54</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVQUAL0</name>
          <description>Slave Qualification for address 0.</description>
          <addressOffset>0x58</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>QUALMODE0</name>
              <description>Qualify mode for slave address 0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVQUAL0</name>
              <description>Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] &lt;= received address &lt;= SLVQUAL0[7:1]).</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MONRXDAT</name>
          <description>Monitor receiver data register.</description>
          <addressOffset>0x80</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x7FF</resetMask>
          <fields>
            <field>
              <name>MONRXDAT</name>
              <description>Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONSTART</name>
              <description>Monitor Received Start.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No start detected. The Monitor function has not detected a Start event on the I2C bus.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Start detected. The Monitor function has detected a Start event on the I2C bus.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRESTART</name>
              <description>Monitor Received Repeated Start.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONNACK</name>
              <description>Monitor Received NACK.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>CTIMER0</name>
      <description>LPC184 Standard counter/timer</description>
      <baseAddress>0x40038000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x88</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>CTIMER0</name>
        <value>23</value>
      </interrupt>
      <registers>
        <register>
          <name>IR</name>
          <description>Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>MR0INT</name>
              <description>Interrupt flag for match channel 0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR1INT</name>
              <description>Interrupt flag for match channel 1.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR2INT</name>
              <description>Interrupt flag for match channel 2.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR3INT</name>
              <description>Interrupt flag for match channel 3.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CR0INT</name>
              <description>Interrupt flag for capture channel 0 event.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CR1INT</name>
              <description>Interrupt flag for capture channel 1 event.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CR2INT</name>
              <description>Interrupt flag for capture channel 2 event.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CR3INT</name>
              <description>Interrupt flag for capture channel 3 event.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TCR</name>
          <description>Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3</resetMask>
          <fields>
            <field>
              <name>CEN</name>
              <description>Counter enable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled.The counters are disabled.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The Timer Counter and Prescale Counter are enabled.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CRST</name>
              <description>Counter reset.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disabled. Do nothing.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>TC</name>
          <description>Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR.</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>TCVAL</name>
              <description>Timer counter value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PR</name>
          <description>Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PRVAL</name>
              <description>Prescale counter value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PC</name>
          <description>Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PCVAL</name>
              <description>Prescale counter value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MCR</name>
          <description>Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF000FFF</resetMask>
          <fields>
            <field>
              <name>MR0I</name>
              <description>Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR0R</name>
              <description>Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR0S</name>
              <description>Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR1I</name>
              <description>Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR1R</name>
              <description>Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR1S</name>
              <description>Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR2I</name>
              <description>Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR2R</name>
              <description>Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR2S</name>
              <description>Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR3I</name>
              <description>Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR3R</name>
              <description>Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR3S</name>
              <description>Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR0RL</name>
              <description>Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR1RL</name>
              <description>Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR2RL</name>
              <description>Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR3RL</name>
              <description>Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MR0</name>
          <description>Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MATCH</name>
              <description>Timer counter match value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MR1</name>
          <description>Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.</description>
          <addressOffset>0x1C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MATCH</name>
              <description>Timer counter match value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MR2</name>
          <description>Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MATCH</name>
              <description>Timer counter match value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MR3</name>
          <description>Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MATCH</name>
              <description>Timer counter match value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR</name>
          <description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFF</resetMask>
          <fields>
            <field>
              <name>CAP0RE</name>
              <description>Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP0FE</name>
              <description>Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP0I</name>
              <description>Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP1RE</name>
              <description>Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP1FE</name>
              <description>Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP1I</name>
              <description>Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP2RE</name>
              <description>Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP2FE</name>
              <description>Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP2I</name>
              <description>Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP3RE</name>
              <description>Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP3FE</name>
              <description>Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP3I</name>
              <description>Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CR0</name>
          <description>Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>CAP</name>
              <description>Timer counter capture value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CR1</name>
          <description>Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.</description>
          <addressOffset>0x30</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>CAP</name>
              <description>Timer counter capture value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CR2</name>
          <description>Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.</description>
          <addressOffset>0x34</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>CAP</name>
              <description>Timer counter capture value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CR3</name>
          <description>Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.</description>
          <addressOffset>0x38</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>CAP</name>
              <description>Timer counter capture value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EMR</name>
          <description>External Match Register. The EMR controls the match function and the external match pins.</description>
          <addressOffset>0x3C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFF</resetMask>
          <fields>
            <field>
              <name>EM0</name>
              <description>External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EM1</name>
              <description>External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EM2</name>
              <description>External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EM3</name>
              <description>External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EMC0</name>
              <description>External Match Control 0. Determines the functionality of External Match 0.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Do Nothing.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Toggle. Toggle the corresponding External Match bit/output.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EMC1</name>
              <description>External Match Control 1. Determines the functionality of External Match 1.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Do Nothing.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Toggle. Toggle the corresponding External Match bit/output.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EMC2</name>
              <description>External Match Control 2. Determines the functionality of External Match 2.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Do Nothing.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Toggle. Toggle the corresponding External Match bit/output.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EMC3</name>
              <description>External Match Control 3. Determines the functionality of External Match 3.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Do Nothing.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Toggle. Toggle the corresponding External Match bit/output.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>CTCR</name>
          <description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
          <addressOffset>0x70</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>CTMODE</name>
              <description>Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer&apos;s Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Timer Mode. Incremented every rising APB bus clock edge.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CINSEL</name>
              <description>Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Channel 0. CAPn.0 for CTIMERn</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Channel 1. CAPn.1 for CTIMERn</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Channel 2. CAPn.2 for CTIMERn</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Channel 3. CAPn.3 for CTIMERn</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ENCC</name>
              <description>Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SELCC</name>
              <description>Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).</description>
                  <value>#110</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>111</name>
                  <description>Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).</description>
                  <value>#111</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PWMC</name>
          <description>PWM Control Register. The PWMCON enables PWM mode for the external match pins.</description>
          <addressOffset>0x74</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>PWMEN0</name>
              <description>PWM mode enable for channel0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Match. CTIMERn_MAT0 is controlled by EM0.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>PWM. PWM mode is enabled for CTIMERn_MAT0.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PWMEN1</name>
              <description>PWM mode enable for channel1.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Match. CTIMERn_MAT01 is controlled by EM1.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>PWM. PWM mode is enabled for CTIMERn_MAT1.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PWMEN2</name>
              <description>PWM mode enable for channel2.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Match. CTIMERn_MAT2 is controlled by EM2.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>PWM. PWM mode is enabled for CTIMERn_MAT2.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PWMEN3</name>
              <description>PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Match. CTIMERn_MAT3 is controlled by EM3.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>PWM. PWM mode is enabled for CT132Bn_MAT3.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>MSR0</name>
          <description>Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.</description>
          <addressOffset>0x78</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MATCH_SHADOW</name>
              <description>Timer counter match value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MSR1</name>
          <description>Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.</description>
          <addressOffset>0x7C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MATCH_SHADOW</name>
              <description>Timer counter match value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MSR2</name>
          <description>Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.</description>
          <addressOffset>0x80</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MATCH_SHADOW</name>
              <description>Timer counter match value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MSR3</name>
          <description>Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.</description>
          <addressOffset>0x84</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MATCH_SHADOW</name>
              <description>Timer counter match value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>FLASH_CTRL</name>
      <description>LPC84x NVMC flash controller</description>
      <baseAddress>0x40040000</baseAddress>
      <addressBlock>
        <offset>0x10</offset>
        <size>0xFDC</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>FLASH</name>
        <value>14</value>
      </interrupt>
      <registers>
        <register>
          <name>FLASHCFG</name>
          <description>Flash configuration register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x2</resetValue>
          <resetMask>0x3</resetMask>
          <fields>
            <field>
              <name>FLASHTIM</name>
              <description>Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>1 system clock flash access time.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>2 system clock flash access time.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>3 system clock flash access time.</description>
                  <value>#10</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>FMSSTART</name>
          <description>Flash signature start address register</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFFF</resetMask>
          <fields>
            <field>
              <name>START</name>
              <description>Signature generation start address (corresponds to AHB byte address bits[18:2]).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FMSSTOP</name>
          <description>Flash signaure stop address register</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x8001FFFF</resetMask>
          <fields>
            <field>
              <name>STOPA</name>
              <description>Stop address for signature generation (the word specified by STOP is included in the address range). The address is in units of memory words, not bytes.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>STRTBIST</name>
              <description>When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FMSW0</name>
          <description>Flash signature generation result register returns the flash signature produced by the embedded signature generator..</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>SIG</name>
              <description>32-bit signature.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FMSTAT</name>
          <description>Flash signature generation status bit</description>
          <addressOffset>0xFE0</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>SIG_DONE</name>
              <description>This status bit is set at the end of signature computation</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FMSTATCLR</name>
          <description>Clear FLASH signature generation status bit</description>
          <addressOffset>0xFE8</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>SIG_DONE_CLR</name>
              <description>When the bit is written to 1, the SIGNATURE_DONE bit is cleared.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>IOCON</name>
      <description>LPC84x I/O pin configuration (IOCON)</description>
      <baseAddress>0x40044000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0xE0</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>PIO0_17</name>
          <description>Digital I/O control for pins PIO0_17</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DACMODE</name>
              <description>DAC mode enable.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_13</name>
          <description>Digital I/O control for pins PIO0_13</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_12</name>
          <description>Digital I/O control for pins PIO0_12</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_5</name>
          <description>Digital I/O control for pins PIO0_5</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_4</name>
          <description>Digital I/O control for pins PIO0_4</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_3</name>
          <description>Digital I/O control for pins PIO0_3</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_2</name>
          <description>Digital I/O control for pins PIO0_2</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_11</name>
          <description>Digital I/O control for pins PIO0_11</description>
          <addressOffset>0x1C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x80</resetValue>
          <resetMask>0xFBFF</resetMask>
          <fields>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>I2CMODE</name>
              <description>Selects I2C mode.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Standard mode/ Fast-mode I2C.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Standard GPIO functionality. Requires external pull-up for GPIO output function.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Fast-mode Plus I2C</description>
                  <value>#10</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_10</name>
          <description>Digital I/O control for pins PIO0_10</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x80</resetValue>
          <resetMask>0xFBFF</resetMask>
          <fields>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>I2CMODE</name>
              <description>Selects I2C mode.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Standard mode/ Fast-mode I2C.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Standard GPIO functionality. Requires external pull-up for GPIO output function.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Fast-mode Plus I2C</description>
                  <value>#10</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_16</name>
          <description>Digital I/O control for pins PIO0_16</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_15</name>
          <description>Digital I/O control for pins PIO0_15</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_1</name>
          <description>Digital I/O control for pins PIO0_1</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_9</name>
          <description>Digital I/O control for pins PIO0_9</description>
          <addressOffset>0x34</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_8</name>
          <description>Digital I/O control for pins PIO0_8</description>
          <addressOffset>0x38</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_7</name>
          <description>Digital I/O control for pins PIO0_7</description>
          <addressOffset>0x3C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_6</name>
          <description>Digital I/O control for pins PIO0_6</description>
          <addressOffset>0x40</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_0</name>
          <description>Digital I/O control for pins PIO0_0</description>
          <addressOffset>0x44</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_14</name>
          <description>Digital I/O control for pins PIO0_14</description>
          <addressOffset>0x48</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_28</name>
          <description>Digital I/O control for pins PIO0_28</description>
          <addressOffset>0x50</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_27</name>
          <description>Digital I/O control for pins PIO0_27</description>
          <addressOffset>0x54</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_26</name>
          <description>Digital I/O control for pins PIO0_26</description>
          <addressOffset>0x58</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_25</name>
          <description>Digital I/O control for pins PIO0_25</description>
          <addressOffset>0x5C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_24</name>
          <description>Digital I/O control for pins PIO0_24</description>
          <addressOffset>0x60</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_23</name>
          <description>Digital I/O control for pins PIO0_23</description>
          <addressOffset>0x64</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_22</name>
          <description>Digital I/O control for pins PIO0_22</description>
          <addressOffset>0x68</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_21</name>
          <description>Digital I/O control for pins PIO0_21</description>
          <addressOffset>0x6C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_20</name>
          <description>Digital I/O control for pins PIO0_20</description>
          <addressOffset>0x70</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_19</name>
          <description>Digital I/O control for pins PIO0_19</description>
          <addressOffset>0x74</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_18</name>
          <description>Digital I/O control for pins PIO0_18</description>
          <addressOffset>0x78</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO1_8</name>
          <description>Digital I/O control for pins PIO1_8</description>
          <addressOffset>0x7C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO1_9</name>
          <description>Digital I/O control for pins PIO1_9</description>
          <addressOffset>0x80</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO1_12</name>
          <description>Digital I/O control for pins PIO1_12</description>
          <addressOffset>0x84</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO1_13</name>
          <description>Digital I/O control for pins PIO1_13</description>
          <addressOffset>0x88</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO0_31</name>
          <description>Digital I/O control for pins PIO0_31</description>
          <addressOffset>0x8C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO1_0</name>
          <description>Digital I/O control for pins PIO1_0</description>
          <addressOffset>0x90</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Enable</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INV</name>
              <description>Invert input</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OD</name>
              <description>Open-drain mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>0</name>
                  <description>Disable.</description>
                  <value>#0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>1</name>
                  <description>Open-drain mode enabled. Remark: This is not a true open-drain mode.</description>
                  <value>#1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>S_MODE</name>
              <description>Digital filter sample mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Bypass input filter.</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>000</name>
                  <description>IOCONCLKDIV0</description>
                  <value>#000</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>001</name>
                  <description>IOCONCLKDIV1</description>
                  <value>#001</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>010</name>
                  <description>IOCONCLKDIV2</description>
                  <value>#010</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>011</name>
                  <description>IOCONCLKDIV3</description>
                  <value>#011</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>100</name>
                  <description>IOCONCLKDIV4</description>
                  <value>#100</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>101</name>
                  <description>IOCONCLKDIV5</description>
                  <value>#101</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>110</name>
                  <description>IOCONCLKDIV6</description>
                  <value>#110</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO1_1</name>
          <description>Digital I/O control for pins PIO1_1</description>
          <addressOffset>0x94</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xB0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>00</name>
                  <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
                  <value>#00</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>01</name>
                  <description>Pull-down. Pull-down resistor enabled.</description>
                  <value>#01</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>10</name>
                  <description>Pull-up. Pull-up resistor enabled.</description>
                  <value>#10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>11</name>
                  <description>Repeater. Repeater mode.</description>
                  <value>#11</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>HYS</name>
              <description>Hysteresis.</description>
              <bitOffset>5</bitOffset>
              <bitWidt