somador4.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.all;

ENTITY somador4 IS
  PORT ( A, B:  IN   STD_LOGIC_VECTOR (3 DOWNTO 0);
         SUM:   OUT  STD_LOGIC_VECTOR (3 DOWNTO 0);
         CARRY: OUT  STD_LOGIC
        );
END somador4;

ARCHITECTURE soma OF somador4 IS
  SIGNAL AUXILIAR: STD_LOGIC_VECTOR (4 DOWNTO 0);
BEGIN
  AUXILIAR <= ('0' & A) + ('0' & B);
  SUM <= AUXILIAR(3 DOWNTO 0);
  CARRY <= AUXILIAR(4);
END soma;