Verilog 8 bit ALU

8bit-ALU.v

module ALU(A, B, OP, Z, OV);
	input signed [7:0] A, B;
	input [2:0] OP;
	output signed [7:0] Z; 
	output OV;

	reg ov;
	reg [7:0] z;


	always@(A or B or OP)
	begin
		ov = 0;
		case(OP)
		0:  begin
			z = A+B; 
			ov = (A[7] && B[7] && ~z[7]) || (~A[7] && ~B[7] && z[7]);
		end
		1:  begin
			z = A-B; 
			ov = (A[7] && ~B[7] && ~z[7]) || (~A[7] && B[7] && z[7]);
		end
		2:  z = (A>B) ? A : B; 
		3:  z = (A<B) ? A : B; 
		4:  z = A <<< 2; 
		5:  z = B >>> 3; 
		endcase
	end
	
	assign OV = ov;
	assign Z = z;
endmodule


module ALU_test();
	reg signed [7:0] a, b;
	reg [2:0] op;
	wire signed [7:0] z;
	wire ov;

	ALU DUT(
		.A(a),
		.B(b),
		.OP(op),
		.Z(z),
		.OV(ov)
	);

	initial
	begin
		// non overflow sum
		a = 2;
		b = 3;
		op = 0;
		#50

		// overflow sum type 1
		a = 64;
		b = 64;
		op = 0;
		#50

		// overflow sum type 2
		a = -60;
		b = -75;
		op = 0;
		#50

		// non overflow subtract
		a = 7;
		b = 3;
		op = 1;
		#50;

		// overflow subtract type 1
		a = -100;
		b = 50;
		op = 1;
		#50;


		// overflow subtract type 2
		a = 100;
		b = -50;
		op = 1;
		#50;

		// max
		a = 12;
		b = 28;
		op = 2;
		#50;

		// max
		a = 15;
		b = -28;
		op = 2;
		#50;

		// min
		a = 64;
		b = 95;
		op = 3;
		#50;

		// min
		a = 100;
		b = -1;
		op = 3;
		#50;

		// right shift
		a = 10;
		b = 0;
		op = 4;
		#50;

		// right shift
		a = -5;
		b = 0;
		op = 4;
		#50;

		// left shift
		a = 0;
		b = 4;
		op = 5;
		#50;

		// left shift
		a = 0;
		b = -8;
		op = 5;
		#50;

	end
endmodule

8 bit ALU written in Verilog which calculates the sum, subtract, min, max, left & right shift of the given numbers.
with an exclusive output bit to determine if overflow has occurred.
The test bench is also provided which tests the device under different circumstances.