AXI VVC channel queue max count

axi_vvc_tb.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library uvvm_util;
context uvvm_util.uvvm_util_context;

library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;

library bitvis_vip_axi;
context bitvis_vip_axi.vvc_context;

entity axi_vvc_tb is
end entity;

architecture sim of axi_vvc_tb is

  -- Constants for VVC Component: axi_vvc
  constant GC_ADDR_WIDTH                            : integer range 1 to C_VVC_CMD_ADDR_MAX_LENGTH := 32;
  constant GC_DATA_WIDTH                            : integer range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 32;
  constant GC_ID_WIDTH                              : integer range 0 to C_VVC_CMD_ID_MAX_LENGTH   := 12;
  constant GC_USER_WIDTH                            : integer range 0 to C_VVC_CMD_USER_MAX_LENGTH := 8;
  constant GC_INSTANCE_IDX                          : natural                                      := 1;
  constant GC_AXI_CONFIG                            : t_axi_bfm_config                             := C_AXI_BFM_CONFIG_DEFAULT;
  constant GC_CMD_QUEUE_COUNT_MAX                   : natural                                      := 1000;
  constant GC_CMD_QUEUE_COUNT_THRESHOLD             : natural                                      := 950;
  constant GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY    : t_alert_level                                := warning;
  constant GC_RESULT_QUEUE_COUNT_MAX                : natural                                      := 1000;
  constant GC_RESULT_QUEUE_COUNT_THRESHOLD          : natural                                      := 950;
  constant GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level                                := warning;

  signal clk    : std_logic;
  signal axi_if : t_axi_if(write_address_channel(awid(GC_ID_WIDTH - 1 downto 0),
                          awaddr(GC_ADDR_WIDTH - 1 downto 0),
                          awuser(GC_USER_WIDTH - 1 downto 0)),
                          write_data_channel(wdata(GC_DATA_WIDTH - 1 downto 0),
                          wstrb((GC_DATA_WIDTH/8) - 1 downto 0),
                          wuser(GC_USER_WIDTH - 1 downto 0)),
                          write_response_channel(bid(GC_ID_WIDTH - 1 downto 0),
                          buser(GC_USER_WIDTH - 1 downto 0)),
                          read_address_channel(arid(GC_ID_WIDTH - 1 downto 0),
                          araddr(GC_ADDR_WIDTH - 1 downto 0),
                          aruser(GC_USER_WIDTH - 1 downto 0)),
                          read_data_channel(rid(GC_ID_WIDTH - 1 downto 0),
                          rdata(GC_DATA_WIDTH - 1 downto 0),
                          ruser(GC_USER_WIDTH - 1 downto 0)));

begin

  clock_generator(clk, 10 ns);

  i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;

  i1_axi_vvc : entity bitvis_vip_axi.axi_vvc
    generic map(
      GC_ADDR_WIDTH                            => GC_ADDR_WIDTH,
      GC_DATA_WIDTH                            => GC_DATA_WIDTH,
      GC_ID_WIDTH                              => GC_ID_WIDTH,
      GC_USER_WIDTH                            => GC_USER_WIDTH,
      GC_INSTANCE_IDX                          => GC_INSTANCE_IDX,
      GC_AXI_CONFIG                            => GC_AXI_CONFIG,
      GC_CMD_QUEUE_COUNT_MAX                   => GC_CMD_QUEUE_COUNT_MAX,
      GC_CMD_QUEUE_COUNT_THRESHOLD             => GC_CMD_QUEUE_COUNT_THRESHOLD,
      GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY    => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
      GC_RESULT_QUEUE_COUNT_MAX                => GC_RESULT_QUEUE_COUNT_MAX,
      GC_RESULT_QUEUE_COUNT_THRESHOLD          => GC_RESULT_QUEUE_COUNT_THRESHOLD,
      GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY
    )
    port map(
      clk               => clk,
      axi_vvc_master_if => axi_if
    );

    process
    begin
      await_uvvm_initialization(VOID);

      for i in 1 to GC_CMD_QUEUE_COUNT_MAX loop
        axi_write(VVCT => AXI_VVCT, vvc_instance_idx => GC_INSTANCE_IDX, awaddr => x"00000000", awlen => x"00", wdata(0) => x"00000000", wstrb(0) => x"F", msg => "Dummy write");
      end loop;
      wait for 1 ns;

      report_alert_counters(FINAL);       -- Report final counters and print conclusion for simulation (Success/Fail)
      log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
      std.env.stop;
      wait;
    end process;

end architecture;