amcjen/gist:c1dd50e23c14bea8b0318d832ce752ee

## gistfile1.txt
PUSHBUTTON INTERFACE
The LTC3101 includes a pushbutton interface that allows a single momentary pushbutton to control the sequenced power-up and power-down of all output rails in coordina- tion with an external microprocessor. In addition, three independent enable pins allow an unused DC/DC converter to be independently disabled and also provide the means to manually implement an alternate power-up sequence.

The LTC3101 can be enabled by either forcing PWRON high or by forcing PWRKEY low. In either case, the DC/DC converters (if enabled by their respective enable pin) will power up in the internally fixed default sequence: buck converter 1, buck converter 2, and finally the buck- boost converter. In the typical application, the power-on sequence is initiated when the PWRKEY is driven low by an external momentary pushbutton. Once the microproces- sor is powered up it must assert PWRON high before the pushbutton is released, thereby forcing the LTC3101 to

remain enabled. Power-down is usually accomplished by having the microprocessor monitor PBSTAT to detect an additional push of the pushbutton. Once this is detected, the microprocessor disables the LTC3101 by forcing PWRON low (or simply releasing PWRON and allowing it be pulled low by its internal pull-down resistor). In this manner, a single external momentary pushbutton is all that is required to provide sequenced power-up and power-down control.

Figure 1 depicts the waveforms in the standard power-up sequence. In this example, it is assumed that all three DC/DC converter rails are used in the application and therefore ENA1, ENA2 and ENA3 are driven high (or tied to the MAX output). An external normally-open pushbutton is connected between ground and the PWRKEY pin. When the pushbutton is not pressed, PWRKEY is pulled high via an internal 400k pull-up resistor. Until the power-up sequence is initiated, the IC is in the standby state, and only the LDO and MAX outputs are active.
The standard power-up sequence is initiated when the pushbutton is pressed, forcing PWRKEY low for a duration that is longer than the 24ms (typical) internal debouncing duration. Once the PWRKEY is held low for the debouncing duration, PBSTAT is driven low to indicate the pushbutton status. In addition, buck converter 1 is enabled and its output begins rising into regulation. Once the feedback voltage of buck converter 1 reaches its power good threshold, buck converter 2 is enabled. After buck converter 2 reaches its power good threshold, the buck- boost converter is enabled. Finally, once the buck-boost output reaches its power good threshold, the Hot Swap output is enabled and simultaneously the microprocessor reset duration begins when a 1μA (nominal) current begins charging the external CRS capacitor. The microprocessor reset output, RESET, is driven low throughout this entire power-up sequence until the CRS pin is charged to 1.2V (typical). Once RESET goes high, the microprocessor in the application initializes and must drive the PWRON input of the LTC3101 high in order to keep the LTC3101 enabled. If PWRON is not driven high by the time PWRKEY returns high (i.e., the pushbutton is released) then the LTC3101 will be disabled and all outputs will be actively discharged to ground.
	PUSHBUTTON INTERFACE
	The LTC3101 includes a pushbutton interface that allows a single momentary pushbutton to control the sequenced power-up and power-down of all output rails in coordina- tion with an external microprocessor. In addition, three independent enable pins allow an unused DC/DC converter to be independently disabled and also provide the means to manually implement an alternate power-up sequence.

	The LTC3101 can be enabled by either forcing PWRON high or by forcing PWRKEY low. In either case, the DC/DC converters (if enabled by their respective enable pin) will power up in the internally fixed default sequence: buck converter 1, buck converter 2, and finally the buck- boost converter. In the typical application, the power-on sequence is initiated when the PWRKEY is driven low by an external momentary pushbutton. Once the microproces- sor is powered up it must assert PWRON high before the pushbutton is released, thereby forcing the LTC3101 to

	remain enabled. Power-down is usually accomplished by having the microprocessor monitor PBSTAT to detect an additional push of the pushbutton. Once this is detected, the microprocessor disables the LTC3101 by forcing PWRON low (or simply releasing PWRON and allowing it be pulled low by its internal pull-down resistor). In this manner, a single external momentary pushbutton is all that is required to provide sequenced power-up and power-down control.

	Figure 1 depicts the waveforms in the standard power-up sequence. In this example, it is assumed that all three DC/DC converter rails are used in the application and therefore ENA1, ENA2 and ENA3 are driven high (or tied to the MAX output). An external normally-open pushbutton is connected between ground and the PWRKEY pin. When the pushbutton is not pressed, PWRKEY is pulled high via an internal 400k pull-up resistor. Until the power-up sequence is initiated, the IC is in the standby state, and only the LDO and MAX outputs are active.
	The standard power-up sequence is initiated when the pushbutton is pressed, forcing PWRKEY low for a duration that is longer than the 24ms (typical) internal debouncing duration. Once the PWRKEY is held low for the debouncing duration, PBSTAT is driven low to indicate the pushbutton status. In addition, buck converter 1 is enabled and its output begins rising into regulation. Once the feedback voltage of buck converter 1 reaches its power good threshold, buck converter 2 is enabled. After buck converter 2 reaches its power good threshold, the buck- boost converter is enabled. Finally, once the buck-boost output reaches its power good threshold, the Hot Swap output is enabled and simultaneously the microprocessor reset duration begins when a 1μA (nominal) current begins charging the external CRS capacitor. The microprocessor reset output, RESET, is driven low throughout this entire power-up sequence until the CRS pin is charged to 1.2V (typical). Once RESET goes high, the microprocessor in the application initializes and must drive the PWRON input of the LTC3101 high in order to keep the LTC3101 enabled. If PWRON is not driven high by the time PWRKEY returns high (i.e., the pushbutton is released) then the LTC3101 will be disabled and all outputs will be actively discharged to ground.