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/ quickDraw.v
Last active
April 17, 2019 21:25
— forked from danielholanda/quickDraw.v
LeFlow - Quick Draw Verilog File
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| // https://www.youtube.com/watch?v=eHeqenSj0VQ | |
| // https://www.reddit.com/r/MachineLearning/comments/9yxzea/r_automatically_going_from_tensorflow_to_fpga/ | |
| // https://github.com/danielholanda/LeFlow | |
| `define MEMORY_CONTROLLER_ADDR_SIZE 64 | |
| `define MEMORY_CONTROLLER_DATA_SIZE 64 | |
| // Number of RAM elements: 16 | |
| `define MEMORY_CONTROLLER_TAG_SIZE 9 | |
| // @param0 = internal global [5 x [5 x [1 x [8 x float]]]] zeroinitializer, align 8 | |
| `define TAG_g_param0 `MEMORY_CONTROLLER_TAG_SIZE'd17 |