verilog tp

gistfile1.txt

module carry_over_adder(a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, s0, s1, s2, s3, s4 ,s5, c0);
	input a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, c0;
	output s0, s1, s2, s3, s4, s5;
	wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20;
	wire c21, c22, c23, c24, c25, c26, c27, c28, c29, c30, c31, c32, c33, c34, c35, c36, c37, c38, c39, c40;
	wire c41, c42, c43, c44;
	not (ci, c0); //notting c0 gate)
	//START OF FIRST SEQUENCE
	nand (c1, a0, b0);
	nor (c2, a0, b0);
	not (c3, c2);
	and (c4, c3, c2);
	xor (s0, c4, c0);
	//END OF FIRST SUM
	//START OF SECOND SUM
	nand (c5, a1, b1);
	nor (c6, a1, b1);
	not (c7, c6);
	and (c8, c7, c5);
	and (c9, c1, ci);
	nor (c10, c9, c2);
	xor (s1, c10, c8);
	//END OF SECOND SUM
	//START OF THIRD SUM
	nand (c11, a2, b2);
	nor (c12, a2, b2);
	not (c13, c12);
	and (c14, c13, c11);
	and (c15, ci, c1, c5);
	and (c16, c5, c2);
	nor (c17, c15, c16, c6);
	xor (s2, c17, c14);
	//END  OF THIRD SUM
	//START OF FOURTH SUM
	nand (c18, a3, b3);
	nor (c19, a3, b3);
	not (c20, c19);
	and (c21, c20, c18);
	and (c22, ci, c1, c5, c11);
	and (c23, c5, c11, c2);
	and (c24, c11, c6);
	nor (c25, c24, c23, c22, c12);
	xor (s3, c25, c21);
	//END OF FOURTH SUM
	//START OF FIFTH SUM
	nand (c26, a4, b4);
	nor (c27, a4, b4);
	not (c28, c27);
	and (c29, c28, c26);
	and (c30, ci, c1, c5, c11, c18);
	and (c31, c5, c11, c18, c2);
	and (c32, c11, c18, c6);
	and (c33, c18, c12);
	nor (c34, c33, c32, c31, c30, c19);
	xor (s4, c34, c29);
	//END OF FIFTH SUM
	//START OF SIXTH SUM
	nand (c35, a5, b5);
	nor (c36, a5, b5);
	not (c37, c36);
	and (c38, c35, c37);
	and (c39, ci, c1, c5, c11, c18, c26);
	and (c40, c5, c11, c18, c26, c2);
	and (c41, c11, c18, c26, c6);
	and (c42, c18, c26, c12);
	and (c43, c26, c19);
	nor (c44, c43, c42, c41, c40, c39, c27);
	xor (s5, c44, c38);
	//END OF SIXTH SUM
	endmodule