Firmware issue with TSC sync on Acer sf314-42

gistfile1.txt

There seems to be a firmware issue with TSC (timestamp counter) on new
AMD Ryzen CPUs in recently released Acer Swift 3 SF314-42 laptops.

The issue is that different cores of the CPU may have TSC running at
different rates or out of sync with each other. This causes a
performance penalty as the operating system is unable to use the TSC,
and has to fall back to another time source.

The issue can be easily reproduced by booting Linux (Windows should be
affected too, but I'm not sure how to diagnose it there). After
booting, check TSC status by issuing the command

    dmesg | grep -E 'tsc|clock'

I'm seeing two possible failure scenarios:

1) one is cores in different CCX running at ~3600 cycle offset:

[    0.276014] x86: Booting SMP configuration:
[    0.276016] .... node  #0, CPUs:      #1 #2 #3
[    0.278678] TSC synchronization [CPU#0 -> CPU#3]:
[    0.278686] Measured 3563 cycles TSC warp between CPUs, turning off TSC clock.
[    0.278688] tsc: Marking TSC unstable due to check_tsc_sync_source failed
[    0.279802]  #4 #5

2) another is TSC on core 1 or 2 running at rate 3900MHz while it
should be running at rate 2375 MHZ:

[    2.010766] clocksource: timekeeping watchdog on CPU2: Marking clocksource 'tsc-early' as unstable because the skew is too large:
[    2.010767] clocksource:                       'hpet' wd_now: 15fa339 wd_last: f1e4d7 mask: ffffffff
[    2.010768] clocksource:                       'tsc-early' cs_now: 836c1ef3b cs_last: 7c2143eaf mask: ffffffffffffffff
[    2.010771] tsc: Marking TSC unstable due to clocksource watchdog
[    2.010797] TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'.


The first issue seems to be reliably reproducible after a soft reboot.