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May 7, 2024 20:35
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| --- /home/andriin/tmp/dump-norm.txt 2024-05-07 13:28:09.633080539 -0700 | |
| +++ /home/andriin/tmp/dump-norm-newer.txt 2024-05-07 13:31:02.977395011 -0700 | |
| @@ -6,6 +6,16 @@ | |
| #endif | |
| enum { | |
| + AAC_ENABLE_INTERRUPT = 0, | |
| + AAC_DISABLE_INTERRUPT = 1, | |
| + AAC_ENABLE_MSIX = 2, | |
| + AAC_DISABLE_MSIX = 3, | |
| + AAC_CLEAR_AIF_BIT = 4, | |
| + AAC_CLEAR_SYNC_BIT = 5, | |
| + AAC_ENABLE_INTX = 6, | |
| +}; | |
| + | |
| +enum { | |
| ACPI_GENL_ATTR_UNSPEC = 0, | |
| ACPI_GENL_ATTR_EVENT = 1, | |
| __ACPI_GENL_ATTR_MAX = 2, | |
| @@ -235,9 +245,10 @@ | |
| AHCI_HFLAG_WAKE_BEFORE_STOP = 4194304, | |
| AHCI_HFLAG_YES_ALPM = 8388608, | |
| AHCI_HFLAG_NO_WRITE_TO_RO = 16777216, | |
| - AHCI_HFLAG_USE_LPM_POLICY = 33554432, | |
| - AHCI_HFLAG_SUSPEND_PHYS = 67108864, | |
| - AHCI_HFLAG_NO_SXS = 268435456, | |
| + AHCI_HFLAG_SUSPEND_PHYS = 33554432, | |
| + AHCI_HFLAG_NO_SXS = 67108864, | |
| + AHCI_HFLAG_43BIT_ONLY = 134217728, | |
| + AHCI_HFLAG_INTEL_PCS_QUIRK = 268435456, | |
| AHCI_FLAG_COMMON = 393346, | |
| ICH_MAP = 144, | |
| PCS_6 = 146, | |
| @@ -270,6 +281,13 @@ | |
| }; | |
| enum { | |
| + AHC_POWER_STATE_D0 = 0, | |
| + AHC_POWER_STATE_D1 = 1, | |
| + AHC_POWER_STATE_D2 = 2, | |
| + AHC_POWER_STATE_D3 = 3, | |
| +}; | |
| + | |
| +enum { | |
| AML_FIELD_ACCESS_ANY = 0, | |
| AML_FIELD_ACCESS_BYTE = 1, | |
| AML_FIELD_ACCESS_WORD = 2, | |
| @@ -309,6 +327,28 @@ | |
| }; | |
| enum { | |
| + ASCII_NULL = 0, | |
| + ASCII_BELL = 7, | |
| + ASCII_BACKSPACE = 8, | |
| + ASCII_IGNORE_FIRST = 8, | |
| + ASCII_HTAB = 9, | |
| + ASCII_LINEFEED = 10, | |
| + ASCII_VTAB = 11, | |
| + ASCII_FORMFEED = 12, | |
| + ASCII_CAR_RET = 13, | |
| + ASCII_IGNORE_LAST = 13, | |
| + ASCII_SHIFTOUT = 14, | |
| + ASCII_SHIFTIN = 15, | |
| + ASCII_CANCEL = 24, | |
| + ASCII_SUBSTITUTE = 26, | |
| + ASCII_ESCAPE = 27, | |
| + ASCII_CSI_IGNORE_FIRST = 32, | |
| + ASCII_CSI_IGNORE_LAST = 63, | |
| + ASCII_DEL = 127, | |
| + ASCII_EXT_CSI = 155, | |
| +}; | |
| + | |
| +enum { | |
| ATA_EH_SPDN_NCQ_OFF = 1, | |
| ATA_EH_SPDN_SPEED_DOWN = 2, | |
| ATA_EH_SPDN_FALLBACK_TO_PIO = 4, | |
| @@ -597,8 +637,14 @@ | |
| ATA_LOG_SATA_NCQ = 16, | |
| ATA_LOG_NCQ_NON_DATA = 18, | |
| ATA_LOG_NCQ_SEND_RECV = 19, | |
| + ATA_LOG_CDL = 24, | |
| + ATA_LOG_CDL_SIZE = 512, | |
| ATA_LOG_IDENTIFY_DEVICE = 48, | |
| + ATA_LOG_SENSE_NCQ = 15, | |
| + ATA_LOG_SENSE_NCQ_SIZE = 1024, | |
| ATA_LOG_CONCURRENT_POSITIONING_RANGES = 71, | |
| + ATA_LOG_SUPPORTED_CAPABILITIES = 3, | |
| + ATA_LOG_CURRENT_SETTINGS = 4, | |
| ATA_LOG_SECURITY = 6, | |
| ATA_LOG_SATA_SETTINGS = 8, | |
| ATA_LOG_ZONED_INFORMATION = 9, | |
| @@ -671,6 +717,7 @@ | |
| SETFEATURES_SPINUP_TIMEOUT = 30000, | |
| SETFEATURES_SATA_ENABLE = 16, | |
| SETFEATURES_SATA_DISABLE = 144, | |
| + SETFEATURES_CDL = 13, | |
| SATA_FPDMA_OFFSET = 1, | |
| SATA_FPDMA_AA = 2, | |
| SATA_DIPM = 3, | |
| @@ -679,6 +726,7 @@ | |
| SATA_SSP = 6, | |
| SATA_DEVSLP = 9, | |
| SETFEATURE_SENSE_DATA = 195, | |
| + SETFEATURE_SENSE_DATA_SUCC_NCQ = 196, | |
| ATA_SET_MAX_ADDR = 0, | |
| ATA_SET_MAX_PASSWD = 1, | |
| ATA_SET_MAX_LOCK = 2, | |
| @@ -763,11 +811,53 @@ | |
| }; | |
| enum { | |
| - AUTOP_INVALID = 0, | |
| - AUTOP_HDD = 1, | |
| - AUTOP_SSD_QD1 = 2, | |
| - AUTOP_SSD_DFL = 3, | |
| - AUTOP_SSD_FAST = 4, | |
| + AUTOFS_DEV_IOCTL_VERSION_CMD = 113, | |
| + AUTOFS_DEV_IOCTL_PROTOVER_CMD = 114, | |
| + AUTOFS_DEV_IOCTL_PROTOSUBVER_CMD = 115, | |
| + AUTOFS_DEV_IOCTL_OPENMOUNT_CMD = 116, | |
| + AUTOFS_DEV_IOCTL_CLOSEMOUNT_CMD = 117, | |
| + AUTOFS_DEV_IOCTL_READY_CMD = 118, | |
| + AUTOFS_DEV_IOCTL_FAIL_CMD = 119, | |
| + AUTOFS_DEV_IOCTL_SETPIPEFD_CMD = 120, | |
| + AUTOFS_DEV_IOCTL_CATATONIC_CMD = 121, | |
| + AUTOFS_DEV_IOCTL_TIMEOUT_CMD = 122, | |
| + AUTOFS_DEV_IOCTL_REQUESTER_CMD = 123, | |
| + AUTOFS_DEV_IOCTL_EXPIRE_CMD = 124, | |
| + AUTOFS_DEV_IOCTL_ASKUMOUNT_CMD = 125, | |
| + AUTOFS_DEV_IOCTL_ISMOUNTPOINT_CMD = 126, | |
| +}; | |
| + | |
| +enum { | |
| + AUTOFS_IOC_EXPIRE_MULTI_CMD = 102, | |
| + AUTOFS_IOC_PROTOSUBVER_CMD = 103, | |
| + AUTOFS_IOC_ASKUMOUNT_CMD = 112, | |
| +}; | |
| + | |
| +enum { | |
| + AUTOFS_IOC_READY_CMD = 96, | |
| + AUTOFS_IOC_FAIL_CMD = 97, | |
| + AUTOFS_IOC_CATATONIC_CMD = 98, | |
| + AUTOFS_IOC_PROTOVER_CMD = 99, | |
| + AUTOFS_IOC_SETTIMEOUT_CMD = 100, | |
| + AUTOFS_IOC_EXPIRE_CMD = 101, | |
| +}; | |
| + | |
| +enum { | |
| + AX25_VALUES_IPDEFMODE = 0, | |
| + AX25_VALUES_AXDEFMODE = 1, | |
| + AX25_VALUES_BACKOFF = 2, | |
| + AX25_VALUES_CONMODE = 3, | |
| + AX25_VALUES_WINDOW = 4, | |
| + AX25_VALUES_EWINDOW = 5, | |
| + AX25_VALUES_T1 = 6, | |
| + AX25_VALUES_T2 = 7, | |
| + AX25_VALUES_T3 = 8, | |
| + AX25_VALUES_IDLE = 9, | |
| + AX25_VALUES_N2 = 10, | |
| + AX25_VALUES_PACLEN = 11, | |
| + AX25_VALUES_PROTOCOL = 12, | |
| + AX25_VALUES_DS_TIMEOUT = 13, | |
| + AX25_MAX_VALUES = 14, | |
| }; | |
| enum { | |
| @@ -783,6 +873,15 @@ | |
| }; | |
| enum { | |
| + BDX_PCI_UNCORE_HA = 0, | |
| + BDX_PCI_UNCORE_IMC = 1, | |
| + BDX_PCI_UNCORE_IRP = 2, | |
| + BDX_PCI_UNCORE_QPI = 3, | |
| + BDX_PCI_UNCORE_R2PCIE = 4, | |
| + BDX_PCI_UNCORE_R3QPI = 5, | |
| +}; | |
| + | |
| +enum { | |
| BIAS = 2147483648, | |
| }; | |
| @@ -793,7 +892,7 @@ | |
| }; | |
| enum { | |
| - BIO_NO_PAGE_REF = 0, | |
| + BIO_PAGE_PINNED = 0, | |
| BIO_CLONED = 1, | |
| BIO_BOUNCED = 2, | |
| BIO_QUIET = 3, | |
| @@ -805,8 +904,9 @@ | |
| BIO_QOS_THROTTLED = 9, | |
| BIO_QOS_MERGED = 10, | |
| BIO_REMAPPED = 11, | |
| - BIO_ZONE_WRITE_LOCKED = 12, | |
| - BIO_FLAG_LAST = 13, | |
| + BIO_ZONE_WRITE_PLUGGING = 12, | |
| + BIO_EMULATES_ZONE_APPEND = 13, | |
| + BIO_FLAG_LAST = 14, | |
| }; | |
| enum { | |
| @@ -889,6 +989,13 @@ | |
| BPF_FIB_LOOKUP_SKIP_NEIGH = 4, | |
| BPF_FIB_LOOKUP_TBID = 8, | |
| BPF_FIB_LOOKUP_SRC = 16, | |
| + BPF_FIB_LOOKUP_MARK = 32, | |
| +}; | |
| + | |
| +enum { | |
| + BPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG = 1, | |
| + BPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL = 2, | |
| + BPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP = 4, | |
| }; | |
| enum { | |
| @@ -954,7 +1061,10 @@ | |
| BPF_F_INNER_MAP = 4096, | |
| BPF_F_LINK = 8192, | |
| BPF_F_PATH_FD = 16384, | |
| + BPF_F_VTYPE_BTF_OBJ_FD = 32768, | |
| BPF_F_TOKEN_FD = 65536, | |
| + BPF_F_SEGV_ON_FAULT = 131072, | |
| + BPF_F_NO_USER_CONV = 262144, | |
| }; | |
| enum { | |
| @@ -1060,6 +1170,10 @@ | |
| }; | |
| enum { | |
| + BPF_SKEL_KERNEL = 1, | |
| +}; | |
| + | |
| +enum { | |
| BPF_SK_LOOKUP_F_REPLACE = 1, | |
| BPF_SK_LOOKUP_F_NO_REUSEPORT = 2, | |
| }; | |
| @@ -1113,7 +1227,8 @@ | |
| BPF_TCP_LISTEN = 10, | |
| BPF_TCP_CLOSING = 11, | |
| BPF_TCP_NEW_SYN_RECV = 12, | |
| - BPF_TCP_MAX_STATES = 13, | |
| + BPF_TCP_BOUND_INACTIVE = 13, | |
| + BPF_TCP_MAX_STATES = 14, | |
| }; | |
| enum { | |
| @@ -1126,6 +1241,131 @@ | |
| }; | |
| enum { | |
| + BRIDGE_QUERIER_UNSPEC = 0, | |
| + BRIDGE_QUERIER_IP_ADDRESS = 1, | |
| + BRIDGE_QUERIER_IP_PORT = 2, | |
| + BRIDGE_QUERIER_IP_OTHER_TIMER = 3, | |
| + BRIDGE_QUERIER_PAD = 4, | |
| + BRIDGE_QUERIER_IPV6_ADDRESS = 5, | |
| + BRIDGE_QUERIER_IPV6_PORT = 6, | |
| + BRIDGE_QUERIER_IPV6_OTHER_TIMER = 7, | |
| + __BRIDGE_QUERIER_MAX = 8, | |
| +}; | |
| + | |
| +enum { | |
| + BRIDGE_VLANDB_DUMP_UNSPEC = 0, | |
| + BRIDGE_VLANDB_DUMP_FLAGS = 1, | |
| + __BRIDGE_VLANDB_DUMP_MAX = 2, | |
| +}; | |
| + | |
| +enum { | |
| + BRIDGE_VLANDB_ENTRY_UNSPEC = 0, | |
| + BRIDGE_VLANDB_ENTRY_INFO = 1, | |
| + BRIDGE_VLANDB_ENTRY_RANGE = 2, | |
| + BRIDGE_VLANDB_ENTRY_STATE = 3, | |
| + BRIDGE_VLANDB_ENTRY_TUNNEL_INFO = 4, | |
| + BRIDGE_VLANDB_ENTRY_STATS = 5, | |
| + BRIDGE_VLANDB_ENTRY_MCAST_ROUTER = 6, | |
| + BRIDGE_VLANDB_ENTRY_MCAST_N_GROUPS = 7, | |
| + BRIDGE_VLANDB_ENTRY_MCAST_MAX_GROUPS = 8, | |
| + BRIDGE_VLANDB_ENTRY_NEIGH_SUPPRESS = 9, | |
| + __BRIDGE_VLANDB_ENTRY_MAX = 10, | |
| +}; | |
| + | |
| +enum { | |
| + BRIDGE_VLANDB_GOPTS_UNSPEC = 0, | |
| + BRIDGE_VLANDB_GOPTS_ID = 1, | |
| + BRIDGE_VLANDB_GOPTS_RANGE = 2, | |
| + BRIDGE_VLANDB_GOPTS_MCAST_SNOOPING = 3, | |
| + BRIDGE_VLANDB_GOPTS_MCAST_IGMP_VERSION = 4, | |
| + BRIDGE_VLANDB_GOPTS_MCAST_MLD_VERSION = 5, | |
| + BRIDGE_VLANDB_GOPTS_MCAST_LAST_MEMBER_CNT = 6, | |
| + BRIDGE_VLANDB_GOPTS_MCAST_STARTUP_QUERY_CNT = 7, | |
| + BRIDGE_VLANDB_GOPTS_MCAST_LAST_MEMBER_INTVL = 8, | |
| + BRIDGE_VLANDB_GOPTS_PAD = 9, | |
| + BRIDGE_VLANDB_GOPTS_MCAST_MEMBERSHIP_INTVL = 10, | |
| + BRIDGE_VLANDB_GOPTS_MCAST_QUERIER_INTVL = 11, | |
| + BRIDGE_VLANDB_GOPTS_MCAST_QUERY_INTVL = 12, | |
| + BRIDGE_VLANDB_GOPTS_MCAST_QUERY_RESPONSE_INTVL = 13, | |
| + BRIDGE_VLANDB_GOPTS_MCAST_STARTUP_QUERY_INTVL = 14, | |
| + BRIDGE_VLANDB_GOPTS_MCAST_QUERIER = 15, | |
| + BRIDGE_VLANDB_GOPTS_MCAST_ROUTER_PORTS = 16, | |
| + BRIDGE_VLANDB_GOPTS_MCAST_QUERIER_STATE = 17, | |
| + BRIDGE_VLANDB_GOPTS_MSTI = 18, | |
| + __BRIDGE_VLANDB_GOPTS_MAX = 19, | |
| +}; | |
| + | |
| +enum { | |
| + BRIDGE_VLANDB_STATS_UNSPEC = 0, | |
| + BRIDGE_VLANDB_STATS_RX_BYTES = 1, | |
| + BRIDGE_VLANDB_STATS_RX_PACKETS = 2, | |
| + BRIDGE_VLANDB_STATS_TX_BYTES = 3, | |
| + BRIDGE_VLANDB_STATS_TX_PACKETS = 4, | |
| + BRIDGE_VLANDB_STATS_PAD = 5, | |
| + __BRIDGE_VLANDB_STATS_MAX = 6, | |
| +}; | |
| + | |
| +enum { | |
| + BRIDGE_VLANDB_TINFO_UNSPEC = 0, | |
| + BRIDGE_VLANDB_TINFO_ID = 1, | |
| + BRIDGE_VLANDB_TINFO_CMD = 2, | |
| + __BRIDGE_VLANDB_TINFO_MAX = 3, | |
| +}; | |
| + | |
| +enum { | |
| + BRIDGE_VLANDB_UNSPEC = 0, | |
| + BRIDGE_VLANDB_ENTRY = 1, | |
| + BRIDGE_VLANDB_GLOBAL_OPTIONS = 2, | |
| + __BRIDGE_VLANDB_MAX = 3, | |
| +}; | |
| + | |
| +enum { | |
| + BRIDGE_XSTATS_UNSPEC = 0, | |
| + BRIDGE_XSTATS_VLAN = 1, | |
| + BRIDGE_XSTATS_MCAST = 2, | |
| + BRIDGE_XSTATS_PAD = 3, | |
| + BRIDGE_XSTATS_STP = 4, | |
| + __BRIDGE_XSTATS_MAX = 5, | |
| +}; | |
| + | |
| +enum { | |
| + BR_FDB_LOCAL = 0, | |
| + BR_FDB_STATIC = 1, | |
| + BR_FDB_STICKY = 2, | |
| + BR_FDB_ADDED_BY_USER = 3, | |
| + BR_FDB_ADDED_BY_EXT_LEARN = 4, | |
| + BR_FDB_OFFLOADED = 5, | |
| + BR_FDB_NOTIFY = 6, | |
| + BR_FDB_NOTIFY_INACTIVE = 7, | |
| + BR_FDB_LOCKED = 8, | |
| + BR_FDB_DYNAMIC_LEARNED = 9, | |
| +}; | |
| + | |
| +enum { | |
| + BR_GROUPFWD_STP = 1, | |
| + BR_GROUPFWD_MACPAUSE = 2, | |
| + BR_GROUPFWD_LACP = 4, | |
| +}; | |
| + | |
| +enum { | |
| + BR_MCAST_DIR_RX = 0, | |
| + BR_MCAST_DIR_TX = 1, | |
| + BR_MCAST_DIR_SIZE = 2, | |
| +}; | |
| + | |
| +enum { | |
| + BR_VLFLAG_PER_PORT_STATS = 1, | |
| + BR_VLFLAG_ADDED_BY_SWITCHDEV = 2, | |
| + BR_VLFLAG_MCAST_ENABLED = 4, | |
| + BR_VLFLAG_GLOBAL_MCAST_ENABLED = 8, | |
| + BR_VLFLAG_NEIGH_SUPPRESS_ENABLED = 16, | |
| +}; | |
| + | |
| +enum { | |
| + BTF_FIELDS_MAX = 11, | |
| +}; | |
| + | |
| +enum { | |
| BTF_FIELD_IGNORE = 0, | |
| BTF_FIELD_FOUND = 1, | |
| }; | |
| @@ -1239,19 +1479,18 @@ | |
| BTRFS_FS_NEED_TRANS_COMMIT = 23, | |
| BTRFS_FS_ACTIVE_ZONE_TRACKING = 24, | |
| BTRFS_FS_FEATURE_CHANGED = 25, | |
| - BTRFS_FS_WRITE_TIME_CHECKS_DISABLED = 26, | |
| + BTRFS_FS_UNALIGNED_TREE_BLOCK = 26, | |
| }; | |
| enum { | |
| - BTRFS_FS_STATE_ERROR = 0, | |
| - BTRFS_FS_STATE_REMOUNTING = 1, | |
| - BTRFS_FS_STATE_RO = 2, | |
| - BTRFS_FS_STATE_TRANS_ABORTED = 3, | |
| - BTRFS_FS_STATE_DEV_REPLACING = 4, | |
| - BTRFS_FS_STATE_DUMMY_FS_INFO = 5, | |
| - BTRFS_FS_STATE_NO_CSUMS = 6, | |
| - BTRFS_FS_STATE_LOG_CLEANUP_ERROR = 7, | |
| - BTRFS_FS_STATE_COUNT = 8, | |
| + BTRFS_FS_STATE_REMOUNTING = 0, | |
| + BTRFS_FS_STATE_RO = 1, | |
| + BTRFS_FS_STATE_TRANS_ABORTED = 2, | |
| + BTRFS_FS_STATE_DEV_REPLACING = 3, | |
| + BTRFS_FS_STATE_DUMMY_FS_INFO = 4, | |
| + BTRFS_FS_STATE_NO_CSUMS = 5, | |
| + BTRFS_FS_STATE_LOG_CLEANUP_ERROR = 6, | |
| + BTRFS_FS_STATE_COUNT = 7, | |
| }; | |
| enum { | |
| @@ -1261,14 +1500,13 @@ | |
| BTRFS_INODE_HAS_ASYNC_EXTENT = 3, | |
| BTRFS_INODE_NEEDS_FULL_SYNC = 4, | |
| BTRFS_INODE_COPY_EVERYTHING = 5, | |
| - BTRFS_INODE_IN_DELALLOC_LIST = 6, | |
| - BTRFS_INODE_HAS_PROPS = 7, | |
| - BTRFS_INODE_SNAPSHOT_FLUSH = 8, | |
| - BTRFS_INODE_NO_XATTRS = 9, | |
| - BTRFS_INODE_NO_DELALLOC_FLUSH = 10, | |
| - BTRFS_INODE_VERITY_IN_PROGRESS = 11, | |
| - BTRFS_INODE_FREE_SPACE_INODE = 12, | |
| - BTRFS_INODE_APPEND_WRITE = 13, | |
| + BTRFS_INODE_HAS_PROPS = 6, | |
| + BTRFS_INODE_SNAPSHOT_FLUSH = 7, | |
| + BTRFS_INODE_NO_XATTRS = 8, | |
| + BTRFS_INODE_NO_DELALLOC_FLUSH = 9, | |
| + BTRFS_INODE_VERITY_IN_PROGRESS = 10, | |
| + BTRFS_INODE_FREE_SPACE_INODE = 11, | |
| + BTRFS_INODE_NO_CAP_XATTR = 12, | |
| }; | |
| enum { | |
| @@ -1291,19 +1529,18 @@ | |
| BTRFS_MOUNT_AUTO_DEFRAG = 65536, | |
| BTRFS_MOUNT_USEBACKUPROOT = 131072, | |
| BTRFS_MOUNT_SKIP_BALANCE = 262144, | |
| - BTRFS_MOUNT_CHECK_INTEGRITY = 524288, | |
| - BTRFS_MOUNT_CHECK_INTEGRITY_DATA = 1048576, | |
| - BTRFS_MOUNT_PANIC_ON_FATAL_ERROR = 2097152, | |
| - BTRFS_MOUNT_RESCAN_UUID_TREE = 4194304, | |
| - BTRFS_MOUNT_FRAGMENT_DATA = 8388608, | |
| - BTRFS_MOUNT_FRAGMENT_METADATA = 16777216, | |
| - BTRFS_MOUNT_FREE_SPACE_TREE = 33554432, | |
| - BTRFS_MOUNT_NOLOGREPLAY = 67108864, | |
| - BTRFS_MOUNT_REF_VERIFY = 134217728, | |
| - BTRFS_MOUNT_DISCARD_ASYNC = 268435456, | |
| - BTRFS_MOUNT_IGNOREBADROOTS = 536870912, | |
| - BTRFS_MOUNT_IGNOREDATACSUMS = 1073741824, | |
| - BTRFS_MOUNT_NODISCARD = 2147483648, | |
| + BTRFS_MOUNT_PANIC_ON_FATAL_ERROR = 524288, | |
| + BTRFS_MOUNT_RESCAN_UUID_TREE = 1048576, | |
| + BTRFS_MOUNT_FRAGMENT_DATA = 2097152, | |
| + BTRFS_MOUNT_FRAGMENT_METADATA = 4194304, | |
| + BTRFS_MOUNT_FREE_SPACE_TREE = 8388608, | |
| + BTRFS_MOUNT_NOLOGREPLAY = 16777216, | |
| + BTRFS_MOUNT_REF_VERIFY = 33554432, | |
| + BTRFS_MOUNT_DISCARD_ASYNC = 67108864, | |
| + BTRFS_MOUNT_IGNOREBADROOTS = 134217728, | |
| + BTRFS_MOUNT_IGNOREDATACSUMS = 268435456, | |
| + BTRFS_MOUNT_NODISCARD = 536870912, | |
| + BTRFS_MOUNT_NOSPACECACHE = 1073741824, | |
| }; | |
| enum { | |
| @@ -1410,8 +1647,29 @@ | |
| }; | |
| enum { | |
| - CEL_UUID = 0, | |
| - VENDOR_DEBUG_UUID = 1, | |
| + CACHE_VALID = 0, | |
| + CACHE_NEGATIVE = 1, | |
| + CACHE_PENDING = 2, | |
| + CACHE_CLEANED = 3, | |
| +}; | |
| + | |
| +enum { | |
| + CAM_DIR_IN = 2, | |
| + CAM_DIR_OUT = 1, | |
| + CAM_DIR_NONE = 3, | |
| +}; | |
| + | |
| +enum { | |
| + CARDBUS_TYPE_DEFAULT = -1, | |
| + CARDBUS_TYPE_TI = 0, | |
| + CARDBUS_TYPE_TI113X = 1, | |
| + CARDBUS_TYPE_TI12XX = 2, | |
| + CARDBUS_TYPE_TI1250 = 3, | |
| + CARDBUS_TYPE_RICOH = 4, | |
| + CARDBUS_TYPE_TOPIC95 = 5, | |
| + CARDBUS_TYPE_TOPIC97 = 6, | |
| + CARDBUS_TYPE_O2MICRO = 7, | |
| + CARDBUS_TYPE_ENE = 8, | |
| }; | |
| enum { | |
| @@ -1421,7 +1679,6 @@ | |
| CFTYPE_NO_PREFIX = 8, | |
| CFTYPE_WORLD_WRITABLE = 16, | |
| CFTYPE_DEBUG = 32, | |
| - CFTYPE_HIDDEN = 64, | |
| __CFTYPE_ONLY_ON_DFL = 65536, | |
| __CFTYPE_NOT_ON_DFL = 131072, | |
| __CFTYPE_ADDED = 262144, | |
| @@ -1466,28 +1723,9 @@ | |
| }; | |
| enum { | |
| - CMCI_STORM_NONE = 0, | |
| - CMCI_STORM_ACTIVE = 1, | |
| - CMCI_STORM_SUBSIDED = 2, | |
| -}; | |
| - | |
| -enum { | |
| - CMD_ALLOWED_OPCODE_ALL = 0, | |
| -}; | |
| - | |
| -enum { | |
| - CMD_IF_REV = 5, | |
| -}; | |
| - | |
| -enum { | |
| - CMD_MODE_POLLING = 0, | |
| - CMD_MODE_EVENTS = 1, | |
| -}; | |
| - | |
| -enum { | |
| - CMD_OWNER_SW = 0, | |
| - CMD_OWNER_HW = 1, | |
| - CMD_STATUS_SUCCESS = 0, | |
| + CLEAN = 0, | |
| + UPDATE_IN_PROGRESS = 1, | |
| + DIRTY = 2, | |
| }; | |
| enum { | |
| @@ -1513,62 +1751,6 @@ | |
| }; | |
| enum { | |
| - COOKIE_KEY_LABEL_LEN = 8, | |
| -}; | |
| - | |
| -enum { | |
| - COST_CTRL = 0, | |
| - COST_MODEL = 1, | |
| - NR_COST_CTRL_PARAMS = 2, | |
| -}; | |
| - | |
| -enum { | |
| - CPER_SEV_RECOVERABLE = 0, | |
| - CPER_SEV_FATAL = 1, | |
| - CPER_SEV_CORRECTED = 2, | |
| - CPER_SEV_INFORMATIONAL = 3, | |
| -}; | |
| - | |
| -enum { | |
| - CQE_L2_OK = 1, | |
| - CQE_L3_OK = 2, | |
| - CQE_L4_OK = 4, | |
| -}; | |
| - | |
| -enum { | |
| - CQE_L4_HDR_TYPE_NONE = 0, | |
| - CQE_L4_HDR_TYPE_TCP_NO_ACK = 1, | |
| - CQE_L4_HDR_TYPE_UDP = 2, | |
| - CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 3, | |
| - CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 4, | |
| -}; | |
| - | |
| -enum { | |
| - CQE_RSS_HTYPE_IP = 12, | |
| - CQE_RSS_IP_NONE = 0, | |
| - CQE_RSS_IPV4 = 1, | |
| - CQE_RSS_IPV6 = 2, | |
| - CQE_RSS_RESERVED = 3, | |
| - CQE_RSS_HTYPE_L4 = 192, | |
| - CQE_RSS_L4_NONE = 0, | |
| - CQE_RSS_L4_TCP = 1, | |
| - CQE_RSS_L4_UDP = 2, | |
| - CQE_RSS_L4_IPSEC = 3, | |
| -}; | |
| - | |
| -enum { | |
| - CQE_STRIDE_64 = 0, | |
| - CQE_STRIDE_128 = 1, | |
| - CQE_STRIDE_128_PAD = 2, | |
| -}; | |
| - | |
| -enum { | |
| - CQ_PID = 0, | |
| - CQ_NUM_CQES = 1, | |
| - CQ_LOG_PG_SZ = 2, | |
| -}; | |
| - | |
| -enum { | |
| CRNG_EMPTY = 0, | |
| CRNG_EARLY = 1, | |
| CRNG_READY = 2, | |
| @@ -1587,6 +1769,11 @@ | |
| }; | |
| enum { | |
| + CRYPTO_AUTHENC_KEYA_UNSPEC = 0, | |
| + CRYPTO_AUTHENC_KEYA_PARAM = 1, | |
| +}; | |
| + | |
| +enum { | |
| CRYPTO_MSG_ALG_REQUEST = 0, | |
| CRYPTO_MSG_ALG_REGISTER = 1, | |
| CRYPTO_MSG_ALG_LOADED = 2, | |
| @@ -1607,6 +1794,63 @@ | |
| }; | |
| enum { | |
| + CSI_DEC_hl_CURSOR_KEYS = 1, | |
| + CSI_DEC_hl_132_COLUMNS = 3, | |
| + CSI_DEC_hl_REVERSE_VIDEO = 5, | |
| + CSI_DEC_hl_ORIGIN_MODE = 6, | |
| + CSI_DEC_hl_AUTOWRAP = 7, | |
| + CSI_DEC_hl_AUTOREPEAT = 8, | |
| + CSI_DEC_hl_MOUSE_X10 = 9, | |
| + CSI_DEC_hl_SHOW_CURSOR = 25, | |
| + CSI_DEC_hl_MOUSE_VT200 = 1000, | |
| +}; | |
| + | |
| +enum { | |
| + CSI_K_CURSOR_TO_LINEEND = 0, | |
| + CSI_K_LINESTART_TO_CURSOR = 1, | |
| + CSI_K_LINE = 2, | |
| +}; | |
| + | |
| +enum { | |
| + CSI_hl_DISPLAY_CTRL = 3, | |
| + CSI_hl_INSERT = 4, | |
| + CSI_hl_AUTO_NL = 20, | |
| +}; | |
| + | |
| +enum { | |
| + CSI_m_DEFAULT = 0, | |
| + CSI_m_BOLD = 1, | |
| + CSI_m_HALF_BRIGHT = 2, | |
| + CSI_m_ITALIC = 3, | |
| + CSI_m_UNDERLINE = 4, | |
| + CSI_m_BLINK = 5, | |
| + CSI_m_REVERSE = 7, | |
| + CSI_m_PRI_FONT = 10, | |
| + CSI_m_ALT_FONT1 = 11, | |
| + CSI_m_ALT_FONT2 = 12, | |
| + CSI_m_DOUBLE_UNDERLINE = 21, | |
| + CSI_m_NORMAL_INTENSITY = 22, | |
| + CSI_m_NO_ITALIC = 23, | |
| + CSI_m_NO_UNDERLINE = 24, | |
| + CSI_m_NO_BLINK = 25, | |
| + CSI_m_NO_REVERSE = 27, | |
| + CSI_m_FG_COLOR_BEG = 30, | |
| + CSI_m_FG_COLOR_END = 37, | |
| + CSI_m_FG_COLOR = 38, | |
| + CSI_m_DEFAULT_FG_COLOR = 39, | |
| + CSI_m_BG_COLOR_BEG = 40, | |
| + CSI_m_BG_COLOR_END = 47, | |
| + CSI_m_BG_COLOR = 48, | |
| + CSI_m_DEFAULT_BG_COLOR = 49, | |
| + CSI_m_BRIGHT_FG_COLOR_BEG = 90, | |
| + CSI_m_BRIGHT_FG_COLOR_END = 97, | |
| + CSI_m_BRIGHT_FG_COLOR_OFF = 60, | |
| + CSI_m_BRIGHT_BG_COLOR_BEG = 100, | |
| + CSI_m_BRIGHT_BG_COLOR_END = 107, | |
| + CSI_m_BRIGHT_BG_COLOR_OFF = 60, | |
| +}; | |
| + | |
| +enum { | |
| CSS_NO_REF = 1, | |
| CSS_ONLINE = 2, | |
| CSS_RELEASED = 4, | |
| @@ -1673,68 +1917,17 @@ | |
| }; | |
| enum { | |
| - CXL_MBOX_CMD_RC_SUCCESS = 0, | |
| - CXL_MBOX_CMD_RC_BACKGROUND = 1, | |
| - CXL_MBOX_CMD_RC_INPUT = 2, | |
| - CXL_MBOX_CMD_RC_UNSUPPORTED = 3, | |
| - CXL_MBOX_CMD_RC_INTERNAL = 4, | |
| - CXL_MBOX_CMD_RC_RETRY = 5, | |
| - CXL_MBOX_CMD_RC_BUSY = 6, | |
| - CXL_MBOX_CMD_RC_MEDIADISABLED = 7, | |
| - CXL_MBOX_CMD_RC_FWINPROGRESS = 8, | |
| - CXL_MBOX_CMD_RC_FWOOO = 9, | |
| - CXL_MBOX_CMD_RC_FWAUTH = 10, | |
| - CXL_MBOX_CMD_RC_FWSLOT = 11, | |
| - CXL_MBOX_CMD_RC_FWROLLBACK = 12, | |
| - CXL_MBOX_CMD_RC_FWRESET = 13, | |
| - CXL_MBOX_CMD_RC_HANDLE = 14, | |
| - CXL_MBOX_CMD_RC_PADDR = 15, | |
| - CXL_MBOX_CMD_RC_POISONLMT = 16, | |
| - CXL_MBOX_CMD_RC_MEDIAFAILURE = 17, | |
| - CXL_MBOX_CMD_RC_ABORT = 18, | |
| - CXL_MBOX_CMD_RC_SECURITY = 19, | |
| - CXL_MBOX_CMD_RC_PASSPHRASE = 20, | |
| - CXL_MBOX_CMD_RC_MBUNSUPPORTED = 21, | |
| - CXL_MBOX_CMD_RC_PAYLOADLEN = 22, | |
| - CXL_MBOX_CMD_RC_LOG = 23, | |
| - CXL_MBOX_CMD_RC_INTERRUPTED = 24, | |
| - CXL_MBOX_CMD_RC_FEATUREVERSION = 25, | |
| - CXL_MBOX_CMD_RC_FEATURESELVALUE = 26, | |
| - CXL_MBOX_CMD_RC_FEATURETRANSFERIP = 27, | |
| - CXL_MBOX_CMD_RC_FEATURETRANSFEROOO = 28, | |
| - CXL_MBOX_CMD_RC_RESOURCEEXHAUSTED = 29, | |
| - CXL_MBOX_CMD_RC_EXTLIST = 30, | |
| + DAD_PROCESS = 0, | |
| + DAD_BEGIN = 1, | |
| + DAD_ABORT = 2, | |
| }; | |
| enum { | |
| - CXL_MEM_COMMAND_ID_INVALID = 0, | |
| - CXL_MEM_COMMAND_ID_IDENTIFY = 1, | |
| - CXL_MEM_COMMAND_ID_RAW = 2, | |
| - CXL_MEM_COMMAND_ID_GET_SUPPORTED_LOGS = 3, | |
| - CXL_MEM_COMMAND_ID_GET_FW_INFO = 4, | |
| - CXL_MEM_COMMAND_ID_GET_PARTITION_INFO = 5, | |
| - CXL_MEM_COMMAND_ID_GET_LSA = 6, | |
| - CXL_MEM_COMMAND_ID_GET_HEALTH_INFO = 7, | |
| - CXL_MEM_COMMAND_ID_GET_LOG = 8, | |
| - CXL_MEM_COMMAND_ID_SET_PARTITION_INFO = 9, | |
| - CXL_MEM_COMMAND_ID_SET_LSA = 10, | |
| - CXL_MEM_COMMAND_ID_GET_ALERT_CONFIG = 11, | |
| - CXL_MEM_COMMAND_ID_SET_ALERT_CONFIG = 12, | |
| - CXL_MEM_COMMAND_ID_GET_SHUTDOWN_STATE = 13, | |
| - CXL_MEM_COMMAND_ID_SET_SHUTDOWN_STATE = 14, | |
| - CXL_MEM_DEPRECATED_ID_GET_POISON = 15, | |
| - CXL_MEM_DEPRECATED_ID_INJECT_POISON = 16, | |
| - CXL_MEM_DEPRECATED_ID_CLEAR_POISON = 17, | |
| - CXL_MEM_COMMAND_ID_GET_SCAN_MEDIA_CAPS = 18, | |
| - CXL_MEM_DEPRECATED_ID_SCAN_MEDIA = 19, | |
| - CXL_MEM_DEPRECATED_ID_GET_SCAN_MEDIA = 20, | |
| - CXL_MEM_COMMAND_ID_MAX = 21, | |
| + DD_DIR_COUNT = 2, | |
| }; | |
| enum { | |
| - DAD_PROCESS = 0, | |
| - DAD_BEGIN = 1, | |
| - DAD_ABORT = 2, | |
| + DD_PRIO_COUNT = 3, | |
| }; | |
| enum { | |
| @@ -1802,7 +1995,8 @@ | |
| DEVCONF_IOAM6_ID_WIDE = 55, | |
| DEVCONF_NDISC_EVICT_NOCARRIER = 56, | |
| DEVCONF_ACCEPT_UNTRACKED_NA = 57, | |
| - DEVCONF_MAX = 58, | |
| + DEVCONF_ACCEPT_RA_MIN_LFT = 58, | |
| + DEVCONF_MAX = 59, | |
| }; | |
| enum { | |
| @@ -1829,6 +2023,10 @@ | |
| }; | |
| enum { | |
| + DIR_OFFSET_MIN = 2, | |
| +}; | |
| + | |
| +enum { | |
| DISCOVERED = 16, | |
| EXPLORED = 32, | |
| FALLTHROUGH = 1, | |
| @@ -1847,37 +2045,6 @@ | |
| }; | |
| enum { | |
| - DM_IO_ACCOUNTED = 0, | |
| - DM_IO_WAS_SPLIT = 1, | |
| -}; | |
| - | |
| -enum { | |
| - DM_TIO_INSIDE_DM_IO = 0, | |
| - DM_TIO_IS_DUPLICATE_BIO = 1, | |
| -}; | |
| - | |
| -enum { | |
| - DM_VERSION_CMD = 0, | |
| - DM_REMOVE_ALL_CMD = 1, | |
| - DM_LIST_DEVICES_CMD = 2, | |
| - DM_DEV_CREATE_CMD = 3, | |
| - DM_DEV_REMOVE_CMD = 4, | |
| - DM_DEV_RENAME_CMD = 5, | |
| - DM_DEV_SUSPEND_CMD = 6, | |
| - DM_DEV_STATUS_CMD = 7, | |
| - DM_DEV_WAIT_CMD = 8, | |
| - DM_TABLE_LOAD_CMD = 9, | |
| - DM_TABLE_CLEAR_CMD = 10, | |
| - DM_TABLE_DEPS_CMD = 11, | |
| - DM_TABLE_STATUS_CMD = 12, | |
| - DM_LIST_VERSIONS_CMD = 13, | |
| - DM_TARGET_MSG_CMD = 14, | |
| - DM_DEV_SET_GEOMETRY_CMD = 15, | |
| - DM_DEV_ARM_POLL_CMD = 16, | |
| - DM_GET_TARGET_VERSION_CMD = 17, | |
| -}; | |
| - | |
| -enum { | |
| DONE_EXPLORING = 0, | |
| KEEP_EXPLORING = 1, | |
| }; | |
| @@ -1911,6 +2078,11 @@ | |
| }; | |
| enum { | |
| + D_SHIFT_LEFT = 0, | |
| + D_SHIFT_RIGHT = 1, | |
| +}; | |
| + | |
| +enum { | |
| EC_FLAGS_QUERY_ENABLED = 0, | |
| EC_FLAGS_EVENT_HANDLER_INSTALLED = 1, | |
| EC_FLAGS_EC_HANDLER_INSTALLED = 2, | |
| @@ -1922,11 +2094,6 @@ | |
| }; | |
| enum { | |
| - EC_FUNCTION_MASK = 32768, | |
| - RELEASE_ALL_PAGES_MASK = 16384, | |
| -}; | |
| - | |
| -enum { | |
| EI_ETYPE_NULL = 0, | |
| EI_ETYPE_ERRNO = 1, | |
| EI_ETYPE_ERRNO_NULL = 2, | |
| @@ -1948,12 +2115,6 @@ | |
| }; | |
| enum { | |
| - EQ_NUM_EQES = 0, | |
| - EQ_INTR = 1, | |
| - EQ_LOG_PG_SZ = 2, | |
| -}; | |
| - | |
| -enum { | |
| ERASE = 0, | |
| WERASE = 1, | |
| KILL = 2, | |
| @@ -1969,25 +2130,6 @@ | |
| }; | |
| enum { | |
| - ESnormal = 0, | |
| - ESesc = 1, | |
| - ESsquare = 2, | |
| - ESgetpars = 3, | |
| - ESfunckey = 4, | |
| - EShash = 5, | |
| - ESsetG0 = 6, | |
| - ESsetG1 = 7, | |
| - ESpercent = 8, | |
| - EScsiignore = 9, | |
| - ESnonstd = 10, | |
| - ESpalette = 11, | |
| - ESosc = 12, | |
| - ESapc = 13, | |
| - ESpm = 14, | |
| - ESdcs = 15, | |
| -}; | |
| - | |
| -enum { | |
| ETHTOOL_A_BITSET_BITS_UNSPEC = 0, | |
| ETHTOOL_A_BITSET_BITS_BIT = 1, | |
| __ETHTOOL_A_BITSET_BITS_CNT = 2, | |
| @@ -2225,8 +2367,9 @@ | |
| ETHTOOL_A_HEADER_DEV_INDEX = 1, | |
| ETHTOOL_A_HEADER_DEV_NAME = 2, | |
| ETHTOOL_A_HEADER_FLAGS = 3, | |
| - __ETHTOOL_A_HEADER_CNT = 4, | |
| - ETHTOOL_A_HEADER_MAX = 3, | |
| + ETHTOOL_A_HEADER_PHY_INDEX = 4, | |
| + __ETHTOOL_A_HEADER_CNT = 5, | |
| + ETHTOOL_A_HEADER_MAX = 4, | |
| }; | |
| enum { | |
| @@ -2381,8 +2524,11 @@ | |
| ETHTOOL_A_PODL_PSE_ADMIN_STATE = 2, | |
| ETHTOOL_A_PODL_PSE_ADMIN_CONTROL = 3, | |
| ETHTOOL_A_PODL_PSE_PW_D_STATUS = 4, | |
| - __ETHTOOL_A_PSE_CNT = 5, | |
| - ETHTOOL_A_PSE_MAX = 4, | |
| + ETHTOOL_A_C33_PSE_ADMIN_STATE = 5, | |
| + ETHTOOL_A_C33_PSE_ADMIN_CONTROL = 6, | |
| + ETHTOOL_A_C33_PSE_PW_D_STATUS = 7, | |
| + __ETHTOOL_A_PSE_CNT = 8, | |
| + ETHTOOL_A_PSE_MAX = 7, | |
| }; | |
| enum { | |
| @@ -2414,8 +2560,9 @@ | |
| ETHTOOL_A_RSS_HFUNC = 3, | |
| ETHTOOL_A_RSS_INDIR = 4, | |
| ETHTOOL_A_RSS_HKEY = 5, | |
| - __ETHTOOL_A_RSS_CNT = 6, | |
| - ETHTOOL_A_RSS_MAX = 5, | |
| + ETHTOOL_A_RSS_INPUT_XFRM = 6, | |
| + __ETHTOOL_A_RSS_CNT = 7, | |
| + ETHTOOL_A_RSS_MAX = 6, | |
| }; | |
| enum { | |
| @@ -2646,6 +2793,55 @@ | |
| }; | |
| enum { | |
| + ETHTOOL_MSG_USER_NONE = 0, | |
| + ETHTOOL_MSG_STRSET_GET = 1, | |
| + ETHTOOL_MSG_LINKINFO_GET = 2, | |
| + ETHTOOL_MSG_LINKINFO_SET = 3, | |
| + ETHTOOL_MSG_LINKMODES_GET = 4, | |
| + ETHTOOL_MSG_LINKMODES_SET = 5, | |
| + ETHTOOL_MSG_LINKSTATE_GET = 6, | |
| + ETHTOOL_MSG_DEBUG_GET = 7, | |
| + ETHTOOL_MSG_DEBUG_SET = 8, | |
| + ETHTOOL_MSG_WOL_GET = 9, | |
| + ETHTOOL_MSG_WOL_SET = 10, | |
| + ETHTOOL_MSG_FEATURES_GET = 11, | |
| + ETHTOOL_MSG_FEATURES_SET = 12, | |
| + ETHTOOL_MSG_PRIVFLAGS_GET = 13, | |
| + ETHTOOL_MSG_PRIVFLAGS_SET = 14, | |
| + ETHTOOL_MSG_RINGS_GET = 15, | |
| + ETHTOOL_MSG_RINGS_SET = 16, | |
| + ETHTOOL_MSG_CHANNELS_GET = 17, | |
| + ETHTOOL_MSG_CHANNELS_SET = 18, | |
| + ETHTOOL_MSG_COALESCE_GET = 19, | |
| + ETHTOOL_MSG_COALESCE_SET = 20, | |
| + ETHTOOL_MSG_PAUSE_GET = 21, | |
| + ETHTOOL_MSG_PAUSE_SET = 22, | |
| + ETHTOOL_MSG_EEE_GET = 23, | |
| + ETHTOOL_MSG_EEE_SET = 24, | |
| + ETHTOOL_MSG_TSINFO_GET = 25, | |
| + ETHTOOL_MSG_CABLE_TEST_ACT = 26, | |
| + ETHTOOL_MSG_CABLE_TEST_TDR_ACT = 27, | |
| + ETHTOOL_MSG_TUNNEL_INFO_GET = 28, | |
| + ETHTOOL_MSG_FEC_GET = 29, | |
| + ETHTOOL_MSG_FEC_SET = 30, | |
| + ETHTOOL_MSG_MODULE_EEPROM_GET = 31, | |
| + ETHTOOL_MSG_STATS_GET = 32, | |
| + ETHTOOL_MSG_PHC_VCLOCKS_GET = 33, | |
| + ETHTOOL_MSG_MODULE_GET = 34, | |
| + ETHTOOL_MSG_MODULE_SET = 35, | |
| + ETHTOOL_MSG_PSE_GET = 36, | |
| + ETHTOOL_MSG_PSE_SET = 37, | |
| + ETHTOOL_MSG_RSS_GET = 38, | |
| + ETHTOOL_MSG_PLCA_GET_CFG = 39, | |
| + ETHTOOL_MSG_PLCA_SET_CFG = 40, | |
| + ETHTOOL_MSG_PLCA_GET_STATUS = 41, | |
| + ETHTOOL_MSG_MM_GET = 42, | |
| + ETHTOOL_MSG_MM_SET = 43, | |
| + __ETHTOOL_MSG_USER_CNT = 44, | |
| + ETHTOOL_MSG_USER_MAX = 43, | |
| +}; | |
| + | |
| +enum { | |
| ETHTOOL_STATS_ETH_PHY = 0, | |
| ETHTOOL_STATS_ETH_MAC = 1, | |
| ETHTOOL_STATS_ETH_CTRL = 2, | |
| @@ -2674,6 +2870,13 @@ | |
| }; | |
| enum { | |
| + EVENTFS_SAVE_MODE = 65536, | |
| + EVENTFS_SAVE_UID = 131072, | |
| + EVENTFS_SAVE_GID = 262144, | |
| + EVENTFS_TOPLEVEL = 524288, | |
| +}; | |
| + | |
| +enum { | |
| EVENT_FILE_FL_ENABLED = 1, | |
| EVENT_FILE_FL_RECORDED_CMD = 2, | |
| EVENT_FILE_FL_RECORDED_TGID = 4, | |
| @@ -2685,6 +2888,7 @@ | |
| EVENT_FILE_FL_TRIGGER_COND = 256, | |
| EVENT_FILE_FL_PID_FILTER = 512, | |
| EVENT_FILE_FL_WAS_ENABLED = 1024, | |
| + EVENT_FILE_FL_FREED = 2048, | |
| }; | |
| enum { | |
| @@ -2699,6 +2903,7 @@ | |
| EVENT_FILE_FL_TRIGGER_COND_BIT = 8, | |
| EVENT_FILE_FL_PID_FILTER_BIT = 9, | |
| EVENT_FILE_FL_WAS_ENABLED_BIT = 10, | |
| + EVENT_FILE_FL_FREED_BIT = 11, | |
| }; | |
| enum { | |
| @@ -2758,8 +2963,7 @@ | |
| enum { | |
| EXT4_MF_MNTDIR_SAMPLED = 0, | |
| - EXT4_MF_FS_ABORTED = 1, | |
| - EXT4_MF_FC_INELIGIBLE = 2, | |
| + EXT4_MF_FC_INELIGIBLE = 1, | |
| }; | |
| enum { | |
| @@ -2789,17 +2993,8 @@ | |
| EXTENT_BUFFER_UNMAPPED = 8, | |
| EXTENT_BUFFER_IN_TREE = 9, | |
| EXTENT_BUFFER_WRITE_ERR = 10, | |
| - EXTENT_BUFFER_NO_CHECK = 11, | |
| -}; | |
| - | |
| -enum { | |
| - EXTENT_FLAG_PINNED = 0, | |
| - EXTENT_FLAG_COMPRESSED = 1, | |
| - EXTENT_FLAG_PREALLOC = 2, | |
| - EXTENT_FLAG_LOGGING = 3, | |
| - EXTENT_FLAG_FILLING = 4, | |
| - EXTENT_FLAG_FS_MAPPING = 5, | |
| - EXTENT_FLAG_MERGED = 6, | |
| + EXTENT_BUFFER_ZONED_ZEROOUT = 11, | |
| + EXTENT_BUFFER_READING = 12, | |
| }; | |
| enum { | |
| @@ -2819,20 +3014,32 @@ | |
| }; | |
| enum { | |
| - FAN_EVENT_INIT = 0, | |
| - FAN_EVENT_REPORTED = 1, | |
| - FAN_EVENT_ANSWERED = 2, | |
| - FAN_EVENT_CANCELED = 3, | |
| + FATTR4_MODE_UMASK = 81, | |
| }; | |
| enum { | |
| - FDB_BYPASS_PATH = 0, | |
| - FDB_TC_OFFLOAD = 1, | |
| - FDB_FT_OFFLOAD = 2, | |
| - FDB_TC_MISS = 3, | |
| - FDB_BR_OFFLOAD = 4, | |
| - FDB_SLOW_PATH = 5, | |
| - FDB_PER_VPORT = 6, | |
| + FBCON_LOGO_CANSHOW = -1, | |
| + FBCON_LOGO_DRAW = -2, | |
| + FBCON_LOGO_DONTSHOW = -3, | |
| +}; | |
| + | |
| +enum { | |
| + FB_BLANK_UNBLANK = 0, | |
| + FB_BLANK_NORMAL = 1, | |
| + FB_BLANK_VSYNC_SUSPEND = 2, | |
| + FB_BLANK_HSYNC_SUSPEND = 3, | |
| + FB_BLANK_POWERDOWN = 4, | |
| +}; | |
| + | |
| +enum { | |
| + FC = 0, | |
| + SPI = 1, | |
| + SAS = 2, | |
| +}; | |
| + | |
| +enum { | |
| + FDB_NOTIFY_BIT = 1, | |
| + FDB_NOTIFY_INACTIVE_BIT = 2, | |
| }; | |
| enum { | |
| @@ -2840,15 +3047,23 @@ | |
| }; | |
| enum { | |
| + FILEID_HIGH_OFF = 0, | |
| + FILEID_LOW_OFF = 1, | |
| + FILE_I_TYPE_OFF = 2, | |
| + EMBED_FH_OFF = 3, | |
| +}; | |
| + | |
| +enum { | |
| FILTER_OTHER = 0, | |
| FILTER_STATIC_STRING = 1, | |
| FILTER_DYN_STRING = 2, | |
| FILTER_RDYN_STRING = 3, | |
| FILTER_PTR_STRING = 4, | |
| FILTER_TRACE_FN = 5, | |
| - FILTER_COMM = 6, | |
| - FILTER_CPU = 7, | |
| - FILTER_STACKTRACE = 8, | |
| + FILTER_CPUMASK = 6, | |
| + FILTER_COMM = 7, | |
| + FILTER_CPU = 8, | |
| + FILTER_STACKTRACE = 9, | |
| }; | |
| enum { | |
| @@ -2857,20 +3072,23 @@ | |
| FILT_ERR_TOO_MANY_OPEN = 2, | |
| FILT_ERR_TOO_MANY_CLOSE = 3, | |
| FILT_ERR_MISSING_QUOTE = 4, | |
| - FILT_ERR_OPERAND_TOO_LONG = 5, | |
| - FILT_ERR_EXPECT_STRING = 6, | |
| - FILT_ERR_EXPECT_DIGIT = 7, | |
| - FILT_ERR_ILLEGAL_FIELD_OP = 8, | |
| - FILT_ERR_FIELD_NOT_FOUND = 9, | |
| - FILT_ERR_ILLEGAL_INTVAL = 10, | |
| - FILT_ERR_BAD_SUBSYS_FILTER = 11, | |
| - FILT_ERR_TOO_MANY_PREDS = 12, | |
| - FILT_ERR_INVALID_FILTER = 13, | |
| - FILT_ERR_IP_FIELD_ONLY = 14, | |
| - FILT_ERR_INVALID_VALUE = 15, | |
| - FILT_ERR_NO_FUNCTION = 16, | |
| - FILT_ERR_ERRNO = 17, | |
| - FILT_ERR_NO_FILTER = 18, | |
| + FILT_ERR_MISSING_BRACE_OPEN = 5, | |
| + FILT_ERR_MISSING_BRACE_CLOSE = 6, | |
| + FILT_ERR_OPERAND_TOO_LONG = 7, | |
| + FILT_ERR_EXPECT_STRING = 8, | |
| + FILT_ERR_EXPECT_DIGIT = 9, | |
| + FILT_ERR_ILLEGAL_FIELD_OP = 10, | |
| + FILT_ERR_FIELD_NOT_FOUND = 11, | |
| + FILT_ERR_ILLEGAL_INTVAL = 12, | |
| + FILT_ERR_BAD_SUBSYS_FILTER = 13, | |
| + FILT_ERR_TOO_MANY_PREDS = 14, | |
| + FILT_ERR_INVALID_FILTER = 15, | |
| + FILT_ERR_INVALID_CPULIST = 16, | |
| + FILT_ERR_IP_FIELD_ONLY = 17, | |
| + FILT_ERR_INVALID_VALUE = 18, | |
| + FILT_ERR_NO_FUNCTION = 19, | |
| + FILT_ERR_ERRNO = 20, | |
| + FILT_ERR_NO_FILTER = 21, | |
| }; | |
| enum { | |
| @@ -2880,12 +3098,9 @@ | |
| }; | |
| enum { | |
| - FLOW_ACT_NO_APPEND = 1, | |
| - FLOW_ACT_IGNORE_FLOW_LEVEL = 2, | |
| -}; | |
| - | |
| -enum { | |
| - FLOW_CONTEXT_HAS_TAG = 1, | |
| + FLASH_METHOD_UNKNOWN = 0, | |
| + FLASH_METHOD_A = 1, | |
| + FLASH_METHOD_B = 2, | |
| }; | |
| enum { | |
| @@ -2895,6 +3110,7 @@ | |
| FOLL_PIN = 524288, | |
| FOLL_FAST_ONLY = 1048576, | |
| FOLL_UNLOCKABLE = 2097152, | |
| + FOLL_MADV_POPULATE = 4194304, | |
| }; | |
| enum { | |
| @@ -2910,6 +3126,7 @@ | |
| FOLL_SPLIT_PMD = 512, | |
| FOLL_PCI_P2PDMA = 1024, | |
| FOLL_INTERRUPTIBLE = 2048, | |
| + FOLL_HONOR_NUMA_FAULT = 4096, | |
| }; | |
| enum { | |
| @@ -2919,6 +3136,40 @@ | |
| }; | |
| enum { | |
| + FOU_ATTR_UNSPEC = 0, | |
| + FOU_ATTR_PORT = 1, | |
| + FOU_ATTR_AF = 2, | |
| + FOU_ATTR_IPPROTO = 3, | |
| + FOU_ATTR_TYPE = 4, | |
| + FOU_ATTR_REMCSUM_NOPARTIAL = 5, | |
| + FOU_ATTR_LOCAL_V4 = 6, | |
| + FOU_ATTR_LOCAL_V6 = 7, | |
| + FOU_ATTR_PEER_V4 = 8, | |
| + FOU_ATTR_PEER_V6 = 9, | |
| + FOU_ATTR_PEER_PORT = 10, | |
| + FOU_ATTR_IFINDEX = 11, | |
| + __FOU_ATTR_MAX = 12, | |
| +}; | |
| + | |
| +enum { | |
| + FOU_CMD_UNSPEC = 0, | |
| + FOU_CMD_ADD = 1, | |
| + FOU_CMD_DEL = 2, | |
| + FOU_CMD_GET = 3, | |
| + __FOU_CMD_MAX = 4, | |
| +}; | |
| + | |
| +enum { | |
| + FOU_ENCAP_UNSPEC = 0, | |
| + FOU_ENCAP_DIRECT = 1, | |
| + FOU_ENCAP_GUE = 2, | |
| +}; | |
| + | |
| +enum { | |
| + FRACTION_DENOM = 128, | |
| +}; | |
| + | |
| +enum { | |
| FRA_UNSPEC = 0, | |
| FRA_DST = 1, | |
| FRA_SRC = 2, | |
| @@ -2989,6 +3240,7 @@ | |
| FTRACE_ITER_MOD = 32, | |
| FTRACE_ITER_ENABLED = 64, | |
| FTRACE_ITER_TOUCHED = 128, | |
| + FTRACE_ITER_ADDRS = 256, | |
| }; | |
| enum { | |
| @@ -3053,13 +3305,6 @@ | |
| }; | |
| enum { | |
| - GHES_SEV_NO = 0, | |
| - GHES_SEV_CORRECTED = 1, | |
| - GHES_SEV_RECOVERABLE = 2, | |
| - GHES_SEV_PANIC = 3, | |
| -}; | |
| - | |
| -enum { | |
| GO_BIT_TIMEOUT_MSECS = 10000, | |
| }; | |
| @@ -3114,7 +3359,8 @@ | |
| }; | |
| enum { | |
| - HANDSHAKE_DSCP = 136, | |
| + HANDSHAKE_NLGRP_NONE = 0, | |
| + HANDSHAKE_NLGRP_TLSHD = 1, | |
| }; | |
| enum { | |
| @@ -3122,6 +3368,34 @@ | |
| }; | |
| enum { | |
| + HBA_IU_TYPE_SCSI_CMD_REQ = 64, | |
| + HBA_IU_TYPE_SCSI_TM_REQ = 65, | |
| + HBA_IU_TYPE_SATA_REQ = 66, | |
| + HBA_IU_TYPE_RESP = 96, | |
| + HBA_IU_TYPE_COALESCED_RESP = 97, | |
| + HBA_IU_TYPE_INT_COALESCING_CFG_REQ = 112, | |
| +}; | |
| + | |
| +enum { | |
| + HBA_RESP_STAT_IO_ERROR = 1, | |
| + HBA_RESP_STAT_IO_ABORTED = 2, | |
| + HBA_RESP_STAT_NO_PATH_TO_DEVICE = 3, | |
| + HBA_RESP_STAT_INVALID_DEVICE = 4, | |
| + HBA_RESP_STAT_HBAMODE_DISABLED = 14, | |
| + HBA_RESP_STAT_UNDERRUN = 81, | |
| + HBA_RESP_STAT_OVERRUN = 117, | |
| +}; | |
| + | |
| +enum { | |
| + HBA_RESP_SVCRES_TASK_COMPLETE = 0, | |
| + HBA_RESP_SVCRES_FAILURE = 1, | |
| + HBA_RESP_SVCRES_TMF_COMPLETE = 2, | |
| + HBA_RESP_SVCRES_TMF_SUCCEEDED = 3, | |
| + HBA_RESP_SVCRES_TMF_REJECTED = 4, | |
| + HBA_RESP_SVCRES_TMF_LUN_INVALID = 5, | |
| +}; | |
| + | |
| +enum { | |
| HCR_IN_PARAM_OFFSET = 0, | |
| HCR_IN_MODIFIER_OFFSET = 8, | |
| HCR_OUT_PARAM_OFFSET = 12, | |
| @@ -3148,12 +3422,36 @@ | |
| }; | |
| enum { | |
| + HMM_NEED_FAULT = 1, | |
| + HMM_NEED_WRITE_FAULT = 2, | |
| + HMM_NEED_ALL_BITS = 3, | |
| +}; | |
| + | |
| +enum { | |
| HP_THREAD_NONE = 0, | |
| HP_THREAD_ACTIVE = 1, | |
| HP_THREAD_PARKED = 2, | |
| }; | |
| enum { | |
| + HSWEP_PCI_UNCORE_HA = 0, | |
| + HSWEP_PCI_UNCORE_IMC = 1, | |
| + HSWEP_PCI_UNCORE_IRP = 2, | |
| + HSWEP_PCI_UNCORE_QPI = 3, | |
| + HSWEP_PCI_UNCORE_R2PCIE = 4, | |
| + HSWEP_PCI_UNCORE_R3QPI = 5, | |
| +}; | |
| + | |
| +enum { | |
| + HUF_flags_bmi2 = 1, | |
| + HUF_flags_optimalDepth = 2, | |
| + HUF_flags_preferRepeat = 4, | |
| + HUF_flags_suspectUncompressible = 8, | |
| + HUF_flags_disableAsm = 16, | |
| + HUF_flags_disableFast = 32, | |
| +}; | |
| + | |
| +enum { | |
| HUGETLB_SHMFS_INODE = 1, | |
| HUGETLB_ANONHUGE_INODE = 2, | |
| }; | |
| @@ -3224,8 +3522,34 @@ | |
| }; | |
| enum { | |
| - ICQ_EXITED = 4, | |
| - ICQ_DESTROYED = 8, | |
| + ICX_PCIE1_PMON_ID = 0, | |
| + ICX_PCIE2_PMON_ID = 1, | |
| + ICX_PCIE3_PMON_ID = 2, | |
| + ICX_PCIE4_PMON_ID = 3, | |
| + ICX_PCIE5_PMON_ID = 4, | |
| + ICX_CBDMA_DMI_PMON_ID = 5, | |
| +}; | |
| + | |
| +enum { | |
| + ICX_PCI_UNCORE_M2M = 0, | |
| + ICX_PCI_UNCORE_UPI = 1, | |
| + ICX_PCI_UNCORE_M3UPI = 2, | |
| +}; | |
| + | |
| +enum { | |
| + IDX_MODULE_ID = 0, | |
| + IDX_ST_OPS_COMMON_VALUE_ID = 1, | |
| +}; | |
| + | |
| +enum { | |
| + IEEE80211_PROBE_FLAG_DIRECTED = 1, | |
| + IEEE80211_PROBE_FLAG_MIN_CONTENT = 2, | |
| + IEEE80211_PROBE_FLAG_RANDOM_SN = 4, | |
| +}; | |
| + | |
| +enum { | |
| + IEEE80211_RX_MSG = 1, | |
| + IEEE80211_TX_STATUS_MSG = 2, | |
| }; | |
| enum { | |
| @@ -3262,6 +3586,27 @@ | |
| }; | |
| enum { | |
| + IFLA_BRIDGE_MST_ENTRY_UNSPEC = 0, | |
| + IFLA_BRIDGE_MST_ENTRY_MSTI = 1, | |
| + IFLA_BRIDGE_MST_ENTRY_STATE = 2, | |
| + __IFLA_BRIDGE_MST_ENTRY_MAX = 3, | |
| +}; | |
| + | |
| +enum { | |
| + IFLA_BRIDGE_MST_UNSPEC = 0, | |
| + IFLA_BRIDGE_MST_ENTRY = 1, | |
| + __IFLA_BRIDGE_MST_MAX = 2, | |
| +}; | |
| + | |
| +enum { | |
| + IFLA_BRIDGE_VLAN_TUNNEL_UNSPEC = 0, | |
| + IFLA_BRIDGE_VLAN_TUNNEL_ID = 1, | |
| + IFLA_BRIDGE_VLAN_TUNNEL_VID = 2, | |
| + IFLA_BRIDGE_VLAN_TUNNEL_FLAGS = 3, | |
| + __IFLA_BRIDGE_VLAN_TUNNEL_MAX = 4, | |
| +}; | |
| + | |
| +enum { | |
| IFLA_BRPORT_UNSPEC = 0, | |
| IFLA_BRPORT_STATE = 1, | |
| IFLA_BRPORT_PRIORITY = 2, | |
| @@ -3306,7 +3651,62 @@ | |
| IFLA_BRPORT_MCAST_N_GROUPS = 41, | |
| IFLA_BRPORT_MCAST_MAX_GROUPS = 42, | |
| IFLA_BRPORT_NEIGH_VLAN_SUPPRESS = 43, | |
| - __IFLA_BRPORT_MAX = 44, | |
| + IFLA_BRPORT_BACKUP_NHID = 44, | |
| + __IFLA_BRPORT_MAX = 45, | |
| +}; | |
| + | |
| +enum { | |
| + IFLA_BR_UNSPEC = 0, | |
| + IFLA_BR_FORWARD_DELAY = 1, | |
| + IFLA_BR_HELLO_TIME = 2, | |
| + IFLA_BR_MAX_AGE = 3, | |
| + IFLA_BR_AGEING_TIME = 4, | |
| + IFLA_BR_STP_STATE = 5, | |
| + IFLA_BR_PRIORITY = 6, | |
| + IFLA_BR_VLAN_FILTERING = 7, | |
| + IFLA_BR_VLAN_PROTOCOL = 8, | |
| + IFLA_BR_GROUP_FWD_MASK = 9, | |
| + IFLA_BR_ROOT_ID = 10, | |
| + IFLA_BR_BRIDGE_ID = 11, | |
| + IFLA_BR_ROOT_PORT = 12, | |
| + IFLA_BR_ROOT_PATH_COST = 13, | |
| + IFLA_BR_TOPOLOGY_CHANGE = 14, | |
| + IFLA_BR_TOPOLOGY_CHANGE_DETECTED = 15, | |
| + IFLA_BR_HELLO_TIMER = 16, | |
| + IFLA_BR_TCN_TIMER = 17, | |
| + IFLA_BR_TOPOLOGY_CHANGE_TIMER = 18, | |
| + IFLA_BR_GC_TIMER = 19, | |
| + IFLA_BR_GROUP_ADDR = 20, | |
| + IFLA_BR_FDB_FLUSH = 21, | |
| + IFLA_BR_MCAST_ROUTER = 22, | |
| + IFLA_BR_MCAST_SNOOPING = 23, | |
| + IFLA_BR_MCAST_QUERY_USE_IFADDR = 24, | |
| + IFLA_BR_MCAST_QUERIER = 25, | |
| + IFLA_BR_MCAST_HASH_ELASTICITY = 26, | |
| + IFLA_BR_MCAST_HASH_MAX = 27, | |
| + IFLA_BR_MCAST_LAST_MEMBER_CNT = 28, | |
| + IFLA_BR_MCAST_STARTUP_QUERY_CNT = 29, | |
| + IFLA_BR_MCAST_LAST_MEMBER_INTVL = 30, | |
| + IFLA_BR_MCAST_MEMBERSHIP_INTVL = 31, | |
| + IFLA_BR_MCAST_QUERIER_INTVL = 32, | |
| + IFLA_BR_MCAST_QUERY_INTVL = 33, | |
| + IFLA_BR_MCAST_QUERY_RESPONSE_INTVL = 34, | |
| + IFLA_BR_MCAST_STARTUP_QUERY_INTVL = 35, | |
| + IFLA_BR_NF_CALL_IPTABLES = 36, | |
| + IFLA_BR_NF_CALL_IP6TABLES = 37, | |
| + IFLA_BR_NF_CALL_ARPTABLES = 38, | |
| + IFLA_BR_VLAN_DEFAULT_PVID = 39, | |
| + IFLA_BR_PAD = 40, | |
| + IFLA_BR_VLAN_STATS_ENABLED = 41, | |
| + IFLA_BR_MCAST_STATS_ENABLED = 42, | |
| + IFLA_BR_MCAST_IGMP_VERSION = 43, | |
| + IFLA_BR_MCAST_MLD_VERSION = 44, | |
| + IFLA_BR_VLAN_STATS_PER_PORT = 45, | |
| + IFLA_BR_MULTI_BOOLOPT = 46, | |
| + IFLA_BR_MCAST_QUERIER_STATE = 47, | |
| + IFLA_BR_FDB_N_LEARNED = 48, | |
| + IFLA_BR_FDB_MAX_LEARNED = 49, | |
| + __IFLA_BR_MAX = 50, | |
| }; | |
| enum { | |
| @@ -3320,6 +3720,54 @@ | |
| }; | |
| enum { | |
| + IFLA_GENEVE_UNSPEC = 0, | |
| + IFLA_GENEVE_ID = 1, | |
| + IFLA_GENEVE_REMOTE = 2, | |
| + IFLA_GENEVE_TTL = 3, | |
| + IFLA_GENEVE_TOS = 4, | |
| + IFLA_GENEVE_PORT = 5, | |
| + IFLA_GENEVE_COLLECT_METADATA = 6, | |
| + IFLA_GENEVE_REMOTE6 = 7, | |
| + IFLA_GENEVE_UDP_CSUM = 8, | |
| + IFLA_GENEVE_UDP_ZERO_CSUM6_TX = 9, | |
| + IFLA_GENEVE_UDP_ZERO_CSUM6_RX = 10, | |
| + IFLA_GENEVE_LABEL = 11, | |
| + IFLA_GENEVE_TTL_INHERIT = 12, | |
| + IFLA_GENEVE_DF = 13, | |
| + IFLA_GENEVE_INNER_PROTO_INHERIT = 14, | |
| + __IFLA_GENEVE_MAX = 15, | |
| +}; | |
| + | |
| +enum { | |
| + IFLA_GRE_UNSPEC = 0, | |
| + IFLA_GRE_LINK = 1, | |
| + IFLA_GRE_IFLAGS = 2, | |
| + IFLA_GRE_OFLAGS = 3, | |
| + IFLA_GRE_IKEY = 4, | |
| + IFLA_GRE_OKEY = 5, | |
| + IFLA_GRE_LOCAL = 6, | |
| + IFLA_GRE_REMOTE = 7, | |
| + IFLA_GRE_TTL = 8, | |
| + IFLA_GRE_TOS = 9, | |
| + IFLA_GRE_PMTUDISC = 10, | |
| + IFLA_GRE_ENCAP_LIMIT = 11, | |
| + IFLA_GRE_FLOWINFO = 12, | |
| + IFLA_GRE_FLAGS = 13, | |
| + IFLA_GRE_ENCAP_TYPE = 14, | |
| + IFLA_GRE_ENCAP_FLAGS = 15, | |
| + IFLA_GRE_ENCAP_SPORT = 16, | |
| + IFLA_GRE_ENCAP_DPORT = 17, | |
| + IFLA_GRE_COLLECT_METADATA = 18, | |
| + IFLA_GRE_IGNORE_DF = 19, | |
| + IFLA_GRE_FWMARK = 20, | |
| + IFLA_GRE_ERSPAN_INDEX = 21, | |
| + IFLA_GRE_ERSPAN_VER = 22, | |
| + IFLA_GRE_ERSPAN_DIR = 23, | |
| + IFLA_GRE_ERSPAN_HWID = 24, | |
| + __IFLA_GRE_MAX = 25, | |
| +}; | |
| + | |
| +enum { | |
| IFLA_INET6_UNSPEC = 0, | |
| IFLA_INET6_FLAGS = 1, | |
| IFLA_INET6_CONF = 2, | |
| @@ -3375,13 +3823,6 @@ | |
| }; | |
| enum { | |
| - IFLA_IPVLAN_UNSPEC = 0, | |
| - IFLA_IPVLAN_MODE = 1, | |
| - IFLA_IPVLAN_FLAGS = 2, | |
| - __IFLA_IPVLAN_MAX = 3, | |
| -}; | |
| - | |
| -enum { | |
| IFLA_NETKIT_UNSPEC = 0, | |
| IFLA_NETKIT_PEER_INFO = 1, | |
| IFLA_NETKIT_PRIMARY = 2, | |
| @@ -3444,6 +3885,20 @@ | |
| }; | |
| enum { | |
| + IFLA_TUN_UNSPEC = 0, | |
| + IFLA_TUN_OWNER = 1, | |
| + IFLA_TUN_GROUP = 2, | |
| + IFLA_TUN_TYPE = 3, | |
| + IFLA_TUN_PI = 4, | |
| + IFLA_TUN_VNET_HDR = 5, | |
| + IFLA_TUN_PERSIST = 6, | |
| + IFLA_TUN_MULTI_QUEUE = 7, | |
| + IFLA_TUN_NUM_QUEUES = 8, | |
| + IFLA_TUN_NUM_DISABLED_QUEUES = 9, | |
| + __IFLA_TUN_MAX = 10, | |
| +}; | |
| + | |
| +enum { | |
| IFLA_UNSPEC = 0, | |
| IFLA_ADDRESS = 1, | |
| IFLA_BROADCAST = 2, | |
| @@ -3510,7 +3965,8 @@ | |
| IFLA_DEVLINK_PORT = 62, | |
| IFLA_GSO_IPV4_MAX_SIZE = 63, | |
| IFLA_GRO_IPV4_MAX_SIZE = 64, | |
| - __IFLA_MAX = 65, | |
| + IFLA_DPLL_PIN = 65, | |
| + __IFLA_MAX = 66, | |
| }; | |
| enum { | |
| @@ -3570,6 +4026,71 @@ | |
| }; | |
| enum { | |
| + IFLA_VLAN_QOS_UNSPEC = 0, | |
| + IFLA_VLAN_QOS_MAPPING = 1, | |
| + __IFLA_VLAN_QOS_MAX = 2, | |
| +}; | |
| + | |
| +enum { | |
| + IFLA_VLAN_UNSPEC = 0, | |
| + IFLA_VLAN_ID = 1, | |
| + IFLA_VLAN_FLAGS = 2, | |
| + IFLA_VLAN_EGRESS_QOS = 3, | |
| + IFLA_VLAN_INGRESS_QOS = 4, | |
| + IFLA_VLAN_PROTOCOL = 5, | |
| + __IFLA_VLAN_MAX = 6, | |
| +}; | |
| + | |
| +enum { | |
| + IFLA_VRF_PORT_UNSPEC = 0, | |
| + IFLA_VRF_PORT_TABLE = 1, | |
| + __IFLA_VRF_PORT_MAX = 2, | |
| +}; | |
| + | |
| +enum { | |
| + IFLA_VRF_UNSPEC = 0, | |
| + IFLA_VRF_TABLE = 1, | |
| + __IFLA_VRF_MAX = 2, | |
| +}; | |
| + | |
| +enum { | |
| + IFLA_VXLAN_UNSPEC = 0, | |
| + IFLA_VXLAN_ID = 1, | |
| + IFLA_VXLAN_GROUP = 2, | |
| + IFLA_VXLAN_LINK = 3, | |
| + IFLA_VXLAN_LOCAL = 4, | |
| + IFLA_VXLAN_TTL = 5, | |
| + IFLA_VXLAN_TOS = 6, | |
| + IFLA_VXLAN_LEARNING = 7, | |
| + IFLA_VXLAN_AGEING = 8, | |
| + IFLA_VXLAN_LIMIT = 9, | |
| + IFLA_VXLAN_PORT_RANGE = 10, | |
| + IFLA_VXLAN_PROXY = 11, | |
| + IFLA_VXLAN_RSC = 12, | |
| + IFLA_VXLAN_L2MISS = 13, | |
| + IFLA_VXLAN_L3MISS = 14, | |
| + IFLA_VXLAN_PORT = 15, | |
| + IFLA_VXLAN_GROUP6 = 16, | |
| + IFLA_VXLAN_LOCAL6 = 17, | |
| + IFLA_VXLAN_UDP_CSUM = 18, | |
| + IFLA_VXLAN_UDP_ZERO_CSUM6_TX = 19, | |
| + IFLA_VXLAN_UDP_ZERO_CSUM6_RX = 20, | |
| + IFLA_VXLAN_REMCSUM_TX = 21, | |
| + IFLA_VXLAN_REMCSUM_RX = 22, | |
| + IFLA_VXLAN_GBP = 23, | |
| + IFLA_VXLAN_REMCSUM_NOPARTIAL = 24, | |
| + IFLA_VXLAN_COLLECT_METADATA = 25, | |
| + IFLA_VXLAN_LABEL = 26, | |
| + IFLA_VXLAN_GPE = 27, | |
| + IFLA_VXLAN_TTL_INHERIT = 28, | |
| + IFLA_VXLAN_DF = 29, | |
| + IFLA_VXLAN_VNIFILTER = 30, | |
| + IFLA_VXLAN_LOCALBYPASS = 31, | |
| + IFLA_VXLAN_LABEL_POLICY = 32, | |
| + __IFLA_VXLAN_MAX = 33, | |
| +}; | |
| + | |
| +enum { | |
| IFLA_XDP_UNSPEC = 0, | |
| IFLA_XDP_FD = 1, | |
| IFLA_XDP_ATTACHED = 2, | |
| @@ -3583,6 +4104,14 @@ | |
| }; | |
| enum { | |
| + IFLA_XFRM_UNSPEC = 0, | |
| + IFLA_XFRM_LINK = 1, | |
| + IFLA_XFRM_IF_ID = 2, | |
| + IFLA_XFRM_COLLECT_METADATA = 3, | |
| + __IFLA_XFRM_MAX = 4, | |
| +}; | |
| + | |
| +enum { | |
| IF_ACT_NONE = -1, | |
| IF_ACT_FILTER = 0, | |
| IF_ACT_START = 1, | |
| @@ -3657,6 +4186,14 @@ | |
| }; | |
| enum { | |
| + INET_DIAG_REQ_NONE = 0, | |
| + INET_DIAG_REQ_BYTECODE = 1, | |
| + INET_DIAG_REQ_SK_BPF_STORAGES = 2, | |
| + INET_DIAG_REQ_PROTOCOL = 3, | |
| + __INET_DIAG_REQ_MAX = 4, | |
| +}; | |
| + | |
| +enum { | |
| INET_ECN_NOT_ECT = 0, | |
| INET_ECN_ECT_1 = 1, | |
| INET_ECN_ECT_0 = 2, | |
| @@ -3665,6 +4202,40 @@ | |
| }; | |
| enum { | |
| + INET_FLAGS_PKTINFO = 0, | |
| + INET_FLAGS_TTL = 1, | |
| + INET_FLAGS_TOS = 2, | |
| + INET_FLAGS_RECVOPTS = 3, | |
| + INET_FLAGS_RETOPTS = 4, | |
| + INET_FLAGS_PASSSEC = 5, | |
| + INET_FLAGS_ORIGDSTADDR = 6, | |
| + INET_FLAGS_CHECKSUM = 7, | |
| + INET_FLAGS_RECVFRAGSIZE = 8, | |
| + INET_FLAGS_RECVERR = 9, | |
| + INET_FLAGS_RECVERR_RFC4884 = 10, | |
| + INET_FLAGS_FREEBIND = 11, | |
| + INET_FLAGS_HDRINCL = 12, | |
| + INET_FLAGS_MC_LOOP = 13, | |
| + INET_FLAGS_MC_ALL = 14, | |
| + INET_FLAGS_TRANSPARENT = 15, | |
| + INET_FLAGS_IS_ICSK = 16, | |
| + INET_FLAGS_NODEFRAG = 17, | |
| + INET_FLAGS_BIND_ADDRESS_NO_PORT = 18, | |
| + INET_FLAGS_DEFER_CONNECT = 19, | |
| + INET_FLAGS_MC6_LOOP = 20, | |
| + INET_FLAGS_RECVERR6_RFC4884 = 21, | |
| + INET_FLAGS_MC6_ALL = 22, | |
| + INET_FLAGS_AUTOFLOWLABEL_SET = 23, | |
| + INET_FLAGS_AUTOFLOWLABEL = 24, | |
| + INET_FLAGS_DONTFRAG = 25, | |
| + INET_FLAGS_RECVERR6 = 26, | |
| + INET_FLAGS_REPFLOW = 27, | |
| + INET_FLAGS_RTALERT_ISOLATE = 28, | |
| + INET_FLAGS_SNDFLOW = 29, | |
| + INET_FLAGS_RTALERT = 30, | |
| +}; | |
| + | |
| +enum { | |
| INET_FRAG_FIRST_IN = 1, | |
| INET_FRAG_LAST_IN = 2, | |
| INET_FRAG_COMPLETE = 4, | |
| @@ -3673,8 +4244,11 @@ | |
| }; | |
| enum { | |
| - INIT = 0, | |
| - DELETE = 1, | |
| + INET_ULP_INFO_UNSPEC = 0, | |
| + INET_ULP_INFO_NAME = 1, | |
| + INET_ULP_INFO_TLS = 2, | |
| + INET_ULP_INFO_MPTCP = 3, | |
| + __INET_ULP_INFO_MAX = 4, | |
| }; | |
| enum { | |
| @@ -3685,6 +4259,96 @@ | |
| }; | |
| enum { | |
| + INTERCEPT_CR0_READ = 0, | |
| + INTERCEPT_CR3_READ = 3, | |
| + INTERCEPT_CR4_READ = 4, | |
| + INTERCEPT_CR8_READ = 8, | |
| + INTERCEPT_CR0_WRITE = 16, | |
| + INTERCEPT_CR3_WRITE = 19, | |
| + INTERCEPT_CR4_WRITE = 20, | |
| + INTERCEPT_CR8_WRITE = 24, | |
| + INTERCEPT_DR0_READ = 32, | |
| + INTERCEPT_DR1_READ = 33, | |
| + INTERCEPT_DR2_READ = 34, | |
| + INTERCEPT_DR3_READ = 35, | |
| + INTERCEPT_DR4_READ = 36, | |
| + INTERCEPT_DR5_READ = 37, | |
| + INTERCEPT_DR6_READ = 38, | |
| + INTERCEPT_DR7_READ = 39, | |
| + INTERCEPT_DR0_WRITE = 48, | |
| + INTERCEPT_DR1_WRITE = 49, | |
| + INTERCEPT_DR2_WRITE = 50, | |
| + INTERCEPT_DR3_WRITE = 51, | |
| + INTERCEPT_DR4_WRITE = 52, | |
| + INTERCEPT_DR5_WRITE = 53, | |
| + INTERCEPT_DR6_WRITE = 54, | |
| + INTERCEPT_DR7_WRITE = 55, | |
| + INTERCEPT_EXCEPTION_OFFSET = 64, | |
| + INTERCEPT_INTR = 96, | |
| + INTERCEPT_NMI = 97, | |
| + INTERCEPT_SMI = 98, | |
| + INTERCEPT_INIT = 99, | |
| + INTERCEPT_VINTR = 100, | |
| + INTERCEPT_SELECTIVE_CR0 = 101, | |
| + INTERCEPT_STORE_IDTR = 102, | |
| + INTERCEPT_STORE_GDTR = 103, | |
| + INTERCEPT_STORE_LDTR = 104, | |
| + INTERCEPT_STORE_TR = 105, | |
| + INTERCEPT_LOAD_IDTR = 106, | |
| + INTERCEPT_LOAD_GDTR = 107, | |
| + INTERCEPT_LOAD_LDTR = 108, | |
| + INTERCEPT_LOAD_TR = 109, | |
| + INTERCEPT_RDTSC = 110, | |
| + INTERCEPT_RDPMC = 111, | |
| + INTERCEPT_PUSHF = 112, | |
| + INTERCEPT_POPF = 113, | |
| + INTERCEPT_CPUID = 114, | |
| + INTERCEPT_RSM = 115, | |
| + INTERCEPT_IRET = 116, | |
| + INTERCEPT_INTn = 117, | |
| + INTERCEPT_INVD = 118, | |
| + INTERCEPT_PAUSE = 119, | |
| + INTERCEPT_HLT = 120, | |
| + INTERCEPT_INVLPG = 121, | |
| + INTERCEPT_INVLPGA = 122, | |
| + INTERCEPT_IOIO_PROT = 123, | |
| + INTERCEPT_MSR_PROT = 124, | |
| + INTERCEPT_TASK_SWITCH = 125, | |
| + INTERCEPT_FERR_FREEZE = 126, | |
| + INTERCEPT_SHUTDOWN = 127, | |
| + INTERCEPT_VMRUN = 128, | |
| + INTERCEPT_VMMCALL = 129, | |
| + INTERCEPT_VMLOAD = 130, | |
| + INTERCEPT_VMSAVE = 131, | |
| + INTERCEPT_STGI = 132, | |
| + INTERCEPT_CLGI = 133, | |
| + INTERCEPT_SKINIT = 134, | |
| + INTERCEPT_RDTSCP = 135, | |
| + INTERCEPT_ICEBP = 136, | |
| + INTERCEPT_WBINVD = 137, | |
| + INTERCEPT_MONITOR = 138, | |
| + INTERCEPT_MWAIT = 139, | |
| + INTERCEPT_MWAIT_COND = 140, | |
| + INTERCEPT_XSETBV = 141, | |
| + INTERCEPT_RDPRU = 142, | |
| + TRAP_EFER_WRITE = 143, | |
| + TRAP_CR0_WRITE = 144, | |
| + TRAP_CR1_WRITE = 145, | |
| + TRAP_CR2_WRITE = 146, | |
| + TRAP_CR3_WRITE = 147, | |
| + TRAP_CR4_WRITE = 148, | |
| + TRAP_CR5_WRITE = 149, | |
| + TRAP_CR6_WRITE = 150, | |
| + TRAP_CR7_WRITE = 151, | |
| + TRAP_CR8_WRITE = 152, | |
| + INTERCEPT_INVLPGB = 160, | |
| + INTERCEPT_INVLPGB_ILLEGAL = 161, | |
| + INTERCEPT_INVPCID = 162, | |
| + INTERCEPT_MCOMMIT = 163, | |
| + INTERCEPT_TLBSYNC = 164, | |
| +}; | |
| + | |
| +enum { | |
| INVERT = 1, | |
| PROCESS_AND = 2, | |
| PROCESS_OR = 4, | |
| @@ -3726,10 +4390,26 @@ | |
| }; | |
| enum { | |
| + IOMMU_SET_DOMAIN_MUST_SUCCEED = 1, | |
| +}; | |
| + | |
| +enum { | |
| IOPRIO_CLASS_NONE = 0, | |
| IOPRIO_CLASS_RT = 1, | |
| IOPRIO_CLASS_BE = 2, | |
| IOPRIO_CLASS_IDLE = 3, | |
| + IOPRIO_CLASS_INVALID = 7, | |
| +}; | |
| + | |
| +enum { | |
| + IOPRIO_HINT_NONE = 0, | |
| + IOPRIO_HINT_DEV_DURATION_LIMIT_1 = 1, | |
| + IOPRIO_HINT_DEV_DURATION_LIMIT_2 = 2, | |
| + IOPRIO_HINT_DEV_DURATION_LIMIT_3 = 3, | |
| + IOPRIO_HINT_DEV_DURATION_LIMIT_4 = 4, | |
| + IOPRIO_HINT_DEV_DURATION_LIMIT_5 = 5, | |
| + IOPRIO_HINT_DEV_DURATION_LIMIT_6 = 6, | |
| + IOPRIO_HINT_DEV_DURATION_LIMIT_7 = 7, | |
| }; | |
| enum { | |
| @@ -3757,70 +4437,11 @@ | |
| }; | |
| enum { | |
| - IORING_CQE_BUFFER_SHIFT = 16, | |
| -}; | |
| - | |
| -enum { | |
| - IORING_MSG_DATA = 0, | |
| - IORING_MSG_SEND_FD = 1, | |
| -}; | |
| - | |
| -enum { | |
| - IORING_REGISTER_BUFFERS = 0, | |
| - IORING_UNREGISTER_BUFFERS = 1, | |
| - IORING_REGISTER_FILES = 2, | |
| - IORING_UNREGISTER_FILES = 3, | |
| - IORING_REGISTER_EVENTFD = 4, | |
| - IORING_UNREGISTER_EVENTFD = 5, | |
| - IORING_REGISTER_FILES_UPDATE = 6, | |
| - IORING_REGISTER_EVENTFD_ASYNC = 7, | |
| - IORING_REGISTER_PROBE = 8, | |
| - IORING_REGISTER_PERSONALITY = 9, | |
| - IORING_UNREGISTER_PERSONALITY = 10, | |
| - IORING_REGISTER_RESTRICTIONS = 11, | |
| - IORING_REGISTER_ENABLE_RINGS = 12, | |
| - IORING_REGISTER_FILES2 = 13, | |
| - IORING_REGISTER_FILES_UPDATE2 = 14, | |
| - IORING_REGISTER_BUFFERS2 = 15, | |
| - IORING_REGISTER_BUFFERS_UPDATE = 16, | |
| - IORING_REGISTER_IOWQ_AFF = 17, | |
| - IORING_UNREGISTER_IOWQ_AFF = 18, | |
| - IORING_REGISTER_IOWQ_MAX_WORKERS = 19, | |
| - IORING_REGISTER_RING_FDS = 20, | |
| - IORING_UNREGISTER_RING_FDS = 21, | |
| - IORING_REGISTER_PBUF_RING = 22, | |
| - IORING_UNREGISTER_PBUF_RING = 23, | |
| - IORING_REGISTER_SYNC_CANCEL = 24, | |
| - IORING_REGISTER_FILE_ALLOC_RANGE = 25, | |
| - IORING_REGISTER_PBUF_STATUS = 26, | |
| - IORING_REGISTER_LAST = 27, | |
| - IORING_REGISTER_USE_REGISTERED_RING = 2147483648, | |
| -}; | |
| - | |
| -enum { | |
| - IORING_RESTRICTION_REGISTER_OP = 0, | |
| - IORING_RESTRICTION_SQE_OP = 1, | |
| - IORING_RESTRICTION_SQE_FLAGS_ALLOWED = 2, | |
| - IORING_RESTRICTION_SQE_FLAGS_REQUIRED = 3, | |
| - IORING_RESTRICTION_LAST = 4, | |
| -}; | |
| - | |
| -enum { | |
| IORING_RSRC_FILE = 0, | |
| IORING_RSRC_BUFFER = 1, | |
| }; | |
| enum { | |
| - IOSQE_FIXED_FILE_BIT = 0, | |
| - IOSQE_IO_DRAIN_BIT = 1, | |
| - IOSQE_IO_LINK_BIT = 2, | |
| - IOSQE_IO_HARDLINK_BIT = 3, | |
| - IOSQE_ASYNC_BIT = 4, | |
| - IOSQE_BUFFER_SELECT_BIT = 5, | |
| - IOSQE_CQE_SKIP_SUCCESS_BIT = 6, | |
| -}; | |
| - | |
| -enum { | |
| IOU_F_TWQ_LAZY_WAKE = 1, | |
| }; | |
| @@ -3832,10 +4453,6 @@ | |
| }; | |
| enum { | |
| - IOU_PBUF_RING_MMAP = 1, | |
| -}; | |
| - | |
| -enum { | |
| IOU_POLL_DONE = 0, | |
| IOU_POLL_NO_ACTION = 1, | |
| IOU_POLL_REMOVE_POLL_USE_RES = 2, | |
| @@ -3990,100 +4607,12 @@ | |
| }; | |
| enum { | |
| - IPSET_ATTR_ETHER = 17, | |
| - IPSET_ATTR_NAME = 18, | |
| - IPSET_ATTR_NAMEREF = 19, | |
| - IPSET_ATTR_IP2 = 20, | |
| - IPSET_ATTR_CIDR2 = 21, | |
| - IPSET_ATTR_IP2_TO = 22, | |
| - IPSET_ATTR_IFACE = 23, | |
| - IPSET_ATTR_BYTES = 24, | |
| - IPSET_ATTR_PACKETS = 25, | |
| - IPSET_ATTR_COMMENT = 26, | |
| - IPSET_ATTR_SKBMARK = 27, | |
| - IPSET_ATTR_SKBPRIO = 28, | |
| - IPSET_ATTR_SKBQUEUE = 29, | |
| - IPSET_ATTR_PAD = 30, | |
| - __IPSET_ATTR_ADT_MAX = 31, | |
| -}; | |
| - | |
| -enum { | |
| - IPSET_ATTR_IP = 1, | |
| - IPSET_ATTR_IP_FROM = 1, | |
| - IPSET_ATTR_IP_TO = 2, | |
| - IPSET_ATTR_CIDR = 3, | |
| - IPSET_ATTR_PORT = 4, | |
| - IPSET_ATTR_PORT_FROM = 4, | |
| - IPSET_ATTR_PORT_TO = 5, | |
| - IPSET_ATTR_TIMEOUT = 6, | |
| - IPSET_ATTR_PROTO = 7, | |
| - IPSET_ATTR_CADT_FLAGS = 8, | |
| - IPSET_ATTR_CADT_LINENO = 9, | |
| - IPSET_ATTR_MARK = 10, | |
| - IPSET_ATTR_MARKMASK = 11, | |
| - IPSET_ATTR_BITMASK = 12, | |
| - IPSET_ATTR_CADT_MAX = 16, | |
| - IPSET_ATTR_INITVAL = 17, | |
| - IPSET_ATTR_HASHSIZE = 18, | |
| - IPSET_ATTR_MAXELEM = 19, | |
| - IPSET_ATTR_NETMASK = 20, | |
| - IPSET_ATTR_BUCKETSIZE = 21, | |
| - IPSET_ATTR_RESIZE = 22, | |
| - IPSET_ATTR_SIZE = 23, | |
| - IPSET_ATTR_ELEMENTS = 24, | |
| - IPSET_ATTR_REFERENCES = 25, | |
| - IPSET_ATTR_MEMSIZE = 26, | |
| - __IPSET_ATTR_CREATE_MAX = 27, | |
| -}; | |
| - | |
| -enum { | |
| - IPSET_ATTR_IPADDR_IPV4 = 1, | |
| - IPSET_ATTR_IPADDR_IPV6 = 2, | |
| - __IPSET_ATTR_IPADDR_MAX = 3, | |
| -}; | |
| - | |
| -enum { | |
| - IPSET_ATTR_UNSPEC = 0, | |
| - IPSET_ATTR_PROTOCOL = 1, | |
| - IPSET_ATTR_SETNAME = 2, | |
| - IPSET_ATTR_TYPENAME = 3, | |
| - IPSET_ATTR_SETNAME2 = 3, | |
| - IPSET_ATTR_REVISION = 4, | |
| - IPSET_ATTR_FAMILY = 5, | |
| - IPSET_ATTR_FLAGS = 6, | |
| - IPSET_ATTR_DATA = 7, | |
| - IPSET_ATTR_ADT = 8, | |
| - IPSET_ATTR_LINENO = 9, | |
| - IPSET_ATTR_PROTOCOL_MIN = 10, | |
| - IPSET_ATTR_REVISION_MIN = 10, | |
| - IPSET_ATTR_INDEX = 11, | |
| - __IPSET_ATTR_CMD_MAX = 12, | |
| -}; | |
| - | |
| -enum { | |
| - IPSET_CB_NET = 0, | |
| - IPSET_CB_PROTO = 1, | |
| - IPSET_CB_DUMP = 2, | |
| - IPSET_CB_INDEX = 3, | |
| - IPSET_CB_PRIVATE = 4, | |
| - IPSET_CB_ARG0 = 5, | |
| -}; | |
| - | |
| -enum { | |
| - IPSET_COUNTER_NONE = 0, | |
| - IPSET_COUNTER_EQ = 1, | |
| - IPSET_COUNTER_NE = 2, | |
| - IPSET_COUNTER_LT = 3, | |
| - IPSET_COUNTER_GT = 4, | |
| -}; | |
| - | |
| -enum { | |
| IPSTATS_MIB_NUM = 0, | |
| IPSTATS_MIB_INPKTS = 1, | |
| IPSTATS_MIB_INOCTETS = 2, | |
| IPSTATS_MIB_INDELIVERS = 3, | |
| IPSTATS_MIB_OUTFORWDATAGRAMS = 4, | |
| - IPSTATS_MIB_OUTPKTS = 5, | |
| + IPSTATS_MIB_OUTREQUESTS = 5, | |
| IPSTATS_MIB_OUTOCTETS = 6, | |
| IPSTATS_MIB_INHDRERRORS = 7, | |
| IPSTATS_MIB_INTOOBIGERRORS = 8, | |
| @@ -4115,7 +4644,8 @@ | |
| IPSTATS_MIB_ECT0PKTS = 34, | |
| IPSTATS_MIB_CEPKTS = 35, | |
| IPSTATS_MIB_REASM_OVERLAPS = 36, | |
| - __IPSTATS_MIB_MAX = 37, | |
| + IPSTATS_MIB_OUTPKTS = 37, | |
| + __IPSTATS_MIB_MAX = 38, | |
| }; | |
| enum { | |
| @@ -4169,6 +4699,29 @@ | |
| }; | |
| enum { | |
| + IP_TUNNEL_CSUM_BIT = 0, | |
| + IP_TUNNEL_ROUTING_BIT = 1, | |
| + IP_TUNNEL_KEY_BIT = 2, | |
| + IP_TUNNEL_SEQ_BIT = 3, | |
| + IP_TUNNEL_STRICT_BIT = 4, | |
| + IP_TUNNEL_REC_BIT = 5, | |
| + IP_TUNNEL_VERSION_BIT = 6, | |
| + IP_TUNNEL_NO_KEY_BIT = 7, | |
| + IP_TUNNEL_DONT_FRAGMENT_BIT = 8, | |
| + IP_TUNNEL_OAM_BIT = 9, | |
| + IP_TUNNEL_CRIT_OPT_BIT = 10, | |
| + IP_TUNNEL_GENEVE_OPT_BIT = 11, | |
| + IP_TUNNEL_VXLAN_OPT_BIT = 12, | |
| + IP_TUNNEL_NOCACHE_BIT = 13, | |
| + IP_TUNNEL_ERSPAN_OPT_BIT = 14, | |
| + IP_TUNNEL_GTP_OPT_BIT = 15, | |
| + IP_TUNNEL_VTI_BIT = 16, | |
| + IP_TUNNEL_SIT_ISATAP_BIT = 16, | |
| + IP_TUNNEL_PFCP_OPT_BIT = 17, | |
| + __IP_TUNNEL_FLAG_NUM = 18, | |
| +}; | |
| + | |
| +enum { | |
| IRQCHIP_FWNODE_REAL = 0, | |
| IRQCHIP_FWNODE_NAMED = 1, | |
| IRQCHIP_FWNODE_NAMED_ID = 2, | |
| @@ -4215,10 +4768,10 @@ | |
| IRQD_SINGLE_TARGET = 16777216, | |
| IRQD_DEFAULT_TRIGGER_SET = 33554432, | |
| IRQD_CAN_RESERVE = 67108864, | |
| - IRQD_MSI_NOMASK_QUIRK = 134217728, | |
| - IRQD_HANDLE_ENFORCE_IRQCTX = 268435456, | |
| - IRQD_AFFINITY_ON_ACTIVATE = 536870912, | |
| - IRQD_IRQ_ENABLED_ON_SUSPEND = 1073741824, | |
| + IRQD_HANDLE_ENFORCE_IRQCTX = 134217728, | |
| + IRQD_AFFINITY_ON_ACTIVATE = 268435456, | |
| + IRQD_IRQ_ENABLED_ON_SUSPEND = 536870912, | |
| + IRQD_RESEND_WHEN_IN_PROGRESS = 1073741824, | |
| }; | |
| enum { | |
| @@ -4306,6 +4859,15 @@ | |
| }; | |
| enum { | |
| + IVBEP_PCI_UNCORE_HA = 0, | |
| + IVBEP_PCI_UNCORE_IMC = 1, | |
| + IVBEP_PCI_UNCORE_IRP = 2, | |
| + IVBEP_PCI_UNCORE_QPI = 3, | |
| + IVBEP_PCI_UNCORE_R2PCIE = 4, | |
| + IVBEP_PCI_UNCORE_R3QPI = 5, | |
| +}; | |
| + | |
| +enum { | |
| I_DATA_SEM_NORMAL = 0, | |
| I_DATA_SEM_OTHER = 1, | |
| I_DATA_SEM_QUOTA = 2, | |
| @@ -4313,13 +4875,8 @@ | |
| }; | |
| enum { | |
| - I_LCOEF_RBPS = 0, | |
| - I_LCOEF_RSEQIOPS = 1, | |
| - I_LCOEF_RRANDIOPS = 2, | |
| - I_LCOEF_WBPS = 3, | |
| - I_LCOEF_WSEQIOPS = 4, | |
| - I_LCOEF_WRANDIOPS = 5, | |
| - NR_I_LCOEFS = 6, | |
| + KBUF_MODE_EXPAND = 1, | |
| + KBUF_MODE_FREE = 2, | |
| }; | |
| enum { | |
| @@ -4337,6 +4894,16 @@ | |
| KF_ARG_LIST_NODE_ID = 2, | |
| KF_ARG_RB_ROOT_ID = 3, | |
| KF_ARG_RB_NODE_ID = 4, | |
| + KF_ARG_WORKQUEUE_ID = 5, | |
| +}; | |
| + | |
| +enum { | |
| + KNL_PCI_UNCORE_MC_UCLK = 0, | |
| + KNL_PCI_UNCORE_MC_DCLK = 1, | |
| + KNL_PCI_UNCORE_EDC_UCLK = 2, | |
| + KNL_PCI_UNCORE_EDC_ECLK = 3, | |
| + KNL_PCI_UNCORE_M2PCIE = 4, | |
| + KNL_PCI_UNCORE_IRP = 5, | |
| }; | |
| enum { | |
| @@ -4344,6 +4911,11 @@ | |
| }; | |
| enum { | |
| + KVM_DEBUGREG_BP_ENABLED = 1, | |
| + KVM_DEBUGREG_WONT_EXIT = 2, | |
| +}; | |
| + | |
| +enum { | |
| KYBER_ASYNC_PERCENT = 75, | |
| }; | |
| @@ -4374,13 +4946,6 @@ | |
| }; | |
| enum { | |
| - LAT_OK = 1, | |
| - LAT_UNKNOWN = 2, | |
| - LAT_UNKNOWN_WRITES = 3, | |
| - LAT_EXCEEDED = 4, | |
| -}; | |
| - | |
| -enum { | |
| LBR_FORMAT_32 = 0, | |
| LBR_FORMAT_LIP = 1, | |
| LBR_FORMAT_EIP = 2, | |
| @@ -4398,13 +4963,8 @@ | |
| }; | |
| enum { | |
| - LCOEF_RPAGE = 0, | |
| - LCOEF_RSEQIO = 1, | |
| - LCOEF_RRANDIO = 2, | |
| - LCOEF_WPAGE = 3, | |
| - LCOEF_WSEQIO = 4, | |
| - LCOEF_WRANDIO = 5, | |
| - NR_LCOEFS = 6, | |
| + LDISC_SEM_NORMAL = 0, | |
| + LDISC_SEM_OTHER = 1, | |
| }; | |
| enum { | |
| @@ -4438,15 +4998,18 @@ | |
| ATA_DFLAG_DMADIR = 1024, | |
| ATA_DFLAG_NCQ_SEND_RECV = 2048, | |
| ATA_DFLAG_NCQ_PRIO = 4096, | |
| - ATA_DFLAG_CFG_MASK = 8191, | |
| - ATA_DFLAG_PIO = 8192, | |
| - ATA_DFLAG_NCQ_OFF = 16384, | |
| - ATA_DFLAG_SLEEPING = 32768, | |
| - ATA_DFLAG_DUBIOUS_XFER = 65536, | |
| - ATA_DFLAG_NO_UNLOAD = 131072, | |
| - ATA_DFLAG_UNLOCK_HPA = 262144, | |
| - ATA_DFLAG_INIT_MASK = 524287, | |
| - ATA_DFLAG_NCQ_PRIO_ENABLED = 524288, | |
| + ATA_DFLAG_CDL = 8192, | |
| + ATA_DFLAG_CFG_MASK = 16383, | |
| + ATA_DFLAG_PIO = 16384, | |
| + ATA_DFLAG_NCQ_OFF = 32768, | |
| + ATA_DFLAG_SLEEPING = 65536, | |
| + ATA_DFLAG_DUBIOUS_XFER = 131072, | |
| + ATA_DFLAG_NO_UNLOAD = 262144, | |
| + ATA_DFLAG_UNLOCK_HPA = 524288, | |
| + ATA_DFLAG_INIT_MASK = 1048575, | |
| + ATA_DFLAG_NCQ_PRIO_ENABLED = 1048576, | |
| + ATA_DFLAG_CDL_ENABLED = 2097152, | |
| + ATA_DFLAG_RESUMING = 4194304, | |
| ATA_DFLAG_DETACH = 16777216, | |
| ATA_DFLAG_DETACHED = 33554432, | |
| ATA_DFLAG_DA = 67108864, | |
| @@ -4454,7 +5017,7 @@ | |
| ATA_DFLAG_ACPI_DISABLED = 268435456, | |
| ATA_DFLAG_D_SENSE = 536870912, | |
| ATA_DFLAG_ZAC = 1073741824, | |
| - ATA_DFLAG_FEATURES_MASK = 201333504, | |
| + ATA_DFLAG_FEATURES_MASK = 201341696, | |
| ATA_DEV_UNKNOWN = 0, | |
| ATA_DEV_ATA = 1, | |
| ATA_DEV_ATA_UNSUP = 2, | |
| @@ -4512,6 +5075,7 @@ | |
| ATA_PFLAG_RESETTING = 256, | |
| ATA_PFLAG_UNLOADING = 512, | |
| ATA_PFLAG_UNLOADED = 1024, | |
| + ATA_PFLAG_RESUMING = 65536, | |
| ATA_PFLAG_SUSPENDED = 131072, | |
| ATA_PFLAG_PM_PENDING = 262144, | |
| ATA_PFLAG_INIT_GTM_VALID = 524288, | |
| @@ -4526,13 +5090,18 @@ | |
| ATA_QCFLAG_CLEAR_EXCL = 32, | |
| ATA_QCFLAG_QUIET = 64, | |
| ATA_QCFLAG_RETRY = 128, | |
| + ATA_QCFLAG_HAS_CDL = 256, | |
| ATA_QCFLAG_EH = 65536, | |
| ATA_QCFLAG_SENSE_VALID = 131072, | |
| ATA_QCFLAG_EH_SCHEDULED = 262144, | |
| + ATA_QCFLAG_EH_SUCCESS_CMD = 524288, | |
| ATA_HOST_SIMPLEX = 1, | |
| ATA_HOST_STARTED = 2, | |
| ATA_HOST_PARALLEL_SCAN = 4, | |
| ATA_HOST_IGNORE_ATA = 8, | |
| + ATA_HOST_NO_PART = 16, | |
| + ATA_HOST_NO_SSC = 32, | |
| + ATA_HOST_NO_DEVSLP = 64, | |
| ATA_TMOUT_BOOT = 30000, | |
| ATA_TMOUT_BOOT_QUICK = 7000, | |
| ATA_TMOUT_INTERNAL_QUICK = 5000, | |
| @@ -4540,7 +5109,7 @@ | |
| ATA_TMOUT_FF_WAIT_LONG = 2000, | |
| ATA_TMOUT_FF_WAIT = 800, | |
| ATA_WAIT_AFTER_RESET = 150, | |
| - ATA_TMOUT_PMP_SRST_WAIT = 5000, | |
| + ATA_TMOUT_PMP_SRST_WAIT = 10000, | |
| ATA_TMOUT_SPURIOUS_PHY = 10000, | |
| BUS_UNKNOWN = 0, | |
| BUS_DMA = 1, | |
| @@ -4574,7 +5143,9 @@ | |
| ATA_EH_RESET = 6, | |
| ATA_EH_ENABLE_LINK = 8, | |
| ATA_EH_PARK = 32, | |
| - ATA_EH_PERDEV_MASK = 33, | |
| + ATA_EH_GET_SUCCESS_SENSE = 64, | |
| + ATA_EH_SET_ACTIVE = 128, | |
| + ATA_EH_PERDEV_MASK = 225, | |
| ATA_EH_ALL_ACTIONS = 15, | |
| ATA_EHI_HOTPLUGGED = 1, | |
| ATA_EHI_NO_AUTOPSY = 4, | |
| @@ -4589,12 +5160,11 @@ | |
| ATA_EHI_TO_SLAVE_MASK = 12, | |
| ATA_EH_MAX_TRIES = 5, | |
| ATA_LINK_RESUME_TRIES = 5, | |
| - ATA_PROBE_MAX_TRIES = 3, | |
| ATA_EH_DEV_TRIES = 3, | |
| ATA_EH_PMP_TRIES = 5, | |
| ATA_EH_PMP_LINK_TRIES = 3, | |
| SATA_PMP_RW_TIMEOUT = 3000, | |
| - ATA_EH_CMD_TIMEOUT_TABLE_SIZE = 7, | |
| + ATA_EH_CMD_TIMEOUT_TABLE_SIZE = 8, | |
| ATA_HORKAGE_DIAGNOSTIC = 1, | |
| ATA_HORKAGE_NODMA = 2, | |
| ATA_HORKAGE_NONCQ = 4, | |
| @@ -4659,6 +5229,13 @@ | |
| }; | |
| enum { | |
| + LINK_XSTATS_TYPE_UNSPEC = 0, | |
| + LINK_XSTATS_TYPE_BRIDGE = 1, | |
| + LINK_XSTATS_TYPE_BOND = 2, | |
| + __LINK_XSTATS_TYPE_MAX = 3, | |
| +}; | |
| + | |
| +enum { | |
| LINUX_MIB_NUM = 0, | |
| LINUX_MIB_SYNCOOKIESSENT = 1, | |
| LINUX_MIB_SYNCOOKIESRECV = 2, | |
| @@ -4786,7 +5363,81 @@ | |
| LINUX_MIB_TCPMIGRATEREQSUCCESS = 124, | |
| LINUX_MIB_TCPMIGRATEREQFAILURE = 125, | |
| LINUX_MIB_TCPPLBREHASH = 126, | |
| - __LINUX_MIB_MAX = 127, | |
| + LINUX_MIB_TCPAOREQUIRED = 127, | |
| + LINUX_MIB_TCPAOBAD = 128, | |
| + LINUX_MIB_TCPAOKEYNOTFOUND = 129, | |
| + LINUX_MIB_TCPAOGOOD = 130, | |
| + LINUX_MIB_TCPAODROPPEDICMPS = 131, | |
| + __LINUX_MIB_MAX = 132, | |
| +}; | |
| + | |
| +enum { | |
| + LINUX_MIB_TLSNUM = 0, | |
| + LINUX_MIB_TLSCURRTXSW = 1, | |
| + LINUX_MIB_TLSCURRRXSW = 2, | |
| + LINUX_MIB_TLSCURRTXDEVICE = 3, | |
| + LINUX_MIB_TLSCURRRXDEVICE = 4, | |
| + LINUX_MIB_TLSTXSW = 5, | |
| + LINUX_MIB_TLSRXSW = 6, | |
| + LINUX_MIB_TLSTXDEVICE = 7, | |
| + LINUX_MIB_TLSRXDEVICE = 8, | |
| + LINUX_MIB_TLSDECRYPTERROR = 9, | |
| + LINUX_MIB_TLSRXDEVICERESYNC = 10, | |
| + LINUX_MIB_TLSDECRYPTRETRY = 11, | |
| + LINUX_MIB_TLSRXNOPADVIOL = 12, | |
| + __LINUX_MIB_TLSMAX = 13, | |
| +}; | |
| + | |
| +enum { | |
| + LINUX_MIB_XFRMNUM = 0, | |
| + LINUX_MIB_XFRMINERROR = 1, | |
| + LINUX_MIB_XFRMINBUFFERERROR = 2, | |
| + LINUX_MIB_XFRMINHDRERROR = 3, | |
| + LINUX_MIB_XFRMINNOSTATES = 4, | |
| + LINUX_MIB_XFRMINSTATEPROTOERROR = 5, | |
| + LINUX_MIB_XFRMINSTATEMODEERROR = 6, | |
| + LINUX_MIB_XFRMINSTATESEQERROR = 7, | |
| + LINUX_MIB_XFRMINSTATEEXPIRED = 8, | |
| + LINUX_MIB_XFRMINSTATEMISMATCH = 9, | |
| + LINUX_MIB_XFRMINSTATEINVALID = 10, | |
| + LINUX_MIB_XFRMINTMPLMISMATCH = 11, | |
| + LINUX_MIB_XFRMINNOPOLS = 12, | |
| + LINUX_MIB_XFRMINPOLBLOCK = 13, | |
| + LINUX_MIB_XFRMINPOLERROR = 14, | |
| + LINUX_MIB_XFRMOUTERROR = 15, | |
| + LINUX_MIB_XFRMOUTBUNDLEGENERROR = 16, | |
| + LINUX_MIB_XFRMOUTBUNDLECHECKERROR = 17, | |
| + LINUX_MIB_XFRMOUTNOSTATES = 18, | |
| + LINUX_MIB_XFRMOUTSTATEPROTOERROR = 19, | |
| + LINUX_MIB_XFRMOUTSTATEMODEERROR = 20, | |
| + LINUX_MIB_XFRMOUTSTATESEQERROR = 21, | |
| + LINUX_MIB_XFRMOUTSTATEEXPIRED = 22, | |
| + LINUX_MIB_XFRMOUTPOLBLOCK = 23, | |
| + LINUX_MIB_XFRMOUTPOLDEAD = 24, | |
| + LINUX_MIB_XFRMOUTPOLERROR = 25, | |
| + LINUX_MIB_XFRMFWDHDRERROR = 26, | |
| + LINUX_MIB_XFRMOUTSTATEINVALID = 27, | |
| + LINUX_MIB_XFRMACQUIREERROR = 28, | |
| + LINUX_MIB_XFRMOUTSTATEDIRERROR = 29, | |
| + LINUX_MIB_XFRMINSTATEDIRERROR = 30, | |
| + __LINUX_MIB_XFRMMAX = 31, | |
| +}; | |
| + | |
| +enum { | |
| + LINUX_RAID_PARTITION = 253, | |
| +}; | |
| + | |
| +enum { | |
| + LOCKF_USED_IN_HARDIRQ = 1, | |
| + LOCKF_USED_IN_HARDIRQ_READ = 2, | |
| + LOCKF_ENABLED_HARDIRQ = 4, | |
| + LOCKF_ENABLED_HARDIRQ_READ = 8, | |
| + LOCKF_USED_IN_SOFTIRQ = 16, | |
| + LOCKF_USED_IN_SOFTIRQ_READ = 32, | |
| + LOCKF_ENABLED_SOFTIRQ = 64, | |
| + LOCKF_ENABLED_SOFTIRQ_READ = 128, | |
| + LOCKF_USED = 256, | |
| + LOCKF_USED_READ = 512, | |
| }; | |
| enum { | |
| @@ -4807,6 +5458,13 @@ | |
| }; | |
| enum { | |
| + LO_FLAGS_READ_ONLY = 1, | |
| + LO_FLAGS_AUTOCLEAR = 4, | |
| + LO_FLAGS_PARTSCAN = 8, | |
| + LO_FLAGS_DIRECT_IO = 16, | |
| +}; | |
| + | |
| +enum { | |
| LWTUNNEL_IP_OPTS_UNSPEC = 0, | |
| LWTUNNEL_IP_OPTS_GENEVE = 1, | |
| LWTUNNEL_IP_OPTS_VXLAN = 2, | |
| @@ -4859,6 +5517,26 @@ | |
| }; | |
| enum { | |
| + LWT_XFRM_UNSPEC = 0, | |
| + LWT_XFRM_IF_ID = 1, | |
| + LWT_XFRM_LINK = 2, | |
| + __LWT_XFRM_MAX = 3, | |
| +}; | |
| + | |
| +enum { | |
| + Lo_unbound = 0, | |
| + Lo_bound = 1, | |
| + Lo_rundown = 2, | |
| + Lo_deleting = 3, | |
| +}; | |
| + | |
| +enum { | |
| + MAGNITUDE_STRONG = 2, | |
| + MAGNITUDE_WEAK = 3, | |
| + MAGNITUDE_NUM = 4, | |
| +}; | |
| + | |
| +enum { | |
| MATCH_MTR = 0, | |
| MATCH_MEQ = 1, | |
| MATCH_MLE = 2, | |
| @@ -4878,10 +5556,6 @@ | |
| }; | |
| enum { | |
| - MAX_MISSES = 3, | |
| -}; | |
| - | |
| -enum { | |
| MAX_OPT_ARGS = 3, | |
| }; | |
| @@ -4902,34 +5576,66 @@ | |
| }; | |
| enum { | |
| - MCQI_FW_RUNNING_VERSION = 0, | |
| - MCQI_FW_STORED_VERSION = 1, | |
| + MDBA_GET_ENTRY_UNSPEC = 0, | |
| + MDBA_GET_ENTRY = 1, | |
| + MDBA_GET_ENTRY_ATTRS = 2, | |
| + __MDBA_GET_ENTRY_MAX = 3, | |
| }; | |
| enum { | |
| - MCQI_INFO_TYPE_CAPABILITIES = 0, | |
| - MCQI_INFO_TYPE_VERSION = 1, | |
| - MCQI_INFO_TYPE_ACTIVATION_METHOD = 5, | |
| + MDBA_MDB_EATTR_UNSPEC = 0, | |
| + MDBA_MDB_EATTR_TIMER = 1, | |
| + MDBA_MDB_EATTR_SRC_LIST = 2, | |
| + MDBA_MDB_EATTR_GROUP_MODE = 3, | |
| + MDBA_MDB_EATTR_SOURCE = 4, | |
| + MDBA_MDB_EATTR_RTPROT = 5, | |
| + MDBA_MDB_EATTR_DST = 6, | |
| + MDBA_MDB_EATTR_DST_PORT = 7, | |
| + MDBA_MDB_EATTR_VNI = 8, | |
| + MDBA_MDB_EATTR_IFINDEX = 9, | |
| + MDBA_MDB_EATTR_SRC_VNI = 10, | |
| + __MDBA_MDB_EATTR_MAX = 11, | |
| }; | |
| enum { | |
| - MCQS_IDENTIFIER_BOOT_IMG = 1, | |
| - MCQS_IDENTIFIER_OEM_NVCONFIG = 4, | |
| - MCQS_IDENTIFIER_MLNX_NVCONFIG = 5, | |
| - MCQS_IDENTIFIER_CS_TOKEN = 6, | |
| - MCQS_IDENTIFIER_DBG_TOKEN = 7, | |
| - MCQS_IDENTIFIER_GEARBOX = 10, | |
| + MDBA_MDB_ENTRY_UNSPEC = 0, | |
| + MDBA_MDB_ENTRY_INFO = 1, | |
| + __MDBA_MDB_ENTRY_MAX = 2, | |
| }; | |
| enum { | |
| - MCQS_UPDATE_STATE_IDLE = 0, | |
| - MCQS_UPDATE_STATE_IN_PROGRESS = 1, | |
| - MCQS_UPDATE_STATE_APPLIED = 2, | |
| - MCQS_UPDATE_STATE_ACTIVE = 3, | |
| - MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET = 4, | |
| - MCQS_UPDATE_STATE_FAILED = 5, | |
| - MCQS_UPDATE_STATE_CANCELED = 6, | |
| - MCQS_UPDATE_STATE_BUSY = 7, | |
| + MDBA_MDB_SRCATTR_UNSPEC = 0, | |
| + MDBA_MDB_SRCATTR_ADDRESS = 1, | |
| + MDBA_MDB_SRCATTR_TIMER = 2, | |
| + __MDBA_MDB_SRCATTR_MAX = 3, | |
| +}; | |
| + | |
| +enum { | |
| + MDBA_MDB_SRCLIST_UNSPEC = 0, | |
| + MDBA_MDB_SRCLIST_ENTRY = 1, | |
| + __MDBA_MDB_SRCLIST_MAX = 2, | |
| +}; | |
| + | |
| +enum { | |
| + MDBA_MDB_UNSPEC = 0, | |
| + MDBA_MDB_ENTRY = 1, | |
| + __MDBA_MDB_MAX = 2, | |
| +}; | |
| + | |
| +enum { | |
| + MDBA_ROUTER_PATTR_UNSPEC = 0, | |
| + MDBA_ROUTER_PATTR_TIMER = 1, | |
| + MDBA_ROUTER_PATTR_TYPE = 2, | |
| + MDBA_ROUTER_PATTR_INET_TIMER = 3, | |
| + MDBA_ROUTER_PATTR_INET6_TIMER = 4, | |
| + MDBA_ROUTER_PATTR_VID = 5, | |
| + __MDBA_ROUTER_PATTR_MAX = 6, | |
| +}; | |
| + | |
| +enum { | |
| + MDBA_ROUTER_UNSPEC = 0, | |
| + MDBA_ROUTER_PORT = 1, | |
| + __MDBA_ROUTER_MAX = 2, | |
| }; | |
| enum { | |
| @@ -4940,6 +5646,47 @@ | |
| }; | |
| enum { | |
| + MDBA_UNSPEC = 0, | |
| + MDBA_MDB = 1, | |
| + MDBA_ROUTER = 2, | |
| + __MDBA_MAX = 3, | |
| +}; | |
| + | |
| +enum { | |
| + MDBE_ATTR_UNSPEC = 0, | |
| + MDBE_ATTR_SOURCE = 1, | |
| + MDBE_ATTR_SRC_LIST = 2, | |
| + MDBE_ATTR_GROUP_MODE = 3, | |
| + MDBE_ATTR_RTPROT = 4, | |
| + MDBE_ATTR_DST = 5, | |
| + MDBE_ATTR_DST_PORT = 6, | |
| + MDBE_ATTR_VNI = 7, | |
| + MDBE_ATTR_IFINDEX = 8, | |
| + MDBE_ATTR_SRC_VNI = 9, | |
| + MDBE_ATTR_STATE_MASK = 10, | |
| + __MDBE_ATTR_MAX = 11, | |
| +}; | |
| + | |
| +enum { | |
| + MDBE_SRCATTR_UNSPEC = 0, | |
| + MDBE_SRCATTR_ADDRESS = 1, | |
| + __MDBE_SRCATTR_MAX = 2, | |
| +}; | |
| + | |
| +enum { | |
| + MDBE_SRC_LIST_UNSPEC = 0, | |
| + MDBE_SRC_LIST_ENTRY = 1, | |
| + __MDBE_SRC_LIST_MAX = 2, | |
| +}; | |
| + | |
| +enum { | |
| + MDB_RTR_TYPE_DISABLED = 0, | |
| + MDB_RTR_TYPE_TEMP_QUERY = 1, | |
| + MDB_RTR_TYPE_PERM = 2, | |
| + MDB_RTR_TYPE_TEMP = 3, | |
| +}; | |
| + | |
| +enum { | |
| MD_RESYNC_NONE = 0, | |
| MD_RESYNC_YIELDED = 1, | |
| MD_RESYNC_DELAYED = 2, | |
| @@ -4963,14 +5710,6 @@ | |
| }; | |
| enum { | |
| - MEMORY_HOTPLUG_MIN_BOOTMEM_TYPE = 12, | |
| - SECTION_INFO = 12, | |
| - MIX_SECTION_INFO = 13, | |
| - NODE_INFO = 14, | |
| - MEMORY_HOTPLUG_MAX_BOOTMEM_TYPE = 14, | |
| -}; | |
| - | |
| -enum { | |
| MEMORY_RECLAIM_SWAPPINESS = 0, | |
| MEMORY_RECLAIM_NULL = 1, | |
| }; | |
| @@ -4994,15 +5733,106 @@ | |
| }; | |
| enum { | |
| - MILLION = 1000000, | |
| - MIN_PERIOD = 1000, | |
| - MAX_PERIOD = 1000000, | |
| - MARGIN_MIN_PCT = 10, | |
| - MARGIN_LOW_PCT = 20, | |
| - MARGIN_TARGET_PCT = 50, | |
| - INUSE_ADJ_STEP_PCT = 25, | |
| - TIMER_SLACK_PCT = 1, | |
| - WEIGHT_ONE = 65536, | |
| + MIPI_DCS_NOP = 0, | |
| + MIPI_DCS_SOFT_RESET = 1, | |
| + MIPI_DCS_GET_COMPRESSION_MODE = 3, | |
| + MIPI_DCS_GET_DISPLAY_ID = 4, | |
| + MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 5, | |
| + MIPI_DCS_GET_RED_CHANNEL = 6, | |
| + MIPI_DCS_GET_GREEN_CHANNEL = 7, | |
| + MIPI_DCS_GET_BLUE_CHANNEL = 8, | |
| + MIPI_DCS_GET_DISPLAY_STATUS = 9, | |
| + MIPI_DCS_GET_POWER_MODE = 10, | |
| + MIPI_DCS_GET_ADDRESS_MODE = 11, | |
| + MIPI_DCS_GET_PIXEL_FORMAT = 12, | |
| + MIPI_DCS_GET_DISPLAY_MODE = 13, | |
| + MIPI_DCS_GET_SIGNAL_MODE = 14, | |
| + MIPI_DCS_GET_DIAGNOSTIC_RESULT = 15, | |
| + MIPI_DCS_ENTER_SLEEP_MODE = 16, | |
| + MIPI_DCS_EXIT_SLEEP_MODE = 17, | |
| + MIPI_DCS_ENTER_PARTIAL_MODE = 18, | |
| + MIPI_DCS_ENTER_NORMAL_MODE = 19, | |
| + MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 20, | |
| + MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 21, | |
| + MIPI_DCS_EXIT_INVERT_MODE = 32, | |
| + MIPI_DCS_ENTER_INVERT_MODE = 33, | |
| + MIPI_DCS_SET_GAMMA_CURVE = 38, | |
| + MIPI_DCS_SET_DISPLAY_OFF = 40, | |
| + MIPI_DCS_SET_DISPLAY_ON = 41, | |
| + MIPI_DCS_SET_COLUMN_ADDRESS = 42, | |
| + MIPI_DCS_SET_PAGE_ADDRESS = 43, | |
| + MIPI_DCS_WRITE_MEMORY_START = 44, | |
| + MIPI_DCS_WRITE_LUT = 45, | |
| + MIPI_DCS_READ_MEMORY_START = 46, | |
| + MIPI_DCS_SET_PARTIAL_ROWS = 48, | |
| + MIPI_DCS_SET_PARTIAL_COLUMNS = 49, | |
| + MIPI_DCS_SET_SCROLL_AREA = 51, | |
| + MIPI_DCS_SET_TEAR_OFF = 52, | |
| + MIPI_DCS_SET_TEAR_ON = 53, | |
| + MIPI_DCS_SET_ADDRESS_MODE = 54, | |
| + MIPI_DCS_SET_SCROLL_START = 55, | |
| + MIPI_DCS_EXIT_IDLE_MODE = 56, | |
| + MIPI_DCS_ENTER_IDLE_MODE = 57, | |
| + MIPI_DCS_SET_PIXEL_FORMAT = 58, | |
| + MIPI_DCS_WRITE_MEMORY_CONTINUE = 60, | |
| + MIPI_DCS_SET_3D_CONTROL = 61, | |
| + MIPI_DCS_READ_MEMORY_CONTINUE = 62, | |
| + MIPI_DCS_GET_3D_CONTROL = 63, | |
| + MIPI_DCS_SET_VSYNC_TIMING = 64, | |
| + MIPI_DCS_SET_TEAR_SCANLINE = 68, | |
| + MIPI_DCS_GET_SCANLINE = 69, | |
| + MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 81, | |
| + MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 82, | |
| + MIPI_DCS_WRITE_CONTROL_DISPLAY = 83, | |
| + MIPI_DCS_GET_CONTROL_DISPLAY = 84, | |
| + MIPI_DCS_WRITE_POWER_SAVE = 85, | |
| + MIPI_DCS_GET_POWER_SAVE = 86, | |
| + MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 94, | |
| + MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 95, | |
| + MIPI_DCS_READ_DDB_START = 161, | |
| + MIPI_DCS_READ_PPS_START = 162, | |
| + MIPI_DCS_READ_DDB_CONTINUE = 168, | |
| + MIPI_DCS_READ_PPS_CONTINUE = 169, | |
| +}; | |
| + | |
| +enum { | |
| + MIPI_DSI_V_SYNC_START = 1, | |
| + MIPI_DSI_V_SYNC_END = 17, | |
| + MIPI_DSI_H_SYNC_START = 33, | |
| + MIPI_DSI_H_SYNC_END = 49, | |
| + MIPI_DSI_COMPRESSION_MODE = 7, | |
| + MIPI_DSI_END_OF_TRANSMISSION = 8, | |
| + MIPI_DSI_COLOR_MODE_OFF = 2, | |
| + MIPI_DSI_COLOR_MODE_ON = 18, | |
| + MIPI_DSI_SHUTDOWN_PERIPHERAL = 34, | |
| + MIPI_DSI_TURN_ON_PERIPHERAL = 50, | |
| + MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 3, | |
| + MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 19, | |
| + MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 35, | |
| + MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 4, | |
| + MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 20, | |
| + MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 36, | |
| + MIPI_DSI_DCS_SHORT_WRITE = 5, | |
| + MIPI_DSI_DCS_SHORT_WRITE_PARAM = 21, | |
| + MIPI_DSI_DCS_READ = 6, | |
| + MIPI_DSI_EXECUTE_QUEUE = 22, | |
| + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 55, | |
| + MIPI_DSI_NULL_PACKET = 9, | |
| + MIPI_DSI_BLANKING_PACKET = 25, | |
| + MIPI_DSI_GENERIC_LONG_WRITE = 41, | |
| + MIPI_DSI_DCS_LONG_WRITE = 57, | |
| + MIPI_DSI_PICTURE_PARAMETER_SET = 10, | |
| + MIPI_DSI_COMPRESSED_PIXEL_STREAM = 11, | |
| + MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 12, | |
| + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 28, | |
| + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 44, | |
| + MIPI_DSI_PACKED_PIXEL_STREAM_30 = 13, | |
| + MIPI_DSI_PACKED_PIXEL_STREAM_36 = 29, | |
| + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 61, | |
| + MIPI_DSI_PACKED_PIXEL_STREAM_16 = 14, | |
| + MIPI_DSI_PACKED_PIXEL_STREAM_18 = 30, | |
| + MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 46, | |
| + MIPI_DSI_PACKED_PIXEL_STREAM_24 = 62, | |
| }; | |
| enum { | |
| @@ -5196,6 +6026,17 @@ | |
| }; | |
| enum { | |
| + MLX4_CQE_L2_TUNNEL_IPOK = -2147483648, | |
| + MLX4_CQE_CVLAN_PRESENT_MASK = 536870912, | |
| + MLX4_CQE_SVLAN_PRESENT_MASK = 1073741824, | |
| + MLX4_CQE_L2_TUNNEL = 134217728, | |
| + MLX4_CQE_L2_TUNNEL_CSUM = 67108864, | |
| + MLX4_CQE_L2_TUNNEL_IPV4 = 33554432, | |
| + MLX4_CQE_QPN_MASK = 16777215, | |
| + MLX4_CQE_VID_MASK = 4095, | |
| +}; | |
| + | |
| +enum { | |
| MLX4_CQE_LLC = 1, | |
| MLX4_CQE_SNAP = 2, | |
| MLX4_CQE_BAD_FCS = 16, | |
| @@ -5208,6 +6049,16 @@ | |
| }; | |
| enum { | |
| + MLX4_CQE_STATUS_IPV4 = 64, | |
| + MLX4_CQE_STATUS_IPV4F = 128, | |
| + MLX4_CQE_STATUS_IPV6 = 256, | |
| + MLX4_CQE_STATUS_IPV4OPT = 512, | |
| + MLX4_CQE_STATUS_TCP = 1024, | |
| + MLX4_CQE_STATUS_UDP = 2048, | |
| + MLX4_CQE_STATUS_IPOK = 4096, | |
| +}; | |
| + | |
| +enum { | |
| MLX4_CQ_DB_REQ_NOT_SOL = 16777216, | |
| MLX4_CQ_DB_REQ_NOT = 33554432, | |
| }; | |
| @@ -5485,6 +6336,17 @@ | |
| }; | |
| enum { | |
| + MLX4_QP_BIT_SRE = 32768, | |
| + MLX4_QP_BIT_SWE = 16384, | |
| + MLX4_QP_BIT_SAE = 8192, | |
| + MLX4_QP_BIT_RRE = 32768, | |
| + MLX4_QP_BIT_RWE = 16384, | |
| + MLX4_QP_BIT_RAE = 8192, | |
| + MLX4_QP_BIT_FPP = 8, | |
| + MLX4_QP_BIT_RIC = 16, | |
| +}; | |
| + | |
| +enum { | |
| MLX4_QP_RATE_LIMIT_NONE = 0, | |
| MLX4_QP_RATE_LIMIT_KBS = 1, | |
| MLX4_QP_RATE_LIMIT_MBS = 2, | |
| @@ -5597,6 +6459,10 @@ | |
| }; | |
| enum { | |
| + MLX4_STRIP_VLAN = 1073741824, | |
| +}; | |
| + | |
| +enum { | |
| MLX4_TUNNEL_OFFLOAD_MODE_NONE = 0, | |
| MLX4_TUNNEL_OFFLOAD_MODE_VXLAN = 1, | |
| }; | |
| @@ -5675,1215 +6541,130 @@ | |
| }; | |
| enum { | |
| - MLX5E_ACTION_NONE = 0, | |
| - MLX5E_ACTION_ADD = 1, | |
| - MLX5E_ACTION_DEL = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5E_FEC_NOFEC = 0, | |
| - MLX5E_FEC_FIRECODE = 1, | |
| - MLX5E_FEC_RS_528_514 = 2, | |
| - MLX5E_FEC_RS_544_514 = 7, | |
| - MLX5E_FEC_LLRS_272_257_1 = 9, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5E_FULLMATCH = 0, | |
| - MLX5E_ALLMULTI = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5E_NDO_UPDATE_STATS = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5E_PORT_BUFFER_CABLE_LEN = 1, | |
| - MLX5E_PORT_BUFFER_PFC = 2, | |
| - MLX5E_PORT_BUFFER_PRIO2BUFFER = 4, | |
| - MLX5E_PORT_BUFFER_SIZE = 8, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5E_PROMISC_FT_LEVEL = 0, | |
| - MLX5E_VLAN_FT_LEVEL = 1, | |
| - MLX5E_L2_FT_LEVEL = 2, | |
| - MLX5E_TTC_FT_LEVEL = 3, | |
| - MLX5E_INNER_TTC_FT_LEVEL = 4, | |
| - MLX5E_FS_TT_UDP_FT_LEVEL = 5, | |
| - MLX5E_FS_TT_ANY_FT_LEVEL = 5, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5E_PTP_STATE_TX = 0, | |
| - MLX5E_PTP_STATE_RX = 1, | |
| - MLX5E_PTP_STATE_NUM_STATES = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5E_RQ_STATE_ENABLED = 0, | |
| - MLX5E_RQ_STATE_RECOVERING = 1, | |
| - MLX5E_RQ_STATE_DIM = 2, | |
| - MLX5E_RQ_STATE_NO_CSUM_COMPLETE = 3, | |
| - MLX5E_RQ_STATE_CSUM_FULL = 4, | |
| - MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX = 5, | |
| - MLX5E_RQ_STATE_SHAMPO = 6, | |
| - MLX5E_RQ_STATE_MINI_CQE_ENHANCED = 7, | |
| - MLX5E_RQ_STATE_XSK = 8, | |
| - MLX5E_NUM_RQ_STATES = 9, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5E_SKB_CB_CQE_HWTSTAMP = 1, | |
| - MLX5E_SKB_CB_PORT_HWTSTAMP = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5E_SQ_STATE_ENABLED = 0, | |
| - MLX5E_SQ_STATE_MPWQE = 1, | |
| - MLX5E_SQ_STATE_RECOVERING = 2, | |
| - MLX5E_SQ_STATE_IPSEC = 3, | |
| - MLX5E_SQ_STATE_DIM = 4, | |
| - MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE = 5, | |
| - MLX5E_SQ_STATE_PENDING_XSK_TX = 6, | |
| - MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC = 7, | |
| - MLX5E_SQ_STATE_XDP_MULTIBUF = 8, | |
| - MLX5E_NUM_SQ_STATES = 9, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5E_STATE_OPENED = 0, | |
| - MLX5E_STATE_DESTROYING = 1, | |
| - MLX5E_STATE_XDP_TX_ENABLED = 2, | |
| - MLX5E_STATE_XDP_ACTIVE = 3, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5E_TC_PRIO = 0, | |
| - MLX5E_NIC_PRIO = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5E_VENDOR_TC_GROUP_NUM = 7, | |
| - MLX5E_LOWEST_PRIO_GROUP = 0, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5E_XDP_CHECK_OK = 1, | |
| - MLX5E_XDP_CHECK_START_MPWQE = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_ADAPTER_PAGE_SHIFT = 12, | |
| - MLX5_ADAPTER_PAGE_SIZE = 4096, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_ATOMIC_REQ_MODE_BE = 0, | |
| - MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_BFREGS_PER_UAR = 4, | |
| - MLX5_MAX_UARS = 256, | |
| - MLX5_NON_FP_BFREGS_PER_UAR = 2, | |
| - MLX5_FP_BFREGS_PER_UAR = 2, | |
| - MLX5_MAX_BFREGS = 512, | |
| - MLX5_UARS_IN_PAGE = 1, | |
| - MLX5_NON_FP_BFREGS_IN_PAGE = 2, | |
| - MLX5_MIN_DYN_BFREGS = 512, | |
| - MLX5_MAX_DYN_BFREGS = 1024, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_BLKS_FOR_RECLAIM_PAGES = 12, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_BW_NO_LIMIT = 0, | |
| - MLX5_100_MBPS_UNIT = 3, | |
| - MLX5_GBPS_UNIT = 4, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CAP_INLINE_MODE_L2 = 0, | |
| - MLX5_CAP_INLINE_MODE_VPORT_CONTEXT = 1, | |
| - MLX5_CAP_INLINE_MODE_NOT_REQUIRED = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CAP_PORT_TYPE_IB = 0, | |
| - MLX5_CAP_PORT_TYPE_ETH = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CMD_DATA = 0, | |
| - MLX5_CMD_TIME = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CMD_DELIVERY_STAT_OK = 0, | |
| - MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 1, | |
| - MLX5_CMD_DELIVERY_STAT_TOK_ERR = 2, | |
| - MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 3, | |
| - MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 4, | |
| - MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 5, | |
| - MLX5_CMD_DELIVERY_STAT_FW_ERR = 6, | |
| - MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 7, | |
| - MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 8, | |
| - MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 9, | |
| - MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 16, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CMD_ENT_STATE_PENDING_COMP = 0, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CMD_OP_QUERY_HCA_CAP = 256, | |
| - MLX5_CMD_OP_QUERY_ADAPTER = 257, | |
| - MLX5_CMD_OP_INIT_HCA = 258, | |
| - MLX5_CMD_OP_TEARDOWN_HCA = 259, | |
| - MLX5_CMD_OP_ENABLE_HCA = 260, | |
| - MLX5_CMD_OP_DISABLE_HCA = 261, | |
| - MLX5_CMD_OP_QUERY_PAGES = 263, | |
| - MLX5_CMD_OP_MANAGE_PAGES = 264, | |
| - MLX5_CMD_OP_SET_HCA_CAP = 265, | |
| - MLX5_CMD_OP_QUERY_ISSI = 266, | |
| - MLX5_CMD_OP_SET_ISSI = 267, | |
| - MLX5_CMD_OP_SET_DRIVER_VERSION = 269, | |
| - MLX5_CMD_OP_QUERY_SF_PARTITION = 273, | |
| - MLX5_CMD_OP_ALLOC_SF = 275, | |
| - MLX5_CMD_OP_DEALLOC_SF = 276, | |
| - MLX5_CMD_OP_SUSPEND_VHCA = 277, | |
| - MLX5_CMD_OP_RESUME_VHCA = 278, | |
| - MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 279, | |
| - MLX5_CMD_OP_SAVE_VHCA_STATE = 280, | |
| - MLX5_CMD_OP_LOAD_VHCA_STATE = 281, | |
| - MLX5_CMD_OP_CREATE_MKEY = 512, | |
| - MLX5_CMD_OP_QUERY_MKEY = 513, | |
| - MLX5_CMD_OP_DESTROY_MKEY = 514, | |
| - MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 515, | |
| - MLX5_CMD_OP_PAGE_FAULT_RESUME = 516, | |
| - MLX5_CMD_OP_ALLOC_MEMIC = 517, | |
| - MLX5_CMD_OP_DEALLOC_MEMIC = 518, | |
| - MLX5_CMD_OP_MODIFY_MEMIC = 519, | |
| - MLX5_CMD_OP_CREATE_EQ = 769, | |
| - MLX5_CMD_OP_DESTROY_EQ = 770, | |
| - MLX5_CMD_OP_QUERY_EQ = 771, | |
| - MLX5_CMD_OP_GEN_EQE = 772, | |
| - MLX5_CMD_OP_CREATE_CQ = 1024, | |
| - MLX5_CMD_OP_DESTROY_CQ = 1025, | |
| - MLX5_CMD_OP_QUERY_CQ = 1026, | |
| - MLX5_CMD_OP_MODIFY_CQ = 1027, | |
| - MLX5_CMD_OP_CREATE_QP = 1280, | |
| - MLX5_CMD_OP_DESTROY_QP = 1281, | |
| - MLX5_CMD_OP_RST2INIT_QP = 1282, | |
| - MLX5_CMD_OP_INIT2RTR_QP = 1283, | |
| - MLX5_CMD_OP_RTR2RTS_QP = 1284, | |
| - MLX5_CMD_OP_RTS2RTS_QP = 1285, | |
| - MLX5_CMD_OP_SQERR2RTS_QP = 1286, | |
| - MLX5_CMD_OP_2ERR_QP = 1287, | |
| - MLX5_CMD_OP_2RST_QP = 1290, | |
| - MLX5_CMD_OP_QUERY_QP = 1291, | |
| - MLX5_CMD_OP_SQD_RTS_QP = 1292, | |
| - MLX5_CMD_OP_INIT2INIT_QP = 1294, | |
| - MLX5_CMD_OP_CREATE_PSV = 1536, | |
| - MLX5_CMD_OP_DESTROY_PSV = 1537, | |
| - MLX5_CMD_OP_CREATE_SRQ = 1792, | |
| - MLX5_CMD_OP_DESTROY_SRQ = 1793, | |
| - MLX5_CMD_OP_QUERY_SRQ = 1794, | |
| - MLX5_CMD_OP_ARM_RQ = 1795, | |
| - MLX5_CMD_OP_CREATE_XRC_SRQ = 1797, | |
| - MLX5_CMD_OP_DESTROY_XRC_SRQ = 1798, | |
| - MLX5_CMD_OP_QUERY_XRC_SRQ = 1799, | |
| - MLX5_CMD_OP_ARM_XRC_SRQ = 1800, | |
| - MLX5_CMD_OP_CREATE_DCT = 1808, | |
| - MLX5_CMD_OP_DESTROY_DCT = 1809, | |
| - MLX5_CMD_OP_DRAIN_DCT = 1810, | |
| - MLX5_CMD_OP_QUERY_DCT = 1811, | |
| - MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 1812, | |
| - MLX5_CMD_OP_CREATE_XRQ = 1815, | |
| - MLX5_CMD_OP_DESTROY_XRQ = 1816, | |
| - MLX5_CMD_OP_QUERY_XRQ = 1817, | |
| - MLX5_CMD_OP_ARM_XRQ = 1818, | |
| - MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 1829, | |
| - MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 1830, | |
| - MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 1831, | |
| - MLX5_CMD_OP_RELEASE_XRQ_ERROR = 1833, | |
| - MLX5_CMD_OP_MODIFY_XRQ = 1834, | |
| - MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 1856, | |
| - MLX5_CMD_OP_QUERY_VPORT_STATE = 1872, | |
| - MLX5_CMD_OP_MODIFY_VPORT_STATE = 1873, | |
| - MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 1874, | |
| - MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 1875, | |
| - MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 1876, | |
| - MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 1877, | |
| - MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 1888, | |
| - MLX5_CMD_OP_SET_ROCE_ADDRESS = 1889, | |
| - MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 1890, | |
| - MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 1891, | |
| - MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 1892, | |
| - MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 1893, | |
| - MLX5_CMD_OP_QUERY_VNIC_ENV = 1903, | |
| - MLX5_CMD_OP_QUERY_VPORT_COUNTER = 1904, | |
| - MLX5_CMD_OP_ALLOC_Q_COUNTER = 1905, | |
| - MLX5_CMD_OP_DEALLOC_Q_COUNTER = 1906, | |
| - MLX5_CMD_OP_QUERY_Q_COUNTER = 1907, | |
| - MLX5_CMD_OP_SET_MONITOR_COUNTER = 1908, | |
| - MLX5_CMD_OP_ARM_MONITOR_COUNTER = 1909, | |
| - MLX5_CMD_OP_SET_PP_RATE_LIMIT = 1920, | |
| - MLX5_CMD_OP_QUERY_RATE_LIMIT = 1921, | |
| - MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 1922, | |
| - MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 1923, | |
| - MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 1924, | |
| - MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 1925, | |
| - MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 1926, | |
| - MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 1927, | |
| - MLX5_CMD_OP_ALLOC_PD = 2048, | |
| - MLX5_CMD_OP_DEALLOC_PD = 2049, | |
| - MLX5_CMD_OP_ALLOC_UAR = 2050, | |
| - MLX5_CMD_OP_DEALLOC_UAR = 2051, | |
| - MLX5_CMD_OP_CONFIG_INT_MODERATION = 2052, | |
| - MLX5_CMD_OP_ACCESS_REG = 2053, | |
| - MLX5_CMD_OP_ATTACH_TO_MCG = 2054, | |
| - MLX5_CMD_OP_DETACH_FROM_MCG = 2055, | |
| - MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 2058, | |
| - MLX5_CMD_OP_MAD_IFC = 1293, | |
| - MLX5_CMD_OP_QUERY_MAD_DEMUX = 2059, | |
| - MLX5_CMD_OP_SET_MAD_DEMUX = 2060, | |
| - MLX5_CMD_OP_NOP = 2061, | |
| - MLX5_CMD_OP_ALLOC_XRCD = 2062, | |
| - MLX5_CMD_OP_DEALLOC_XRCD = 2063, | |
| - MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 2070, | |
| - MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 2071, | |
| - MLX5_CMD_OP_QUERY_CONG_STATUS = 2082, | |
| - MLX5_CMD_OP_MODIFY_CONG_STATUS = 2083, | |
| - MLX5_CMD_OP_QUERY_CONG_PARAMS = 2084, | |
| - MLX5_CMD_OP_MODIFY_CONG_PARAMS = 2085, | |
| - MLX5_CMD_OP_QUERY_CONG_STATISTICS = 2086, | |
| - MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 2087, | |
| - MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 2088, | |
| - MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 2089, | |
| - MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 2090, | |
| - MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 2091, | |
| - MLX5_CMD_OP_SET_WOL_ROL = 2096, | |
| - MLX5_CMD_OP_QUERY_WOL_ROL = 2097, | |
| - MLX5_CMD_OP_CREATE_LAG = 2112, | |
| - MLX5_CMD_OP_MODIFY_LAG = 2113, | |
| - MLX5_CMD_OP_QUERY_LAG = 2114, | |
| - MLX5_CMD_OP_DESTROY_LAG = 2115, | |
| - MLX5_CMD_OP_CREATE_VPORT_LAG = 2116, | |
| - MLX5_CMD_OP_DESTROY_VPORT_LAG = 2117, | |
| - MLX5_CMD_OP_CREATE_TIR = 2304, | |
| - MLX5_CMD_OP_MODIFY_TIR = 2305, | |
| - MLX5_CMD_OP_DESTROY_TIR = 2306, | |
| - MLX5_CMD_OP_QUERY_TIR = 2307, | |
| - MLX5_CMD_OP_CREATE_SQ = 2308, | |
| - MLX5_CMD_OP_MODIFY_SQ = 2309, | |
| - MLX5_CMD_OP_DESTROY_SQ = 2310, | |
| - MLX5_CMD_OP_QUERY_SQ = 2311, | |
| - MLX5_CMD_OP_CREATE_RQ = 2312, | |
| - MLX5_CMD_OP_MODIFY_RQ = 2313, | |
| - MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 2320, | |
| - MLX5_CMD_OP_DESTROY_RQ = 2314, | |
| - MLX5_CMD_OP_QUERY_RQ = 2315, | |
| - MLX5_CMD_OP_CREATE_RMP = 2316, | |
| - MLX5_CMD_OP_MODIFY_RMP = 2317, | |
| - MLX5_CMD_OP_DESTROY_RMP = 2318, | |
| - MLX5_CMD_OP_QUERY_RMP = 2319, | |
| - MLX5_CMD_OP_CREATE_TIS = 2322, | |
| - MLX5_CMD_OP_MODIFY_TIS = 2323, | |
| - MLX5_CMD_OP_DESTROY_TIS = 2324, | |
| - MLX5_CMD_OP_QUERY_TIS = 2325, | |
| - MLX5_CMD_OP_CREATE_RQT = 2326, | |
| - MLX5_CMD_OP_MODIFY_RQT = 2327, | |
| - MLX5_CMD_OP_DESTROY_RQT = 2328, | |
| - MLX5_CMD_OP_QUERY_RQT = 2329, | |
| - MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 2351, | |
| - MLX5_CMD_OP_CREATE_FLOW_TABLE = 2352, | |
| - MLX5_CMD_OP_DESTROY_FLOW_TABLE = 2353, | |
| - MLX5_CMD_OP_QUERY_FLOW_TABLE = 2354, | |
| - MLX5_CMD_OP_CREATE_FLOW_GROUP = 2355, | |
| - MLX5_CMD_OP_DESTROY_FLOW_GROUP = 2356, | |
| - MLX5_CMD_OP_QUERY_FLOW_GROUP = 2357, | |
| - MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 2358, | |
| - MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 2359, | |
| - MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 2360, | |
| - MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 2361, | |
| - MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 2362, | |
| - MLX5_CMD_OP_QUERY_FLOW_COUNTER = 2363, | |
| - MLX5_CMD_OP_MODIFY_FLOW_TABLE = 2364, | |
| - MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 2365, | |
| - MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 2366, | |
| - MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 2367, | |
| - MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 2368, | |
| - MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 2369, | |
| - MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 2370, | |
| - MLX5_CMD_OP_FPGA_CREATE_QP = 2400, | |
| - MLX5_CMD_OP_FPGA_MODIFY_QP = 2401, | |
| - MLX5_CMD_OP_FPGA_QUERY_QP = 2402, | |
| - MLX5_CMD_OP_FPGA_DESTROY_QP = 2403, | |
| - MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 2404, | |
| - MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 2560, | |
| - MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 2561, | |
| - MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 2562, | |
| - MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 2563, | |
| - MLX5_CMD_OP_CREATE_UCTX = 2564, | |
| - MLX5_CMD_OP_DESTROY_UCTX = 2566, | |
| - MLX5_CMD_OP_CREATE_UMEM = 2568, | |
| - MLX5_CMD_OP_DESTROY_UMEM = 2570, | |
| - MLX5_CMD_OP_SYNC_STEERING = 2816, | |
| - MLX5_CMD_OP_QUERY_VHCA_STATE = 2829, | |
| - MLX5_CMD_OP_MODIFY_VHCA_STATE = 2830, | |
| - MLX5_CMD_OP_SYNC_CRYPTO = 2834, | |
| - MLX5_CMD_OP_MAX = 2835, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CMD_STAT_OK = 0, | |
| - MLX5_CMD_STAT_INT_ERR = 1, | |
| - MLX5_CMD_STAT_BAD_OP_ERR = 2, | |
| - MLX5_CMD_STAT_BAD_PARAM_ERR = 3, | |
| - MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 4, | |
| - MLX5_CMD_STAT_BAD_RES_ERR = 5, | |
| - MLX5_CMD_STAT_RES_BUSY = 6, | |
| - MLX5_CMD_STAT_LIM_ERR = 8, | |
| - MLX5_CMD_STAT_BAD_RES_STATE_ERR = 9, | |
| - MLX5_CMD_STAT_IX_ERR = 10, | |
| - MLX5_CMD_STAT_NO_RES_ERR = 15, | |
| - MLX5_CMD_STAT_BAD_INP_LEN_ERR = 80, | |
| - MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 81, | |
| - MLX5_CMD_STAT_BAD_QP_STATE_ERR = 16, | |
| - MLX5_CMD_STAT_BAD_PKT_ERR = 48, | |
| - MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 64, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CMD_TIMEOUT_RECOVER_MSEC = 5000, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_COMP_EQ_SIZE = 1024, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CQE_COMPRESS_LAYOUT_BASIC = 0, | |
| - MLX5_CQE_COMPRESS_LAYOUT_ENHANCED = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CQE_FORMAT_CSUM = 1, | |
| - MLX5_CQE_FORMAT_CSUM_STRIDX = 3, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CQE_OWNER_MASK = 1, | |
| - MLX5_CQE_REQ = 0, | |
| - MLX5_CQE_RESP_WR_IMM = 1, | |
| - MLX5_CQE_RESP_SEND = 2, | |
| - MLX5_CQE_RESP_SEND_IMM = 3, | |
| - MLX5_CQE_RESP_SEND_INV = 4, | |
| - MLX5_CQE_RESIZE_CQ = 5, | |
| - MLX5_CQE_SIG_ERR = 12, | |
| - MLX5_CQE_REQ_ERR = 13, | |
| - MLX5_CQE_RESP_ERR = 14, | |
| - MLX5_CQE_INVALID = 15, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR = 1, | |
| - MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR = 2, | |
| - MLX5_CQE_SYNDROME_LOCAL_PROT_ERR = 4, | |
| - MLX5_CQE_SYNDROME_WR_FLUSH_ERR = 5, | |
| - MLX5_CQE_SYNDROME_MW_BIND_ERR = 6, | |
| - MLX5_CQE_SYNDROME_BAD_RESP_ERR = 16, | |
| - MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR = 17, | |
| - MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 18, | |
| - MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR = 19, | |
| - MLX5_CQE_SYNDROME_REMOTE_OP_ERR = 20, | |
| - MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 21, | |
| - MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 22, | |
| - MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR = 34, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CQ_DB_REQ_NOT_SOL = 16777216, | |
| - MLX5_CQ_DB_REQ_NOT = 0, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CQ_MODIFY_PERIOD = 1, | |
| - MLX5_CQ_MODIFY_COUNT = 2, | |
| - MLX5_CQ_MODIFY_OVERRUN = 4, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0, | |
| - MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 1, | |
| - MLX5_CQ_PERIOD_NUM_MODES = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0, | |
| - MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 1, | |
| - MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 2, | |
| - MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 3, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_CRYPTO_DEK_ALL_TYPE = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_DCB_CHG_RESET = 0, | |
| - MLX5_DCB_NO_CHG = 1, | |
| - MLX5_DCB_CHG_NO_RESET = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_DRIVER_STATUS_ABORTED = 254, | |
| - MLX5_DRIVER_SYND = 3135045854, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_DROP_HEALTH_WORK = 0, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_EN_RD = 1, | |
| - MLX5_EN_WR = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_EQE_OWNER_INIT_VAL = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_EQ_DOORBEL_OFFSET = 64, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_EQ_POLLING_BUDGET = 128, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_ESWITCH_LEGACY = 0, | |
| - MLX5_ESWITCH_OFFLOADS = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_ETH_WQE_L3_INNER_CSUM = 16, | |
| - MLX5_ETH_WQE_L4_INNER_CSUM = 32, | |
| - MLX5_ETH_WQE_L3_CSUM = 64, | |
| - MLX5_ETH_WQE_L4_CSUM = 128, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_EVENT_MODE_DISABLE = 0, | |
| - MLX5_EVENT_MODE_REPETETIVE = 1, | |
| - MLX5_EVENT_MODE_ONCE_TILL_ARM = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_EXE_ASO_FLOW_METER = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_FLOW_CONTEXT_ACTION_ALLOW = 1, | |
| - MLX5_FLOW_CONTEXT_ACTION_DROP = 2, | |
| - MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 4, | |
| - MLX5_FLOW_CONTEXT_ACTION_COUNT = 8, | |
| - MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 16, | |
| - MLX5_FLOW_CONTEXT_ACTION_DECAP = 32, | |
| - MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 64, | |
| - MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 128, | |
| - MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 256, | |
| - MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 1024, | |
| - MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 2048, | |
| - MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 4096, | |
| - MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 8192, | |
| - MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 16384, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO = 65536, | |
| - MLX5_FLOW_CONTEXT_ACTION_ENCRYPT = 131072, | |
| - MLX5_FLOW_CONTEXT_ACTION_DECRYPT = 262144, | |
| - MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS = 524288, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_FLOW_DEST_VPORT_VHCA_ID = 1, | |
| - MLX5_FLOW_DEST_VPORT_REFORMAT_ID = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT = 1, | |
| - MLX5_FLOW_TABLE_TUNNEL_EN_DECAP = 2, | |
| - MLX5_FLOW_TABLE_TERMINATION = 4, | |
| - MLX5_FLOW_TABLE_UNMANAGED = 8, | |
| - MLX5_FLOW_TABLE_OTHER_VPORT = 16, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_FW_RESET_FLAGS_RESET_REQUESTED = 0, | |
| - MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST = 1, | |
| - MLX5_FW_RESET_FLAGS_PENDING_COMP = 2, | |
| - MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS = 3, | |
| - MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED = 4, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 12, | |
| - MLX5_GENERAL_OBJECT_TYPES_IPSEC = 19, | |
| - MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 32, | |
| - MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 36, | |
| - MLX5_GENERAL_OBJECT_TYPES_MACSEC = 39, | |
| - MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 71, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0, | |
| - MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 1, | |
| - MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 5, | |
| - MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT = 7, | |
| - MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 8, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_HASH_FIELD_SEL_SRC_IP = 1, | |
| - MLX5_HASH_FIELD_SEL_DST_IP = 2, | |
| - MLX5_HASH_FIELD_SEL_L4_SPORT = 4, | |
| - MLX5_HASH_FIELD_SEL_L4_DPORT = 8, | |
| - MLX5_HASH_FIELD_SEL_IPSEC_SPI = 16, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_HCA_VPORT_SEL_PORT_GUID = 1, | |
| - MLX5_HCA_VPORT_SEL_NODE_GUID = 2, | |
| - MLX5_HCA_VPORT_SEL_STATE_POLICY = 4, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_HEALTH_SYNDR_FW_ERR = 1, | |
| - MLX5_HEALTH_SYNDR_IRISC_ERR = 7, | |
| - MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 8, | |
| - MLX5_HEALTH_SYNDR_CRC_ERR = 9, | |
| - MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 10, | |
| - MLX5_HEALTH_SYNDR_HW_FTL_ERR = 11, | |
| - MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 12, | |
| - MLX5_HEALTH_SYNDR_EQ_ERR = 13, | |
| - MLX5_HEALTH_SYNDR_EQ_INV = 14, | |
| - MLX5_HEALTH_SYNDR_FFSER_ERR = 15, | |
| - MLX5_HEALTH_SYNDR_HIGH_TEMP = 16, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_HW_START_PADDING = 2147483648, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_IEEE_802_3_COUNTERS_GROUP = 0, | |
| - MLX5_RFC_2863_COUNTERS_GROUP = 1, | |
| - MLX5_RFC_2819_COUNTERS_GROUP = 2, | |
| - MLX5_RFC_3635_COUNTERS_GROUP = 3, | |
| - MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 5, | |
| - MLX5_PER_PRIORITY_COUNTERS_GROUP = 16, | |
| - MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 17, | |
| - MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 18, | |
| - MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 19, | |
| - MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 22, | |
| - MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 32, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_INGRESS_DIR = 0, | |
| - MLX5_EGRESS_DIR = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_INLINE_SEG = 2147483648, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_LAG_EGRESS_PORT_1 = 1, | |
| - MLX5_LAG_EGRESS_PORT_2 = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_LAG_FLAG_NDEVS_READY = 0, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_LAG_MODE_FLAG_HASH_BASED = 0, | |
| - MLX5_LAG_MODE_FLAG_SHARED_FDB = 1, | |
| - MLX5_LAG_MODE_FLAG_FDB_SEL_MODE_NATIVE = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_LAG_P1 = 0, | |
| - MLX5_LAG_P2 = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, | |
| - MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, | |
| - MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_LOSSY_POOL = 0, | |
| - MLX5_LOSSLESS_POOL = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MATCH_OUTER_HEADERS = 1, | |
| - MLX5_MATCH_MISC_PARAMETERS = 2, | |
| - MLX5_MATCH_INNER_HEADERS = 4, | |
| - MLX5_MATCH_MISC_PARAMETERS_2 = 8, | |
| - MLX5_MATCH_MISC_PARAMETERS_3 = 16, | |
| - MLX5_MATCH_MISC_PARAMETERS_4 = 32, | |
| - MLX5_MATCH_MISC_PARAMETERS_5 = 64, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MAX_COMMANDS = 32, | |
| - MLX5_CMD_DATA_BLOCK_SIZE = 512, | |
| - MLX5_PCI_CMD_XPORT = 7, | |
| - MLX5_MKEY_BSF_OCTO_SIZE = 4, | |
| - MLX5_MAX_PSVS = 4, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MAX_PORTS = 4, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MAX_RECLAIM_TIME_MILI = 5000, | |
| - MLX5_NUM_4K_IN_PAGE = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MFRL_REG_RESET_LEVEL0 = 1, | |
| - MLX5_MFRL_REG_RESET_LEVEL3 = 8, | |
| - MLX5_MFRL_REG_RESET_LEVEL6 = 64, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MFRL_REG_RESET_STATE_IDLE = 0, | |
| - MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, | |
| - MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, | |
| - MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, | |
| - MLX5_MFRL_REG_RESET_STATE_NACK = 4, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = 1, | |
| - MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MIN_PKEY_TABLE_SIZE = 128, | |
| - MLX5_MAX_LOG_PKEY_TABLE = 5, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MKC_ACCESS_MODE_PA = 0, | |
| - MLX5_MKC_ACCESS_MODE_MTT = 1, | |
| - MLX5_MKC_ACCESS_MODE_KLMS = 2, | |
| - MLX5_MKC_ACCESS_MODE_KSM = 3, | |
| - MLX5_MKC_ACCESS_MODE_SW_ICM = 4, | |
| - MLX5_MKC_ACCESS_MODE_MEMIC = 5, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 1, | |
| - MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = 32768, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MTPPS_FS_ENABLE = 1, | |
| - MLX5_MTPPS_FS_PATTERN = 4, | |
| - MLX5_MTPPS_FS_PIN_MODE = 8, | |
| - MLX5_MTPPS_FS_TIME_STAMP = 16, | |
| - MLX5_MTPPS_FS_OUT_PULSE_DURATION = 32, | |
| - MLX5_MTPPS_FS_ENH_OUT_PER_ADJ = 128, | |
| - MLX5_MTPPS_FS_NPPS_PERIOD = 512, | |
| - MLX5_MTPPS_FS_OUT_PULSE_DURATION_NS = 1024, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_IN = 1, | |
| - MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_OUT = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0, | |
| - MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MTUTC_OPERATION_ADJUST_TIME_MIN = -32768, | |
| - MLX5_MTUTC_OPERATION_ADJUST_TIME_MAX = 32767, | |
| - MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MIN = -200000, | |
| - MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MAX = 200000, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 1, | |
| - MLX5_MTUTC_OPERATION_ADJUST_TIME = 2, | |
| - MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 3, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_NIC_IFC_FULL = 0, | |
| - MLX5_NIC_IFC_DISABLED = 1, | |
| - MLX5_NIC_IFC_NO_DRAM_NIC = 2, | |
| - MLX5_NIC_IFC_SW_RESET = 7, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_NO_INLINE_DATA = 0, | |
| - MLX5_INLINE_DATA32_SEG = 1, | |
| - MLX5_INLINE_DATA64_SEG = 2, | |
| - MLX5_COMPRESSED = 3, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 11, | |
| - MLX5_OBJ_TYPE_VIRTIO_NET_Q = 13, | |
| - MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 28, | |
| - MLX5_OBJ_TYPE_MATCH_DEFINER = 24, | |
| - MLX5_OBJ_TYPE_PAGE_TRACK = 70, | |
| - MLX5_OBJ_TYPE_MKEY = 65281, | |
| - MLX5_OBJ_TYPE_QP = 65282, | |
| - MLX5_OBJ_TYPE_PSV = 65283, | |
| - MLX5_OBJ_TYPE_RMP = 65284, | |
| - MLX5_OBJ_TYPE_XRC_SRQ = 65285, | |
| - MLX5_OBJ_TYPE_RQ = 65286, | |
| - MLX5_OBJ_TYPE_SQ = 65287, | |
| - MLX5_OBJ_TYPE_TIR = 65288, | |
| - MLX5_OBJ_TYPE_TIS = 65289, | |
| - MLX5_OBJ_TYPE_DCT = 65290, | |
| - MLX5_OBJ_TYPE_XRQ = 65291, | |
| - MLX5_OBJ_TYPE_RQT = 65294, | |
| - MLX5_OBJ_TYPE_FLOW_COUNTER = 65295, | |
| - MLX5_OBJ_TYPE_CQ = 65296, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_OBJ_TYPE_SW_ICM = 8, | |
| - MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 35, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_OCTWORD = 16, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_OPCODE_NOP = 0, | |
| - MLX5_OPCODE_SEND_INVAL = 1, | |
| - MLX5_OPCODE_RDMA_WRITE = 8, | |
| - MLX5_OPCODE_RDMA_WRITE_IMM = 9, | |
| - MLX5_OPCODE_SEND = 10, | |
| - MLX5_OPCODE_SEND_IMM = 11, | |
| - MLX5_OPCODE_LSO = 14, | |
| - MLX5_OPCODE_RDMA_READ = 16, | |
| - MLX5_OPCODE_ATOMIC_CS = 17, | |
| - MLX5_OPCODE_ATOMIC_FA = 18, | |
| - MLX5_OPCODE_ATOMIC_MASKED_CS = 20, | |
| - MLX5_OPCODE_ATOMIC_MASKED_FA = 21, | |
| - MLX5_OPCODE_BIND_MW = 24, | |
| - MLX5_OPCODE_CONFIG_CMD = 31, | |
| - MLX5_OPCODE_ENHANCED_MPSW = 41, | |
| - MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0, | |
| - MLX5_RECV_OPCODE_SEND = 1, | |
| - MLX5_RECV_OPCODE_SEND_IMM = 2, | |
| - MLX5_RECV_OPCODE_SEND_INVAL = 3, | |
| - MLX5_CQE_OPCODE_ERROR = 30, | |
| - MLX5_CQE_OPCODE_RESIZE = 22, | |
| - MLX5_OPCODE_SET_PSV = 32, | |
| - MLX5_OPCODE_GET_PSV = 33, | |
| - MLX5_OPCODE_CHECK_PSV = 34, | |
| - MLX5_OPCODE_DUMP = 35, | |
| - MLX5_OPCODE_RGET_PSV = 38, | |
| - MLX5_OPCODE_RCHECK_PSV = 39, | |
| - MLX5_OPCODE_UMR = 37, | |
| - MLX5_OPCODE_FLOW_TBL_ACCESS = 44, | |
| - MLX5_OPCODE_ACCESS_ASO = 45, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_OUT_PATTERN_PULSE = 0, | |
| - MLX5_OUT_PATTERN_PERIODIC = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_PAGES_CANT_GIVE = 0, | |
| - MLX5_PAGES_GIVE = 1, | |
| - MLX5_PAGES_TAKE = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_PCI_DEV_IS_VF = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_PCI_POWER_COULD_NOT_BE_READ = 0, | |
| - MLX5_PCI_POWER_SUFFICIENT_REPORTED = 1, | |
| - MLX5_PCI_POWER_INSUFFICIENT_REPORTED = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_PF_NOTIFY_DISABLE_VF = 0, | |
| - MLX5_PF_NOTIFY_ENABLE_VF = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_PIN_MODE_IN = 0, | |
| - MLX5_PIN_MODE_OUT = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
| - MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, | |
| - MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, | |
| - MLX5_PORT_CHANGE_SUBTYPE_LID = 6, | |
| - MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, | |
| - MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, | |
| - MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1, | |
| - MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 2, | |
| - MLX5_PRIV_FLAGS_DETACH = 4, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_PROF_MASK_QP_SIZE = 1, | |
| - MLX5_PROF_MASK_MR_CACHE = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_PTYS_IB = 1, | |
| - MLX5_PTYS_EN = 4, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_QP_ST_RC = 0, | |
| - MLX5_QP_ST_UC = 1, | |
| - MLX5_QP_ST_UD = 2, | |
| - MLX5_QP_ST_XRC = 3, | |
| - MLX5_QP_ST_MLX = 4, | |
| - MLX5_QP_ST_DCI = 5, | |
| - MLX5_QP_ST_DCT = 6, | |
| - MLX5_QP_ST_QP0 = 7, | |
| - MLX5_QP_ST_QP1 = 8, | |
| - MLX5_QP_ST_RAW_ETHERTYPE = 9, | |
| - MLX5_QP_ST_RAW_IPV6 = 10, | |
| - MLX5_QP_ST_SNIFFER = 11, | |
| - MLX5_QP_ST_SYNC_UMR = 14, | |
| - MLX5_QP_ST_PTP_1588 = 13, | |
| - MLX5_QP_ST_REG_UMR = 12, | |
| - MLX5_QP_ST_MAX = 13, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0, | |
| - MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 4, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 1, | |
| - MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 2, | |
| - MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 3, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_RCV_DBR = 0, | |
| - MLX5_SND_DBR = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_REG_SBPR = 45057, | |
| - MLX5_REG_SBCM = 45058, | |
| - MLX5_REG_QPTS = 16386, | |
| - MLX5_REG_QETCR = 16389, | |
| - MLX5_REG_QTCT = 16394, | |
| - MLX5_REG_QPDPM = 16403, | |
| - MLX5_REG_QCAM = 16409, | |
| - MLX5_REG_DCBX_PARAM = 16416, | |
| - MLX5_REG_DCBX_APP = 16417, | |
| - MLX5_REG_FPGA_CAP = 16418, | |
| - MLX5_REG_FPGA_CTRL = 16419, | |
| - MLX5_REG_FPGA_ACCESS_REG = 16420, | |
| - MLX5_REG_CORE_DUMP = 16430, | |
| - MLX5_REG_PCAP = 20481, | |
| - MLX5_REG_PMTU = 20483, | |
| - MLX5_REG_PTYS = 20484, | |
| - MLX5_REG_PAOS = 20486, | |
| - MLX5_REG_PFCC = 20487, | |
| - MLX5_REG_PPCNT = 20488, | |
| - MLX5_REG_PPTB = 20491, | |
| - MLX5_REG_PBMC = 20492, | |
| - MLX5_REG_PMAOS = 20498, | |
| - MLX5_REG_PUDE = 20489, | |
| - MLX5_REG_PMPE = 20496, | |
| - MLX5_REG_PELC = 20494, | |
| - MLX5_REG_PVLC = 20495, | |
| - MLX5_REG_PCMR = 20545, | |
| - MLX5_REG_PDDR = 20529, | |
| - MLX5_REG_PMLP = 20482, | |
| - MLX5_REG_PPLM = 20515, | |
| - MLX5_REG_PCAM = 20607, | |
| - MLX5_REG_NODE_DESC = 24577, | |
| - MLX5_REG_HOST_ENDIANNESS = 28676, | |
| - MLX5_REG_MTMP = 36874, | |
| - MLX5_REG_MCIA = 36884, | |
| - MLX5_REG_MFRL = 36904, | |
| - MLX5_REG_MLCR = 36907, | |
| - MLX5_REG_MRTC = 36909, | |
| - MLX5_REG_MTRC_CAP = 36928, | |
| - MLX5_REG_MTRC_CONF = 36929, | |
| - MLX5_REG_MTRC_STDB = 36930, | |
| - MLX5_REG_MTRC_CTRL = 36931, | |
| - MLX5_REG_MPEIN = 36944, | |
| - MLX5_REG_MPCNT = 36945, | |
| - MLX5_REG_MTPPS = 36947, | |
| - MLX5_REG_MTPPSE = 36948, | |
| - MLX5_REG_MTUTC = 36949, | |
| - MLX5_REG_MPEGC = 36950, | |
| - MLX5_REG_MCQS = 36960, | |
| - MLX5_REG_MCQI = 36961, | |
| - MLX5_REG_MCC = 36962, | |
| - MLX5_REG_MCDA = 36963, | |
| - MLX5_REG_MCAM = 36991, | |
| - MLX5_REG_MIRC = 37218, | |
| - MLX5_REG_SBCAM = 45087, | |
| - MLX5_REG_RESOURCE_DUMP = 49152, | |
| - MLX5_REG_DTOR = 49166, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0, | |
| - MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 1, | |
| - MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0, | |
| - MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 1, | |
| - MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_RQC_STATE_RST = 0, | |
| - MLX5_RQC_STATE_RDY = 1, | |
| - MLX5_RQC_STATE_ERR = 3, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_RX_HASH_FN_NONE = 0, | |
| - MLX5_RX_HASH_FN_INVERTED_XOR8 = 1, | |
| - MLX5_RX_HASH_FN_TOEPLITZ = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_SEND_WQE_DS = 16, | |
| - MLX5_SEND_WQE_BB = 64, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_SEND_WQE_MAX_WQEBBS = 16, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_SENSOR_NO_ERR = 0, | |
| - MLX5_SENSOR_PCI_COMM_ERR = 1, | |
| - MLX5_SENSOR_PCI_ERR = 2, | |
| - MLX5_SENSOR_NIC_DISABLED = 3, | |
| - MLX5_SENSOR_NIC_SW_RESET = 4, | |
| - MLX5_SENSOR_FW_SYND_RFR = 5, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0, | |
| - MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 1, | |
| - MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 2, | |
| - MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 3, | |
| - MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 4, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0, | |
| - MLX5_SET_HCA_CAP_OP_MOD_ODP = 2, | |
| - MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 3, | |
| - MLX5_SET_HCA_CAP_OP_MOD_ROCE = 4, | |
| - MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 32, | |
| - MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 37, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_SEVERITY_MASK = 7, | |
| - MLX5_SEVERITY_VALID_MASK = 8, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_SHARED_RESOURCE_UID = 65535, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_SQC_STATE_RST = 0, | |
| - MLX5_SQC_STATE_RDY = 1, | |
| - MLX5_SQC_STATE_ERR = 3, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0, | |
| - MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 1, | |
| - MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0, | |
| - MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0, | |
| - MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 1, | |
| - MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0, | |
| - MLX5_TIMESTAMP_FORMAT_DEFAULT = 1, | |
| - MLX5_TIMESTAMP_FORMAT_REAL_TIME = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_TIRC_DISP_TYPE_DIRECT = 0, | |
| - MLX5_TIRC_DISP_TYPE_INDIRECT = 1, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = 1, | |
| - MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = 2, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 1, | |
| - MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 2, | |
| + MM_FILEPAGES = 0, | |
| + MM_ANONPAGES = 1, | |
| + MM_SWAPENTS = 2, | |
| + MM_SHMEMPAGES = 3, | |
| + NR_MM_COUNTERS = 4, | |
| }; | |
| enum { | |
| - MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0, | |
| - MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 1, | |
| - MLX5_TRACER_SUBTYPE_STRINGS_DB_UPDATE = 2, | |
| + MOUNTPROC3_NULL = 0, | |
| + MOUNTPROC3_MNT = 1, | |
| + MOUNTPROC3_DUMP = 2, | |
| + MOUNTPROC3_UMNT = 3, | |
| + MOUNTPROC3_UMNTALL = 4, | |
| + MOUNTPROC3_EXPORT = 5, | |
| }; | |
| enum { | |
| - MLX5_UMR_TRANSLATION_OFFSET_EN = 16, | |
| - MLX5_UMR_CHECK_NOT_FREE = 32, | |
| - MLX5_UMR_CHECK_FREE = 64, | |
| - MLX5_UMR_INLINE = 128, | |
| + MOUNTPROC_NULL = 0, | |
| + MOUNTPROC_MNT = 1, | |
| + MOUNTPROC_DUMP = 2, | |
| + MOUNTPROC_UMNT = 3, | |
| + MOUNTPROC_UMNTALL = 4, | |
| + MOUNTPROC_EXPORT = 5, | |
| }; | |
| enum { | |
| - MLX5_VPORT_ADMIN_STATE_DOWN = 0, | |
| - MLX5_VPORT_ADMIN_STATE_UP = 1, | |
| - MLX5_VPORT_ADMIN_STATE_AUTO = 2, | |
| + MOXA_SUPP_RS232 = 1, | |
| + MOXA_SUPP_RS422 = 2, | |
| + MOXA_SUPP_RS485 = 4, | |
| }; | |
| enum { | |
| - MLX5_VPORT_PF = 0, | |
| - MLX5_VPORT_FIRST_VF = 1, | |
| - MLX5_VPORT_ECPF = 65534, | |
| - MLX5_VPORT_UPLINK = 65535, | |
| + MPLS_IPTUNNEL_UNSPEC = 0, | |
| + MPLS_IPTUNNEL_DST = 1, | |
| + MPLS_IPTUNNEL_TTL = 2, | |
| + __MPLS_IPTUNNEL_MAX = 3, | |
| }; | |
| enum { | |
| - MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0, | |
| - MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 1, | |
| - MLX5_VPORT_STATE_OP_MOD_UPLINK = 2, | |
| + MPLS_STATS_UNSPEC = 0, | |
| + MPLS_STATS_LINK = 1, | |
| + __MPLS_STATS_MAX = 2, | |
| }; | |
| enum { | |
| - MLX5_VSC_SPACE_SCAN_CRSPACE = 7, | |
| + MPOL_DEFAULT = 0, | |
| + MPOL_PREFERRED = 1, | |
| + MPOL_BIND = 2, | |
| + MPOL_INTERLEAVE = 3, | |
| + MPOL_LOCAL = 4, | |
| + MPOL_PREFERRED_MANY = 5, | |
| + MPOL_WEIGHTED_INTERLEAVE = 6, | |
| + MPOL_MAX = 7, | |
| }; | |
| enum { | |
| - MLX5_WQE_CTRL_CQ_UPDATE = 8, | |
| - MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 12, | |
| - MLX5_WQE_CTRL_SOLICITED = 2, | |
| + MPTCP_CMSG_TS = 1, | |
| + MPTCP_CMSG_INQ = 2, | |
| }; | |
| enum { | |
| - MLX5_WQ_END_PAD_MODE_NONE = 0, | |
| - MLX5_WQ_END_PAD_MODE_ALIGN = 1, | |
| + MPTCP_PM_ADDR_ATTR_UNSPEC = 0, | |
| + MPTCP_PM_ADDR_ATTR_FAMILY = 1, | |
| + MPTCP_PM_ADDR_ATTR_ID = 2, | |
| + MPTCP_PM_ADDR_ATTR_ADDR4 = 3, | |
| + MPTCP_PM_ADDR_ATTR_ADDR6 = 4, | |
| + MPTCP_PM_ADDR_ATTR_PORT = 5, | |
| + MPTCP_PM_ADDR_ATTR_FLAGS = 6, | |
| + MPTCP_PM_ADDR_ATTR_IF_IDX = 7, | |
| + __MPTCP_PM_ADDR_ATTR_MAX = 8, | |
| }; | |
| enum { | |
| - MLX5_WQ_TYPE_LINKED_LIST = 0, | |
| - MLX5_WQ_TYPE_CYCLIC = 1, | |
| - MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 2, | |
| - MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 3, | |
| + MPTCP_PM_ATTR_UNSPEC = 0, | |
| + MPTCP_PM_ATTR_ADDR = 1, | |
| + MPTCP_PM_ATTR_RCV_ADD_ADDRS = 2, | |
| + MPTCP_PM_ATTR_SUBFLOWS = 3, | |
| + MPTCP_PM_ATTR_TOKEN = 4, | |
| + MPTCP_PM_ATTR_LOC_ID = 5, | |
| + MPTCP_PM_ATTR_ADDR_REMOTE = 6, | |
| + __MPTCP_ATTR_AFTER_LAST = 7, | |
| }; | |
| enum { | |
| - MMOP_OFFLINE = 0, | |
| - MMOP_ONLINE = 1, | |
| - MMOP_ONLINE_KERNEL = 2, | |
| - MMOP_ONLINE_MOVABLE = 3, | |
| + MPTCP_PM_CMD_UNSPEC = 0, | |
| + MPTCP_PM_CMD_ADD_ADDR = 1, | |
| + MPTCP_PM_CMD_DEL_ADDR = 2, | |
| + MPTCP_PM_CMD_GET_ADDR = 3, | |
| + MPTCP_PM_CMD_FLUSH_ADDRS = 4, | |
| + MPTCP_PM_CMD_SET_LIMITS = 5, | |
| + MPTCP_PM_CMD_GET_LIMITS = 6, | |
| + MPTCP_PM_CMD_SET_FLAGS = 7, | |
| + MPTCP_PM_CMD_ANNOUNCE = 8, | |
| + MPTCP_PM_CMD_REMOVE = 9, | |
| + MPTCP_PM_CMD_SUBFLOW_CREATE = 10, | |
| + MPTCP_PM_CMD_SUBFLOW_DESTROY = 11, | |
| + __MPTCP_PM_CMD_AFTER_LAST = 12, | |
| }; | |
| enum { | |
| - MM_FILEPAGES = 0, | |
| - MM_ANONPAGES = 1, | |
| - MM_SWAPENTS = 2, | |
| - MM_SHMEMPAGES = 3, | |
| - NR_MM_COUNTERS = 4, | |
| + MPTCP_PM_ENDPOINT_ADDR = 1, | |
| + __MPTCP_PM_ENDPOINT_MAX = 2, | |
| }; | |
| enum { | |
| - MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 1, | |
| - MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 2, | |
| + MPTCP_SUBFLOW_ATTR_UNSPEC = 0, | |
| + MPTCP_SUBFLOW_ATTR_TOKEN_REM = 1, | |
| + MPTCP_SUBFLOW_ATTR_TOKEN_LOC = 2, | |
| + MPTCP_SUBFLOW_ATTR_RELWRITE_SEQ = 3, | |
| + MPTCP_SUBFLOW_ATTR_MAP_SEQ = 4, | |
| + MPTCP_SUBFLOW_ATTR_MAP_SFSEQ = 5, | |
| + MPTCP_SUBFLOW_ATTR_SSN_OFFSET = 6, | |
| + MPTCP_SUBFLOW_ATTR_MAP_DATALEN = 7, | |
| + MPTCP_SUBFLOW_ATTR_FLAGS = 8, | |
| + MPTCP_SUBFLOW_ATTR_ID_REM = 9, | |
| + MPTCP_SUBFLOW_ATTR_ID_LOC = 10, | |
| + MPTCP_SUBFLOW_ATTR_PAD = 11, | |
| + __MPTCP_SUBFLOW_ATTR_MAX = 12, | |
| }; | |
| enum { | |
| - MPOL_DEFAULT = 0, | |
| - MPOL_PREFERRED = 1, | |
| - MPOL_BIND = 2, | |
| - MPOL_INTERLEAVE = 3, | |
| - MPOL_LOCAL = 4, | |
| - MPOL_PREFERRED_MANY = 5, | |
| - MPOL_MAX = 6, | |
| + MSGLOOP_IN_PROG = 0, | |
| + MSGLOOP_MSGCOMPLETE = 1, | |
| + MSGLOOP_TERMINATED = 2, | |
| }; | |
| enum { | |
| @@ -6894,7 +6675,8 @@ | |
| MSI_FLAG_DEV_SYSFS = 16, | |
| MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS = 32, | |
| MSI_FLAG_FREE_MSI_DESCS = 64, | |
| - MSI_FLAG_NOMASK_QUIRK = 128, | |
| + MSI_FLAG_USE_DEV_FWNODE = 128, | |
| + MSI_FLAG_PARENT_PM_DEV = 256, | |
| MSI_GENERIC_FLAGS_MASK = 65535, | |
| MSI_DOMAIN_FLAGS_MASK = 4294901760, | |
| MSI_FLAG_MULTI_PCI_MSI = 65536, | |
| @@ -6902,13 +6684,6 @@ | |
| MSI_FLAG_LEVEL_CAPABLE = 262144, | |
| MSI_FLAG_MSIX_CONTIGUOUS = 524288, | |
| MSI_FLAG_PCI_MSIX_ALLOC_DYN = 1048576, | |
| - MSI_FLAG_PCI_IMS = 2097152, | |
| -}; | |
| - | |
| -enum { | |
| - MTD_OPS_PLACE_OOB = 0, | |
| - MTD_OPS_AUTO_OOB = 1, | |
| - MTD_OPS_RAW = 2, | |
| }; | |
| enum { | |
| @@ -6919,6 +6694,45 @@ | |
| }; | |
| enum { | |
| + M_I17 = 0, | |
| + M_I20 = 1, | |
| + M_I20_SR = 2, | |
| + M_I24 = 3, | |
| + M_I24_8_1 = 4, | |
| + M_I24_10_1 = 5, | |
| + M_I27_11_1 = 6, | |
| + M_MINI = 7, | |
| + M_MINI_3_1 = 8, | |
| + M_MINI_4_1 = 9, | |
| + M_MB = 10, | |
| + M_MB_2 = 11, | |
| + M_MB_3 = 12, | |
| + M_MB_5_1 = 13, | |
| + M_MB_6_1 = 14, | |
| + M_MB_7_1 = 15, | |
| + M_MB_SR = 16, | |
| + M_MBA = 17, | |
| + M_MBA_3 = 18, | |
| + M_MBP = 19, | |
| + M_MBP_2 = 20, | |
| + M_MBP_2_2 = 21, | |
| + M_MBP_SR = 22, | |
| + M_MBP_4 = 23, | |
| + M_MBP_5_1 = 24, | |
| + M_MBP_5_2 = 25, | |
| + M_MBP_5_3 = 26, | |
| + M_MBP_6_1 = 27, | |
| + M_MBP_6_2 = 28, | |
| + M_MBP_7_1 = 29, | |
| + M_MBP_8_2 = 30, | |
| + M_UNKNOWN = 31, | |
| +}; | |
| + | |
| +enum { | |
| + NAMESZ = 12, | |
| +}; | |
| + | |
| +enum { | |
| NAPIF_STATE_SCHED = 1, | |
| NAPIF_STATE_MISSED = 2, | |
| NAPIF_STATE_DISABLE = 4, | |
| @@ -6928,8 +6742,12 @@ | |
| NAPIF_STATE_IN_BUSY_POLL = 64, | |
| NAPIF_STATE_PREFER_BUSY_POLL = 128, | |
| NAPIF_STATE_THREADED = 256, | |
| - NAPIF_STATE_DRV0 = 512, | |
| - NAPIF_STATE_SCHED_THREADED = 1024, | |
| + NAPIF_STATE_SCHED_THREADED = 512, | |
| +}; | |
| + | |
| +enum { | |
| + NAPI_F_PREFER_BUSY_POLL = 1, | |
| + NAPI_F_END_ON_RESCHED = 2, | |
| }; | |
| enum { | |
| @@ -6942,8 +6760,7 @@ | |
| NAPI_STATE_IN_BUSY_POLL = 6, | |
| NAPI_STATE_PREFER_BUSY_POLL = 7, | |
| NAPI_STATE_THREADED = 8, | |
| - NAPI_STATE_DRV0 = 9, | |
| - NAPI_STATE_SCHED_THREADED = 10, | |
| + NAPI_STATE_SCHED_THREADED = 9, | |
| }; | |
| enum { | |
| @@ -6969,6 +6786,26 @@ | |
| }; | |
| enum { | |
| + NDD_UNARMED = 1, | |
| + NDD_LOCKED = 2, | |
| + NDD_SECURITY_OVERWRITE = 3, | |
| + NDD_WORK_PENDING = 4, | |
| + NDD_LABELING = 6, | |
| + NDD_INCOHERENT = 7, | |
| + NDD_REGISTER_SYNC = 8, | |
| + ND_IOCTL_MAX_BUFLEN = 4194304, | |
| + ND_CMD_MAX_ELEM = 5, | |
| + ND_CMD_MAX_ENVELOPE = 256, | |
| + ND_MAX_MAPPINGS = 32, | |
| + ND_REGION_PAGEMAP = 0, | |
| + ND_REGION_PERSIST_CACHE = 1, | |
| + ND_REGION_PERSIST_MEMCTRL = 2, | |
| + ND_REGION_ASYNC = 3, | |
| + ND_REGION_CXL = 4, | |
| + DPA_RESOURCE_ADJUSTED = 1, | |
| +}; | |
| + | |
| +enum { | |
| NDTA_UNSPEC = 0, | |
| NDTA_NAME = 1, | |
| NDTA_THRESH1 = 2, | |
| @@ -7046,6 +6883,11 @@ | |
| }; | |
| enum { | |
| + NESTED_SYNC_IMM_BIT = 0, | |
| + NESTED_SYNC_TODO_BIT = 1, | |
| +}; | |
| + | |
| +enum { | |
| NETCONFA_UNSPEC = 0, | |
| NETCONFA_IFINDEX = 1, | |
| NETCONFA_FORWARDING = 2, | |
| @@ -7064,8 +6906,9 @@ | |
| NETDEV_A_DEV_XDP_FEATURES = 3, | |
| NETDEV_A_DEV_XDP_ZC_MAX_SEGS = 4, | |
| NETDEV_A_DEV_XDP_RX_METADATA_FEATURES = 5, | |
| - __NETDEV_A_DEV_MAX = 6, | |
| - NETDEV_A_DEV_MAX = 5, | |
| + NETDEV_A_DEV_XSK_FEATURES = 6, | |
| + __NETDEV_A_DEV_MAX = 7, | |
| + NETDEV_A_DEV_MAX = 6, | |
| }; | |
| enum { | |
| @@ -7106,6 +6949,39 @@ | |
| }; | |
| enum { | |
| + NETDEV_A_QSTATS_IFINDEX = 1, | |
| + NETDEV_A_QSTATS_QUEUE_TYPE = 2, | |
| + NETDEV_A_QSTATS_QUEUE_ID = 3, | |
| + NETDEV_A_QSTATS_SCOPE = 4, | |
| + NETDEV_A_QSTATS_RX_PACKETS = 8, | |
| + NETDEV_A_QSTATS_RX_BYTES = 9, | |
| + NETDEV_A_QSTATS_TX_PACKETS = 10, | |
| + NETDEV_A_QSTATS_TX_BYTES = 11, | |
| + NETDEV_A_QSTATS_RX_ALLOC_FAIL = 12, | |
| + NETDEV_A_QSTATS_RX_HW_DROPS = 13, | |
| + NETDEV_A_QSTATS_RX_HW_DROP_OVERRUNS = 14, | |
| + NETDEV_A_QSTATS_RX_CSUM_UNNECESSARY = 15, | |
| + NETDEV_A_QSTATS_RX_CSUM_NONE = 16, | |
| + NETDEV_A_QSTATS_RX_CSUM_BAD = 17, | |
| + NETDEV_A_QSTATS_RX_HW_GRO_PACKETS = 18, | |
| + NETDEV_A_QSTATS_RX_HW_GRO_BYTES = 19, | |
| + NETDEV_A_QSTATS_RX_HW_GRO_WIRE_PACKETS = 20, | |
| + NETDEV_A_QSTATS_RX_HW_GRO_WIRE_BYTES = 21, | |
| + NETDEV_A_QSTATS_RX_HW_DROP_RATELIMITS = 22, | |
| + NETDEV_A_QSTATS_TX_HW_DROPS = 23, | |
| + NETDEV_A_QSTATS_TX_HW_DROP_ERRORS = 24, | |
| + NETDEV_A_QSTATS_TX_CSUM_NONE = 25, | |
| + NETDEV_A_QSTATS_TX_NEEDS_CSUM = 26, | |
| + NETDEV_A_QSTATS_TX_HW_GSO_PACKETS = 27, | |
| + NETDEV_A_QSTATS_TX_HW_GSO_BYTES = 28, | |
| + NETDEV_A_QSTATS_TX_HW_GSO_WIRE_PACKETS = 29, | |
| + NETDEV_A_QSTATS_TX_HW_GSO_WIRE_BYTES = 30, | |
| + NETDEV_A_QSTATS_TX_HW_DROP_RATELIMITS = 31, | |
| + __NETDEV_A_QSTATS_MAX = 32, | |
| + NETDEV_A_QSTATS_MAX = 31, | |
| +}; | |
| + | |
| +enum { | |
| NETDEV_A_QUEUE_ID = 1, | |
| NETDEV_A_QUEUE_IFINDEX = 2, | |
| NETDEV_A_QUEUE_TYPE = 3, | |
| @@ -7126,8 +7002,9 @@ | |
| NETDEV_CMD_PAGE_POOL_STATS_GET = 9, | |
| NETDEV_CMD_QUEUE_GET = 10, | |
| NETDEV_CMD_NAPI_GET = 11, | |
| - __NETDEV_CMD_MAX = 12, | |
| - NETDEV_CMD_MAX = 11, | |
| + NETDEV_CMD_QSTATS_GET = 12, | |
| + __NETDEV_CMD_MAX = 13, | |
| + NETDEV_CMD_MAX = 12, | |
| }; | |
| enum { | |
| @@ -7230,12 +7107,14 @@ | |
| }; | |
| enum { | |
| - NETLINK_DIAG_MEMINFO = 0, | |
| - NETLINK_DIAG_GROUPS = 1, | |
| - NETLINK_DIAG_RX_RING = 2, | |
| - NETLINK_DIAG_TX_RING = 3, | |
| - NETLINK_DIAG_FLAGS = 4, | |
| - __NETLINK_DIAG_MAX = 5, | |
| + NETLINK_F_KERNEL_SOCKET = 0, | |
| + NETLINK_F_RECV_PKTINFO = 1, | |
| + NETLINK_F_BROADCAST_SEND_ERROR = 2, | |
| + NETLINK_F_RECV_NO_ENOBUFS = 3, | |
| + NETLINK_F_LISTEN_ALL_NSID = 4, | |
| + NETLINK_F_CAP_ACK = 5, | |
| + NETLINK_F_EXT_ACK = 6, | |
| + NETLINK_F_STRICT_CHK = 7, | |
| }; | |
| enum { | |
| @@ -7271,6 +7150,13 @@ | |
| }; | |
| enum { | |
| + NFEA_UNSPEC = 0, | |
| + NFEA_ACTIVITY_NOTIFY = 1, | |
| + NFEA_DONT_REFRESH = 2, | |
| + __NFEA_MAX = 3, | |
| +}; | |
| + | |
| +enum { | |
| NFNL_BATCH_FAILURE = 1, | |
| NFNL_BATCH_DONE = 2, | |
| NFNL_BATCH_REPLAY = 4, | |
| @@ -7288,6 +7174,53 @@ | |
| }; | |
| enum { | |
| + NFP_NET_CFG_MBOX_CMD_FS_ADD_V4 = 0, | |
| + NFP_NET_CFG_MBOX_CMD_FS_DEL_V4 = 1, | |
| + NFP_NET_CFG_MBOX_CMD_FS_ADD_V6 = 2, | |
| + NFP_NET_CFG_MBOX_CMD_FS_DEL_V6 = 3, | |
| + NFP_NET_CFG_MBOX_CMD_FS_ADD_ETHTYPE = 4, | |
| + NFP_NET_CFG_MBOX_CMD_FS_DEL_ETHTYPE = 5, | |
| +}; | |
| + | |
| +enum { | |
| + NFP_SPEED_1G = 0, | |
| + NFP_SPEED_10G = 1, | |
| + NFP_SPEED_25G = 2, | |
| + NFP_SPEED_40G = 3, | |
| + NFP_SPEED_50G = 4, | |
| + NFP_SPEED_100G = 5, | |
| + NFP_SUP_SPEED_NUMBER = 6, | |
| +}; | |
| + | |
| +enum { | |
| + NFS_IOHDR_ERROR = 0, | |
| + NFS_IOHDR_EOF = 1, | |
| + NFS_IOHDR_REDO = 2, | |
| + NFS_IOHDR_STAT = 3, | |
| + NFS_IOHDR_RESEND_PNFS = 4, | |
| + NFS_IOHDR_RESEND_MDS = 5, | |
| + NFS_IOHDR_UNSTABLE_WRITES = 6, | |
| +}; | |
| + | |
| +enum { | |
| + NF_BPF_CT_OPTS_SZ = 12, | |
| +}; | |
| + | |
| +enum { | |
| + NHA_GROUP_STATS_ENTRY_UNSPEC = 0, | |
| + NHA_GROUP_STATS_ENTRY_ID = 1, | |
| + NHA_GROUP_STATS_ENTRY_PACKETS = 2, | |
| + NHA_GROUP_STATS_ENTRY_PACKETS_HW = 3, | |
| + __NHA_GROUP_STATS_ENTRY_MAX = 4, | |
| +}; | |
| + | |
| +enum { | |
| + NHA_GROUP_STATS_UNSPEC = 0, | |
| + NHA_GROUP_STATS_ENTRY = 1, | |
| + __NHA_GROUP_STATS_MAX = 2, | |
| +}; | |
| + | |
| +enum { | |
| NHA_RES_BUCKET_UNSPEC = 0, | |
| NHA_RES_BUCKET_PAD = 0, | |
| NHA_RES_BUCKET_INDEX = 1, | |
| @@ -7321,7 +7254,11 @@ | |
| NHA_FDB = 11, | |
| NHA_RES_GROUP = 12, | |
| NHA_RES_BUCKET = 13, | |
| - __NHA_MAX = 14, | |
| + NHA_OP_FLAGS = 14, | |
| + NHA_GROUP_STATS = 15, | |
| + NHA_HW_STATS_ENABLE = 16, | |
| + NHA_HW_STATS_USED = 17, | |
| + __NHA_MAX = 18, | |
| }; | |
| enum { | |
| @@ -7351,6 +7288,116 @@ | |
| }; | |
| enum { | |
| + NLBL_CALIPSO_A_UNSPEC = 0, | |
| + NLBL_CALIPSO_A_DOI = 1, | |
| + NLBL_CALIPSO_A_MTYPE = 2, | |
| + __NLBL_CALIPSO_A_MAX = 3, | |
| +}; | |
| + | |
| +enum { | |
| + NLBL_CALIPSO_C_UNSPEC = 0, | |
| + NLBL_CALIPSO_C_ADD = 1, | |
| + NLBL_CALIPSO_C_REMOVE = 2, | |
| + NLBL_CALIPSO_C_LIST = 3, | |
| + NLBL_CALIPSO_C_LISTALL = 4, | |
| + __NLBL_CALIPSO_C_MAX = 5, | |
| +}; | |
| + | |
| +enum { | |
| + NLBL_CIPSOV4_A_UNSPEC = 0, | |
| + NLBL_CIPSOV4_A_DOI = 1, | |
| + NLBL_CIPSOV4_A_MTYPE = 2, | |
| + NLBL_CIPSOV4_A_TAG = 3, | |
| + NLBL_CIPSOV4_A_TAGLST = 4, | |
| + NLBL_CIPSOV4_A_MLSLVLLOC = 5, | |
| + NLBL_CIPSOV4_A_MLSLVLREM = 6, | |
| + NLBL_CIPSOV4_A_MLSLVL = 7, | |
| + NLBL_CIPSOV4_A_MLSLVLLST = 8, | |
| + NLBL_CIPSOV4_A_MLSCATLOC = 9, | |
| + NLBL_CIPSOV4_A_MLSCATREM = 10, | |
| + NLBL_CIPSOV4_A_MLSCAT = 11, | |
| + NLBL_CIPSOV4_A_MLSCATLST = 12, | |
| + __NLBL_CIPSOV4_A_MAX = 13, | |
| +}; | |
| + | |
| +enum { | |
| + NLBL_CIPSOV4_C_UNSPEC = 0, | |
| + NLBL_CIPSOV4_C_ADD = 1, | |
| + NLBL_CIPSOV4_C_REMOVE = 2, | |
| + NLBL_CIPSOV4_C_LIST = 3, | |
| + NLBL_CIPSOV4_C_LISTALL = 4, | |
| + __NLBL_CIPSOV4_C_MAX = 5, | |
| +}; | |
| + | |
| +enum { | |
| + NLBL_MGMT_A_UNSPEC = 0, | |
| + NLBL_MGMT_A_DOMAIN = 1, | |
| + NLBL_MGMT_A_PROTOCOL = 2, | |
| + NLBL_MGMT_A_VERSION = 3, | |
| + NLBL_MGMT_A_CV4DOI = 4, | |
| + NLBL_MGMT_A_IPV6ADDR = 5, | |
| + NLBL_MGMT_A_IPV6MASK = 6, | |
| + NLBL_MGMT_A_IPV4ADDR = 7, | |
| + NLBL_MGMT_A_IPV4MASK = 8, | |
| + NLBL_MGMT_A_ADDRSELECTOR = 9, | |
| + NLBL_MGMT_A_SELECTORLIST = 10, | |
| + NLBL_MGMT_A_FAMILY = 11, | |
| + NLBL_MGMT_A_CLPDOI = 12, | |
| + __NLBL_MGMT_A_MAX = 13, | |
| +}; | |
| + | |
| +enum { | |
| + NLBL_MGMT_C_UNSPEC = 0, | |
| + NLBL_MGMT_C_ADD = 1, | |
| + NLBL_MGMT_C_REMOVE = 2, | |
| + NLBL_MGMT_C_LISTALL = 3, | |
| + NLBL_MGMT_C_ADDDEF = 4, | |
| + NLBL_MGMT_C_REMOVEDEF = 5, | |
| + NLBL_MGMT_C_LISTDEF = 6, | |
| + NLBL_MGMT_C_PROTOCOLS = 7, | |
| + NLBL_MGMT_C_VERSION = 8, | |
| + __NLBL_MGMT_C_MAX = 9, | |
| +}; | |
| + | |
| +enum { | |
| + NLBL_UNLABEL_A_UNSPEC = 0, | |
| + NLBL_UNLABEL_A_ACPTFLG = 1, | |
| + NLBL_UNLABEL_A_IPV6ADDR = 2, | |
| + NLBL_UNLABEL_A_IPV6MASK = 3, | |
| + NLBL_UNLABEL_A_IPV4ADDR = 4, | |
| + NLBL_UNLABEL_A_IPV4MASK = 5, | |
| + NLBL_UNLABEL_A_IFACE = 6, | |
| + NLBL_UNLABEL_A_SECCTX = 7, | |
| + __NLBL_UNLABEL_A_MAX = 8, | |
| +}; | |
| + | |
| +enum { | |
| + NLBL_UNLABEL_C_UNSPEC = 0, | |
| + NLBL_UNLABEL_C_ACCEPT = 1, | |
| + NLBL_UNLABEL_C_LIST = 2, | |
| + NLBL_UNLABEL_C_STATICADD = 3, | |
| + NLBL_UNLABEL_C_STATICREMOVE = 4, | |
| + NLBL_UNLABEL_C_STATICLIST = 5, | |
| + NLBL_UNLABEL_C_STATICADDDEF = 6, | |
| + NLBL_UNLABEL_C_STATICREMOVEDEF = 7, | |
| + NLBL_UNLABEL_C_STATICLISTDEF = 8, | |
| + __NLBL_UNLABEL_C_MAX = 9, | |
| +}; | |
| + | |
| +enum { | |
| + NLM_LCK_GRANTED = 0, | |
| + NLM_LCK_DENIED = 1, | |
| + NLM_LCK_DENIED_NOLOCKS = 2, | |
| + NLM_LCK_BLOCKED = 3, | |
| + NLM_LCK_DENIED_GRACE_PERIOD = 4, | |
| + NLM_DEADLCK = 5, | |
| + NLM_ROFS = 6, | |
| + NLM_STALE_FH = 7, | |
| + NLM_FBIG = 8, | |
| + NLM_FAILED = 9, | |
| +}; | |
| + | |
| +enum { | |
| NMI_LOCAL = 0, | |
| NMI_UNKNOWN = 1, | |
| NMI_SERR = 2, | |
| @@ -7359,12 +7406,6 @@ | |
| }; | |
| enum { | |
| - NODE_SIZE = 256, | |
| - KEYS_PER_NODE = 16, | |
| - RECS_PER_LEAF = 15, | |
| -}; | |
| - | |
| -enum { | |
| NONE_FORCE_HPET_RESUME = 0, | |
| OLD_ICH_FORCE_HPET_RESUME = 1, | |
| ICH_FORCE_HPET_RESUME = 2, | |
| @@ -7374,46 +7415,53 @@ | |
| }; | |
| enum { | |
| - NUM_TRIAL_SAMPLES = 8192, | |
| - MAX_SAMPLES_PER_BIT = 66, | |
| + NONE_SVM_INSTR = 0, | |
| + SVM_INSTR_VMRUN = 1, | |
| + SVM_INSTR_VMLOAD = 2, | |
| + SVM_INSTR_VMSAVE = 3, | |
| }; | |
| enum { | |
| - NVMEM_ADD = 1, | |
| - NVMEM_REMOVE = 2, | |
| - NVMEM_CELL_ADD = 3, | |
| - NVMEM_CELL_REMOVE = 4, | |
| + NOTHING = 0, | |
| + DELETE = 1, | |
| + ADD = 2, | |
| + CHANGE = 3, | |
| }; | |
| enum { | |
| - NVME_AEN_CFG_NS_ATTR = 256, | |
| - NVME_AEN_CFG_FW_ACT = 512, | |
| - NVME_AEN_CFG_ANA_CHANGE = 2048, | |
| - NVME_AEN_CFG_DISC_CHANGE = -2147483648, | |
| + NSIM_TRAP_ID_BASE = 93, | |
| + NSIM_TRAP_ID_FID_MISS = 94, | |
| }; | |
| enum { | |
| - NVME_AER_ERROR = 0, | |
| - NVME_AER_SMART = 1, | |
| - NVME_AER_NOTICE = 2, | |
| - NVME_AER_CSS = 6, | |
| - NVME_AER_VS = 7, | |
| + NSMPROC_NULL = 0, | |
| + NSMPROC_STAT = 1, | |
| + NSMPROC_MON = 2, | |
| + NSMPROC_UNMON = 3, | |
| + NSMPROC_UNMON_ALL = 4, | |
| + NSMPROC_SIMU_CRASH = 5, | |
| + NSMPROC_NOTIFY = 6, | |
| }; | |
| enum { | |
| - NVME_AER_ERROR_PERSIST_INT_ERR = 3, | |
| + NUM_TRIAL_SAMPLES = 8192, | |
| + MAX_SAMPLES_PER_BIT = 66, | |
| }; | |
| enum { | |
| - NVME_AER_NOTICE_NS_CHANGED = 0, | |
| - NVME_AER_NOTICE_FW_ACT_STARTING = 1, | |
| - NVME_AER_NOTICE_ANA = 3, | |
| - NVME_AER_NOTICE_DISC_CHANGED = 240, | |
| + NVMEM_ADD = 1, | |
| + NVMEM_REMOVE = 2, | |
| + NVMEM_CELL_ADD = 3, | |
| + NVMEM_CELL_REMOVE = 4, | |
| + NVMEM_LAYOUT_ADD = 5, | |
| + NVMEM_LAYOUT_REMOVE = 6, | |
| }; | |
| enum { | |
| - NVME_CAP_CSS_NVM = 1, | |
| - NVME_CAP_CSS_CSI = 64, | |
| + NVME_AEN_BIT_NS_ATTR = 8, | |
| + NVME_AEN_BIT_FW_ACT = 9, | |
| + NVME_AEN_BIT_ANA_CHANGE = 11, | |
| + NVME_AEN_BIT_DISC_CHANGE = 31, | |
| }; | |
| enum { | |
| @@ -7441,47 +7489,6 @@ | |
| }; | |
| enum { | |
| - NVME_CMBMSC_CRE = 1, | |
| - NVME_CMBMSC_CMSE = 2, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_CMBSZ_SQS = 1, | |
| - NVME_CMBSZ_CQS = 2, | |
| - NVME_CMBSZ_LISTS = 4, | |
| - NVME_CMBSZ_RDS = 8, | |
| - NVME_CMBSZ_WDS = 16, | |
| - NVME_CMBSZ_SZ_SHIFT = 12, | |
| - NVME_CMBSZ_SZ_MASK = 1048575, | |
| - NVME_CMBSZ_SZU_SHIFT = 8, | |
| - NVME_CMBSZ_SZU_MASK = 15, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_CMD_EFFECTS_CSUPP = 1, | |
| - NVME_CMD_EFFECTS_LBCC = 2, | |
| - NVME_CMD_EFFECTS_NCC = 4, | |
| - NVME_CMD_EFFECTS_NIC = 8, | |
| - NVME_CMD_EFFECTS_CCC = 16, | |
| - NVME_CMD_EFFECTS_CSE_MASK = 458752, | |
| - NVME_CMD_EFFECTS_UUID_SEL = 524288, | |
| - NVME_CMD_EFFECTS_SCOPE_MASK = 4293918720, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_CMD_FUSE_FIRST = 1, | |
| - NVME_CMD_FUSE_SECOND = 2, | |
| - NVME_CMD_SGL_METABUF = 64, | |
| - NVME_CMD_SGL_METASEG = 128, | |
| - NVME_CMD_SGL_ALL = 192, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_CSI_NVM = 0, | |
| - NVME_CSI_ZNS = 2, | |
| -}; | |
| - | |
| -enum { | |
| NVME_CSTS_RDY = 1, | |
| NVME_CSTS_CFS = 2, | |
| NVME_CSTS_NSSRO = 16, | |
| @@ -7493,177 +7500,6 @@ | |
| }; | |
| enum { | |
| - NVME_CTRL_CMIC_MULTI_PORT = 1, | |
| - NVME_CTRL_CMIC_MULTI_CTRL = 2, | |
| - NVME_CTRL_CMIC_ANA = 8, | |
| - NVME_CTRL_ONCS_COMPARE = 1, | |
| - NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 2, | |
| - NVME_CTRL_ONCS_DSM = 4, | |
| - NVME_CTRL_ONCS_WRITE_ZEROES = 8, | |
| - NVME_CTRL_ONCS_RESERVATIONS = 32, | |
| - NVME_CTRL_ONCS_TIMESTAMP = 64, | |
| - NVME_CTRL_VWC_PRESENT = 1, | |
| - NVME_CTRL_OACS_SEC_SUPP = 1, | |
| - NVME_CTRL_OACS_NS_MNGT_SUPP = 8, | |
| - NVME_CTRL_OACS_DIRECTIVES = 32, | |
| - NVME_CTRL_OACS_DBBUF_SUPP = 256, | |
| - NVME_CTRL_LPA_CMD_EFFECTS_LOG = 2, | |
| - NVME_CTRL_CTRATT_128_ID = 1, | |
| - NVME_CTRL_CTRATT_NON_OP_PSP = 2, | |
| - NVME_CTRL_CTRATT_NVM_SETS = 4, | |
| - NVME_CTRL_CTRATT_READ_RECV_LVLS = 8, | |
| - NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 16, | |
| - NVME_CTRL_CTRATT_PREDICTABLE_LAT = 32, | |
| - NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 128, | |
| - NVME_CTRL_CTRATT_UUID_LIST = 512, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_DSMGMT_IDR = 1, | |
| - NVME_DSMGMT_IDW = 2, | |
| - NVME_DSMGMT_AD = 4, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_ENABLE_ACRE = 1, | |
| - NVME_ENABLE_LBAFEE = 1, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_HOST_MEM_ENABLE = 1, | |
| - NVME_HOST_MEM_RETURN = 2, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_ID_CNS_NS = 0, | |
| - NVME_ID_CNS_CTRL = 1, | |
| - NVME_ID_CNS_NS_ACTIVE_LIST = 2, | |
| - NVME_ID_CNS_NS_DESC_LIST = 3, | |
| - NVME_ID_CNS_CS_NS = 5, | |
| - NVME_ID_CNS_CS_CTRL = 6, | |
| - NVME_ID_CNS_NS_CS_INDEP = 8, | |
| - NVME_ID_CNS_NS_PRESENT_LIST = 16, | |
| - NVME_ID_CNS_NS_PRESENT = 17, | |
| - NVME_ID_CNS_CTRL_NS_LIST = 18, | |
| - NVME_ID_CNS_CTRL_LIST = 19, | |
| - NVME_ID_CNS_SCNDRY_CTRL_LIST = 21, | |
| - NVME_ID_CNS_NS_GRANULARITY = 22, | |
| - NVME_ID_CNS_UUID_LIST = 23, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_ID_NS_NVM_STS_MASK = 63, | |
| - NVME_ID_NS_NVM_GUARD_SHIFT = 7, | |
| - NVME_ID_NS_NVM_GUARD_MASK = 3, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_IOCTL_VEC = 1, | |
| - NVME_IOCTL_PARTITION = 2, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_NIDT_EUI64 = 1, | |
| - NVME_NIDT_NGUID = 2, | |
| - NVME_NIDT_UUID = 3, | |
| - NVME_NIDT_CSI = 4, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_NSTAT_NRDY = 1, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_NS_FEAT_THIN = 1, | |
| - NVME_NS_FEAT_ATOMICS = 2, | |
| - NVME_NS_FEAT_IO_OPT = 16, | |
| - NVME_NS_ATTR_RO = 1, | |
| - NVME_NS_FLBAS_LBA_MASK = 15, | |
| - NVME_NS_FLBAS_LBA_UMASK = 96, | |
| - NVME_NS_FLBAS_LBA_SHIFT = 1, | |
| - NVME_NS_FLBAS_META_EXT = 16, | |
| - NVME_NS_NMIC_SHARED = 1, | |
| - NVME_LBAF_RP_BEST = 0, | |
| - NVME_LBAF_RP_BETTER = 1, | |
| - NVME_LBAF_RP_GOOD = 2, | |
| - NVME_LBAF_RP_DEGRADED = 3, | |
| - NVME_NS_DPC_PI_LAST = 16, | |
| - NVME_NS_DPC_PI_FIRST = 8, | |
| - NVME_NS_DPC_PI_TYPE3 = 4, | |
| - NVME_NS_DPC_PI_TYPE2 = 2, | |
| - NVME_NS_DPC_PI_TYPE1 = 1, | |
| - NVME_NS_DPS_PI_FIRST = 8, | |
| - NVME_NS_DPS_PI_MASK = 7, | |
| - NVME_NS_DPS_PI_TYPE1 = 1, | |
| - NVME_NS_DPS_PI_TYPE2 = 2, | |
| - NVME_NS_DPS_PI_TYPE3 = 3, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_NVM_NS_16B_GUARD = 0, | |
| - NVME_NVM_NS_32B_GUARD = 1, | |
| - NVME_NVM_NS_64B_GUARD = 2, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_PS_FLAGS_MAX_POWER_SCALE = 1, | |
| - NVME_PS_FLAGS_NON_OP_STATE = 2, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_QUEUE_PHYS_CONTIG = 1, | |
| - NVME_CQ_IRQ_ENABLED = 2, | |
| - NVME_SQ_PRIO_URGENT = 0, | |
| - NVME_SQ_PRIO_HIGH = 2, | |
| - NVME_SQ_PRIO_MEDIUM = 4, | |
| - NVME_SQ_PRIO_LOW = 6, | |
| - NVME_FEAT_ARBITRATION = 1, | |
| - NVME_FEAT_POWER_MGMT = 2, | |
| - NVME_FEAT_LBA_RANGE = 3, | |
| - NVME_FEAT_TEMP_THRESH = 4, | |
| - NVME_FEAT_ERR_RECOVERY = 5, | |
| - NVME_FEAT_VOLATILE_WC = 6, | |
| - NVME_FEAT_NUM_QUEUES = 7, | |
| - NVME_FEAT_IRQ_COALESCE = 8, | |
| - NVME_FEAT_IRQ_CONFIG = 9, | |
| - NVME_FEAT_WRITE_ATOMIC = 10, | |
| - NVME_FEAT_ASYNC_EVENT = 11, | |
| - NVME_FEAT_AUTO_PST = 12, | |
| - NVME_FEAT_HOST_MEM_BUF = 13, | |
| - NVME_FEAT_TIMESTAMP = 14, | |
| - NVME_FEAT_KATO = 15, | |
| - NVME_FEAT_HCTM = 16, | |
| - NVME_FEAT_NOPSC = 17, | |
| - NVME_FEAT_RRL = 18, | |
| - NVME_FEAT_PLM_CONFIG = 19, | |
| - NVME_FEAT_PLM_WINDOW = 20, | |
| - NVME_FEAT_HOST_BEHAVIOR = 22, | |
| - NVME_FEAT_SANITIZE = 23, | |
| - NVME_FEAT_SW_PROGRESS = 128, | |
| - NVME_FEAT_HOST_ID = 129, | |
| - NVME_FEAT_RESV_MASK = 130, | |
| - NVME_FEAT_RESV_PERSIST = 131, | |
| - NVME_FEAT_WRITE_PROTECT = 132, | |
| - NVME_FEAT_VENDOR_START = 192, | |
| - NVME_FEAT_VENDOR_END = 255, | |
| - NVME_LOG_ERROR = 1, | |
| - NVME_LOG_SMART = 2, | |
| - NVME_LOG_FW_SLOT = 3, | |
| - NVME_LOG_CHANGED_NS = 4, | |
| - NVME_LOG_CMD_EFFECTS = 5, | |
| - NVME_LOG_DEVICE_SELF_TEST = 6, | |
| - NVME_LOG_TELEMETRY_HOST = 7, | |
| - NVME_LOG_TELEMETRY_CTRL = 8, | |
| - NVME_LOG_ENDURANCE_GROUP = 9, | |
| - NVME_LOG_ANA = 12, | |
| - NVME_LOG_DISC = 112, | |
| - NVME_LOG_RESERVATION = 128, | |
| - NVME_FWACT_REPL = 0, | |
| - NVME_FWACT_REPL_ACTV = 8, | |
| - NVME_FWACT_ACTV = 16, | |
| -}; | |
| - | |
| -enum { | |
| NVME_REG_CAP = 0, | |
| NVME_REG_VS = 8, | |
| NVME_REG_INTMS = 12, | |
| @@ -7690,177 +7526,102 @@ | |
| }; | |
| enum { | |
| - NVME_REQ_CANCELLED = 1, | |
| - NVME_REQ_USERCMD = 2, | |
| - NVME_MPATH_IO_STATS = 4, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_RW_LR = 32768, | |
| - NVME_RW_FUA = 16384, | |
| - NVME_RW_APPEND_PIREMAP = 512, | |
| - NVME_RW_DSM_FREQ_UNSPEC = 0, | |
| - NVME_RW_DSM_FREQ_TYPICAL = 1, | |
| - NVME_RW_DSM_FREQ_RARE = 2, | |
| - NVME_RW_DSM_FREQ_READS = 3, | |
| - NVME_RW_DSM_FREQ_WRITES = 4, | |
| - NVME_RW_DSM_FREQ_RW = 5, | |
| - NVME_RW_DSM_FREQ_ONCE = 6, | |
| - NVME_RW_DSM_FREQ_PREFETCH = 7, | |
| - NVME_RW_DSM_FREQ_TEMP = 8, | |
| - NVME_RW_DSM_LATENCY_NONE = 0, | |
| - NVME_RW_DSM_LATENCY_IDLE = 16, | |
| - NVME_RW_DSM_LATENCY_NORM = 32, | |
| - NVME_RW_DSM_LATENCY_LOW = 48, | |
| - NVME_RW_DSM_SEQ_REQ = 64, | |
| - NVME_RW_DSM_COMPRESSED = 128, | |
| - NVME_RW_PRINFO_PRCHK_REF = 1024, | |
| - NVME_RW_PRINFO_PRCHK_APP = 2048, | |
| - NVME_RW_PRINFO_PRCHK_GUARD = 4096, | |
| - NVME_RW_PRINFO_PRACT = 8192, | |
| - NVME_RW_DTYPE_STREAMS = 16, | |
| - NVME_WZ_DEAC = 512, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_SC_SUCCESS = 0, | |
| - NVME_SC_INVALID_OPCODE = 1, | |
| - NVME_SC_INVALID_FIELD = 2, | |
| - NVME_SC_CMDID_CONFLICT = 3, | |
| - NVME_SC_DATA_XFER_ERROR = 4, | |
| - NVME_SC_POWER_LOSS = 5, | |
| - NVME_SC_INTERNAL = 6, | |
| - NVME_SC_ABORT_REQ = 7, | |
| - NVME_SC_ABORT_QUEUE = 8, | |
| - NVME_SC_FUSED_FAIL = 9, | |
| - NVME_SC_FUSED_MISSING = 10, | |
| - NVME_SC_INVALID_NS = 11, | |
| - NVME_SC_CMD_SEQ_ERROR = 12, | |
| - NVME_SC_SGL_INVALID_LAST = 13, | |
| - NVME_SC_SGL_INVALID_COUNT = 14, | |
| - NVME_SC_SGL_INVALID_DATA = 15, | |
| - NVME_SC_SGL_INVALID_METADATA = 16, | |
| - NVME_SC_SGL_INVALID_TYPE = 17, | |
| - NVME_SC_CMB_INVALID_USE = 18, | |
| - NVME_SC_PRP_INVALID_OFFSET = 19, | |
| - NVME_SC_ATOMIC_WU_EXCEEDED = 20, | |
| - NVME_SC_OP_DENIED = 21, | |
| - NVME_SC_SGL_INVALID_OFFSET = 22, | |
| - NVME_SC_RESERVED = 23, | |
| - NVME_SC_HOST_ID_INCONSIST = 24, | |
| - NVME_SC_KA_TIMEOUT_EXPIRED = 25, | |
| - NVME_SC_KA_TIMEOUT_INVALID = 26, | |
| - NVME_SC_ABORTED_PREEMPT_ABORT = 27, | |
| - NVME_SC_SANITIZE_FAILED = 28, | |
| - NVME_SC_SANITIZE_IN_PROGRESS = 29, | |
| - NVME_SC_SGL_INVALID_GRANULARITY = 30, | |
| - NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 31, | |
| - NVME_SC_NS_WRITE_PROTECTED = 32, | |
| - NVME_SC_CMD_INTERRUPTED = 33, | |
| - NVME_SC_TRANSIENT_TR_ERR = 34, | |
| - NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 36, | |
| - NVME_SC_INVALID_IO_CMD_SET = 44, | |
| - NVME_SC_LBA_RANGE = 128, | |
| - NVME_SC_CAP_EXCEEDED = 129, | |
| - NVME_SC_NS_NOT_READY = 130, | |
| - NVME_SC_RESERVATION_CONFLICT = 131, | |
| - NVME_SC_FORMAT_IN_PROGRESS = 132, | |
| - NVME_SC_CQ_INVALID = 256, | |
| - NVME_SC_QID_INVALID = 257, | |
| - NVME_SC_QUEUE_SIZE = 258, | |
| - NVME_SC_ABORT_LIMIT = 259, | |
| - NVME_SC_ABORT_MISSING = 260, | |
| - NVME_SC_ASYNC_LIMIT = 261, | |
| - NVME_SC_FIRMWARE_SLOT = 262, | |
| - NVME_SC_FIRMWARE_IMAGE = 263, | |
| - NVME_SC_INVALID_VECTOR = 264, | |
| - NVME_SC_INVALID_LOG_PAGE = 265, | |
| - NVME_SC_INVALID_FORMAT = 266, | |
| - NVME_SC_FW_NEEDS_CONV_RESET = 267, | |
| - NVME_SC_INVALID_QUEUE = 268, | |
| - NVME_SC_FEATURE_NOT_SAVEABLE = 269, | |
| - NVME_SC_FEATURE_NOT_CHANGEABLE = 270, | |
| - NVME_SC_FEATURE_NOT_PER_NS = 271, | |
| - NVME_SC_FW_NEEDS_SUBSYS_RESET = 272, | |
| - NVME_SC_FW_NEEDS_RESET = 273, | |
| - NVME_SC_FW_NEEDS_MAX_TIME = 274, | |
| - NVME_SC_FW_ACTIVATE_PROHIBITED = 275, | |
| - NVME_SC_OVERLAPPING_RANGE = 276, | |
| - NVME_SC_NS_INSUFFICIENT_CAP = 277, | |
| - NVME_SC_NS_ID_UNAVAILABLE = 278, | |
| - NVME_SC_NS_ALREADY_ATTACHED = 280, | |
| - NVME_SC_NS_IS_PRIVATE = 281, | |
| - NVME_SC_NS_NOT_ATTACHED = 282, | |
| - NVME_SC_THIN_PROV_NOT_SUPP = 283, | |
| - NVME_SC_CTRL_LIST_INVALID = 284, | |
| - NVME_SC_SELT_TEST_IN_PROGRESS = 285, | |
| - NVME_SC_BP_WRITE_PROHIBITED = 286, | |
| - NVME_SC_CTRL_ID_INVALID = 287, | |
| - NVME_SC_SEC_CTRL_STATE_INVALID = 288, | |
| - NVME_SC_CTRL_RES_NUM_INVALID = 289, | |
| - NVME_SC_RES_ID_INVALID = 290, | |
| - NVME_SC_PMR_SAN_PROHIBITED = 291, | |
| - NVME_SC_ANA_GROUP_ID_INVALID = 292, | |
| - NVME_SC_ANA_ATTACH_FAILED = 293, | |
| - NVME_SC_BAD_ATTRIBUTES = 384, | |
| - NVME_SC_INVALID_PI = 385, | |
| - NVME_SC_READ_ONLY = 386, | |
| - NVME_SC_ONCS_NOT_SUPPORTED = 387, | |
| - NVME_SC_CONNECT_FORMAT = 384, | |
| - NVME_SC_CONNECT_CTRL_BUSY = 385, | |
| - NVME_SC_CONNECT_INVALID_PARAM = 386, | |
| - NVME_SC_CONNECT_RESTART_DISC = 387, | |
| - NVME_SC_CONNECT_INVALID_HOST = 388, | |
| - NVME_SC_DISCOVERY_RESTART = 400, | |
| - NVME_SC_AUTH_REQUIRED = 401, | |
| - NVME_SC_ZONE_BOUNDARY_ERROR = 440, | |
| - NVME_SC_ZONE_FULL = 441, | |
| - NVME_SC_ZONE_READ_ONLY = 442, | |
| - NVME_SC_ZONE_OFFLINE = 443, | |
| - NVME_SC_ZONE_INVALID_WRITE = 444, | |
| - NVME_SC_ZONE_TOO_MANY_ACTIVE = 445, | |
| - NVME_SC_ZONE_TOO_MANY_OPEN = 446, | |
| - NVME_SC_ZONE_INVALID_TRANSITION = 447, | |
| - NVME_SC_WRITE_FAULT = 640, | |
| - NVME_SC_READ_ERROR = 641, | |
| - NVME_SC_GUARD_CHECK = 642, | |
| - NVME_SC_APPTAG_CHECK = 643, | |
| - NVME_SC_REFTAG_CHECK = 644, | |
| - NVME_SC_COMPARE_FAILED = 645, | |
| - NVME_SC_ACCESS_DENIED = 646, | |
| - NVME_SC_UNWRITTEN_BLOCK = 647, | |
| - NVME_SC_INTERNAL_PATH_ERROR = 768, | |
| - NVME_SC_ANA_PERSISTENT_LOSS = 769, | |
| - NVME_SC_ANA_INACCESSIBLE = 770, | |
| - NVME_SC_ANA_TRANSITION = 771, | |
| - NVME_SC_CTRL_PATH_ERROR = 864, | |
| - NVME_SC_HOST_PATH_ERROR = 880, | |
| - NVME_SC_HOST_ABORTED_CMD = 881, | |
| - NVME_SC_CRD = 6144, | |
| - NVME_SC_MORE = 8192, | |
| - NVME_SC_DNR = 16384, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_SGL_FMT_DATA_DESC = 0, | |
| - NVME_SGL_FMT_SEG_DESC = 2, | |
| - NVME_SGL_FMT_LAST_SEG_DESC = 3, | |
| - NVME_KEY_SGL_FMT_DATA_DESC = 4, | |
| - NVME_TRANSPORT_SGL_DATA_DESC = 5, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_SMART_CRIT_SPARE = 1, | |
| - NVME_SMART_CRIT_TEMPERATURE = 2, | |
| - NVME_SMART_CRIT_RELIABILITY = 4, | |
| - NVME_SMART_CRIT_MEDIA = 8, | |
| - NVME_SMART_CRIT_VOLATILE_MEMORY = 16, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_TEMP_THRESH_MASK = 65535, | |
| - NVME_TEMP_THRESH_SELECT_SHIFT = 16, | |
| - NVME_TEMP_THRESH_TYPE_UNDER = 1048576, | |
| + NV_MMIO_BAR = 5, | |
| + NV_PORTS = 2, | |
| + NV_PIO_MASK = 31, | |
| + NV_MWDMA_MASK = 7, | |
| + NV_UDMA_MASK = 127, | |
| + NV_PORT0_SCR_REG_OFFSET = 0, | |
| + NV_PORT1_SCR_REG_OFFSET = 64, | |
| + NV_INT_STATUS = 16, | |
| + NV_INT_ENABLE = 17, | |
| + NV_INT_STATUS_CK804 = 1088, | |
| + NV_INT_ENABLE_CK804 = 1089, | |
| + NV_INT_DEV = 1, | |
| + NV_INT_PM = 2, | |
| + NV_INT_ADDED = 4, | |
| + NV_INT_REMOVED = 8, | |
| + NV_INT_PORT_SHIFT = 4, | |
| + NV_INT_ALL = 15, | |
| + NV_INT_MASK = 13, | |
| + NV_INT_CONFIG = 18, | |
| + NV_INT_CONFIG_METHD = 1, | |
| + NV_MCP_SATA_CFG_20 = 80, | |
| + NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 4, | |
| + NV_MCP_SATA_CFG_20_PORT0_EN = 131072, | |
| + NV_MCP_SATA_CFG_20_PORT1_EN = 65536, | |
| + NV_MCP_SATA_CFG_20_PORT0_PWB_EN = 16384, | |
| + NV_MCP_SATA_CFG_20_PORT1_PWB_EN = 4096, | |
| + NV_ADMA_MAX_CPBS = 32, | |
| + NV_ADMA_CPB_SZ = 128, | |
| + NV_ADMA_APRD_SZ = 16, | |
| + NV_ADMA_SGTBL_LEN = 56, | |
| + NV_ADMA_SGTBL_TOTAL_LEN = 61, | |
| + NV_ADMA_SGTBL_SZ = 896, | |
| + NV_ADMA_PORT_PRIV_DMA_SZ = 32768, | |
| + NV_ADMA_GEN = 1024, | |
| + NV_ADMA_GEN_CTL = 0, | |
| + NV_ADMA_NOTIFIER_CLEAR = 48, | |
| + NV_ADMA_PORT = 1152, | |
| + NV_ADMA_PORT_SIZE = 256, | |
| + NV_ADMA_CTL = 64, | |
| + NV_ADMA_CPB_COUNT = 66, | |
| + NV_ADMA_NEXT_CPB_IDX = 67, | |
| + NV_ADMA_STAT = 68, | |
| + NV_ADMA_CPB_BASE_LOW = 72, | |
| + NV_ADMA_CPB_BASE_HIGH = 76, | |
| + NV_ADMA_APPEND = 80, | |
| + NV_ADMA_NOTIFIER = 104, | |
| + NV_ADMA_NOTIFIER_ERROR = 108, | |
| + NV_ADMA_CTL_HOTPLUG_IEN = 1, | |
| + NV_ADMA_CTL_CHANNEL_RESET = 32, | |
| + NV_ADMA_CTL_GO = 128, | |
| + NV_ADMA_CTL_AIEN = 256, | |
| + NV_ADMA_CTL_READ_NON_COHERENT = 2048, | |
| + NV_ADMA_CTL_WRITE_NON_COHERENT = 4096, | |
| + NV_CPB_RESP_DONE = 1, | |
| + NV_CPB_RESP_ATA_ERR = 8, | |
| + NV_CPB_RESP_CMD_ERR = 16, | |
| + NV_CPB_RESP_CPB_ERR = 128, | |
| + NV_CPB_CTL_CPB_VALID = 1, | |
| + NV_CPB_CTL_QUEUE = 2, | |
| + NV_CPB_CTL_APRD_VALID = 4, | |
| + NV_CPB_CTL_IEN = 8, | |
| + NV_CPB_CTL_FPDMA = 16, | |
| + NV_APRD_WRITE = 2, | |
| + NV_APRD_END = 4, | |
| + NV_APRD_CONT = 8, | |
| + NV_ADMA_STAT_TIMEOUT = 1, | |
| + NV_ADMA_STAT_HOTUNPLUG = 2, | |
| + NV_ADMA_STAT_HOTPLUG = 4, | |
| + NV_ADMA_STAT_CPBERR = 16, | |
| + NV_ADMA_STAT_SERROR = 32, | |
| + NV_ADMA_STAT_CMD_COMPLETE = 64, | |
| + NV_ADMA_STAT_IDLE = 256, | |
| + NV_ADMA_STAT_LEGACY = 512, | |
| + NV_ADMA_STAT_STOPPED = 1024, | |
| + NV_ADMA_STAT_DONE = 4096, | |
| + NV_ADMA_STAT_ERR = 17, | |
| + NV_ADMA_PORT_REGISTER_MODE = 1, | |
| + NV_ADMA_ATAPI_SETUP_COMPLETE = 2, | |
| + NV_CTL_MCP55 = 1024, | |
| + NV_INT_STATUS_MCP55 = 1088, | |
| + NV_INT_ENABLE_MCP55 = 1092, | |
| + NV_NCQ_REG_MCP55 = 1096, | |
| + NV_INT_ALL_MCP55 = 65535, | |
| + NV_INT_PORT_SHIFT_MCP55 = 16, | |
| + NV_INT_MASK_MCP55 = 65533, | |
| + NV_CTL_PRI_SWNCQ = 2, | |
| + NV_CTL_SEC_SWNCQ = 4, | |
| + NV_SWNCQ_IRQ_DEV = 1, | |
| + NV_SWNCQ_IRQ_PM = 2, | |
| + NV_SWNCQ_IRQ_ADDED = 4, | |
| + NV_SWNCQ_IRQ_REMOVED = 8, | |
| + NV_SWNCQ_IRQ_BACKOUT = 16, | |
| + NV_SWNCQ_IRQ_SDBFIS = 32, | |
| + NV_SWNCQ_IRQ_DHREGFIS = 64, | |
| + NV_SWNCQ_IRQ_DMASETUP = 128, | |
| + NV_SWNCQ_IRQ_HOTPLUG = 12, | |
| }; | |
| enum { | |
| @@ -7869,33 +7630,6 @@ | |
| }; | |
| enum { | |
| - ONLINE_POLICY_CONTIG_ZONES = 0, | |
| - ONLINE_POLICY_AUTO_MOVABLE = 1, | |
| -}; | |
| - | |
| -enum { | |
| - OPT_LOWERDIR = 0, | |
| - OPT_UPPERDIR = 1, | |
| - OPT_WORKDIR = 2, | |
| - OPT_DEFAULT_PERMISSIONS = 3, | |
| - OPT_REDIRECT_DIR = 4, | |
| - OPT_INDEX_ON = 5, | |
| - OPT_INDEX_OFF = 6, | |
| - OPT_UUID_ON = 7, | |
| - OPT_UUID_OFF = 8, | |
| - OPT_NFS_EXPORT_ON = 9, | |
| - OPT_USERXATTR = 10, | |
| - OPT_NFS_EXPORT_OFF = 11, | |
| - OPT_XINO_ON = 12, | |
| - OPT_XINO_OFF = 13, | |
| - OPT_XINO_AUTO = 14, | |
| - OPT_METACOPY_ON = 15, | |
| - OPT_METACOPY_OFF = 16, | |
| - OPT_VOLATILE = 17, | |
| - OPT_ERR = 18, | |
| -}; | |
| - | |
| -enum { | |
| OPT_UID = 0, | |
| OPT_GID = 1, | |
| OPT_MODE = 2, | |
| @@ -7906,70 +7640,84 @@ | |
| }; | |
| enum { | |
| - OVL_XINO_OFF = 0, | |
| - OVL_XINO_AUTO = 1, | |
| - OVL_XINO_ON = 2, | |
| + OUTSIDE_GUEST_MODE = 0, | |
| + IN_GUEST_MODE = 1, | |
| + EXITING_GUEST_MODE = 2, | |
| + READING_SHADOW_PAGE_TABLES = 3, | |
| +}; | |
| + | |
| +enum { | |
| + OVERRIDE_NONE = 0, | |
| + OVERRIDE_BASE = 1, | |
| + OVERRIDE_STRIDE = 2, | |
| + OVERRIDE_HEIGHT = 4, | |
| + OVERRIDE_WIDTH = 8, | |
| }; | |
| enum { | |
| Opt_acl = 0, | |
| - Opt_noacl = 1, | |
| - Opt_clear_cache = 2, | |
| - Opt_commit_interval = 3, | |
| - Opt_compress = 4, | |
| - Opt_compress_force = 5, | |
| - Opt_compress_force_type = 6, | |
| - Opt_compress_type = 7, | |
| - Opt_degraded = 8, | |
| - Opt_device = 9, | |
| - Opt_fatal_errors = 10, | |
| - Opt_flushoncommit = 11, | |
| - Opt_noflushoncommit = 12, | |
| - Opt_max_inline = 13, | |
| - Opt_barrier = 14, | |
| - Opt_nobarrier = 15, | |
| - Opt_datacow = 16, | |
| - Opt_nodatacow = 17, | |
| - Opt_datasum = 18, | |
| - Opt_nodatasum = 19, | |
| - Opt_defrag = 20, | |
| - Opt_nodefrag = 21, | |
| - Opt_discard = 22, | |
| - Opt_nodiscard = 23, | |
| - Opt_discard_mode = 24, | |
| - Opt_norecovery = 25, | |
| - Opt_ratio = 26, | |
| - Opt_rescan_uuid_tree = 27, | |
| - Opt_skip_balance = 28, | |
| - Opt_space_cache = 29, | |
| - Opt_no_space_cache = 30, | |
| - Opt_space_cache_version = 31, | |
| - Opt_ssd = 32, | |
| - Opt_nossd = 33, | |
| - Opt_ssd_spread = 34, | |
| - Opt_nossd_spread = 35, | |
| - Opt_subvol = 36, | |
| - Opt_subvol_empty = 37, | |
| - Opt_subvolid = 38, | |
| - Opt_thread_pool = 39, | |
| - Opt_treelog = 40, | |
| - Opt_notreelog = 41, | |
| - Opt_user_subvol_rm_allowed = 42, | |
| - Opt_rescue = 43, | |
| - Opt_usebackuproot = 44, | |
| - Opt_nologreplay = 45, | |
| - Opt_ignorebadroots = 46, | |
| - Opt_ignoredatacsums = 47, | |
| - Opt_rescue_all = 48, | |
| - Opt_recovery = 49, | |
| - Opt_inode_cache = 50, | |
| - Opt_noinode_cache = 51, | |
| - Opt_check_integrity = 52, | |
| - Opt_check_integrity_including_extent_data = 53, | |
| - Opt_check_integrity_print_mask = 54, | |
| - Opt_enospc_debug = 55, | |
| - Opt_noenospc_debug = 56, | |
| - Opt_err = 57, | |
| + Opt_clear_cache = 1, | |
| + Opt_commit_interval = 2, | |
| + Opt_compress = 3, | |
| + Opt_compress_force = 4, | |
| + Opt_compress_force_type = 5, | |
| + Opt_compress_type = 6, | |
| + Opt_degraded = 7, | |
| + Opt_device = 8, | |
| + Opt_fatal_errors = 9, | |
| + Opt_flushoncommit = 10, | |
| + Opt_max_inline = 11, | |
| + Opt_barrier = 12, | |
| + Opt_datacow = 13, | |
| + Opt_datasum = 14, | |
| + Opt_defrag = 15, | |
| + Opt_discard = 16, | |
| + Opt_discard_mode = 17, | |
| + Opt_ratio = 18, | |
| + Opt_rescan_uuid_tree = 19, | |
| + Opt_skip_balance = 20, | |
| + Opt_space_cache = 21, | |
| + Opt_space_cache_version = 22, | |
| + Opt_ssd = 23, | |
| + Opt_ssd_spread = 24, | |
| + Opt_subvol = 25, | |
| + Opt_subvol_empty = 26, | |
| + Opt_subvolid = 27, | |
| + Opt_thread_pool = 28, | |
| + Opt_treelog = 29, | |
| + Opt_user_subvol_rm_allowed = 30, | |
| + Opt_rescue = 31, | |
| + Opt_usebackuproot = 32, | |
| + Opt_nologreplay = 33, | |
| + Opt_ignorebadroots = 34, | |
| + Opt_ignoredatacsums = 35, | |
| + Opt_rescue_all = 36, | |
| + Opt_enospc_debug = 37, | |
| + Opt_err = 38, | |
| +}; | |
| + | |
| +enum { | |
| + Opt_block = 0, | |
| + Opt_check = 1, | |
| + Opt_cruft = 2, | |
| + Opt_gid = 3, | |
| + Opt_ignore = 4, | |
| + Opt_iocharset = 5, | |
| + Opt_map = 6, | |
| + Opt_mode = 7, | |
| + Opt_nojoliet = 8, | |
| + Opt_norock = 9, | |
| + Opt_sb = 10, | |
| + Opt_session = 11, | |
| + Opt_uid = 12, | |
| + Opt_unhide = 13, | |
| + Opt_utf8 = 14, | |
| + Opt_err___2 = 15, | |
| + Opt_nocompress = 16, | |
| + Opt_hide = 17, | |
| + Opt_showassoc = 18, | |
| + Opt_dmode = 19, | |
| + Opt_overriderockperm = 20, | |
| }; | |
| enum { | |
| @@ -7979,7 +7727,7 @@ | |
| Opt_nogrpid = 3, | |
| Opt_resgid = 4, | |
| Opt_resuid = 5, | |
| - Opt_sb = 6, | |
| + Opt_sb___2 = 6, | |
| Opt_nouid32 = 7, | |
| Opt_debug = 8, | |
| Opt_removed = 9, | |
| @@ -8008,8 +7756,8 @@ | |
| Opt_quota = 32, | |
| Opt_noquota = 33, | |
| Opt_barrier___2 = 34, | |
| - Opt_nobarrier___2 = 35, | |
| - Opt_err___2 = 36, | |
| + Opt_nobarrier = 35, | |
| + Opt_err___3 = 36, | |
| Opt_usrquota = 37, | |
| Opt_grpquota = 38, | |
| Opt_prjquota = 39, | |
| @@ -8032,7 +7780,7 @@ | |
| Opt_dioread_nolock = 56, | |
| Opt_dioread_lock = 57, | |
| Opt_discard___2 = 58, | |
| - Opt_nodiscard___2 = 59, | |
| + Opt_nodiscard = 59, | |
| Opt_init_itable = 60, | |
| Opt_noinit_itable = 61, | |
| Opt_max_dir_size_kb = 62, | |
| @@ -8048,53 +7796,45 @@ | |
| }; | |
| enum { | |
| - Opt_check_n = 0, | |
| - Opt_check_r = 1, | |
| - Opt_check_s = 2, | |
| - Opt_uid = 3, | |
| - Opt_gid = 4, | |
| - Opt_umask = 5, | |
| - Opt_dmask = 6, | |
| - Opt_fmask = 7, | |
| - Opt_allow_utime = 8, | |
| - Opt_codepage = 9, | |
| - Opt_usefree = 10, | |
| - Opt_nocase = 11, | |
| - Opt_quiet = 12, | |
| - Opt_showexec = 13, | |
| - Opt_debug___2 = 14, | |
| - Opt_immutable = 15, | |
| - Opt_dots = 16, | |
| - Opt_nodots = 17, | |
| - Opt_charset = 18, | |
| - Opt_shortname_lower = 19, | |
| - Opt_shortname_win95 = 20, | |
| - Opt_shortname_winnt = 21, | |
| - Opt_shortname_mixed = 22, | |
| - Opt_utf8_no = 23, | |
| - Opt_utf8_yes = 24, | |
| - Opt_uni_xl_no = 25, | |
| - Opt_uni_xl_yes = 26, | |
| - Opt_nonumtail_no = 27, | |
| - Opt_nonumtail_yes = 28, | |
| - Opt_obsolete = 29, | |
| - Opt_flush = 30, | |
| - Opt_tz_utc = 31, | |
| - Opt_rodir = 32, | |
| - Opt_err_cont = 33, | |
| - Opt_err_panic = 34, | |
| - Opt_err_ro = 35, | |
| - Opt_discard___3 = 36, | |
| - Opt_nfs = 37, | |
| - Opt_time_offset = 38, | |
| - Opt_nfs_stale_rw = 39, | |
| - Opt_nfs_nostale_ro = 40, | |
| - Opt_err___3 = 41, | |
| - Opt_dos1xfloppy = 42, | |
| + Opt_debug___2 = 0, | |
| + Opt_dfltuid = 1, | |
| + Opt_dfltgid = 2, | |
| + Opt_afid = 3, | |
| + Opt_uname = 4, | |
| + Opt_remotename = 5, | |
| + Opt_cache = 6, | |
| + Opt_cachetag = 7, | |
| + Opt_nodevmap = 8, | |
| + Opt_noxattr = 9, | |
| + Opt_directio = 10, | |
| + Opt_ignoreqv = 11, | |
| + Opt_access = 12, | |
| + Opt_posixacl = 13, | |
| + Opt_locktimeout = 14, | |
| + Opt_err___4 = 15, | |
| }; | |
| enum { | |
| - Opt_err___4 = 0, | |
| + Opt_direct = 0, | |
| + Opt_fd = 1, | |
| + Opt_gid___2 = 2, | |
| + Opt_ignore___2 = 3, | |
| + Opt_indirect = 4, | |
| + Opt_maxproto = 5, | |
| + Opt_minproto = 6, | |
| + Opt_offset = 7, | |
| + Opt_pgrp = 8, | |
| + Opt_strictexpire = 9, | |
| + Opt_uid___2 = 10, | |
| +}; | |
| + | |
| +enum { | |
| + Opt_discard_sync = 0, | |
| + Opt_discard_async = 1, | |
| +}; | |
| + | |
| +enum { | |
| + Opt_err___5 = 0, | |
| Opt_enc = 1, | |
| Opt_hash = 2, | |
| }; | |
| @@ -8109,77 +7849,113 @@ | |
| }; | |
| enum { | |
| - Opt_kmsg_bytes = 0, | |
| - Opt_err___5 = 1, | |
| + Opt_fatal_errors_panic = 0, | |
| + Opt_fatal_errors_bug = 1, | |
| }; | |
| enum { | |
| - Opt_logbufs = 0, | |
| - Opt_logbsize = 1, | |
| - Opt_logdev = 2, | |
| - Opt_rtdev = 3, | |
| - Opt_wsync = 4, | |
| - Opt_noalign = 5, | |
| - Opt_swalloc = 6, | |
| - Opt_sunit = 7, | |
| - Opt_swidth = 8, | |
| - Opt_nouuid = 9, | |
| - Opt_grpid___2 = 10, | |
| - Opt_nogrpid___2 = 11, | |
| - Opt_bsdgroups = 12, | |
| - Opt_sysvgroups = 13, | |
| - Opt_allocsize = 14, | |
| - Opt_norecovery___2 = 15, | |
| - Opt_inode64 = 16, | |
| - Opt_inode32 = 17, | |
| - Opt_ikeep = 18, | |
| - Opt_noikeep = 19, | |
| - Opt_largeio = 20, | |
| - Opt_nolargeio = 21, | |
| - Opt_attr2 = 22, | |
| - Opt_noattr2 = 23, | |
| - Opt_filestreams = 24, | |
| - Opt_quota___2 = 25, | |
| - Opt_noquota___2 = 26, | |
| - Opt_usrquota___2 = 27, | |
| - Opt_grpquota___2 = 28, | |
| - Opt_prjquota___2 = 29, | |
| - Opt_uquota = 30, | |
| - Opt_gquota = 31, | |
| - Opt_pquota = 32, | |
| - Opt_uqnoenforce = 33, | |
| - Opt_gqnoenforce = 34, | |
| - Opt_pqnoenforce = 35, | |
| - Opt_qnoenforce = 36, | |
| - Opt_discard___4 = 37, | |
| - Opt_nodiscard___3 = 38, | |
| - Opt_dax___2 = 39, | |
| - Opt_dax_enum = 40, | |
| - Opt_discard_sync = 41, | |
| + Opt_local_lock_all = 0, | |
| + Opt_local_lock_flock = 1, | |
| + Opt_local_lock_none = 2, | |
| + Opt_local_lock_posix = 3, | |
| }; | |
| enum { | |
| - Opt_uid___2 = 0, | |
| - Opt_gid___2 = 1, | |
| - Opt_mode = 2, | |
| - Opt_ptmxmode = 3, | |
| - Opt_newinstance = 4, | |
| - Opt_max = 5, | |
| - Opt_err___6 = 6, | |
| + Opt_lookupcache_all = 0, | |
| + Opt_lookupcache_none = 1, | |
| + Opt_lookupcache_positive = 2, | |
| +}; | |
| + | |
| +enum { | |
| + Opt_msize = 0, | |
| + Opt_trans = 1, | |
| + Opt_legacy = 2, | |
| + Opt_version = 3, | |
| + Opt_err___6 = 4, | |
| +}; | |
| + | |
| +enum { | |
| + Opt_port = 0, | |
| + Opt_rfdno = 1, | |
| + Opt_wfdno = 2, | |
| + Opt_err___7 = 3, | |
| + Opt_privport = 4, | |
| +}; | |
| + | |
| +enum { | |
| + Opt_rescue_usebackuproot = 0, | |
| + Opt_rescue_nologreplay = 1, | |
| + Opt_rescue_ignorebadroots = 2, | |
| + Opt_rescue_ignoredatacsums = 3, | |
| + Opt_rescue_parameter_all = 4, | |
| +}; | |
| + | |
| +enum { | |
| + Opt_sec_krb5 = 0, | |
| + Opt_sec_krb5i = 1, | |
| + Opt_sec_krb5p = 2, | |
| + Opt_sec_lkey = 3, | |
| + Opt_sec_lkeyi = 4, | |
| + Opt_sec_lkeyp = 5, | |
| + Opt_sec_none = 6, | |
| + Opt_sec_spkm = 7, | |
| + Opt_sec_spkmi = 8, | |
| + Opt_sec_spkmp = 9, | |
| + Opt_sec_sys = 10, | |
| + nr__Opt_sec = 11, | |
| +}; | |
| + | |
| +enum { | |
| + Opt_space_cache_v1 = 0, | |
| + Opt_space_cache_v2 = 1, | |
| }; | |
| enum { | |
| Opt_uid___3 = 0, | |
| Opt_gid___3 = 1, | |
| Opt_mode___2 = 2, | |
| - Opt_err___7 = 3, | |
| }; | |
| enum { | |
| - PACKETS_PER_SECOND = 20, | |
| - PACKETS_BURSTABLE = 5, | |
| - PACKET_COST = 50000000, | |
| - TOKEN_MAX = 250000000, | |
| + Opt_uid___4 = 0, | |
| + Opt_gid___4 = 1, | |
| + Opt_mode___3 = 2, | |
| + Opt_ptmxmode = 3, | |
| + Opt_newinstance = 4, | |
| + Opt_max = 5, | |
| + Opt_err___8 = 6, | |
| +}; | |
| + | |
| +enum { | |
| + Opt_vers_2 = 0, | |
| + Opt_vers_3 = 1, | |
| + Opt_vers_4 = 2, | |
| + Opt_vers_4_0 = 3, | |
| + Opt_vers_4_1 = 4, | |
| + Opt_vers_4_2 = 5, | |
| +}; | |
| + | |
| +enum { | |
| + Opt_write_lazy = 0, | |
| + Opt_write_eager = 1, | |
| + Opt_write_wait = 2, | |
| +}; | |
| + | |
| +enum { | |
| + Opt_xprt_rdma = 0, | |
| + Opt_xprt_rdma6 = 1, | |
| + Opt_xprt_tcp = 2, | |
| + Opt_xprt_tcp6 = 3, | |
| + Opt_xprt_udp = 4, | |
| + Opt_xprt_udp6 = 5, | |
| + nr__Opt_xprt = 6, | |
| +}; | |
| + | |
| +enum { | |
| + Opt_xprtsec_none = 0, | |
| + Opt_xprtsec_tls = 1, | |
| + Opt_xprtsec_mtls = 2, | |
| + nr__Opt_xprtsec = 3, | |
| }; | |
| enum { | |
| @@ -8189,9 +7965,9 @@ | |
| }; | |
| enum { | |
| - PARSE_INVALID = 1, | |
| - PARSE_NOT_LONGNAME = 2, | |
| - PARSE_EOF = 3, | |
| + PAGE_WAS_MAPPED = 1, | |
| + PAGE_WAS_MLOCKED = 2, | |
| + PAGE_OLD_STATES = 3, | |
| }; | |
| enum { | |
| @@ -8231,6 +8007,16 @@ | |
| }; | |
| enum { | |
| + PCMCIA_IOPORT_0 = 0, | |
| + PCMCIA_IOPORT_1 = 1, | |
| + PCMCIA_IOMEM_0 = 2, | |
| + PCMCIA_IOMEM_1 = 3, | |
| + PCMCIA_IOMEM_2 = 4, | |
| + PCMCIA_IOMEM_3 = 5, | |
| + PCMCIA_NUM_RESOURCES = 6, | |
| +}; | |
| + | |
| +enum { | |
| PCONFIG_CPUID_SUBLEAF_INVALID = 0, | |
| PCONFIG_CPUID_SUBLEAF_TARGETID = 1, | |
| }; | |
| @@ -8287,6 +8073,8 @@ | |
| PERF_X86_EVENT_PEBS_STLAT = 32768, | |
| PERF_X86_EVENT_AMD_BRS = 65536, | |
| PERF_X86_EVENT_PEBS_LAT_HYBRID = 131072, | |
| + PERF_X86_EVENT_NEEDS_BRANCH_STACK = 262144, | |
| + PERF_X86_EVENT_BRANCH_COUNTERS = 524288, | |
| }; | |
| enum { | |
| @@ -8316,6 +8104,49 @@ | |
| }; | |
| enum { | |
| + PG_BUSY = 0, | |
| + PG_MAPPED = 1, | |
| + PG_FOLIO = 2, | |
| + PG_CLEAN = 3, | |
| + PG_COMMIT_TO_DS = 4, | |
| + PG_INODE_REF = 5, | |
| + PG_HEADLOCK = 6, | |
| + PG_TEARDOWN = 7, | |
| + PG_UNLOCKPAGE = 8, | |
| + PG_UPTODATE = 9, | |
| + PG_WB_END = 10, | |
| + PG_REMOVE = 11, | |
| + PG_CONTENDED1 = 12, | |
| + PG_CONTENDED2 = 13, | |
| +}; | |
| + | |
| +enum { | |
| + PIIX_IOCFG = 84, | |
| + ICH5_PMR = 144, | |
| + ICH5_PCS = 146, | |
| + PIIX_SIDPR_BAR = 5, | |
| + PIIX_SIDPR_LEN = 16, | |
| + PIIX_SIDPR_IDX = 0, | |
| + PIIX_SIDPR_DATA = 4, | |
| + PIIX_FLAG_CHECKINTR = 268435456, | |
| + PIIX_FLAG_SIDPR = 536870912, | |
| + PIIX_PATA_FLAGS = 1, | |
| + PIIX_SATA_FLAGS = 268435458, | |
| + PIIX_FLAG_PIO16 = 1073741824, | |
| + PIIX_80C_PRI = 48, | |
| + PIIX_80C_SEC = 192, | |
| + P0 = 0, | |
| + P1 = 1, | |
| + P2 = 2, | |
| + P3 = 3, | |
| + IDE = -1, | |
| + NA = -2, | |
| + RV = -3, | |
| + PIIX_AHCI_DEVICE = 6, | |
| + PIIX_HOST_BROKEN_SUSPEND = 16777216, | |
| +}; | |
| + | |
| +enum { | |
| PIM_TYPE_HELLO = 0, | |
| PIM_TYPE_REGISTER = 1, | |
| PIM_TYPE_REGISTER_STOP = 2, | |
| @@ -8350,7 +8181,8 @@ | |
| POLICYDB_CAP_NNP_NOSUID_TRANSITION = 5, | |
| POLICYDB_CAP_GENFS_SECLABEL_SYMLINKS = 6, | |
| POLICYDB_CAP_IOCTL_SKIP_CLOEXEC = 7, | |
| - __POLICYDB_CAP_MAX = 8, | |
| + POLICYDB_CAP_USERSPACE_INITIAL_CONTEXT = 8, | |
| + __POLICYDB_CAP_MAX = 9, | |
| }; | |
| enum { | |
| @@ -8360,26 +8192,42 @@ | |
| }; | |
| enum { | |
| - POOL_MANAGER_ACTIVE = 1, | |
| - POOL_DISASSOCIATED = 4, | |
| - WORKER_DIE = 2, | |
| - WORKER_IDLE = 4, | |
| - WORKER_PREP = 8, | |
| - WORKER_CPU_INTENSIVE = 64, | |
| - WORKER_UNBOUND = 128, | |
| - WORKER_REBOUND = 256, | |
| - WORKER_NOT_RUNNING = 456, | |
| - NR_STD_WORKER_POOLS = 2, | |
| - UNBOUND_POOL_HASH_ORDER = 6, | |
| - BUSY_WORKER_HASH_ORDER = 6, | |
| - MAX_IDLE_WORKERS_RATIO = 4, | |
| - IDLE_WORKER_TIMEOUT = 300000, | |
| - MAYDAY_INITIAL_TIMEOUT = 10, | |
| - MAYDAY_INTERVAL = 100, | |
| - CREATE_COOLDOWN = 1000, | |
| - RESCUER_NICE_LEVEL = -20, | |
| - HIGHPRI_NICE_LEVEL = -20, | |
| - WQ_NAME_LEN = 24, | |
| + POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN = 0, | |
| + POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL = 1, | |
| + POWER_SUPPLY_CAPACITY_LEVEL_LOW = 2, | |
| + POWER_SUPPLY_CAPACITY_LEVEL_NORMAL = 3, | |
| + POWER_SUPPLY_CAPACITY_LEVEL_HIGH = 4, | |
| + POWER_SUPPLY_CAPACITY_LEVEL_FULL = 5, | |
| +}; | |
| + | |
| +enum { | |
| + POWER_SUPPLY_CHARGE_TYPE_UNKNOWN = 0, | |
| + POWER_SUPPLY_CHARGE_TYPE_NONE = 1, | |
| + POWER_SUPPLY_CHARGE_TYPE_TRICKLE = 2, | |
| + POWER_SUPPLY_CHARGE_TYPE_FAST = 3, | |
| + POWER_SUPPLY_CHARGE_TYPE_STANDARD = 4, | |
| + POWER_SUPPLY_CHARGE_TYPE_ADAPTIVE = 5, | |
| + POWER_SUPPLY_CHARGE_TYPE_CUSTOM = 6, | |
| + POWER_SUPPLY_CHARGE_TYPE_LONGLIFE = 7, | |
| + POWER_SUPPLY_CHARGE_TYPE_BYPASS = 8, | |
| +}; | |
| + | |
| +enum { | |
| + POWER_SUPPLY_HEALTH_UNKNOWN = 0, | |
| + POWER_SUPPLY_HEALTH_GOOD = 1, | |
| + POWER_SUPPLY_HEALTH_OVERHEAT = 2, | |
| + POWER_SUPPLY_HEALTH_DEAD = 3, | |
| + POWER_SUPPLY_HEALTH_OVERVOLTAGE = 4, | |
| + POWER_SUPPLY_HEALTH_UNSPEC_FAILURE = 5, | |
| + POWER_SUPPLY_HEALTH_COLD = 6, | |
| + POWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE = 7, | |
| + POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE = 8, | |
| + POWER_SUPPLY_HEALTH_OVERCURRENT = 9, | |
| + POWER_SUPPLY_HEALTH_CALIBRATION_REQUIRED = 10, | |
| + POWER_SUPPLY_HEALTH_WARM = 11, | |
| + POWER_SUPPLY_HEALTH_COOL = 12, | |
| + POWER_SUPPLY_HEALTH_HOT = 13, | |
| + POWER_SUPPLY_HEALTH_NO_BATTERY = 14, | |
| }; | |
| enum { | |
| @@ -8418,22 +8266,18 @@ | |
| }; | |
| enum { | |
| - PSAMPLE_ATTR_IIFINDEX = 0, | |
| - PSAMPLE_ATTR_OIFINDEX = 1, | |
| - PSAMPLE_ATTR_ORIGSIZE = 2, | |
| - PSAMPLE_ATTR_SAMPLE_GROUP = 3, | |
| - PSAMPLE_ATTR_GROUP_SEQ = 4, | |
| - PSAMPLE_ATTR_SAMPLE_RATE = 5, | |
| - PSAMPLE_ATTR_DATA = 6, | |
| - PSAMPLE_ATTR_GROUP_REFCOUNT = 7, | |
| - PSAMPLE_ATTR_TUNNEL = 8, | |
| - PSAMPLE_ATTR_PAD = 9, | |
| - PSAMPLE_ATTR_OUT_TC = 10, | |
| - PSAMPLE_ATTR_OUT_TC_OCC = 11, | |
| - PSAMPLE_ATTR_LATENCY = 12, | |
| - PSAMPLE_ATTR_TIMESTAMP = 13, | |
| - PSAMPLE_ATTR_PROTO = 14, | |
| - __PSAMPLE_ATTR_MAX = 15, | |
| + PROC_ROOT_INO = 1, | |
| + PROC_IPC_INIT_INO = 4026531839, | |
| + PROC_UTS_INIT_INO = 4026531838, | |
| + PROC_USER_INIT_INO = 4026531837, | |
| + PROC_PID_INIT_INO = 4026531836, | |
| + PROC_CGROUP_INIT_INO = 4026531835, | |
| + PROC_TIME_INIT_INO = 4026531834, | |
| +}; | |
| + | |
| +enum { | |
| + PSS = 0, | |
| + PPC = 1, | |
| }; | |
| enum { | |
| @@ -8453,52 +8297,6 @@ | |
| }; | |
| enum { | |
| - QOS_ENABLE = 0, | |
| - QOS_CTRL = 1, | |
| - NR_QOS_CTRL_PARAMS = 2, | |
| -}; | |
| - | |
| -enum { | |
| - QOS_RPPM = 0, | |
| - QOS_RLAT = 1, | |
| - QOS_WPPM = 2, | |
| - QOS_WLAT = 3, | |
| - QOS_MIN = 4, | |
| - QOS_MAX = 5, | |
| - NR_QOS_PARAMS = 6, | |
| -}; | |
| - | |
| -enum { | |
| - QP_PID = 0, | |
| - QP_STATE = 1, | |
| - QP_XPORT = 2, | |
| - QP_MTU = 3, | |
| - QP_N_RECV = 4, | |
| - QP_RECV_SZ = 5, | |
| - QP_N_SEND = 6, | |
| - QP_LOG_PG_SZ = 7, | |
| - QP_RQPN = 8, | |
| -}; | |
| - | |
| -enum { | |
| - QUOTA_NL_A_UNSPEC = 0, | |
| - QUOTA_NL_A_QTYPE = 1, | |
| - QUOTA_NL_A_EXCESS_ID = 2, | |
| - QUOTA_NL_A_WARNING = 3, | |
| - QUOTA_NL_A_DEV_MAJOR = 4, | |
| - QUOTA_NL_A_DEV_MINOR = 5, | |
| - QUOTA_NL_A_CAUSED_ID = 6, | |
| - QUOTA_NL_A_PAD = 7, | |
| - __QUOTA_NL_A_MAX = 8, | |
| -}; | |
| - | |
| -enum { | |
| - QUOTA_NL_C_UNSPEC = 0, | |
| - QUOTA_NL_C_WARNING = 1, | |
| - __QUOTA_NL_C_MAX = 2, | |
| -}; | |
| - | |
| -enum { | |
| Q_REQUEUE_PI_NONE = 0, | |
| Q_REQUEUE_PI_IGNORE = 1, | |
| Q_REQUEUE_PI_IN_PROGRESS = 2, | |
| @@ -8541,43 +8339,6 @@ | |
| }; | |
| enum { | |
| - RCD = 0, | |
| - RCH_DP = 1, | |
| - DEVICE = 2, | |
| - LD = 3, | |
| - FMLD = 4, | |
| - RP = 5, | |
| - DSP = 6, | |
| - USP = 7, | |
| -}; | |
| - | |
| -enum { | |
| - RDMA_RX_IPSEC_PRIO = 0, | |
| - RDMA_RX_COUNTERS_PRIO = 1, | |
| - RDMA_RX_BYPASS_PRIO = 2, | |
| - RDMA_RX_KERNEL_PRIO = 3, | |
| -}; | |
| - | |
| -enum { | |
| - RDMA_TX_COUNTERS_PRIO = 0, | |
| - RDMA_TX_IPSEC_PRIO = 1, | |
| - RDMA_TX_BYPASS_PRIO = 2, | |
| -}; | |
| - | |
| -enum { | |
| - RDT_FLAG_CMT = 0, | |
| - RDT_FLAG_MBM_TOTAL = 1, | |
| - RDT_FLAG_MBM_LOCAL = 2, | |
| - RDT_FLAG_L3_CAT = 3, | |
| - RDT_FLAG_L3_CDP = 4, | |
| - RDT_FLAG_L2_CAT = 5, | |
| - RDT_FLAG_L2_CDP = 6, | |
| - RDT_FLAG_MBA = 7, | |
| - RDT_FLAG_SMBA = 8, | |
| - RDT_FLAG_BMEC = 9, | |
| -}; | |
| - | |
| -enum { | |
| READA_NONE = 0, | |
| READA_BACK = 1, | |
| READA_FORWARD = 2, | |
| @@ -8599,12 +8360,6 @@ | |
| }; | |
| enum { | |
| - REG_OP_ISFREE = 0, | |
| - REG_OP_ALLOC = 1, | |
| - REG_OP_RELEASE = 2, | |
| -}; | |
| - | |
| -enum { | |
| REQ_FSEQ_PREFLUSH = 1, | |
| REQ_FSEQ_DATA = 2, | |
| REQ_FSEQ_POSTFLUSH = 4, | |
| @@ -8614,40 +8369,6 @@ | |
| }; | |
| enum { | |
| - REQ_F_FIXED_FILE = 1, | |
| - REQ_F_IO_DRAIN = 2, | |
| - REQ_F_LINK = 4, | |
| - REQ_F_HARDLINK = 8, | |
| - REQ_F_FORCE_ASYNC = 16, | |
| - REQ_F_BUFFER_SELECT = 32, | |
| - REQ_F_CQE_SKIP = 64, | |
| - REQ_F_FAIL = 256, | |
| - REQ_F_INFLIGHT = 512, | |
| - REQ_F_CUR_POS = 1024, | |
| - REQ_F_NOWAIT = 2048, | |
| - REQ_F_LINK_TIMEOUT = 4096, | |
| - REQ_F_NEED_CLEANUP = 8192, | |
| - REQ_F_POLLED = 16384, | |
| - REQ_F_BUFFER_SELECTED = 32768, | |
| - REQ_F_BUFFER_RING = 65536, | |
| - REQ_F_REISSUE = 131072, | |
| - REQ_F_SUPPORT_NOWAIT = 536870912, | |
| - REQ_F_ISREG = 1073741824, | |
| - REQ_F_CREDS = 262144, | |
| - REQ_F_REFCOUNT = 524288, | |
| - REQ_F_ARM_LTIMEOUT = 1048576, | |
| - REQ_F_ASYNC_DATA = 2097152, | |
| - REQ_F_SKIP_LINK_CQES = 4194304, | |
| - REQ_F_SINGLE_POLL = 8388608, | |
| - REQ_F_DOUBLE_POLL = 16777216, | |
| - REQ_F_PARTIAL_IO = 33554432, | |
| - REQ_F_APOLL_MULTISHOT = 67108864, | |
| - REQ_F_CLEAR_POLLIN = 134217728, | |
| - REQ_F_HASH_LOCKED = 268435456, | |
| - REQ_F_POLL_NO_LAZY = 2147483648, | |
| -}; | |
| - | |
| -enum { | |
| REQ_F_FIXED_FILE_BIT = 0, | |
| REQ_F_IO_DRAIN_BIT = 1, | |
| REQ_F_LINK_BIT = 2, | |
| @@ -8672,14 +8393,18 @@ | |
| REQ_F_SKIP_LINK_CQES_BIT = 22, | |
| REQ_F_SINGLE_POLL_BIT = 23, | |
| REQ_F_DOUBLE_POLL_BIT = 24, | |
| - REQ_F_PARTIAL_IO_BIT = 25, | |
| - REQ_F_APOLL_MULTISHOT_BIT = 26, | |
| - REQ_F_CLEAR_POLLIN_BIT = 27, | |
| - REQ_F_HASH_LOCKED_BIT = 28, | |
| - REQ_F_SUPPORT_NOWAIT_BIT = 29, | |
| - REQ_F_ISREG_BIT = 30, | |
| - REQ_F_POLL_NO_LAZY_BIT = 31, | |
| - __REQ_F_LAST_BIT = 32, | |
| + REQ_F_APOLL_MULTISHOT_BIT = 25, | |
| + REQ_F_CLEAR_POLLIN_BIT = 26, | |
| + REQ_F_HASH_LOCKED_BIT = 27, | |
| + REQ_F_SUPPORT_NOWAIT_BIT = 28, | |
| + REQ_F_ISREG_BIT = 29, | |
| + REQ_F_POLL_NO_LAZY_BIT = 30, | |
| + REQ_F_CANCEL_SEQ_BIT = 31, | |
| + REQ_F_CAN_POLL_BIT = 32, | |
| + REQ_F_BL_EMPTY_BIT = 33, | |
| + REQ_F_BL_NO_RECYCLE_BIT = 34, | |
| + REQ_F_BUFFERS_COMMIT_BIT = 35, | |
| + __REQ_F_LAST_BIT = 36, | |
| }; | |
| enum { | |
| @@ -8706,23 +8431,62 @@ | |
| }; | |
| enum { | |
| - RNG_SEED_LENGTH = 32, | |
| + RET_PF_CONTINUE = 0, | |
| + RET_PF_RETRY = 1, | |
| + RET_PF_EMULATE = 2, | |
| + RET_PF_INVALID = 3, | |
| + RET_PF_FIXED = 4, | |
| + RET_PF_SPURIOUS = 5, | |
| }; | |
| enum { | |
| - RQ_WAIT_BUSY_PCT = 5, | |
| - UNBUSY_THR_PCT = 75, | |
| - MIN_DELAY_THR_PCT = 500, | |
| - MAX_DELAY_THR_PCT = 25000, | |
| - MIN_DELAY = 250, | |
| - MAX_DELAY = 250000, | |
| - DFGV_USAGE_PCT = 50, | |
| - DFGV_PERIOD = 100000, | |
| - MAX_LAGGING_PERIODS = 10, | |
| - IOC_PAGE_SHIFT = 12, | |
| - IOC_PAGE_SIZE = 4096, | |
| - IOC_SECT_TO_PAGE_SHIFT = 3, | |
| - LCOEF_RANDIO_PAGES = 4096, | |
| + RPCAUTH_info = 0, | |
| + RPCAUTH_EOF = 1, | |
| +}; | |
| + | |
| +enum { | |
| + RPCAUTH_lockd = 0, | |
| + RPCAUTH_mount = 1, | |
| + RPCAUTH_nfs = 2, | |
| + RPCAUTH_portmap = 3, | |
| + RPCAUTH_statd = 4, | |
| + RPCAUTH_nfsd4_cb = 5, | |
| + RPCAUTH_cache = 6, | |
| + RPCAUTH_nfsd = 7, | |
| + RPCAUTH_gssd = 8, | |
| + RPCAUTH_RootEOF = 9, | |
| +}; | |
| + | |
| +enum { | |
| + RPCBPROC_NULL = 0, | |
| + RPCBPROC_SET = 1, | |
| + RPCBPROC_UNSET = 2, | |
| + RPCBPROC_GETPORT = 3, | |
| + RPCBPROC_GETADDR = 3, | |
| + RPCBPROC_DUMP = 4, | |
| + RPCBPROC_CALLIT = 5, | |
| + RPCBPROC_BCAST = 5, | |
| + RPCBPROC_GETTIME = 6, | |
| + RPCBPROC_UADDR2TADDR = 7, | |
| + RPCBPROC_TADDR2UADDR = 8, | |
| + RPCBPROC_GETVERSADDR = 9, | |
| + RPCBPROC_INDIRECT = 10, | |
| + RPCBPROC_GETADDRLIST = 11, | |
| + RPCBPROC_GETSTAT = 12, | |
| +}; | |
| + | |
| +enum { | |
| + RPC_PIPEFS_MOUNT = 0, | |
| + RPC_PIPEFS_UMOUNT = 1, | |
| +}; | |
| + | |
| +enum { | |
| + RQ_SECURE = 0, | |
| + RQ_LOCAL = 1, | |
| + RQ_USEDEFERRAL = 2, | |
| + RQ_DROPME = 3, | |
| + RQ_VICTIM = 4, | |
| + RQ_DATA = 5, | |
| }; | |
| enum { | |
| @@ -8840,24 +8604,17 @@ | |
| }; | |
| enum { | |
| - RWB_DEF_DEPTH = 16, | |
| - RWB_WINDOW_NSEC = 100000000, | |
| - RWB_MIN_WRITE_SAMPLES = 3, | |
| - RWB_UNKNOWN_BUMP = 5, | |
| -}; | |
| - | |
| -enum { | |
| Root_NFS = 255, | |
| Root_CIFS = 254, | |
| + Root_Generic = 253, | |
| Root_RAM0 = 1048576, | |
| - Root_RAM1 = 1048577, | |
| - Root_FD0 = 2097152, | |
| - Root_HDA1 = 3145729, | |
| - Root_HDA2 = 3145730, | |
| - Root_SDA1 = 8388609, | |
| - Root_SDA2 = 8388610, | |
| - Root_HDC1 = 23068673, | |
| - Root_SR0 = 11534336, | |
| +}; | |
| + | |
| +enum { | |
| + Rworksched = 1, | |
| + Rpending = 2, | |
| + Wworksched = 4, | |
| + Wpending = 8, | |
| }; | |
| enum { | |
| @@ -8866,6 +8623,21 @@ | |
| }; | |
| enum { | |
| + SAS_DATAPRES_NO_DATA = 0, | |
| + SAS_DATAPRES_RESPONSE_DATA = 1, | |
| + SAS_DATAPRES_SENSE_DATA = 2, | |
| +}; | |
| + | |
| +enum { | |
| + SAS_DEV_GONE = 0, | |
| + SAS_DEV_FOUND = 1, | |
| + SAS_DEV_DESTROY = 2, | |
| + SAS_DEV_EH_PENDING = 3, | |
| + SAS_DEV_LU_RESET = 4, | |
| + SAS_DEV_RESET = 5, | |
| +}; | |
| + | |
| +enum { | |
| SB_UNFROZEN = 0, | |
| SB_FREEZE_WRITE = 1, | |
| SB_FREEZE_PAGEFAULT = 2, | |
| @@ -8874,22 +8646,29 @@ | |
| }; | |
| enum { | |
| - SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0, | |
| - SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 1, | |
| - SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 2, | |
| - SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 3, | |
| - SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 4, | |
| + SCM_TSTAMP_SND = 0, | |
| + SCM_TSTAMP_SCHED = 1, | |
| + SCM_TSTAMP_ACK = 2, | |
| }; | |
| enum { | |
| - SCHEDULING_HIERARCHY_E_SWITCH = 2, | |
| - SCHEDULING_HIERARCHY_NIC = 3, | |
| + SCTP_AUTH_HMAC_ID_RESERVED_0 = 0, | |
| + SCTP_AUTH_HMAC_ID_SHA1 = 1, | |
| + SCTP_AUTH_HMAC_ID_RESERVED_2 = 2, | |
| + SCTP_AUTH_HMAC_ID_SHA256 = 3, | |
| + __SCTP_AUTH_HMAC_MAX = 4, | |
| }; | |
| enum { | |
| - SCM_TSTAMP_SND = 0, | |
| - SCM_TSTAMP_SCHED = 1, | |
| - SCM_TSTAMP_ACK = 2, | |
| + SCTP_CHUNK_FLAG_T = 1, | |
| +}; | |
| + | |
| +enum { | |
| + SCTP_MAX_DUP_TSNS = 16, | |
| +}; | |
| + | |
| +enum { | |
| + SCTP_MAX_STREAM = 65535, | |
| }; | |
| enum { | |
| @@ -8901,12 +8680,13 @@ | |
| SD_ASYM_CPUCAPACITY = 32, | |
| SD_ASYM_CPUCAPACITY_FULL = 64, | |
| SD_SHARE_CPUCAPACITY = 128, | |
| - SD_SHARE_PKG_RESOURCES = 256, | |
| - SD_SERIALIZE = 512, | |
| - SD_ASYM_PACKING = 1024, | |
| - SD_PREFER_SIBLING = 2048, | |
| - SD_OVERLAP = 4096, | |
| - SD_NUMA = 8192, | |
| + SD_CLUSTER = 256, | |
| + SD_SHARE_LLC = 512, | |
| + SD_SERIALIZE = 1024, | |
| + SD_ASYM_PACKING = 2048, | |
| + SD_PREFER_SIBLING = 4096, | |
| + SD_OVERLAP = 8192, | |
| + SD_NUMA = 16384, | |
| }; | |
| enum { | |
| @@ -8942,8 +8722,7 @@ | |
| SECTION_HAS_MEM_MAP_BIT = 1, | |
| SECTION_IS_ONLINE_BIT = 2, | |
| SECTION_IS_EARLY_BIT = 3, | |
| - SECTION_TAINT_ZONE_DEVICE_BIT = 4, | |
| - SECTION_MAP_LAST_BIT = 5, | |
| + SECTION_MAP_LAST_BIT = 4, | |
| }; | |
| enum { | |
| @@ -8968,45 +8747,200 @@ | |
| }; | |
| enum { | |
| + SEG6_IPTUNNEL_UNSPEC = 0, | |
| + SEG6_IPTUNNEL_SRH = 1, | |
| + __SEG6_IPTUNNEL_MAX = 2, | |
| +}; | |
| + | |
| +enum { | |
| + SEG6_IPTUN_MODE_INLINE = 0, | |
| + SEG6_IPTUN_MODE_ENCAP = 1, | |
| + SEG6_IPTUN_MODE_L2ENCAP = 2, | |
| + SEG6_IPTUN_MODE_ENCAP_RED = 3, | |
| + SEG6_IPTUN_MODE_L2ENCAP_RED = 4, | |
| +}; | |
| + | |
| +enum { | |
| + SEG6_LOCAL_ACTION_UNSPEC = 0, | |
| + SEG6_LOCAL_ACTION_END = 1, | |
| + SEG6_LOCAL_ACTION_END_X = 2, | |
| + SEG6_LOCAL_ACTION_END_T = 3, | |
| + SEG6_LOCAL_ACTION_END_DX2 = 4, | |
| + SEG6_LOCAL_ACTION_END_DX6 = 5, | |
| + SEG6_LOCAL_ACTION_END_DX4 = 6, | |
| + SEG6_LOCAL_ACTION_END_DT6 = 7, | |
| + SEG6_LOCAL_ACTION_END_DT4 = 8, | |
| + SEG6_LOCAL_ACTION_END_B6 = 9, | |
| + SEG6_LOCAL_ACTION_END_B6_ENCAP = 10, | |
| + SEG6_LOCAL_ACTION_END_BM = 11, | |
| + SEG6_LOCAL_ACTION_END_S = 12, | |
| + SEG6_LOCAL_ACTION_END_AS = 13, | |
| + SEG6_LOCAL_ACTION_END_AM = 14, | |
| + SEG6_LOCAL_ACTION_END_BPF = 15, | |
| + SEG6_LOCAL_ACTION_END_DT46 = 16, | |
| + __SEG6_LOCAL_ACTION_MAX = 17, | |
| +}; | |
| + | |
| +enum { | |
| + SEG6_LOCAL_BPF_PROG_UNSPEC = 0, | |
| + SEG6_LOCAL_BPF_PROG = 1, | |
| + SEG6_LOCAL_BPF_PROG_NAME = 2, | |
| + __SEG6_LOCAL_BPF_PROG_MAX = 3, | |
| +}; | |
| + | |
| +enum { | |
| + SEG6_LOCAL_CNT_UNSPEC = 0, | |
| + SEG6_LOCAL_CNT_PAD = 1, | |
| + SEG6_LOCAL_CNT_PACKETS = 2, | |
| + SEG6_LOCAL_CNT_BYTES = 3, | |
| + SEG6_LOCAL_CNT_ERRORS = 4, | |
| + __SEG6_LOCAL_CNT_MAX = 5, | |
| +}; | |
| + | |
| +enum { | |
| + SEG6_LOCAL_FLV_OP_UNSPEC = 0, | |
| + SEG6_LOCAL_FLV_OP_PSP = 1, | |
| + SEG6_LOCAL_FLV_OP_USP = 2, | |
| + SEG6_LOCAL_FLV_OP_USD = 3, | |
| + SEG6_LOCAL_FLV_OP_NEXT_CSID = 4, | |
| + __SEG6_LOCAL_FLV_OP_MAX = 5, | |
| +}; | |
| + | |
| +enum { | |
| + SEG6_LOCAL_FLV_UNSPEC = 0, | |
| + SEG6_LOCAL_FLV_OPERATION = 1, | |
| + SEG6_LOCAL_FLV_LCBLOCK_BITS = 2, | |
| + SEG6_LOCAL_FLV_LCNODE_FN_BITS = 3, | |
| + __SEG6_LOCAL_FLV_MAX = 4, | |
| +}; | |
| + | |
| +enum { | |
| + SEG6_LOCAL_UNSPEC = 0, | |
| + SEG6_LOCAL_ACTION = 1, | |
| + SEG6_LOCAL_SRH = 2, | |
| + SEG6_LOCAL_TABLE = 3, | |
| + SEG6_LOCAL_NH4 = 4, | |
| + SEG6_LOCAL_NH6 = 5, | |
| + SEG6_LOCAL_IIF = 6, | |
| + SEG6_LOCAL_OIF = 7, | |
| + SEG6_LOCAL_BPF = 8, | |
| + SEG6_LOCAL_VRFTABLE = 9, | |
| + SEG6_LOCAL_COUNTERS = 10, | |
| + SEG6_LOCAL_FLAVORS = 11, | |
| + __SEG6_LOCAL_MAX = 12, | |
| +}; | |
| + | |
| +enum { | |
| SELNL_MSG_SETENFORCE = 16, | |
| SELNL_MSG_POLICYLOAD = 17, | |
| SELNL_MSG_MAX = 18, | |
| }; | |
| enum { | |
| - SETWA_FLAGS_APICID = 1, | |
| - SETWA_FLAGS_MEM = 2, | |
| - SETWA_FLAGS_PCIE_SBDF = 4, | |
| + SFP_PHYS_ID = 0, | |
| + SFP_PHYS_EXT_ID = 1, | |
| + SFP_PHYS_EXT_ID_SFP = 4, | |
| + SFP_CONNECTOR = 2, | |
| + SFP_COMPLIANCE = 3, | |
| + SFP_ENCODING = 11, | |
| + SFP_BR_NOMINAL = 12, | |
| + SFP_RATE_ID = 13, | |
| + SFF_RID_8079 = 1, | |
| + SFF_RID_8431_RX_ONLY = 2, | |
| + SFF_RID_8431_TX_ONLY = 4, | |
| + SFF_RID_8431 = 6, | |
| + SFF_RID_10G8G = 14, | |
| + SFP_LINK_LEN_SM_KM = 14, | |
| + SFP_LINK_LEN_SM_100M = 15, | |
| + SFP_LINK_LEN_50UM_OM2_10M = 16, | |
| + SFP_LINK_LEN_62_5UM_OM1_10M = 17, | |
| + SFP_LINK_LEN_COPPER_1M = 18, | |
| + SFP_LINK_LEN_50UM_OM4_10M = 18, | |
| + SFP_LINK_LEN_50UM_OM3_10M = 19, | |
| + SFP_VENDOR_NAME = 20, | |
| + SFP_VENDOR_OUI = 37, | |
| + SFP_VENDOR_PN = 40, | |
| + SFP_VENDOR_REV = 56, | |
| + SFP_OPTICAL_WAVELENGTH_MSB = 60, | |
| + SFP_OPTICAL_WAVELENGTH_LSB = 61, | |
| + SFP_CABLE_SPEC = 60, | |
| + SFP_CC_BASE = 63, | |
| + SFP_OPTIONS = 64, | |
| + SFP_OPTIONS_HIGH_POWER_LEVEL = 8192, | |
| + SFP_OPTIONS_PAGING_A2 = 4096, | |
| + SFP_OPTIONS_RETIMER = 2048, | |
| + SFP_OPTIONS_COOLED_XCVR = 1024, | |
| + SFP_OPTIONS_POWER_DECL = 512, | |
| + SFP_OPTIONS_RX_LINEAR_OUT = 256, | |
| + SFP_OPTIONS_RX_DECISION_THRESH = 128, | |
| + SFP_OPTIONS_TUNABLE_TX = 64, | |
| + SFP_OPTIONS_RATE_SELECT = 32, | |
| + SFP_OPTIONS_TX_DISABLE = 16, | |
| + SFP_OPTIONS_TX_FAULT = 8, | |
| + SFP_OPTIONS_LOS_INVERTED = 4, | |
| + SFP_OPTIONS_LOS_NORMAL = 2, | |
| + SFP_BR_MAX = 66, | |
| + SFP_BR_MIN = 67, | |
| + SFP_VENDOR_SN = 68, | |
| + SFP_DATECODE = 84, | |
| + SFP_DIAGMON = 92, | |
| + SFP_DIAGMON_DDM = 64, | |
| + SFP_DIAGMON_INT_CAL = 32, | |
| + SFP_DIAGMON_EXT_CAL = 16, | |
| + SFP_DIAGMON_RXPWR_AVG = 8, | |
| + SFP_DIAGMON_ADDRMODE = 4, | |
| + SFP_ENHOPTS = 93, | |
| + SFP_ENHOPTS_ALARMWARN = 128, | |
| + SFP_ENHOPTS_SOFT_TX_DISABLE = 64, | |
| + SFP_ENHOPTS_SOFT_TX_FAULT = 32, | |
| + SFP_ENHOPTS_SOFT_RX_LOS = 16, | |
| + SFP_ENHOPTS_SOFT_RATE_SELECT = 8, | |
| + SFP_ENHOPTS_APP_SELECT_SFF8079 = 4, | |
| + SFP_ENHOPTS_SOFT_RATE_SFF8431 = 2, | |
| + SFP_SFF8472_COMPLIANCE = 94, | |
| + SFP_SFF8472_COMPLIANCE_NONE = 0, | |
| + SFP_SFF8472_COMPLIANCE_REV9_3 = 1, | |
| + SFP_SFF8472_COMPLIANCE_REV9_5 = 2, | |
| + SFP_SFF8472_COMPLIANCE_REV10_2 = 3, | |
| + SFP_SFF8472_COMPLIANCE_REV10_4 = 4, | |
| + SFP_SFF8472_COMPLIANCE_REV11_0 = 5, | |
| + SFP_SFF8472_COMPLIANCE_REV11_3 = 6, | |
| + SFP_SFF8472_COMPLIANCE_REV11_4 = 7, | |
| + SFP_SFF8472_COMPLIANCE_REV12_0 = 8, | |
| + SFP_CC_EXT = 95, | |
| }; | |
| enum { | |
| - SEV_RET_NO_FW_CALL = -1, | |
| - SEV_RET_SUCCESS = 0, | |
| - SEV_RET_INVALID_PLATFORM_STATE = 1, | |
| - SEV_RET_INVALID_GUEST_STATE = 2, | |
| - SEV_RET_INAVLID_CONFIG = 3, | |
| - SEV_RET_INVALID_LEN = 4, | |
| - SEV_RET_ALREADY_OWNED = 5, | |
| - SEV_RET_INVALID_CERTIFICATE = 6, | |
| - SEV_RET_POLICY_FAILURE = 7, | |
| - SEV_RET_INACTIVE = 8, | |
| - SEV_RET_INVALID_ADDRESS = 9, | |
| - SEV_RET_BAD_SIGNATURE = 10, | |
| - SEV_RET_BAD_MEASUREMENT = 11, | |
| - SEV_RET_ASID_OWNED = 12, | |
| - SEV_RET_INVALID_ASID = 13, | |
| - SEV_RET_WBINVD_REQUIRED = 14, | |
| - SEV_RET_DFFLUSH_REQUIRED = 15, | |
| - SEV_RET_INVALID_GUEST = 16, | |
| - SEV_RET_INVALID_COMMAND = 17, | |
| - SEV_RET_ACTIVE = 18, | |
| - SEV_RET_HWSEV_RET_PLATFORM = 19, | |
| - SEV_RET_HWSEV_RET_UNSAFE = 20, | |
| - SEV_RET_UNSUPPORTED = 21, | |
| - SEV_RET_INVALID_PARAM = 22, | |
| - SEV_RET_RESOURCE_LIMIT = 23, | |
| - SEV_RET_SECURE_DATA_INVALID = 24, | |
| - SEV_RET_MAX = 25, | |
| + SIL_MMIO_BAR = 5, | |
| + SIL_FLAG_NO_SATA_IRQ = 268435456, | |
| + SIL_FLAG_RERR_ON_DMA_ACT = 536870912, | |
| + SIL_FLAG_MOD15WRITE = 1073741824, | |
| + SIL_DFL_PORT_FLAGS = 2, | |
| + sil_3112 = 0, | |
| + sil_3112_no_sata_irq = 1, | |
| + sil_3512 = 2, | |
| + sil_3114 = 3, | |
| + SIL_SYSCFG = 72, | |
| + SIL_MASK_IDE0_INT = 4194304, | |
| + SIL_MASK_IDE1_INT = 8388608, | |
| + SIL_MASK_IDE2_INT = 16777216, | |
| + SIL_MASK_IDE3_INT = 33554432, | |
| + SIL_MASK_2PORT = 12582912, | |
| + SIL_MASK_4PORT = 62914560, | |
| + SIL_INTR_STEERING = 2, | |
| + SIL_DMA_ENABLE = 1, | |
| + SIL_DMA_RDWR = 8, | |
| + SIL_DMA_SATA_IRQ = 16, | |
| + SIL_DMA_ACTIVE = 65536, | |
| + SIL_DMA_ERROR = 131072, | |
| + SIL_DMA_COMPLETE = 262144, | |
| + SIL_DMA_N_SATA_IRQ = 64, | |
| + SIL_DMA_N_ACTIVE = 16777216, | |
| + SIL_DMA_N_ERROR = 33554432, | |
| + SIL_DMA_N_COMPLETE = 67108864, | |
| + SIL_SIEN_N = 65536, | |
| + SIL_QUIRK_MOD15WRITE = 1, | |
| + SIL_QUIRK_UDMA5MAX = 2, | |
| }; | |
| enum { | |
| @@ -9064,6 +8998,14 @@ | |
| }; | |
| enum { | |
| + SKX_PCI_UNCORE_IMC = 0, | |
| + SKX_PCI_UNCORE_M2M = 1, | |
| + SKX_PCI_UNCORE_UPI = 2, | |
| + SKX_PCI_UNCORE_M2PCIE = 3, | |
| + SKX_PCI_UNCORE_M3UPI = 4, | |
| +}; | |
| + | |
| +enum { | |
| SK_DIAG_BPF_STORAGE_NONE = 0, | |
| SK_DIAG_BPF_STORAGE_PAD = 1, | |
| SK_DIAG_BPF_STORAGE_MAP_ID = 2, | |
| @@ -9103,10 +9045,28 @@ | |
| }; | |
| enum { | |
| - SOCKET_URING_OP_SIOCINQ = 0, | |
| - SOCKET_URING_OP_SIOCOUTQ = 1, | |
| - SOCKET_URING_OP_GETSOCKOPT = 2, | |
| - SOCKET_URING_OP_SETSOCKOPT = 3, | |
| + SNBEP_PCI_UNCORE_HA = 0, | |
| + SNBEP_PCI_UNCORE_IMC = 1, | |
| + SNBEP_PCI_UNCORE_QPI = 2, | |
| + SNBEP_PCI_UNCORE_R2PCIE = 3, | |
| + SNBEP_PCI_UNCORE_R3QPI = 4, | |
| +}; | |
| + | |
| +enum { | |
| + SNB_PCI_UNCORE_IMC = 0, | |
| +}; | |
| + | |
| +enum { | |
| + SNR_PCI_UNCORE_M2M = 0, | |
| + SNR_PCI_UNCORE_PCIE3 = 1, | |
| +}; | |
| + | |
| +enum { | |
| + SNR_QAT_PMON_ID = 0, | |
| + SNR_CBDMA_DMI_PMON_ID = 1, | |
| + SNR_NIS_PMON_ID = 2, | |
| + SNR_DLB_PMON_ID = 3, | |
| + SNR_PCIE_GEN3_PMON_ID = 4, | |
| }; | |
| enum { | |
| @@ -9139,6 +9099,45 @@ | |
| }; | |
| enum { | |
| + SPI_BLIST_NOIUS = 1, | |
| +}; | |
| + | |
| +enum { | |
| + SP_TASK_PENDING = 0, | |
| + SP_NEED_VICTIM = 1, | |
| + SP_VICTIM_REMAINS = 2, | |
| +}; | |
| + | |
| +enum { | |
| + SR_DMAR_FECTL_REG = 0, | |
| + SR_DMAR_FEDATA_REG = 1, | |
| + SR_DMAR_FEADDR_REG = 2, | |
| + SR_DMAR_FEUADDR_REG = 3, | |
| + MAX_SR_DMAR_REGS = 4, | |
| +}; | |
| + | |
| +enum { | |
| + SUNRPC_PIPEFS_NFS_PRIO = 0, | |
| + SUNRPC_PIPEFS_RPC_PRIO = 1, | |
| +}; | |
| + | |
| +enum { | |
| + SUN_WHOLE_DISK = 5, | |
| + LINUX_RAID_PARTITION___2 = 253, | |
| +}; | |
| + | |
| +enum { | |
| + SVC_HANDSHAKE_TO = 5000, | |
| +}; | |
| + | |
| +enum { | |
| + SVC_POOL_AUTO = -1, | |
| + SVC_POOL_GLOBAL = 0, | |
| + SVC_POOL_PERCPU = 1, | |
| + SVC_POOL_PERNODE = 2, | |
| +}; | |
| + | |
| +enum { | |
| SWITCHTEC_GAS_MRPC_OFFSET = 0, | |
| SWITCHTEC_GAS_TOP_CFG_OFFSET = 4096, | |
| SWITCHTEC_GAS_SW_EVENT_OFFSET = 6144, | |
| @@ -9217,8 +9216,10 @@ | |
| }; | |
| enum { | |
| - TASK_IOWAIT = 1, | |
| - TASK_IOWAIT_ACCT = 2, | |
| + TASK_SWITCH_CALL = 0, | |
| + TASK_SWITCH_IRET = 1, | |
| + TASK_SWITCH_JMP = 2, | |
| + TASK_SWITCH_GATE = 3, | |
| }; | |
| enum { | |
| @@ -9231,6 +9232,20 @@ | |
| }; | |
| enum { | |
| + TCA_ACT_BPF_UNSPEC = 0, | |
| + TCA_ACT_BPF_TM = 1, | |
| + TCA_ACT_BPF_PARMS = 2, | |
| + TCA_ACT_BPF_OPS_LEN = 3, | |
| + TCA_ACT_BPF_OPS = 4, | |
| + TCA_ACT_BPF_FD = 5, | |
| + TCA_ACT_BPF_NAME = 6, | |
| + TCA_ACT_BPF_PAD = 7, | |
| + TCA_ACT_BPF_TAG = 8, | |
| + TCA_ACT_BPF_ID = 9, | |
| + __TCA_ACT_BPF_MAX = 10, | |
| +}; | |
| + | |
| +enum { | |
| TCA_ACT_UNSPEC = 0, | |
| TCA_ACT_KIND = 1, | |
| TCA_ACT_OPTIONS = 2, | |
| @@ -9246,6 +9261,44 @@ | |
| }; | |
| enum { | |
| + TCA_BPF_UNSPEC = 0, | |
| + TCA_BPF_ACT = 1, | |
| + TCA_BPF_POLICE = 2, | |
| + TCA_BPF_CLASSID = 3, | |
| + TCA_BPF_OPS_LEN = 4, | |
| + TCA_BPF_OPS = 5, | |
| + TCA_BPF_FD = 6, | |
| + TCA_BPF_NAME = 7, | |
| + TCA_BPF_FLAGS = 8, | |
| + TCA_BPF_FLAGS_GEN = 9, | |
| + TCA_BPF_TAG = 10, | |
| + TCA_BPF_ID = 11, | |
| + __TCA_BPF_MAX = 12, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_CGROUP_UNSPEC = 0, | |
| + TCA_CGROUP_ACT = 1, | |
| + TCA_CGROUP_POLICE = 2, | |
| + TCA_CGROUP_EMATCHES = 3, | |
| + __TCA_CGROUP_MAX = 4, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_EMATCH_TREE_UNSPEC = 0, | |
| + TCA_EMATCH_TREE_HDR = 1, | |
| + TCA_EMATCH_TREE_LIST = 2, | |
| + __TCA_EMATCH_TREE_MAX = 3, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_FLOWER_KEY_CFM_OPT_UNSPEC = 0, | |
| + TCA_FLOWER_KEY_CFM_MD_LEVEL = 1, | |
| + TCA_FLOWER_KEY_CFM_OPCODE = 2, | |
| + __TCA_FLOWER_KEY_CFM_OPT_MAX = 3, | |
| +}; | |
| + | |
| +enum { | |
| TCA_FLOWER_KEY_CT_FLAGS_NEW = 1, | |
| TCA_FLOWER_KEY_CT_FLAGS_ESTABLISHED = 2, | |
| TCA_FLOWER_KEY_CT_FLAGS_RELATED = 4, | |
| @@ -9256,6 +9309,231 @@ | |
| }; | |
| enum { | |
| + TCA_FLOWER_KEY_ENC_OPTS_UNSPEC = 0, | |
| + TCA_FLOWER_KEY_ENC_OPTS_GENEVE = 1, | |
| + TCA_FLOWER_KEY_ENC_OPTS_VXLAN = 2, | |
| + TCA_FLOWER_KEY_ENC_OPTS_ERSPAN = 3, | |
| + TCA_FLOWER_KEY_ENC_OPTS_GTP = 4, | |
| + TCA_FLOWER_KEY_ENC_OPTS_PFCP = 5, | |
| + __TCA_FLOWER_KEY_ENC_OPTS_MAX = 6, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_FLOWER_KEY_ENC_OPT_ERSPAN_UNSPEC = 0, | |
| + TCA_FLOWER_KEY_ENC_OPT_ERSPAN_VER = 1, | |
| + TCA_FLOWER_KEY_ENC_OPT_ERSPAN_INDEX = 2, | |
| + TCA_FLOWER_KEY_ENC_OPT_ERSPAN_DIR = 3, | |
| + TCA_FLOWER_KEY_ENC_OPT_ERSPAN_HWID = 4, | |
| + __TCA_FLOWER_KEY_ENC_OPT_ERSPAN_MAX = 5, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_FLOWER_KEY_ENC_OPT_GENEVE_UNSPEC = 0, | |
| + TCA_FLOWER_KEY_ENC_OPT_GENEVE_CLASS = 1, | |
| + TCA_FLOWER_KEY_ENC_OPT_GENEVE_TYPE = 2, | |
| + TCA_FLOWER_KEY_ENC_OPT_GENEVE_DATA = 3, | |
| + __TCA_FLOWER_KEY_ENC_OPT_GENEVE_MAX = 4, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_FLOWER_KEY_ENC_OPT_GTP_UNSPEC = 0, | |
| + TCA_FLOWER_KEY_ENC_OPT_GTP_PDU_TYPE = 1, | |
| + TCA_FLOWER_KEY_ENC_OPT_GTP_QFI = 2, | |
| + __TCA_FLOWER_KEY_ENC_OPT_GTP_MAX = 3, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_FLOWER_KEY_ENC_OPT_PFCP_UNSPEC = 0, | |
| + TCA_FLOWER_KEY_ENC_OPT_PFCP_TYPE = 1, | |
| + TCA_FLOWER_KEY_ENC_OPT_PFCP_SEID = 2, | |
| + __TCA_FLOWER_KEY_ENC_OPT_PFCP_MAX = 3, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_FLOWER_KEY_ENC_OPT_VXLAN_UNSPEC = 0, | |
| + TCA_FLOWER_KEY_ENC_OPT_VXLAN_GBP = 1, | |
| + __TCA_FLOWER_KEY_ENC_OPT_VXLAN_MAX = 2, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_FLOWER_KEY_FLAGS_IS_FRAGMENT = 1, | |
| + TCA_FLOWER_KEY_FLAGS_FRAG_IS_FIRST = 2, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_FLOWER_KEY_MPLS_OPTS_UNSPEC = 0, | |
| + TCA_FLOWER_KEY_MPLS_OPTS_LSE = 1, | |
| + __TCA_FLOWER_KEY_MPLS_OPTS_MAX = 2, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_FLOWER_KEY_MPLS_OPT_LSE_UNSPEC = 0, | |
| + TCA_FLOWER_KEY_MPLS_OPT_LSE_DEPTH = 1, | |
| + TCA_FLOWER_KEY_MPLS_OPT_LSE_TTL = 2, | |
| + TCA_FLOWER_KEY_MPLS_OPT_LSE_BOS = 3, | |
| + TCA_FLOWER_KEY_MPLS_OPT_LSE_TC = 4, | |
| + TCA_FLOWER_KEY_MPLS_OPT_LSE_LABEL = 5, | |
| + __TCA_FLOWER_KEY_MPLS_OPT_LSE_MAX = 6, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_FLOWER_UNSPEC = 0, | |
| + TCA_FLOWER_CLASSID = 1, | |
| + TCA_FLOWER_INDEV = 2, | |
| + TCA_FLOWER_ACT = 3, | |
| + TCA_FLOWER_KEY_ETH_DST = 4, | |
| + TCA_FLOWER_KEY_ETH_DST_MASK = 5, | |
| + TCA_FLOWER_KEY_ETH_SRC = 6, | |
| + TCA_FLOWER_KEY_ETH_SRC_MASK = 7, | |
| + TCA_FLOWER_KEY_ETH_TYPE = 8, | |
| + TCA_FLOWER_KEY_IP_PROTO = 9, | |
| + TCA_FLOWER_KEY_IPV4_SRC = 10, | |
| + TCA_FLOWER_KEY_IPV4_SRC_MASK = 11, | |
| + TCA_FLOWER_KEY_IPV4_DST = 12, | |
| + TCA_FLOWER_KEY_IPV4_DST_MASK = 13, | |
| + TCA_FLOWER_KEY_IPV6_SRC = 14, | |
| + TCA_FLOWER_KEY_IPV6_SRC_MASK = 15, | |
| + TCA_FLOWER_KEY_IPV6_DST = 16, | |
| + TCA_FLOWER_KEY_IPV6_DST_MASK = 17, | |
| + TCA_FLOWER_KEY_TCP_SRC = 18, | |
| + TCA_FLOWER_KEY_TCP_DST = 19, | |
| + TCA_FLOWER_KEY_UDP_SRC = 20, | |
| + TCA_FLOWER_KEY_UDP_DST = 21, | |
| + TCA_FLOWER_FLAGS = 22, | |
| + TCA_FLOWER_KEY_VLAN_ID = 23, | |
| + TCA_FLOWER_KEY_VLAN_PRIO = 24, | |
| + TCA_FLOWER_KEY_VLAN_ETH_TYPE = 25, | |
| + TCA_FLOWER_KEY_ENC_KEY_ID = 26, | |
| + TCA_FLOWER_KEY_ENC_IPV4_SRC = 27, | |
| + TCA_FLOWER_KEY_ENC_IPV4_SRC_MASK = 28, | |
| + TCA_FLOWER_KEY_ENC_IPV4_DST = 29, | |
| + TCA_FLOWER_KEY_ENC_IPV4_DST_MASK = 30, | |
| + TCA_FLOWER_KEY_ENC_IPV6_SRC = 31, | |
| + TCA_FLOWER_KEY_ENC_IPV6_SRC_MASK = 32, | |
| + TCA_FLOWER_KEY_ENC_IPV6_DST = 33, | |
| + TCA_FLOWER_KEY_ENC_IPV6_DST_MASK = 34, | |
| + TCA_FLOWER_KEY_TCP_SRC_MASK = 35, | |
| + TCA_FLOWER_KEY_TCP_DST_MASK = 36, | |
| + TCA_FLOWER_KEY_UDP_SRC_MASK = 37, | |
| + TCA_FLOWER_KEY_UDP_DST_MASK = 38, | |
| + TCA_FLOWER_KEY_SCTP_SRC_MASK = 39, | |
| + TCA_FLOWER_KEY_SCTP_DST_MASK = 40, | |
| + TCA_FLOWER_KEY_SCTP_SRC = 41, | |
| + TCA_FLOWER_KEY_SCTP_DST = 42, | |
| + TCA_FLOWER_KEY_ENC_UDP_SRC_PORT = 43, | |
| + TCA_FLOWER_KEY_ENC_UDP_SRC_PORT_MASK = 44, | |
| + TCA_FLOWER_KEY_ENC_UDP_DST_PORT = 45, | |
| + TCA_FLOWER_KEY_ENC_UDP_DST_PORT_MASK = 46, | |
| + TCA_FLOWER_KEY_FLAGS = 47, | |
| + TCA_FLOWER_KEY_FLAGS_MASK = 48, | |
| + TCA_FLOWER_KEY_ICMPV4_CODE = 49, | |
| + TCA_FLOWER_KEY_ICMPV4_CODE_MASK = 50, | |
| + TCA_FLOWER_KEY_ICMPV4_TYPE = 51, | |
| + TCA_FLOWER_KEY_ICMPV4_TYPE_MASK = 52, | |
| + TCA_FLOWER_KEY_ICMPV6_CODE = 53, | |
| + TCA_FLOWER_KEY_ICMPV6_CODE_MASK = 54, | |
| + TCA_FLOWER_KEY_ICMPV6_TYPE = 55, | |
| + TCA_FLOWER_KEY_ICMPV6_TYPE_MASK = 56, | |
| + TCA_FLOWER_KEY_ARP_SIP = 57, | |
| + TCA_FLOWER_KEY_ARP_SIP_MASK = 58, | |
| + TCA_FLOWER_KEY_ARP_TIP = 59, | |
| + TCA_FLOWER_KEY_ARP_TIP_MASK = 60, | |
| + TCA_FLOWER_KEY_ARP_OP = 61, | |
| + TCA_FLOWER_KEY_ARP_OP_MASK = 62, | |
| + TCA_FLOWER_KEY_ARP_SHA = 63, | |
| + TCA_FLOWER_KEY_ARP_SHA_MASK = 64, | |
| + TCA_FLOWER_KEY_ARP_THA = 65, | |
| + TCA_FLOWER_KEY_ARP_THA_MASK = 66, | |
| + TCA_FLOWER_KEY_MPLS_TTL = 67, | |
| + TCA_FLOWER_KEY_MPLS_BOS = 68, | |
| + TCA_FLOWER_KEY_MPLS_TC = 69, | |
| + TCA_FLOWER_KEY_MPLS_LABEL = 70, | |
| + TCA_FLOWER_KEY_TCP_FLAGS = 71, | |
| + TCA_FLOWER_KEY_TCP_FLAGS_MASK = 72, | |
| + TCA_FLOWER_KEY_IP_TOS = 73, | |
| + TCA_FLOWER_KEY_IP_TOS_MASK = 74, | |
| + TCA_FLOWER_KEY_IP_TTL = 75, | |
| + TCA_FLOWER_KEY_IP_TTL_MASK = 76, | |
| + TCA_FLOWER_KEY_CVLAN_ID = 77, | |
| + TCA_FLOWER_KEY_CVLAN_PRIO = 78, | |
| + TCA_FLOWER_KEY_CVLAN_ETH_TYPE = 79, | |
| + TCA_FLOWER_KEY_ENC_IP_TOS = 80, | |
| + TCA_FLOWER_KEY_ENC_IP_TOS_MASK = 81, | |
| + TCA_FLOWER_KEY_ENC_IP_TTL = 82, | |
| + TCA_FLOWER_KEY_ENC_IP_TTL_MASK = 83, | |
| + TCA_FLOWER_KEY_ENC_OPTS = 84, | |
| + TCA_FLOWER_KEY_ENC_OPTS_MASK = 85, | |
| + TCA_FLOWER_IN_HW_COUNT = 86, | |
| + TCA_FLOWER_KEY_PORT_SRC_MIN = 87, | |
| + TCA_FLOWER_KEY_PORT_SRC_MAX = 88, | |
| + TCA_FLOWER_KEY_PORT_DST_MIN = 89, | |
| + TCA_FLOWER_KEY_PORT_DST_MAX = 90, | |
| + TCA_FLOWER_KEY_CT_STATE = 91, | |
| + TCA_FLOWER_KEY_CT_STATE_MASK = 92, | |
| + TCA_FLOWER_KEY_CT_ZONE = 93, | |
| + TCA_FLOWER_KEY_CT_ZONE_MASK = 94, | |
| + TCA_FLOWER_KEY_CT_MARK = 95, | |
| + TCA_FLOWER_KEY_CT_MARK_MASK = 96, | |
| + TCA_FLOWER_KEY_CT_LABELS = 97, | |
| + TCA_FLOWER_KEY_CT_LABELS_MASK = 98, | |
| + TCA_FLOWER_KEY_MPLS_OPTS = 99, | |
| + TCA_FLOWER_KEY_HASH = 100, | |
| + TCA_FLOWER_KEY_HASH_MASK = 101, | |
| + TCA_FLOWER_KEY_NUM_OF_VLANS = 102, | |
| + TCA_FLOWER_KEY_PPPOE_SID = 103, | |
| + TCA_FLOWER_KEY_PPP_PROTO = 104, | |
| + TCA_FLOWER_KEY_L2TPV3_SID = 105, | |
| + TCA_FLOWER_L2_MISS = 106, | |
| + TCA_FLOWER_KEY_CFM = 107, | |
| + TCA_FLOWER_KEY_SPI = 108, | |
| + TCA_FLOWER_KEY_SPI_MASK = 109, | |
| + __TCA_FLOWER_MAX = 110, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_FQ_CODEL_UNSPEC = 0, | |
| + TCA_FQ_CODEL_TARGET = 1, | |
| + TCA_FQ_CODEL_LIMIT = 2, | |
| + TCA_FQ_CODEL_INTERVAL = 3, | |
| + TCA_FQ_CODEL_ECN = 4, | |
| + TCA_FQ_CODEL_FLOWS = 5, | |
| + TCA_FQ_CODEL_QUANTUM = 6, | |
| + TCA_FQ_CODEL_CE_THRESHOLD = 7, | |
| + TCA_FQ_CODEL_DROP_BATCH_SIZE = 8, | |
| + TCA_FQ_CODEL_MEMORY_LIMIT = 9, | |
| + TCA_FQ_CODEL_CE_THRESHOLD_SELECTOR = 10, | |
| + TCA_FQ_CODEL_CE_THRESHOLD_MASK = 11, | |
| + __TCA_FQ_CODEL_MAX = 12, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_FQ_CODEL_XSTATS_QDISC = 0, | |
| + TCA_FQ_CODEL_XSTATS_CLASS = 1, | |
| +}; | |
| + | |
| +enum { | |
| + TCA_FQ_UNSPEC = 0, | |
| + TCA_FQ_PLIMIT = 1, | |
| + TCA_FQ_FLOW_PLIMIT = 2, | |
| + TCA_FQ_QUANTUM = 3, | |
| + TCA_FQ_INITIAL_QUANTUM = 4, | |
| + TCA_FQ_RATE_ENABLE = 5, | |
| + TCA_FQ_FLOW_DEFAULT_RATE = 6, | |
| + TCA_FQ_FLOW_MAX_RATE = 7, | |
| + TCA_FQ_BUCKETS_LOG = 8, | |
| + TCA_FQ_FLOW_REFILL_DELAY = 9, | |
| + TCA_FQ_ORPHAN_MASK = 10, | |
| + TCA_FQ_LOW_RATE_THRESHOLD = 11, | |
| + TCA_FQ_CE_THRESHOLD = 12, | |
| + TCA_FQ_TIMER_SLACK = 13, | |
| + TCA_FQ_HORIZON = 14, | |
| + TCA_FQ_HORIZON_DROP = 15, | |
| + TCA_FQ_PRIOMAP = 16, | |
| + TCA_FQ_WEIGHTS = 17, | |
| + __TCA_FQ_MAX = 18, | |
| +}; | |
| + | |
| +enum { | |
| TCA_ROOT_UNSPEC = 0, | |
| TCA_ROOT_TAB = 1, | |
| TCA_ROOT_FLAGS = 2, | |
| @@ -9319,6 +9597,7 @@ | |
| TCPF_LISTEN = 1024, | |
| TCPF_CLOSING = 2048, | |
| TCPF_NEW_SYN_RECV = 4096, | |
| + TCPF_BOUND_INACTIVE = 8192, | |
| }; | |
| enum { | |
| @@ -9363,7 +9642,8 @@ | |
| TCP_LISTEN = 10, | |
| TCP_CLOSING = 11, | |
| TCP_NEW_SYN_RECV = 12, | |
| - TCP_MAX_STATES = 13, | |
| + TCP_BOUND_INACTIVE = 13, | |
| + TCP_MAX_STATES = 14, | |
| }; | |
| enum { | |
| @@ -9469,9 +9749,81 @@ | |
| }; | |
| enum { | |
| - TC_MQPRIO_MODE_DCB = 0, | |
| - TC_MQPRIO_MODE_CHANNEL = 1, | |
| - __TC_MQPRIO_MODE_MAX = 2, | |
| + TEST_NONE = 0, | |
| + TEST_CORE = 1, | |
| + TEST_CPUS = 2, | |
| + TEST_PLATFORM = 3, | |
| + TEST_DEVICES = 4, | |
| + TEST_FREEZER = 5, | |
| + __TEST_AFTER_LAST = 6, | |
| +}; | |
| + | |
| +enum { | |
| + TKIP_DECRYPT_OK = 0, | |
| + TKIP_DECRYPT_NO_EXT_IV = -1, | |
| + TKIP_DECRYPT_INVALID_KEYIDX = -2, | |
| + TKIP_DECRYPT_REPLAY = -3, | |
| +}; | |
| + | |
| +enum { | |
| + TLSV4 = 0, | |
| + TLSV6 = 1, | |
| + TLS_NUM_PROTS = 2, | |
| +}; | |
| + | |
| +enum { | |
| + TLS_ALERT_DESC_CLOSE_NOTIFY = 0, | |
| + TLS_ALERT_DESC_UNEXPECTED_MESSAGE = 10, | |
| + TLS_ALERT_DESC_BAD_RECORD_MAC = 20, | |
| + TLS_ALERT_DESC_RECORD_OVERFLOW = 22, | |
| + TLS_ALERT_DESC_HANDSHAKE_FAILURE = 40, | |
| + TLS_ALERT_DESC_BAD_CERTIFICATE = 42, | |
| + TLS_ALERT_DESC_UNSUPPORTED_CERTIFICATE = 43, | |
| + TLS_ALERT_DESC_CERTIFICATE_REVOKED = 44, | |
| + TLS_ALERT_DESC_CERTIFICATE_EXPIRED = 45, | |
| + TLS_ALERT_DESC_CERTIFICATE_UNKNOWN = 46, | |
| + TLS_ALERT_DESC_ILLEGAL_PARAMETER = 47, | |
| + TLS_ALERT_DESC_UNKNOWN_CA = 48, | |
| + TLS_ALERT_DESC_ACCESS_DENIED = 49, | |
| + TLS_ALERT_DESC_DECODE_ERROR = 50, | |
| + TLS_ALERT_DESC_DECRYPT_ERROR = 51, | |
| + TLS_ALERT_DESC_TOO_MANY_CIDS_REQUESTED = 52, | |
| + TLS_ALERT_DESC_PROTOCOL_VERSION = 70, | |
| + TLS_ALERT_DESC_INSUFFICIENT_SECURITY = 71, | |
| + TLS_ALERT_DESC_INTERNAL_ERROR = 80, | |
| + TLS_ALERT_DESC_INAPPROPRIATE_FALLBACK = 86, | |
| + TLS_ALERT_DESC_USER_CANCELED = 90, | |
| + TLS_ALERT_DESC_MISSING_EXTENSION = 109, | |
| + TLS_ALERT_DESC_UNSUPPORTED_EXTENSION = 110, | |
| + TLS_ALERT_DESC_UNRECOGNIZED_NAME = 112, | |
| + TLS_ALERT_DESC_BAD_CERTIFICATE_STATUS_RESPONSE = 113, | |
| + TLS_ALERT_DESC_UNKNOWN_PSK_IDENTITY = 115, | |
| + TLS_ALERT_DESC_CERTIFICATE_REQUIRED = 116, | |
| + TLS_ALERT_DESC_NO_APPLICATION_PROTOCOL = 120, | |
| +}; | |
| + | |
| +enum { | |
| + TLS_ALERT_LEVEL_WARNING = 1, | |
| + TLS_ALERT_LEVEL_FATAL = 2, | |
| +}; | |
| + | |
| +enum { | |
| + TLS_BASE = 0, | |
| + TLS_SW = 1, | |
| + TLS_HW = 2, | |
| + TLS_HW_RECORD = 3, | |
| + TLS_NUM_CONFIG = 4, | |
| +}; | |
| + | |
| +enum { | |
| + TLS_INFO_UNSPEC = 0, | |
| + TLS_INFO_VERSION = 1, | |
| + TLS_INFO_CIPHER = 2, | |
| + TLS_INFO_TXCONF = 3, | |
| + TLS_INFO_RXCONF = 4, | |
| + TLS_INFO_ZC_RO_TX = 5, | |
| + TLS_INFO_RX_NO_PAD = 6, | |
| + __TLS_INFO_MAX = 7, | |
| }; | |
| enum { | |
| @@ -9482,6 +9834,16 @@ | |
| }; | |
| enum { | |
| + TLS_RECORD_TYPE_CHANGE_CIPHER_SPEC = 20, | |
| + TLS_RECORD_TYPE_ALERT = 21, | |
| + TLS_RECORD_TYPE_HANDSHAKE = 22, | |
| + TLS_RECORD_TYPE_DATA = 23, | |
| + TLS_RECORD_TYPE_HEARTBEAT = 24, | |
| + TLS_RECORD_TYPE_TLS12_CID = 25, | |
| + TLS_RECORD_TYPE_ACK = 26, | |
| +}; | |
| + | |
| +enum { | |
| TOO_MANY_CLOSE = -1, | |
| TOO_MANY_OPEN = -2, | |
| MISSING_QUOTE = -3, | |
| @@ -9494,60 +9856,85 @@ | |
| TP_ERR_REFCNT_OPEN_BRACE = 3, | |
| TP_ERR_BAD_REFCNT_SUFFIX = 4, | |
| TP_ERR_BAD_UPROBE_OFFS = 5, | |
| - TP_ERR_MAXACT_NO_KPROBE = 6, | |
| + TP_ERR_BAD_MAXACT_TYPE = 6, | |
| TP_ERR_BAD_MAXACT = 7, | |
| TP_ERR_MAXACT_TOO_BIG = 8, | |
| TP_ERR_BAD_PROBE_ADDR = 9, | |
| TP_ERR_NON_UNIQ_SYMBOL = 10, | |
| TP_ERR_BAD_RETPROBE = 11, | |
| - TP_ERR_BAD_ADDR_SUFFIX = 12, | |
| - TP_ERR_NO_GROUP_NAME = 13, | |
| - TP_ERR_GROUP_TOO_LONG = 14, | |
| - TP_ERR_BAD_GROUP_NAME = 15, | |
| - TP_ERR_NO_EVENT_NAME = 16, | |
| - TP_ERR_EVENT_TOO_LONG = 17, | |
| - TP_ERR_BAD_EVENT_NAME = 18, | |
| - TP_ERR_EVENT_EXIST = 19, | |
| - TP_ERR_RETVAL_ON_PROBE = 20, | |
| - TP_ERR_BAD_STACK_NUM = 21, | |
| - TP_ERR_BAD_ARG_NUM = 22, | |
| - TP_ERR_BAD_VAR = 23, | |
| - TP_ERR_BAD_REG_NAME = 24, | |
| - TP_ERR_BAD_MEM_ADDR = 25, | |
| - TP_ERR_BAD_IMM = 26, | |
| - TP_ERR_IMMSTR_NO_CLOSE = 27, | |
| - TP_ERR_FILE_ON_KPROBE = 28, | |
| - TP_ERR_BAD_FILE_OFFS = 29, | |
| - TP_ERR_SYM_ON_UPROBE = 30, | |
| - TP_ERR_TOO_MANY_OPS = 31, | |
| - TP_ERR_DEREF_NEED_BRACE = 32, | |
| - TP_ERR_BAD_DEREF_OFFS = 33, | |
| - TP_ERR_DEREF_OPEN_BRACE = 34, | |
| - TP_ERR_COMM_CANT_DEREF = 35, | |
| - TP_ERR_BAD_FETCH_ARG = 36, | |
| - TP_ERR_ARRAY_NO_CLOSE = 37, | |
| - TP_ERR_BAD_ARRAY_SUFFIX = 38, | |
| - TP_ERR_BAD_ARRAY_NUM = 39, | |
| - TP_ERR_ARRAY_TOO_BIG = 40, | |
| - TP_ERR_BAD_TYPE = 41, | |
| - TP_ERR_BAD_STRING = 42, | |
| - TP_ERR_BAD_SYMSTRING = 43, | |
| - TP_ERR_BAD_BITFIELD = 44, | |
| - TP_ERR_ARG_NAME_TOO_LONG = 45, | |
| - TP_ERR_NO_ARG_NAME = 46, | |
| - TP_ERR_BAD_ARG_NAME = 47, | |
| - TP_ERR_USED_ARG_NAME = 48, | |
| - TP_ERR_ARG_TOO_LONG = 49, | |
| - TP_ERR_NO_ARG_BODY = 50, | |
| - TP_ERR_BAD_INSN_BNDRY = 51, | |
| - TP_ERR_FAIL_REG_PROBE = 52, | |
| - TP_ERR_DIFF_PROBE_TYPE = 53, | |
| - TP_ERR_DIFF_ARG_TYPE = 54, | |
| - TP_ERR_SAME_PROBE = 55, | |
| - TP_ERR_NO_EVENT_INFO = 56, | |
| - TP_ERR_BAD_ATTACH_EVENT = 57, | |
| - TP_ERR_BAD_ATTACH_ARG = 58, | |
| - TP_ERR_NO_EP_FILTER = 59, | |
| + TP_ERR_NO_TRACEPOINT = 12, | |
| + TP_ERR_BAD_ADDR_SUFFIX = 13, | |
| + TP_ERR_NO_GROUP_NAME = 14, | |
| + TP_ERR_GROUP_TOO_LONG = 15, | |
| + TP_ERR_BAD_GROUP_NAME = 16, | |
| + TP_ERR_NO_EVENT_NAME = 17, | |
| + TP_ERR_EVENT_TOO_LONG = 18, | |
| + TP_ERR_BAD_EVENT_NAME = 19, | |
| + TP_ERR_EVENT_EXIST = 20, | |
| + TP_ERR_RETVAL_ON_PROBE = 21, | |
| + TP_ERR_NO_RETVAL = 22, | |
| + TP_ERR_BAD_STACK_NUM = 23, | |
| + TP_ERR_BAD_ARG_NUM = 24, | |
| + TP_ERR_BAD_VAR = 25, | |
| + TP_ERR_BAD_REG_NAME = 26, | |
| + TP_ERR_BAD_MEM_ADDR = 27, | |
| + TP_ERR_BAD_IMM = 28, | |
| + TP_ERR_IMMSTR_NO_CLOSE = 29, | |
| + TP_ERR_FILE_ON_KPROBE = 30, | |
| + TP_ERR_BAD_FILE_OFFS = 31, | |
| + TP_ERR_SYM_ON_UPROBE = 32, | |
| + TP_ERR_TOO_MANY_OPS = 33, | |
| + TP_ERR_DEREF_NEED_BRACE = 34, | |
| + TP_ERR_BAD_DEREF_OFFS = 35, | |
| + TP_ERR_DEREF_OPEN_BRACE = 36, | |
| + TP_ERR_COMM_CANT_DEREF = 37, | |
| + TP_ERR_BAD_FETCH_ARG = 38, | |
| + TP_ERR_ARRAY_NO_CLOSE = 39, | |
| + TP_ERR_BAD_ARRAY_SUFFIX = 40, | |
| + TP_ERR_BAD_ARRAY_NUM = 41, | |
| + TP_ERR_ARRAY_TOO_BIG = 42, | |
| + TP_ERR_BAD_TYPE = 43, | |
| + TP_ERR_BAD_STRING = 44, | |
| + TP_ERR_BAD_SYMSTRING = 45, | |
| + TP_ERR_BAD_BITFIELD = 46, | |
| + TP_ERR_ARG_NAME_TOO_LONG = 47, | |
| + TP_ERR_NO_ARG_NAME = 48, | |
| + TP_ERR_BAD_ARG_NAME = 49, | |
| + TP_ERR_USED_ARG_NAME = 50, | |
| + TP_ERR_ARG_TOO_LONG = 51, | |
| + TP_ERR_NO_ARG_BODY = 52, | |
| + TP_ERR_BAD_INSN_BNDRY = 53, | |
| + TP_ERR_FAIL_REG_PROBE = 54, | |
| + TP_ERR_DIFF_PROBE_TYPE = 55, | |
| + TP_ERR_DIFF_ARG_TYPE = 56, | |
| + TP_ERR_SAME_PROBE = 57, | |
| + TP_ERR_NO_EVENT_INFO = 58, | |
| + TP_ERR_BAD_ATTACH_EVENT = 59, | |
| + TP_ERR_BAD_ATTACH_ARG = 60, | |
| + TP_ERR_NO_EP_FILTER = 61, | |
| + TP_ERR_NOSUP_BTFARG = 62, | |
| + TP_ERR_NO_BTFARG = 63, | |
| + TP_ERR_NO_BTF_ENTRY = 64, | |
| + TP_ERR_BAD_VAR_ARGS = 65, | |
| + TP_ERR_NOFENTRY_ARGS = 66, | |
| + TP_ERR_DOUBLE_ARGS = 67, | |
| + TP_ERR_ARGS_2LONG = 68, | |
| + TP_ERR_ARGIDX_2BIG = 69, | |
| + TP_ERR_NO_PTR_STRCT = 70, | |
| + TP_ERR_NOSUP_DAT_ARG = 71, | |
| + TP_ERR_BAD_HYPHEN = 72, | |
| + TP_ERR_NO_BTF_FIELD = 73, | |
| + TP_ERR_BAD_BTF_TID = 74, | |
| + TP_ERR_BAD_TYPE4STR = 75, | |
| + TP_ERR_NEED_STRING_TYPE = 76, | |
| +}; | |
| + | |
| +enum { | |
| + TRACEFS_EVENT_INODE = 2, | |
| + TRACEFS_EVENT_TOP_INODE = 4, | |
| + TRACEFS_GID_PERM_SET = 8, | |
| + TRACEFS_UID_PERM_SET = 16, | |
| + TRACEFS_INSTANCE_INODE = 32, | |
| }; | |
| enum { | |
| @@ -9572,7 +9959,22 @@ | |
| TRACE_EVENT_FL_KPROBE = 64, | |
| TRACE_EVENT_FL_UPROBE = 128, | |
| TRACE_EVENT_FL_EPROBE = 256, | |
| - TRACE_EVENT_FL_CUSTOM = 512, | |
| + TRACE_EVENT_FL_FPROBE = 512, | |
| + TRACE_EVENT_FL_CUSTOM = 1024, | |
| +}; | |
| + | |
| +enum { | |
| + TRACE_EVENT_FL_FILTERED_BIT = 0, | |
| + TRACE_EVENT_FL_CAP_ANY_BIT = 1, | |
| + TRACE_EVENT_FL_NO_SET_FILTER_BIT = 2, | |
| + TRACE_EVENT_FL_IGNORE_ENABLE_BIT = 3, | |
| + TRACE_EVENT_FL_TRACEPOINT_BIT = 4, | |
| + TRACE_EVENT_FL_DYNAMIC_BIT = 5, | |
| + TRACE_EVENT_FL_KPROBE_BIT = 6, | |
| + TRACE_EVENT_FL_UPROBE_BIT = 7, | |
| + TRACE_EVENT_FL_EPROBE_BIT = 8, | |
| + TRACE_EVENT_FL_FPROBE_BIT = 9, | |
| + TRACE_EVENT_FL_CUSTOM_BIT = 10, | |
| }; | |
| enum { | |
| @@ -9621,14 +10023,8 @@ | |
| }; | |
| enum { | |
| - TSAR_ELEMENT_TSAR_TYPE_DWRR = 0, | |
| - TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 1, | |
| - TSAR_ELEMENT_TSAR_TYPE_ETS = 2, | |
| -}; | |
| - | |
| -enum { | |
| - UC_LOCAL_LB = 0, | |
| - MC_LOCAL_LB = 1, | |
| + TTY_LOCK_NORMAL = 0, | |
| + TTY_LOCK_SLAVE = 1, | |
| }; | |
| enum { | |
| @@ -9638,6 +10034,18 @@ | |
| }; | |
| enum { | |
| + UDP_FLAGS_CORK = 0, | |
| + UDP_FLAGS_NO_CHECK6_TX = 1, | |
| + UDP_FLAGS_NO_CHECK6_RX = 2, | |
| + UDP_FLAGS_GRO_ENABLED = 3, | |
| + UDP_FLAGS_ACCEPT_FRAGLIST = 4, | |
| + UDP_FLAGS_ACCEPT_L4 = 5, | |
| + UDP_FLAGS_ENCAP_ENABLED = 6, | |
| + UDP_FLAGS_UDPLITE_SEND_CC = 7, | |
| + UDP_FLAGS_UDPLITE_RECV_CC = 8, | |
| +}; | |
| + | |
| +enum { | |
| UDP_MIB_NUM = 0, | |
| UDP_MIB_INDATAGRAMS = 1, | |
| UDP_MIB_NOPORTS = 2, | |
| @@ -9666,13 +10074,96 @@ | |
| }; | |
| enum { | |
| - VHCA_ID_TYPE_HW = 0, | |
| - VHCA_ID_TYPE_SW = 1, | |
| + UNCORE_TYPE_DF = 0, | |
| + UNCORE_TYPE_L3 = 1, | |
| + UNCORE_TYPE_UMC = 2, | |
| + UNCORE_TYPE_MAX = 3, | |
| }; | |
| enum { | |
| - VPORT_STATE_DOWN = 0, | |
| - VPORT_STATE_UP = 1, | |
| + UNDEFINED_CAPABLE = 0, | |
| + SYSTEM_INTEL_MSR_CAPABLE = 1, | |
| + SYSTEM_AMD_MSR_CAPABLE = 2, | |
| + SYSTEM_IO_CAPABLE = 3, | |
| +}; | |
| + | |
| +enum { | |
| + VCPU_SREG_ES = 0, | |
| + VCPU_SREG_CS = 1, | |
| + VCPU_SREG_SS = 2, | |
| + VCPU_SREG_DS = 3, | |
| + VCPU_SREG_FS = 4, | |
| + VCPU_SREG_GS = 5, | |
| + VCPU_SREG_TR = 6, | |
| + VCPU_SREG_LDTR = 7, | |
| +}; | |
| + | |
| +enum { | |
| + VERBOSE_STATUS = 1, | |
| +}; | |
| + | |
| +enum { | |
| + VETH_INFO_UNSPEC = 0, | |
| + VETH_INFO_PEER = 1, | |
| + __VETH_INFO_MAX = 2, | |
| +}; | |
| + | |
| +enum { | |
| + VIA_STRFILT_CNT_SHIFT = 16, | |
| + VIA_STRFILT_FAIL = 32768, | |
| + VIA_STRFILT_ENABLE = 16384, | |
| + VIA_RAWBITS_ENABLE = 8192, | |
| + VIA_RNG_ENABLE = 64, | |
| + VIA_NOISESRC1 = 256, | |
| + VIA_NOISESRC2 = 512, | |
| + VIA_XSTORE_CNT_MASK = 15, | |
| + VIA_RNG_CHUNK_8 = 0, | |
| + VIA_RNG_CHUNK_4 = 1, | |
| + VIA_RNG_CHUNK_4_MASK = 4294967295, | |
| + VIA_RNG_CHUNK_2 = 2, | |
| + VIA_RNG_CHUNK_2_MASK = 65535, | |
| + VIA_RNG_CHUNK_1 = 3, | |
| + VIA_RNG_CHUNK_1_MASK = 255, | |
| +}; | |
| + | |
| +enum { | |
| + VMCB_INTERCEPTS = 0, | |
| + VMCB_PERM_MAP = 1, | |
| + VMCB_ASID = 2, | |
| + VMCB_INTR = 3, | |
| + VMCB_NPT = 4, | |
| + VMCB_CR = 5, | |
| + VMCB_DR = 6, | |
| + VMCB_DT = 7, | |
| + VMCB_SEG = 8, | |
| + VMCB_CR2 = 9, | |
| + VMCB_LBR = 10, | |
| + VMCB_AVIC = 11, | |
| + VMCB_SW = 31, | |
| +}; | |
| + | |
| +enum { | |
| + VMGENID_SIZE = 16, | |
| +}; | |
| + | |
| +enum { | |
| + VMX_VMREAD_BITMAP = 0, | |
| + VMX_VMWRITE_BITMAP = 1, | |
| + VMX_BITMAP_NR = 2, | |
| +}; | |
| + | |
| +enum { | |
| + VNIFILTER_ENTRY_STATS_UNSPEC = 0, | |
| + VNIFILTER_ENTRY_STATS_RX_BYTES = 1, | |
| + VNIFILTER_ENTRY_STATS_RX_PKTS = 2, | |
| + VNIFILTER_ENTRY_STATS_RX_DROPS = 3, | |
| + VNIFILTER_ENTRY_STATS_RX_ERRORS = 4, | |
| + VNIFILTER_ENTRY_STATS_TX_BYTES = 5, | |
| + VNIFILTER_ENTRY_STATS_TX_PKTS = 6, | |
| + VNIFILTER_ENTRY_STATS_TX_DROPS = 7, | |
| + VNIFILTER_ENTRY_STATS_TX_ERRORS = 8, | |
| + VNIFILTER_ENTRY_STATS_PAD = 9, | |
| + __VNIFILTER_ENTRY_STATS_MAX = 10, | |
| }; | |
| enum { | |
| @@ -9681,23 +10172,10 @@ | |
| }; | |
| enum { | |
| - VSC_CTRL_OFFSET = 4, | |
| - VSC_COUNTER_OFFSET = 8, | |
| - VSC_SEMAPHORE_OFFSET = 12, | |
| - VSC_ADDR_OFFSET = 16, | |
| - VSC_DATA_OFFSET = 20, | |
| - VSC_FLAG_BIT_OFFS = 31, | |
| - VSC_FLAG_BIT_LEN = 1, | |
| - VSC_SYND_BIT_OFFS = 30, | |
| - VSC_SYND_BIT_LEN = 1, | |
| - VSC_ADDR_BIT_OFFS = 0, | |
| - VSC_ADDR_BIT_LEN = 30, | |
| - VSC_SPACE_BIT_OFFS = 0, | |
| - VSC_SPACE_BIT_LEN = 16, | |
| - VSC_SIZE_VLD_BIT_OFFS = 28, | |
| - VSC_SIZE_VLD_BIT_LEN = 1, | |
| - VSC_STATUS_BIT_OFFS = 29, | |
| - VSC_STATUS_BIT_LEN = 3, | |
| + VSOCK_VQ_RX = 0, | |
| + VSOCK_VQ_TX = 1, | |
| + VSOCK_VQ_EVENT = 2, | |
| + VSOCK_VQ_MAX = 3, | |
| }; | |
| enum { | |
| @@ -9715,72 +10193,39 @@ | |
| }; | |
| enum { | |
| - WALK_TRAILING = 1, | |
| - WALK_MORE = 2, | |
| - WALK_NOFOLLOW = 4, | |
| -}; | |
| - | |
| -enum { | |
| - WBT_RWQ_BG = 0, | |
| - WBT_RWQ_KSWAPD = 1, | |
| - WBT_RWQ_DISCARD = 2, | |
| - WBT_NUM_RWQ = 3, | |
| + VXLAN_VNIFILTER_ENTRY_UNSPEC = 0, | |
| + VXLAN_VNIFILTER_ENTRY_START = 1, | |
| + VXLAN_VNIFILTER_ENTRY_END = 2, | |
| + VXLAN_VNIFILTER_ENTRY_GROUP = 3, | |
| + VXLAN_VNIFILTER_ENTRY_GROUP6 = 4, | |
| + VXLAN_VNIFILTER_ENTRY_STATS = 5, | |
| + __VXLAN_VNIFILTER_ENTRY_MAX = 6, | |
| }; | |
| enum { | |
| - WBT_STATE_ON_DEFAULT = 1, | |
| - WBT_STATE_ON_MANUAL = 2, | |
| - WBT_STATE_OFF_DEFAULT = 3, | |
| - WBT_STATE_OFF_MANUAL = 4, | |
| + VXLAN_VNIFILTER_UNSPEC = 0, | |
| + VXLAN_VNIFILTER_ENTRY = 1, | |
| + __VXLAN_VNIFILTER_MAX = 2, | |
| }; | |
| enum { | |
| - WORK_DONE_BIT = 0, | |
| - WORK_ORDER_DONE_BIT = 1, | |
| + VXLAN_VNI_STATS_RX = 0, | |
| + VXLAN_VNI_STATS_RX_DROPS = 1, | |
| + VXLAN_VNI_STATS_RX_ERRORS = 2, | |
| + VXLAN_VNI_STATS_TX = 3, | |
| + VXLAN_VNI_STATS_TX_DROPS = 4, | |
| + VXLAN_VNI_STATS_TX_ERRORS = 5, | |
| }; | |
| enum { | |
| - WORK_STRUCT_PENDING_BIT = 0, | |
| - WORK_STRUCT_INACTIVE_BIT = 1, | |
| - WORK_STRUCT_PWQ_BIT = 2, | |
| - WORK_STRUCT_LINKED_BIT = 3, | |
| - WORK_STRUCT_COLOR_SHIFT = 4, | |
| - WORK_STRUCT_COLOR_BITS = 4, | |
| - WORK_STRUCT_PENDING = 1, | |
| - WORK_STRUCT_INACTIVE = 2, | |
| - WORK_STRUCT_PWQ = 4, | |
| - WORK_STRUCT_LINKED = 8, | |
| - WORK_STRUCT_STATIC = 0, | |
| - WORK_NR_COLORS = 16, | |
| - WORK_CPU_UNBOUND = 512, | |
| - WORK_STRUCT_FLAG_BITS = 8, | |
| - WORK_OFFQ_FLAG_BASE = 4, | |
| - __WORK_OFFQ_CANCELING = 4, | |
| - WORK_OFFQ_FLAG_BITS = 1, | |
| - WORK_OFFQ_POOL_SHIFT = 5, | |
| - WORK_OFFQ_LEFT = 59, | |
| - WORK_OFFQ_POOL_BITS = 31, | |
| - WORK_BUSY_PENDING = 1, | |
| - WORK_BUSY_RUNNING = 2, | |
| - WORKER_DESC_LEN = 24, | |
| + WALK_TRAILING = 1, | |
| + WALK_MORE = 2, | |
| + WALK_NOFOLLOW = 4, | |
| }; | |
| enum { | |
| - WQ_UNBOUND = 2, | |
| - WQ_FREEZABLE = 4, | |
| - WQ_MEM_RECLAIM = 8, | |
| - WQ_HIGHPRI = 16, | |
| - WQ_CPU_INTENSIVE = 32, | |
| - WQ_SYSFS = 64, | |
| - WQ_POWER_EFFICIENT = 128, | |
| - __WQ_DESTROYING = 32768, | |
| - __WQ_DRAINING = 65536, | |
| - __WQ_ORDERED = 131072, | |
| - __WQ_LEGACY = 262144, | |
| - __WQ_ORDERED_EXPLICIT = 524288, | |
| - WQ_MAX_ACTIVE = 512, | |
| - WQ_MAX_UNBOUND_PER_CPU = 4, | |
| - WQ_DFL_ACTIVE = 256, | |
| + WORK_DONE_BIT = 0, | |
| + WORK_ORDER_DONE_BIT = 1, | |
| }; | |
| enum { | |
| @@ -9850,12 +10295,6 @@ | |
| }; | |
| enum { | |
| - XDP_METADATA_KFUNC_RX_TIMESTAMP = 0, | |
| - XDP_METADATA_KFUNC_RX_HASH = 1, | |
| - MAX_XDP_METADATA_KFUNC = 2, | |
| -}; | |
| - | |
| -enum { | |
| XFRM_DEV_OFFLOAD_IN = 1, | |
| XFRM_DEV_OFFLOAD_OUT = 2, | |
| XFRM_DEV_OFFLOAD_FWD = 3, | |
| @@ -9939,39 +10378,38 @@ | |
| }; | |
| enum { | |
| - XFS_ERR_DEFAULT = 0, | |
| - XFS_ERR_EIO = 1, | |
| - XFS_ERR_ENOSPC = 2, | |
| - XFS_ERR_ENODEV = 3, | |
| - XFS_ERR_ERRNO_MAX = 4, | |
| -}; | |
| - | |
| -enum { | |
| - XFS_ERR_METADATA = 0, | |
| - XFS_ERR_CLASS_MAX = 1, | |
| -}; | |
| - | |
| -enum { | |
| - XFS_LOWSP_1_PCNT = 0, | |
| - XFS_LOWSP_2_PCNT = 1, | |
| - XFS_LOWSP_3_PCNT = 2, | |
| - XFS_LOWSP_4_PCNT = 3, | |
| - XFS_LOWSP_5_PCNT = 4, | |
| - XFS_LOWSP_MAX = 5, | |
| + XPT_BUSY = 0, | |
| + XPT_CONN = 1, | |
| + XPT_CLOSE = 2, | |
| + XPT_DATA = 3, | |
| + XPT_TEMP = 4, | |
| + XPT_DEAD = 5, | |
| + XPT_CHNGBUF = 6, | |
| + XPT_DEFERRED = 7, | |
| + XPT_OLD = 8, | |
| + XPT_LISTENER = 9, | |
| + XPT_CACHE_AUTH = 10, | |
| + XPT_LOCAL = 11, | |
| + XPT_KILL_TEMP = 12, | |
| + XPT_CONG_CTRL = 13, | |
| + XPT_HANDSHAKE = 14, | |
| + XPT_TLS_SESSION = 15, | |
| + XPT_PEER_AUTH = 16, | |
| }; | |
| enum { | |
| - XFS_QLOWSP_1_PCNT = 0, | |
| - XFS_QLOWSP_3_PCNT = 1, | |
| - XFS_QLOWSP_5_PCNT = 2, | |
| - XFS_QLOWSP_MAX = 3, | |
| + XT_CONNMARK_SET = 0, | |
| + XT_CONNMARK_SAVE = 1, | |
| + XT_CONNMARK_RESTORE = 2, | |
| }; | |
| enum { | |
| - XFS_QM_TRANS_USR = 0, | |
| - XFS_QM_TRANS_GRP = 1, | |
| - XFS_QM_TRANS_PRJ = 2, | |
| - XFS_QM_TRANS_DQTYPES = 3, | |
| + XT_CT_NOTRACK = 1, | |
| + XT_CT_NOTRACK_ALIAS = 2, | |
| + XT_CT_ZONE_DIR_ORIG = 4, | |
| + XT_CT_ZONE_DIR_REPL = 8, | |
| + XT_CT_ZONE_MARK = 16, | |
| + XT_CT_MASK = 31, | |
| }; | |
| enum { | |
| @@ -10060,6 +10498,33 @@ | |
| __EXTENT_CLEAR_ALL_BITS_BIT = 15, | |
| EXTENT_CLEAR_ALL_BITS = 32768, | |
| __EXTENT_CLEAR_ALL_BITS_SEQ = 15, | |
| + __EXTENT_NOWAIT_BIT = 16, | |
| + EXTENT_NOWAIT = 65536, | |
| + __EXTENT_NOWAIT_SEQ = 16, | |
| +}; | |
| + | |
| +enum { | |
| + __EXTENT_FLAG_PINNED_BIT = 0, | |
| + EXTENT_FLAG_PINNED = 1, | |
| + __EXTENT_FLAG_PINNED_SEQ = 0, | |
| + __EXTENT_FLAG_COMPRESS_ZLIB_BIT = 1, | |
| + EXTENT_FLAG_COMPRESS_ZLIB = 2, | |
| + __EXTENT_FLAG_COMPRESS_ZLIB_SEQ = 1, | |
| + __EXTENT_FLAG_COMPRESS_LZO_BIT = 2, | |
| + EXTENT_FLAG_COMPRESS_LZO = 4, | |
| + __EXTENT_FLAG_COMPRESS_LZO_SEQ = 2, | |
| + __EXTENT_FLAG_COMPRESS_ZSTD_BIT = 3, | |
| + EXTENT_FLAG_COMPRESS_ZSTD = 8, | |
| + __EXTENT_FLAG_COMPRESS_ZSTD_SEQ = 3, | |
| + __EXTENT_FLAG_PREALLOC_BIT = 4, | |
| + EXTENT_FLAG_PREALLOC = 16, | |
| + __EXTENT_FLAG_PREALLOC_SEQ = 4, | |
| + __EXTENT_FLAG_LOGGING_BIT = 5, | |
| + EXTENT_FLAG_LOGGING = 32, | |
| + __EXTENT_FLAG_LOGGING_SEQ = 5, | |
| + __EXTENT_FLAG_MERGED_BIT = 6, | |
| + EXTENT_FLAG_MERGED = 64, | |
| + __EXTENT_FLAG_MERGED_SEQ = 6, | |
| }; | |
| enum { | |
| @@ -10093,12 +10558,6 @@ | |
| __PAGE_SET_ORDERED_BIT = 3, | |
| PAGE_SET_ORDERED = 8, | |
| __PAGE_SET_ORDERED_SEQ = 3, | |
| - __PAGE_SET_ERROR_BIT = 4, | |
| - PAGE_SET_ERROR = 16, | |
| - __PAGE_SET_ERROR_SEQ = 4, | |
| - __PAGE_LOCK_BIT = 5, | |
| - PAGE_LOCK = 32, | |
| - __PAGE_LOCK_SEQ = 5, | |
| }; | |
| enum { | |
| @@ -10121,10 +10580,10 @@ | |
| }; | |
| enum { | |
| - __SCHED_FEAT_GENTLE_FAIR_SLEEPERS = 0, | |
| - __SCHED_FEAT_START_DEBIT = 1, | |
| - __SCHED_FEAT_NEXT_BUDDY = 2, | |
| - __SCHED_FEAT_LAST_BUDDY = 3, | |
| + __SCHED_FEAT_PLACE_LAG = 0, | |
| + __SCHED_FEAT_PLACE_DEADLINE_INITIAL = 1, | |
| + __SCHED_FEAT_RUN_TO_PARITY = 2, | |
| + __SCHED_FEAT_NEXT_BUDDY = 3, | |
| __SCHED_FEAT_CACHE_HOT_BUDDY = 4, | |
| __SCHED_FEAT_WAKEUP_PREEMPTION = 5, | |
| __SCHED_FEAT_HRTICK = 6, | |
| @@ -10132,23 +10591,19 @@ | |
| __SCHED_FEAT_DOUBLE_TICK = 8, | |
| __SCHED_FEAT_NONTASK_CAPACITY = 9, | |
| __SCHED_FEAT_TTWU_QUEUE = 10, | |
| - __SCHED_FEAT_SIS_PROP = 11, | |
| - __SCHED_FEAT_SIS_UTIL = 12, | |
| - __SCHED_FEAT_WARN_DOUBLE_CLOCK = 13, | |
| - __SCHED_FEAT_RT_PUSH_IPI = 14, | |
| - __SCHED_FEAT_RT_RUNTIME_SHARE = 15, | |
| - __SCHED_FEAT_LB_MIN = 16, | |
| - __SCHED_FEAT_ATTACH_AGE_LOAD = 17, | |
| - __SCHED_FEAT_WA_IDLE = 18, | |
| - __SCHED_FEAT_WA_WEIGHT = 19, | |
| - __SCHED_FEAT_WA_BIAS = 20, | |
| - __SCHED_FEAT_UTIL_EST = 21, | |
| - __SCHED_FEAT_UTIL_EST_FASTUP = 22, | |
| - __SCHED_FEAT_LATENCY_WARN = 23, | |
| - __SCHED_FEAT_ALT_PERIOD = 24, | |
| - __SCHED_FEAT_BASE_SLICE = 25, | |
| - __SCHED_FEAT_SHARED_RUNQ = 26, | |
| - __SCHED_FEAT_NR = 27, | |
| + __SCHED_FEAT_SIS_UTIL = 11, | |
| + __SCHED_FEAT_WARN_DOUBLE_CLOCK = 12, | |
| + __SCHED_FEAT_RT_PUSH_IPI = 13, | |
| + __SCHED_FEAT_RT_RUNTIME_SHARE = 14, | |
| + __SCHED_FEAT_LB_MIN = 15, | |
| + __SCHED_FEAT_ATTACH_AGE_LOAD = 16, | |
| + __SCHED_FEAT_WA_IDLE = 17, | |
| + __SCHED_FEAT_WA_WEIGHT = 18, | |
| + __SCHED_FEAT_WA_BIAS = 19, | |
| + __SCHED_FEAT_UTIL_EST = 20, | |
| + __SCHED_FEAT_LATENCY_WARN = 21, | |
| + __SCHED_FEAT_HZ_BW = 22, | |
| + __SCHED_FEAT_NR = 23, | |
| }; | |
| enum { | |
| @@ -10160,32 +10615,44 @@ | |
| __SD_ASYM_CPUCAPACITY = 5, | |
| __SD_ASYM_CPUCAPACITY_FULL = 6, | |
| __SD_SHARE_CPUCAPACITY = 7, | |
| - __SD_SHARE_PKG_RESOURCES = 8, | |
| - __SD_SERIALIZE = 9, | |
| - __SD_ASYM_PACKING = 10, | |
| - __SD_PREFER_SIBLING = 11, | |
| - __SD_OVERLAP = 12, | |
| - __SD_NUMA = 13, | |
| - __SD_FLAG_CNT = 14, | |
| + __SD_CLUSTER = 8, | |
| + __SD_SHARE_LLC = 9, | |
| + __SD_SERIALIZE = 10, | |
| + __SD_ASYM_PACKING = 11, | |
| + __SD_PREFER_SIBLING = 12, | |
| + __SD_OVERLAP = 13, | |
| + __SD_NUMA = 14, | |
| + __SD_FLAG_CNT = 15, | |
| }; | |
| enum { | |
| - __XBTS_lookup = 0, | |
| - __XBTS_compare = 1, | |
| - __XBTS_insrec = 2, | |
| - __XBTS_delrec = 3, | |
| - __XBTS_newroot = 4, | |
| - __XBTS_killroot = 5, | |
| - __XBTS_increment = 6, | |
| - __XBTS_decrement = 7, | |
| - __XBTS_lshift = 8, | |
| - __XBTS_rshift = 9, | |
| - __XBTS_split = 10, | |
| - __XBTS_join = 11, | |
| - __XBTS_alloc = 12, | |
| - __XBTS_free = 13, | |
| - __XBTS_moves = 14, | |
| - __XBTS_MAX = 15, | |
| + ___GFP_DMA_BIT = 0, | |
| + ___GFP_HIGHMEM_BIT = 1, | |
| + ___GFP_DMA32_BIT = 2, | |
| + ___GFP_MOVABLE_BIT = 3, | |
| + ___GFP_RECLAIMABLE_BIT = 4, | |
| + ___GFP_HIGH_BIT = 5, | |
| + ___GFP_IO_BIT = 6, | |
| + ___GFP_FS_BIT = 7, | |
| + ___GFP_ZERO_BIT = 8, | |
| + ___GFP_UNUSED_BIT = 9, | |
| + ___GFP_DIRECT_RECLAIM_BIT = 10, | |
| + ___GFP_KSWAPD_RECLAIM_BIT = 11, | |
| + ___GFP_WRITE_BIT = 12, | |
| + ___GFP_NOWARN_BIT = 13, | |
| + ___GFP_RETRY_MAYFAIL_BIT = 14, | |
| + ___GFP_NOFAIL_BIT = 15, | |
| + ___GFP_NORETRY_BIT = 16, | |
| + ___GFP_MEMALLOC_BIT = 17, | |
| + ___GFP_COMP_BIT = 18, | |
| + ___GFP_NOMEMALLOC_BIT = 19, | |
| + ___GFP_HARDWALL_BIT = 20, | |
| + ___GFP_THISNODE_BIT = 21, | |
| + ___GFP_ACCOUNT_BIT = 22, | |
| + ___GFP_ZEROTAGS_BIT = 23, | |
| + ___GFP_NOLOCKDEP_BIT = 24, | |
| + ___GFP_NO_OBJ_EXT_BIT = 25, | |
| + ___GFP_LAST_BIT = 26, | |
| }; | |
| enum { | |
| @@ -10213,6 +10680,42 @@ | |
| }; | |
| enum { | |
| + __ctx_convertBPF_PROG_TYPE_SOCKET_FILTER = 0, | |
| + __ctx_convertBPF_PROG_TYPE_SCHED_CLS = 1, | |
| + __ctx_convertBPF_PROG_TYPE_SCHED_ACT = 2, | |
| + __ctx_convertBPF_PROG_TYPE_XDP = 3, | |
| + __ctx_convertBPF_PROG_TYPE_CGROUP_SKB = 4, | |
| + __ctx_convertBPF_PROG_TYPE_CGROUP_SOCK = 5, | |
| + __ctx_convertBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 6, | |
| + __ctx_convertBPF_PROG_TYPE_LWT_IN = 7, | |
| + __ctx_convertBPF_PROG_TYPE_LWT_OUT = 8, | |
| + __ctx_convertBPF_PROG_TYPE_LWT_XMIT = 9, | |
| + __ctx_convertBPF_PROG_TYPE_LWT_SEG6LOCAL = 10, | |
| + __ctx_convertBPF_PROG_TYPE_SOCK_OPS = 11, | |
| + __ctx_convertBPF_PROG_TYPE_SK_SKB = 12, | |
| + __ctx_convertBPF_PROG_TYPE_SK_MSG = 13, | |
| + __ctx_convertBPF_PROG_TYPE_FLOW_DISSECTOR = 14, | |
| + __ctx_convertBPF_PROG_TYPE_KPROBE = 15, | |
| + __ctx_convertBPF_PROG_TYPE_TRACEPOINT = 16, | |
| + __ctx_convertBPF_PROG_TYPE_PERF_EVENT = 17, | |
| + __ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT = 18, | |
| + __ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 19, | |
| + __ctx_convertBPF_PROG_TYPE_TRACING = 20, | |
| + __ctx_convertBPF_PROG_TYPE_CGROUP_DEVICE = 21, | |
| + __ctx_convertBPF_PROG_TYPE_CGROUP_SYSCTL = 22, | |
| + __ctx_convertBPF_PROG_TYPE_CGROUP_SOCKOPT = 23, | |
| + __ctx_convertBPF_PROG_TYPE_LIRC_MODE2 = 24, | |
| + __ctx_convertBPF_PROG_TYPE_SK_REUSEPORT = 25, | |
| + __ctx_convertBPF_PROG_TYPE_SK_LOOKUP = 26, | |
| + __ctx_convertBPF_PROG_TYPE_STRUCT_OPS = 27, | |
| + __ctx_convertBPF_PROG_TYPE_EXT = 28, | |
| + __ctx_convertBPF_PROG_TYPE_LSM = 29, | |
| + __ctx_convertBPF_PROG_TYPE_SYSCALL = 30, | |
| + __ctx_convertBPF_PROG_TYPE_NETFILTER = 31, | |
| + __ctx_convert_unused = 32, | |
| +}; | |
| + | |
| +enum { | |
| attr_noop = 0, | |
| attr_delayed_allocation_blocks = 1, | |
| attr_session_write_kbytes = 2, | |
| @@ -10256,6 +10759,22 @@ | |
| }; | |
| enum { | |
| + kvm_ioeventfd_flag_nr_datamatch = 0, | |
| + kvm_ioeventfd_flag_nr_pio = 1, | |
| + kvm_ioeventfd_flag_nr_deassign = 2, | |
| + kvm_ioeventfd_flag_nr_virtio_ccw_notify = 3, | |
| + kvm_ioeventfd_flag_nr_fast_mmio = 4, | |
| + kvm_ioeventfd_flag_nr_max = 5, | |
| +}; | |
| + | |
| +enum { | |
| + mask_exec = 0, | |
| + mask_write = 1, | |
| + mask_read = 2, | |
| + mask_append = 3, | |
| +}; | |
| + | |
| +enum { | |
| none = 0, | |
| day = 1, | |
| month = 2, | |
| @@ -10269,6 +10788,13 @@ | |
| }; | |
| enum { | |
| + preempt_dynamic_undefined = -1, | |
| + preempt_dynamic_none = 0, | |
| + preempt_dynamic_voluntary = 1, | |
| + preempt_dynamic_full = 2, | |
| +}; | |
| + | |
| +enum { | |
| ptr_explicit = 0, | |
| ptr_ext4_sb_info_offset = 1, | |
| ptr_ext4_super_block_offset = 2, | |
| @@ -10278,13 +10804,13 @@ | |
| st_wordstart = 0, | |
| st_wordcmp = 1, | |
| st_wordskip = 2, | |
| + st_bufcpy = 3, | |
| }; | |
| enum { | |
| st_wordstart___2 = 0, | |
| st_wordcmp___2 = 1, | |
| st_wordskip___2 = 2, | |
| - st_bufcpy = 3, | |
| }; | |
| enum { | |
| @@ -10301,13 +10827,25 @@ | |
| BIT_DStream_overflow = 3, | |
| } BIT_DStream_status; | |
| -enum E1000_INVM_STRUCTURE_TYPE { | |
| - E1000_INVM_UNINITIALIZED_STRUCTURE = 0, | |
| - E1000_INVM_WORD_AUTOLOAD_STRUCTURE = 1, | |
| - E1000_INVM_CSR_AUTOLOAD_STRUCTURE = 2, | |
| - E1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE = 3, | |
| - E1000_INVM_RSA_KEY_SHA256_STRUCTURE = 4, | |
| - E1000_INVM_INVALIDATED_STRUCTURE = 15, | |
| +enum CSI_J { | |
| + CSI_J_CURSOR_TO_END = 0, | |
| + CSI_J_START_TO_CURSOR = 1, | |
| + CSI_J_VISIBLE = 2, | |
| + CSI_J_FULL = 3, | |
| +}; | |
| + | |
| +enum CSI_right_square_bracket { | |
| + CSI_RSB_COLOR_FOR_UNDERLINE = 1, | |
| + CSI_RSB_COLOR_FOR_HALF_BRIGHT = 2, | |
| + CSI_RSB_MAKE_CUR_COLOR_DEFAULT = 8, | |
| + CSI_RSB_BLANKING_INTERVAL = 9, | |
| + CSI_RSB_BELL_FREQUENCY = 10, | |
| + CSI_RSB_BELL_DURATION = 11, | |
| + CSI_RSB_BRING_CONSOLE_TO_FRONT = 12, | |
| + CSI_RSB_UNBLANK = 13, | |
| + CSI_RSB_VESA_OFF_INTERVAL = 14, | |
| + CSI_RSB_BRING_PREV_CONSOLE_TO_FRONT = 15, | |
| + CSI_RSB_CURSOR_BLINK_INTERVAL = 16, | |
| }; | |
| typedef enum { | |
| @@ -10332,12 +10870,28 @@ | |
| HUF_repeat_valid = 2, | |
| } HUF_repeat; | |
| +enum HV_GENERIC_SET_FORMAT { | |
| + HV_GENERIC_SET_SPARSE_4K = 0, | |
| + HV_GENERIC_SET_ALL = 1, | |
| +}; | |
| + | |
| enum KTHREAD_BITS { | |
| KTHREAD_IS_PER_CPU = 0, | |
| KTHREAD_SHOULD_STOP = 1, | |
| KTHREAD_SHOULD_PARK = 2, | |
| }; | |
| +typedef enum { | |
| + MPTBASE_DRIVER = 0, | |
| + MPTCTL_DRIVER = 1, | |
| + MPTSPI_DRIVER = 2, | |
| + MPTFC_DRIVER = 3, | |
| + MPTSAS_DRIVER = 4, | |
| + MPTLAN_DRIVER = 5, | |
| + MPTSTM_DRIVER = 6, | |
| + MPTUNKNOWN_DRIVER = 7, | |
| +} MPT_DRIVER_CLASS; | |
| + | |
| enum OID { | |
| OID_id_dsa_with_sha1 = 0, | |
| OID_id_dsa = 1, | |
| @@ -10350,94 +10904,248 @@ | |
| OID_id_ecdsa_with_sha384 = 8, | |
| OID_id_ecdsa_with_sha512 = 9, | |
| OID_rsaEncryption = 10, | |
| - OID_md2WithRSAEncryption = 11, | |
| - OID_md3WithRSAEncryption = 12, | |
| - OID_md4WithRSAEncryption = 13, | |
| - OID_sha1WithRSAEncryption = 14, | |
| - OID_sha256WithRSAEncryption = 15, | |
| - OID_sha384WithRSAEncryption = 16, | |
| - OID_sha512WithRSAEncryption = 17, | |
| - OID_sha224WithRSAEncryption = 18, | |
| - OID_data = 19, | |
| - OID_signed_data = 20, | |
| - OID_email_address = 21, | |
| - OID_contentType = 22, | |
| - OID_messageDigest = 23, | |
| - OID_signingTime = 24, | |
| - OID_smimeCapabilites = 25, | |
| - OID_smimeAuthenticatedAttrs = 26, | |
| - OID_md2 = 27, | |
| - OID_md4 = 28, | |
| - OID_md5 = 29, | |
| - OID_mskrb5 = 30, | |
| - OID_krb5 = 31, | |
| - OID_krb5u2u = 32, | |
| - OID_msIndirectData = 33, | |
| - OID_msStatementType = 34, | |
| - OID_msSpOpusInfo = 35, | |
| - OID_msPeImageDataObjId = 36, | |
| - OID_msIndividualSPKeyPurpose = 37, | |
| - OID_msOutlookExpress = 38, | |
| - OID_ntlmssp = 39, | |
| - OID_spnego = 40, | |
| - OID_IAKerb = 41, | |
| - OID_PKU2U = 42, | |
| - OID_Scram = 43, | |
| - OID_certAuthInfoAccess = 44, | |
| - OID_sha1 = 45, | |
| - OID_id_ansip384r1 = 46, | |
| - OID_sha256 = 47, | |
| - OID_sha384 = 48, | |
| - OID_sha512 = 49, | |
| - OID_sha224 = 50, | |
| - OID_commonName = 51, | |
| - OID_surname = 52, | |
| - OID_countryName = 53, | |
| - OID_locality = 54, | |
| - OID_stateOrProvinceName = 55, | |
| - OID_organizationName = 56, | |
| - OID_organizationUnitName = 57, | |
| - OID_title = 58, | |
| - OID_description = 59, | |
| - OID_name = 60, | |
| - OID_givenName = 61, | |
| - OID_initials = 62, | |
| - OID_generationalQualifier = 63, | |
| - OID_subjectKeyIdentifier = 64, | |
| - OID_keyUsage = 65, | |
| - OID_subjectAltName = 66, | |
| - OID_issuerAltName = 67, | |
| - OID_basicConstraints = 68, | |
| - OID_crlDistributionPoints = 69, | |
| - OID_certPolicies = 70, | |
| - OID_authorityKeyIdentifier = 71, | |
| - OID_extKeyUsage = 72, | |
| - OID_NetlogonMechanism = 73, | |
| - OID_appleLocalKdcSupported = 74, | |
| - OID_gostCPSignA = 75, | |
| - OID_gostCPSignB = 76, | |
| - OID_gostCPSignC = 77, | |
| - OID_gost2012PKey256 = 78, | |
| - OID_gost2012PKey512 = 79, | |
| - OID_gost2012Digest256 = 80, | |
| - OID_gost2012Digest512 = 81, | |
| - OID_gost2012Signature256 = 82, | |
| - OID_gost2012Signature512 = 83, | |
| - OID_gostTC26Sign256A = 84, | |
| - OID_gostTC26Sign256B = 85, | |
| - OID_gostTC26Sign256C = 86, | |
| - OID_gostTC26Sign256D = 87, | |
| - OID_gostTC26Sign512A = 88, | |
| - OID_gostTC26Sign512B = 89, | |
| - OID_gostTC26Sign512C = 90, | |
| - OID_sm2 = 91, | |
| - OID_sm3 = 92, | |
| - OID_SM2_with_SM3 = 93, | |
| - OID_sm3WithRSAEncryption = 94, | |
| - OID_TPMLoadableKey = 95, | |
| - OID_TPMImportableKey = 96, | |
| - OID_TPMSealedData = 97, | |
| - OID__NR = 98, | |
| + OID_sha1WithRSAEncryption = 11, | |
| + OID_sha256WithRSAEncryption = 12, | |
| + OID_sha384WithRSAEncryption = 13, | |
| + OID_sha512WithRSAEncryption = 14, | |
| + OID_sha224WithRSAEncryption = 15, | |
| + OID_data = 16, | |
| + OID_signed_data = 17, | |
| + OID_email_address = 18, | |
| + OID_contentType = 19, | |
| + OID_messageDigest = 20, | |
| + OID_signingTime = 21, | |
| + OID_smimeCapabilites = 22, | |
| + OID_smimeAuthenticatedAttrs = 23, | |
| + OID_mskrb5 = 24, | |
| + OID_krb5 = 25, | |
| + OID_krb5u2u = 26, | |
| + OID_msIndirectData = 27, | |
| + OID_msStatementType = 28, | |
| + OID_msSpOpusInfo = 29, | |
| + OID_msPeImageDataObjId = 30, | |
| + OID_msIndividualSPKeyPurpose = 31, | |
| + OID_msOutlookExpress = 32, | |
| + OID_ntlmssp = 33, | |
| + OID_negoex = 34, | |
| + OID_spnego = 35, | |
| + OID_IAKerb = 36, | |
| + OID_PKU2U = 37, | |
| + OID_Scram = 38, | |
| + OID_certAuthInfoAccess = 39, | |
| + OID_sha1 = 40, | |
| + OID_id_ansip384r1 = 41, | |
| + OID_id_ansip521r1 = 42, | |
| + OID_sha256 = 43, | |
| + OID_sha384 = 44, | |
| + OID_sha512 = 45, | |
| + OID_sha224 = 46, | |
| + OID_commonName = 47, | |
| + OID_surname = 48, | |
| + OID_countryName = 49, | |
| + OID_locality = 50, | |
| + OID_stateOrProvinceName = 51, | |
| + OID_organizationName = 52, | |
| + OID_organizationUnitName = 53, | |
| + OID_title = 54, | |
| + OID_description = 55, | |
| + OID_name = 56, | |
| + OID_givenName = 57, | |
| + OID_initials = 58, | |
| + OID_generationalQualifier = 59, | |
| + OID_subjectKeyIdentifier = 60, | |
| + OID_keyUsage = 61, | |
| + OID_subjectAltName = 62, | |
| + OID_issuerAltName = 63, | |
| + OID_basicConstraints = 64, | |
| + OID_crlDistributionPoints = 65, | |
| + OID_certPolicies = 66, | |
| + OID_authorityKeyIdentifier = 67, | |
| + OID_extKeyUsage = 68, | |
| + OID_NetlogonMechanism = 69, | |
| + OID_appleLocalKdcSupported = 70, | |
| + OID_gostCPSignA = 71, | |
| + OID_gostCPSignB = 72, | |
| + OID_gostCPSignC = 73, | |
| + OID_gost2012PKey256 = 74, | |
| + OID_gost2012PKey512 = 75, | |
| + OID_gost2012Digest256 = 76, | |
| + OID_gost2012Digest512 = 77, | |
| + OID_gost2012Signature256 = 78, | |
| + OID_gost2012Signature512 = 79, | |
| + OID_gostTC26Sign256A = 80, | |
| + OID_gostTC26Sign256B = 81, | |
| + OID_gostTC26Sign256C = 82, | |
| + OID_gostTC26Sign256D = 83, | |
| + OID_gostTC26Sign512A = 84, | |
| + OID_gostTC26Sign512B = 85, | |
| + OID_gostTC26Sign512C = 86, | |
| + OID_sm2 = 87, | |
| + OID_sm3 = 88, | |
| + OID_SM2_with_SM3 = 89, | |
| + OID_sm3WithRSAEncryption = 90, | |
| + OID_TPMLoadableKey = 91, | |
| + OID_TPMImportableKey = 92, | |
| + OID_TPMSealedData = 93, | |
| + OID_sha3_256 = 94, | |
| + OID_sha3_384 = 95, | |
| + OID_sha3_512 = 96, | |
| + OID_id_ecdsa_with_sha3_256 = 97, | |
| + OID_id_ecdsa_with_sha3_384 = 98, | |
| + OID_id_ecdsa_with_sha3_512 = 99, | |
| + OID_id_rsassa_pkcs1_v1_5_with_sha3_256 = 100, | |
| + OID_id_rsassa_pkcs1_v1_5_with_sha3_384 = 101, | |
| + OID_id_rsassa_pkcs1_v1_5_with_sha3_512 = 102, | |
| + OID__NR = 103, | |
| +}; | |
| + | |
| +enum P4_ESCR_EMASKS { | |
| + P4_EVENT_TC_DELIVER_MODE__DD = 512, | |
| + P4_EVENT_TC_DELIVER_MODE__DB = 1024, | |
| + P4_EVENT_TC_DELIVER_MODE__DI = 2048, | |
| + P4_EVENT_TC_DELIVER_MODE__BD = 4096, | |
| + P4_EVENT_TC_DELIVER_MODE__BB = 8192, | |
| + P4_EVENT_TC_DELIVER_MODE__BI = 16384, | |
| + P4_EVENT_TC_DELIVER_MODE__ID = 32768, | |
| + P4_EVENT_BPU_FETCH_REQUEST__TCMISS = 512, | |
| + P4_EVENT_ITLB_REFERENCE__HIT = 512, | |
| + P4_EVENT_ITLB_REFERENCE__MISS = 1024, | |
| + P4_EVENT_ITLB_REFERENCE__HIT_UK = 2048, | |
| + P4_EVENT_MEMORY_CANCEL__ST_RB_FULL = 2048, | |
| + P4_EVENT_MEMORY_CANCEL__64K_CONF = 4096, | |
| + P4_EVENT_MEMORY_COMPLETE__LSC = 512, | |
| + P4_EVENT_MEMORY_COMPLETE__SSC = 1024, | |
| + P4_EVENT_LOAD_PORT_REPLAY__SPLIT_LD = 1024, | |
| + P4_EVENT_STORE_PORT_REPLAY__SPLIT_ST = 1024, | |
| + P4_EVENT_MOB_LOAD_REPLAY__NO_STA = 1024, | |
| + P4_EVENT_MOB_LOAD_REPLAY__NO_STD = 4096, | |
| + P4_EVENT_MOB_LOAD_REPLAY__PARTIAL_DATA = 8192, | |
| + P4_EVENT_MOB_LOAD_REPLAY__UNALGN_ADDR = 16384, | |
| + P4_EVENT_PAGE_WALK_TYPE__DTMISS = 512, | |
| + P4_EVENT_PAGE_WALK_TYPE__ITMISS = 1024, | |
| + P4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_HITS = 512, | |
| + P4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_HITE = 1024, | |
| + P4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_HITM = 2048, | |
| + P4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_HITS = 4096, | |
| + P4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_HITE = 8192, | |
| + P4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_HITM = 16384, | |
| + P4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_MISS = 131072, | |
| + P4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_MISS = 262144, | |
| + P4_EVENT_BSQ_CACHE_REFERENCE__WR_2ndL_MISS = 524288, | |
| + P4_EVENT_IOQ_ALLOCATION__DEFAULT = 512, | |
| + P4_EVENT_IOQ_ALLOCATION__ALL_READ = 16384, | |
| + P4_EVENT_IOQ_ALLOCATION__ALL_WRITE = 32768, | |
| + P4_EVENT_IOQ_ALLOCATION__MEM_UC = 65536, | |
| + P4_EVENT_IOQ_ALLOCATION__MEM_WC = 131072, | |
| + P4_EVENT_IOQ_ALLOCATION__MEM_WT = 262144, | |
| + P4_EVENT_IOQ_ALLOCATION__MEM_WP = 524288, | |
| + P4_EVENT_IOQ_ALLOCATION__MEM_WB = 1048576, | |
| + P4_EVENT_IOQ_ALLOCATION__OWN = 4194304, | |
| + P4_EVENT_IOQ_ALLOCATION__OTHER = 8388608, | |
| + P4_EVENT_IOQ_ALLOCATION__PREFETCH = 16777216, | |
| + P4_EVENT_IOQ_ACTIVE_ENTRIES__DEFAULT = 512, | |
| + P4_EVENT_IOQ_ACTIVE_ENTRIES__ALL_READ = 16384, | |
| + P4_EVENT_IOQ_ACTIVE_ENTRIES__ALL_WRITE = 32768, | |
| + P4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_UC = 65536, | |
| + P4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WC = 131072, | |
| + P4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WT = 262144, | |
| + P4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WP = 524288, | |
| + P4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WB = 1048576, | |
| + P4_EVENT_IOQ_ACTIVE_ENTRIES__OWN = 4194304, | |
| + P4_EVENT_IOQ_ACTIVE_ENTRIES__OTHER = 8388608, | |
| + P4_EVENT_IOQ_ACTIVE_ENTRIES__PREFETCH = 16777216, | |
| + P4_EVENT_FSB_DATA_ACTIVITY__DRDY_DRV = 512, | |
| + P4_EVENT_FSB_DATA_ACTIVITY__DRDY_OWN = 1024, | |
| + P4_EVENT_FSB_DATA_ACTIVITY__DRDY_OTHER = 2048, | |
| + P4_EVENT_FSB_DATA_ACTIVITY__DBSY_DRV = 4096, | |
| + P4_EVENT_FSB_DATA_ACTIVITY__DBSY_OWN = 8192, | |
| + P4_EVENT_FSB_DATA_ACTIVITY__DBSY_OTHER = 16384, | |
| + P4_EVENT_BSQ_ALLOCATION__REQ_TYPE0 = 512, | |
| + P4_EVENT_BSQ_ALLOCATION__REQ_TYPE1 = 1024, | |
| + P4_EVENT_BSQ_ALLOCATION__REQ_LEN0 = 2048, | |
| + P4_EVENT_BSQ_ALLOCATION__REQ_LEN1 = 4096, | |
| + P4_EVENT_BSQ_ALLOCATION__REQ_IO_TYPE = 16384, | |
| + P4_EVENT_BSQ_ALLOCATION__REQ_LOCK_TYPE = 32768, | |
| + P4_EVENT_BSQ_ALLOCATION__REQ_CACHE_TYPE = 65536, | |
| + P4_EVENT_BSQ_ALLOCATION__REQ_SPLIT_TYPE = 131072, | |
| + P4_EVENT_BSQ_ALLOCATION__REQ_DEM_TYPE = 262144, | |
| + P4_EVENT_BSQ_ALLOCATION__REQ_ORD_TYPE = 524288, | |
| + P4_EVENT_BSQ_ALLOCATION__MEM_TYPE0 = 1048576, | |
| + P4_EVENT_BSQ_ALLOCATION__MEM_TYPE1 = 2097152, | |
| + P4_EVENT_BSQ_ALLOCATION__MEM_TYPE2 = 4194304, | |
| + P4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_TYPE0 = 512, | |
| + P4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_TYPE1 = 1024, | |
| + P4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_LEN0 = 2048, | |
| + P4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_LEN1 = 4096, | |
| + P4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_IO_TYPE = 16384, | |
| + P4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_LOCK_TYPE = 32768, | |
| + P4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_CACHE_TYPE = 65536, | |
| + P4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_SPLIT_TYPE = 131072, | |
| + P4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_DEM_TYPE = 262144, | |
| + P4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_ORD_TYPE = 524288, | |
| + P4_EVENT_BSQ_ACTIVE_ENTRIES__MEM_TYPE0 = 1048576, | |
| + P4_EVENT_BSQ_ACTIVE_ENTRIES__MEM_TYPE1 = 2097152, | |
| + P4_EVENT_BSQ_ACTIVE_ENTRIES__MEM_TYPE2 = 4194304, | |
| + P4_EVENT_SSE_INPUT_ASSIST__ALL = 16777216, | |
| + P4_EVENT_PACKED_SP_UOP__ALL = 16777216, | |
| + P4_EVENT_PACKED_DP_UOP__ALL = 16777216, | |
| + P4_EVENT_SCALAR_SP_UOP__ALL = 16777216, | |
| + P4_EVENT_SCALAR_DP_UOP__ALL = 16777216, | |
| + P4_EVENT_64BIT_MMX_UOP__ALL = 16777216, | |
| + P4_EVENT_128BIT_MMX_UOP__ALL = 16777216, | |
| + P4_EVENT_X87_FP_UOP__ALL = 16777216, | |
| + P4_EVENT_TC_MISC__FLUSH = 8192, | |
| + P4_EVENT_GLOBAL_POWER_EVENTS__RUNNING = 512, | |
| + P4_EVENT_TC_MS_XFER__CISC = 512, | |
| + P4_EVENT_UOP_QUEUE_WRITES__FROM_TC_BUILD = 512, | |
| + P4_EVENT_UOP_QUEUE_WRITES__FROM_TC_DELIVER = 1024, | |
| + P4_EVENT_UOP_QUEUE_WRITES__FROM_ROM = 2048, | |
| + P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__CONDITIONAL = 1024, | |
| + P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__CALL = 2048, | |
| + P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__RETURN = 4096, | |
| + P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__INDIRECT = 8192, | |
| + P4_EVENT_RETIRED_BRANCH_TYPE__CONDITIONAL = 1024, | |
| + P4_EVENT_RETIRED_BRANCH_TYPE__CALL = 2048, | |
| + P4_EVENT_RETIRED_BRANCH_TYPE__RETURN = 4096, | |
| + P4_EVENT_RETIRED_BRANCH_TYPE__INDIRECT = 8192, | |
| + P4_EVENT_RESOURCE_STALL__SBFULL = 16384, | |
| + P4_EVENT_WC_BUFFER__WCB_EVICTS = 512, | |
| + P4_EVENT_WC_BUFFER__WCB_FULL_EVICTS = 1024, | |
| + P4_EVENT_FRONT_END_EVENT__NBOGUS = 512, | |
| + P4_EVENT_FRONT_END_EVENT__BOGUS = 1024, | |
| + P4_EVENT_EXECUTION_EVENT__NBOGUS0 = 512, | |
| + P4_EVENT_EXECUTION_EVENT__NBOGUS1 = 1024, | |
| + P4_EVENT_EXECUTION_EVENT__NBOGUS2 = 2048, | |
| + P4_EVENT_EXECUTION_EVENT__NBOGUS3 = 4096, | |
| + P4_EVENT_EXECUTION_EVENT__BOGUS0 = 8192, | |
| + P4_EVENT_EXECUTION_EVENT__BOGUS1 = 16384, | |
| + P4_EVENT_EXECUTION_EVENT__BOGUS2 = 32768, | |
| + P4_EVENT_EXECUTION_EVENT__BOGUS3 = 65536, | |
| + P4_EVENT_REPLAY_EVENT__NBOGUS = 512, | |
| + P4_EVENT_REPLAY_EVENT__BOGUS = 1024, | |
| + P4_EVENT_INSTR_RETIRED__NBOGUSNTAG = 512, | |
| + P4_EVENT_INSTR_RETIRED__NBOGUSTAG = 1024, | |
| + P4_EVENT_INSTR_RETIRED__BOGUSNTAG = 2048, | |
| + P4_EVENT_INSTR_RETIRED__BOGUSTAG = 4096, | |
| + P4_EVENT_UOPS_RETIRED__NBOGUS = 512, | |
| + P4_EVENT_UOPS_RETIRED__BOGUS = 1024, | |
| + P4_EVENT_UOP_TYPE__TAGLOADS = 1024, | |
| + P4_EVENT_UOP_TYPE__TAGSTORES = 2048, | |
| + P4_EVENT_BRANCH_RETIRED__MMNP = 512, | |
| + P4_EVENT_BRANCH_RETIRED__MMNM = 1024, | |
| + P4_EVENT_BRANCH_RETIRED__MMTP = 2048, | |
| + P4_EVENT_BRANCH_RETIRED__MMTM = 4096, | |
| + P4_EVENT_MISPRED_BRANCH_RETIRED__NBOGUS = 512, | |
| + P4_EVENT_X87_ASSIST__FPSU = 512, | |
| + P4_EVENT_X87_ASSIST__FPSO = 1024, | |
| + P4_EVENT_X87_ASSIST__POAO = 2048, | |
| + P4_EVENT_X87_ASSIST__POAU = 4096, | |
| + P4_EVENT_X87_ASSIST__PREA = 8192, | |
| + P4_EVENT_MACHINE_CLEAR__CLEAR = 512, | |
| + P4_EVENT_MACHINE_CLEAR__MOCLEAR = 1024, | |
| + P4_EVENT_MACHINE_CLEAR__SMCLEAR = 2048, | |
| + P4_EVENT_INSTR_COMPLETED__NBOGUS = 512, | |
| + P4_EVENT_INSTR_COMPLETED__BOGUS = 1024, | |
| }; | |
| enum P4_EVENTS { | |
| @@ -10489,6 +11197,55 @@ | |
| P4_EVENT_INSTR_COMPLETED = 45, | |
| }; | |
| +enum P4_EVENT_OPCODES { | |
| + P4_EVENT_TC_DELIVER_MODE_OPCODE = 257, | |
| + P4_EVENT_BPU_FETCH_REQUEST_OPCODE = 768, | |
| + P4_EVENT_ITLB_REFERENCE_OPCODE = 6147, | |
| + P4_EVENT_MEMORY_CANCEL_OPCODE = 517, | |
| + P4_EVENT_MEMORY_COMPLETE_OPCODE = 2050, | |
| + P4_EVENT_LOAD_PORT_REPLAY_OPCODE = 1026, | |
| + P4_EVENT_STORE_PORT_REPLAY_OPCODE = 1282, | |
| + P4_EVENT_MOB_LOAD_REPLAY_OPCODE = 770, | |
| + P4_EVENT_PAGE_WALK_TYPE_OPCODE = 260, | |
| + P4_EVENT_BSQ_CACHE_REFERENCE_OPCODE = 3079, | |
| + P4_EVENT_IOQ_ALLOCATION_OPCODE = 774, | |
| + P4_EVENT_IOQ_ACTIVE_ENTRIES_OPCODE = 6662, | |
| + P4_EVENT_FSB_DATA_ACTIVITY_OPCODE = 5894, | |
| + P4_EVENT_BSQ_ALLOCATION_OPCODE = 1287, | |
| + P4_EVENT_BSQ_ACTIVE_ENTRIES_OPCODE = 1543, | |
| + P4_EVENT_SSE_INPUT_ASSIST_OPCODE = 13313, | |
| + P4_EVENT_PACKED_SP_UOP_OPCODE = 2049, | |
| + P4_EVENT_PACKED_DP_UOP_OPCODE = 3073, | |
| + P4_EVENT_SCALAR_SP_UOP_OPCODE = 2561, | |
| + P4_EVENT_SCALAR_DP_UOP_OPCODE = 3585, | |
| + P4_EVENT_64BIT_MMX_UOP_OPCODE = 513, | |
| + P4_EVENT_128BIT_MMX_UOP_OPCODE = 6657, | |
| + P4_EVENT_X87_FP_UOP_OPCODE = 1025, | |
| + P4_EVENT_TC_MISC_OPCODE = 1537, | |
| + P4_EVENT_GLOBAL_POWER_EVENTS_OPCODE = 4870, | |
| + P4_EVENT_TC_MS_XFER_OPCODE = 1280, | |
| + P4_EVENT_UOP_QUEUE_WRITES_OPCODE = 2304, | |
| + P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE_OPCODE = 1282, | |
| + P4_EVENT_RETIRED_BRANCH_TYPE_OPCODE = 1026, | |
| + P4_EVENT_RESOURCE_STALL_OPCODE = 257, | |
| + P4_EVENT_WC_BUFFER_OPCODE = 1285, | |
| + P4_EVENT_B2B_CYCLES_OPCODE = 5635, | |
| + P4_EVENT_BNR_OPCODE = 2051, | |
| + P4_EVENT_SNOOP_OPCODE = 1539, | |
| + P4_EVENT_RESPONSE_OPCODE = 1027, | |
| + P4_EVENT_FRONT_END_EVENT_OPCODE = 2053, | |
| + P4_EVENT_EXECUTION_EVENT_OPCODE = 3077, | |
| + P4_EVENT_REPLAY_EVENT_OPCODE = 2309, | |
| + P4_EVENT_INSTR_RETIRED_OPCODE = 516, | |
| + P4_EVENT_UOPS_RETIRED_OPCODE = 260, | |
| + P4_EVENT_UOP_TYPE_OPCODE = 514, | |
| + P4_EVENT_BRANCH_RETIRED_OPCODE = 1541, | |
| + P4_EVENT_MISPRED_BRANCH_RETIRED_OPCODE = 772, | |
| + P4_EVENT_X87_ASSIST_OPCODE = 773, | |
| + P4_EVENT_MACHINE_CLEAR_OPCODE = 517, | |
| + P4_EVENT_INSTR_COMPLETED_OPCODE = 1796, | |
| +}; | |
| + | |
| enum P4_PEBS_METRIC { | |
| P4_PEBS_METRIC__none = 0, | |
| P4_PEBS_METRIC__1stl_cache_load_miss_retired = 1, | |
| @@ -10508,60 +11265,26 @@ | |
| SHIFT_RIGHT = 1, | |
| }; | |
| -enum SUPPORTED_CODE { | |
| - CODE_ASF1 = 0, | |
| - CODE_ASF2 = 1, | |
| - CODE_PASSTHRU = 2, | |
| - CODE_PT_SEC = 3, | |
| - CODE_UMP = 4, | |
| - CODE_BOOT = 5, | |
| - CODE_DASH = 6, | |
| - CODE_MCTP_PASSTHRU = 7, | |
| - CODE_PM_OFFLOAD = 8, | |
| - CODE_MDNS_SD_OFFLOAD = 9, | |
| - CODE_DISC_OFFLOAD = 10, | |
| - CODE_MUSTANG = 11, | |
| - CODE_ARP_BATCH = 12, | |
| - CODE_SMASH = 13, | |
| - CODE_APE_DIAG = 14, | |
| - CODE_APE_PATCH = 15, | |
| - CODE_TANG_PATCH = 16, | |
| - CODE_KONG_FW = 17, | |
| - CODE_KONG_PATCH = 18, | |
| - CODE_BONO_FW = 19, | |
| - CODE_BONO_PATCH = 20, | |
| - CODE_CHIMP_PATCH = 21, | |
| - MAX_CODE_TYPE = 22, | |
| -}; | |
| - | |
| -enum SUPPORTED_FAMILY { | |
| - DEVICE_5702_3_4_FAMILY = 0, | |
| - DEVICE_5705_FAMILY = 1, | |
| - DEVICE_SHASTA_FAMILY = 2, | |
| - DEVICE_5706_FAMILY = 3, | |
| - DEVICE_5714_FAMILY = 4, | |
| - DEVICE_STANFORD_FAMILY = 5, | |
| - DEVICE_STANFORD_ME_FAMILY = 6, | |
| - DEVICE_SOLEDAD_FAMILY = 7, | |
| - DEVICE_CILAI_FAMILY = 8, | |
| - DEVICE_ASPEN_FAMILY = 9, | |
| - DEVICE_ASPEN_PLUS_FAMILY = 10, | |
| - DEVICE_LOGAN_FAMILY = 11, | |
| - DEVICE_LOGAN_5762 = 12, | |
| - DEVICE_LOGAN_57767 = 13, | |
| - DEVICE_LOGAN_57787 = 14, | |
| - DEVICE_LOGAN_5725 = 15, | |
| - DEVICE_SAWTOOTH_FAMILY = 16, | |
| - DEVICE_COTOPAXI_FAMILY = 17, | |
| - DEVICE_SNAGGLETOOTH_FAMILY = 18, | |
| - DEVICE_CUMULUS_FAMILY = 19, | |
| - MAX_DEVICE_FAMILY = 20, | |
| +enum SS4_PACKET_ID { | |
| + SS4_PACKET_ID_IDLE = 0, | |
| + SS4_PACKET_ID_ONE = 1, | |
| + SS4_PACKET_ID_TWO = 2, | |
| + SS4_PACKET_ID_MULTI = 3, | |
| + SS4_PACKET_ID_STICK = 4, | |
| }; | |
| enum TPM_OPS_FLAGS { | |
| TPM_OPS_AUTO_STARTUP = 1, | |
| }; | |
| +enum V7_PACKET_ID { | |
| + V7_PACKET_ID_IDLE = 0, | |
| + V7_PACKET_ID_TWO = 1, | |
| + V7_PACKET_ID_MULTI = 2, | |
| + V7_PACKET_ID_NEW = 3, | |
| + V7_PACKET_ID_UNKNOWN = 4, | |
| +}; | |
| + | |
| typedef enum { | |
| ZSTD_e_continue = 0, | |
| ZSTD_e_flush = 1, | |
| @@ -10577,14 +11300,17 @@ | |
| ZSTD_error_frameParameter_windowTooLarge = 16, | |
| ZSTD_error_corruption_detected = 20, | |
| ZSTD_error_checksum_wrong = 22, | |
| + ZSTD_error_literals_headerWrong = 24, | |
| ZSTD_error_dictionary_corrupted = 30, | |
| ZSTD_error_dictionary_wrong = 32, | |
| ZSTD_error_dictionaryCreation_failed = 34, | |
| ZSTD_error_parameter_unsupported = 40, | |
| + ZSTD_error_parameter_combination_unsupported = 41, | |
| ZSTD_error_parameter_outOfBound = 42, | |
| ZSTD_error_tableLog_tooLarge = 44, | |
| ZSTD_error_maxSymbolValue_tooLarge = 46, | |
| ZSTD_error_maxSymbolValue_tooSmall = 48, | |
| + ZSTD_error_stabilityCondition_notRespected = 50, | |
| ZSTD_error_stage_wrong = 60, | |
| ZSTD_error_init_missing = 62, | |
| ZSTD_error_memory_allocation = 64, | |
| @@ -10592,10 +11318,14 @@ | |
| ZSTD_error_dstSize_tooSmall = 70, | |
| ZSTD_error_srcSize_wrong = 72, | |
| ZSTD_error_dstBuffer_null = 74, | |
| + ZSTD_error_noForwardProgress_destFull = 80, | |
| + ZSTD_error_noForwardProgress_inputEmpty = 82, | |
| ZSTD_error_frameIndex_tooLarge = 100, | |
| ZSTD_error_seekableIO = 102, | |
| ZSTD_error_dstBuffer_wrong = 104, | |
| ZSTD_error_srcBuffer_wrong = 105, | |
| + ZSTD_error_sequenceProducer_failed = 106, | |
| + ZSTD_error_externalSequences_invalid = 107, | |
| ZSTD_error_maxCode = 120, | |
| } ZSTD_ErrorCode; | |
| @@ -10666,6 +11396,10 @@ | |
| ZSTD_c_experimentalParam13 = 1010, | |
| ZSTD_c_experimentalParam14 = 1011, | |
| ZSTD_c_experimentalParam15 = 1012, | |
| + ZSTD_c_experimentalParam16 = 1013, | |
| + ZSTD_c_experimentalParam17 = 1014, | |
| + ZSTD_c_experimentalParam18 = 1015, | |
| + ZSTD_c_experimentalParam19 = 1016, | |
| } ZSTD_cParameter; | |
| typedef enum { | |
| @@ -10688,8 +11422,9 @@ | |
| typedef enum { | |
| ZSTD_cwksp_alloc_objects = 0, | |
| - ZSTD_cwksp_alloc_buffers = 1, | |
| + ZSTD_cwksp_alloc_aligned_init_once = 1, | |
| ZSTD_cwksp_alloc_aligned = 2, | |
| + ZSTD_cwksp_alloc_buffers = 3, | |
| } ZSTD_cwksp_alloc_phase_e; | |
| typedef enum { | |
| @@ -10703,6 +11438,7 @@ | |
| ZSTD_d_experimentalParam2 = 1001, | |
| ZSTD_d_experimentalParam3 = 1002, | |
| ZSTD_d_experimentalParam4 = 1003, | |
| + ZSTD_d_experimentalParam5 = 1004, | |
| } ZSTD_dParameter; | |
| typedef enum { | |
| @@ -10849,6 +11585,112 @@ | |
| ZSTD_btultra2 = 9, | |
| } ZSTD_strategy; | |
| +typedef enum { | |
| + ZSTD_tfp_forCCtx = 0, | |
| + ZSTD_tfp_forCDict = 1, | |
| +} ZSTD_tableFillPurpose_e; | |
| + | |
| +enum _MpiIocLogInfoFc { | |
| + MPI_IOCLOGINFO_FC_INIT_BASE = 536870912, | |
| + MPI_IOCLOGINFO_FC_INIT_ERROR_OUT_OF_ORDER_FRAME = 536870913, | |
| + MPI_IOCLOGINFO_FC_INIT_ERROR_BAD_START_OF_FRAME = 536870914, | |
| + MPI_IOCLOGINFO_FC_INIT_ERROR_BAD_END_OF_FRAME = 536870915, | |
| + MPI_IOCLOGINFO_FC_INIT_ERROR_OVER_RUN = 536870916, | |
| + MPI_IOCLOGINFO_FC_INIT_ERROR_RX_OTHER = 536870917, | |
| + MPI_IOCLOGINFO_FC_INIT_ERROR_SUBPROC_DEAD = 536870918, | |
| + MPI_IOCLOGINFO_FC_INIT_ERROR_RX_OVERRUN = 536870919, | |
| + MPI_IOCLOGINFO_FC_INIT_ERROR_RX_BAD_STATUS = 536870920, | |
| + MPI_IOCLOGINFO_FC_INIT_ERROR_RX_UNEXPECTED_FRAME = 536870921, | |
| + MPI_IOCLOGINFO_FC_INIT_ERROR_LINK_FAILURE = 536870922, | |
| + MPI_IOCLOGINFO_FC_INIT_ERROR_TX_TIMEOUT = 536870923, | |
| + MPI_IOCLOGINFO_FC_TARGET_BASE = 553648128, | |
| + MPI_IOCLOGINFO_FC_TARGET_NO_PDISC = 553648129, | |
| + MPI_IOCLOGINFO_FC_TARGET_NO_LOGIN = 553648130, | |
| + MPI_IOCLOGINFO_FC_TARGET_DOAR_KILLED_BY_LIP = 553648131, | |
| + MPI_IOCLOGINFO_FC_TARGET_DIAR_KILLED_BY_LIP = 553648132, | |
| + MPI_IOCLOGINFO_FC_TARGET_DIAR_MISSING_DATA = 553648133, | |
| + MPI_IOCLOGINFO_FC_TARGET_DONR_KILLED_BY_LIP = 553648134, | |
| + MPI_IOCLOGINFO_FC_TARGET_WRSP_KILLED_BY_LIP = 553648135, | |
| + MPI_IOCLOGINFO_FC_TARGET_DINR_KILLED_BY_LIP = 553648136, | |
| + MPI_IOCLOGINFO_FC_TARGET_DINR_MISSING_DATA = 553648137, | |
| + MPI_IOCLOGINFO_FC_TARGET_MRSP_KILLED_BY_LIP = 553648138, | |
| + MPI_IOCLOGINFO_FC_TARGET_NO_CLASS_3 = 553648139, | |
| + MPI_IOCLOGINFO_FC_TARGET_LOGIN_NOT_VALID = 553648140, | |
| + MPI_IOCLOGINFO_FC_TARGET_FROM_OUTBOUND = 553648142, | |
| + MPI_IOCLOGINFO_FC_TARGET_WAITING_FOR_DATA_IN = 553648143, | |
| + MPI_IOCLOGINFO_FC_LAN_BASE = 570425344, | |
| + MPI_IOCLOGINFO_FC_LAN_TRANS_SGL_MISSING = 570425345, | |
| + MPI_IOCLOGINFO_FC_LAN_TRANS_WRONG_PLACE = 570425346, | |
| + MPI_IOCLOGINFO_FC_LAN_TRANS_RES_BITS_SET = 570425347, | |
| + MPI_IOCLOGINFO_FC_LAN_WRONG_SGL_FLAG = 570425348, | |
| + MPI_IOCLOGINFO_FC_MSG_BASE = 587202560, | |
| + MPI_IOCLOGINFO_FC_LINK_BASE = 603979776, | |
| + MPI_IOCLOGINFO_FC_LINK_LOOP_INIT_TIMEOUT = 603979777, | |
| + MPI_IOCLOGINFO_FC_LINK_ALREADY_INITIALIZED = 603979778, | |
| + MPI_IOCLOGINFO_FC_LINK_LINK_NOT_ESTABLISHED = 603979779, | |
| + MPI_IOCLOGINFO_FC_LINK_CRC_ERROR = 603979780, | |
| + MPI_IOCLOGINFO_FC_CTX_BASE = 620756992, | |
| + MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET = 637534208, | |
| + MPI_IOCLOGINFO_FC_INVALID_FIELD_MAX_OFFSET = 654311423, | |
| + MPI_IOCLOGINFO_FC_STATE_CHANGE = 654311424, | |
| +}; | |
| + | |
| +enum ___mac80211_drop_reason { | |
| + ___RX_CONTINUE = 1, | |
| + ___RX_QUEUED = 0, | |
| + ___RX_DROP_MONITOR = 131072, | |
| + ___RX_DROP_M_UNEXPECTED_4ADDR_FRAME = 131073, | |
| + ___RX_DROP_M_BAD_BCN_KEYIDX = 131074, | |
| + ___RX_DROP_M_BAD_MGMT_KEYIDX = 131075, | |
| + ___RX_DROP_UNUSABLE = 65536, | |
| + ___RX_DROP_U_MIC_FAIL = 65537, | |
| + ___RX_DROP_U_REPLAY = 65538, | |
| + ___RX_DROP_U_BAD_MMIE = 65539, | |
| + ___RX_DROP_U_DUP = 65540, | |
| + ___RX_DROP_U_SPURIOUS = 65541, | |
| + ___RX_DROP_U_DECRYPT_FAIL = 65542, | |
| + ___RX_DROP_U_NO_KEY_ID = 65543, | |
| + ___RX_DROP_U_BAD_CIPHER = 65544, | |
| + ___RX_DROP_U_OOM = 65545, | |
| + ___RX_DROP_U_NONSEQ_PN = 65546, | |
| + ___RX_DROP_U_BAD_KEY_COLOR = 65547, | |
| + ___RX_DROP_U_BAD_4ADDR = 65548, | |
| + ___RX_DROP_U_BAD_AMSDU = 65549, | |
| + ___RX_DROP_U_BAD_AMSDU_CIPHER = 65550, | |
| + ___RX_DROP_U_INVALID_8023 = 65551, | |
| + ___RX_DROP_U_RUNT_ACTION = 65552, | |
| + ___RX_DROP_U_UNPROT_ACTION = 65553, | |
| + ___RX_DROP_U_UNPROT_DUAL = 65554, | |
| + ___RX_DROP_U_UNPROT_UCAST_MGMT = 65555, | |
| + ___RX_DROP_U_UNPROT_MCAST_MGMT = 65556, | |
| + ___RX_DROP_U_UNPROT_BEACON = 65557, | |
| + ___RX_DROP_U_UNPROT_UNICAST_PUB_ACTION = 65558, | |
| + ___RX_DROP_U_UNPROT_ROBUST_ACTION = 65559, | |
| + ___RX_DROP_U_ACTION_UNKNOWN_SRC = 65560, | |
| + ___RX_DROP_U_REJECTED_ACTION_RESPONSE = 65561, | |
| + ___RX_DROP_U_EXPECT_DEFRAG_PROT = 65562, | |
| + ___RX_DROP_U_WEP_DEC_FAIL = 65563, | |
| + ___RX_DROP_U_NO_IV = 65564, | |
| + ___RX_DROP_U_NO_ICV = 65565, | |
| + ___RX_DROP_U_AP_RX_GROUPCAST = 65566, | |
| + ___RX_DROP_U_SHORT_MMIC = 65567, | |
| + ___RX_DROP_U_MMIC_FAIL = 65568, | |
| + ___RX_DROP_U_SHORT_TKIP = 65569, | |
| + ___RX_DROP_U_TKIP_FAIL = 65570, | |
| + ___RX_DROP_U_SHORT_CCMP = 65571, | |
| + ___RX_DROP_U_SHORT_CCMP_MIC = 65572, | |
| + ___RX_DROP_U_SHORT_GCMP = 65573, | |
| + ___RX_DROP_U_SHORT_GCMP_MIC = 65574, | |
| + ___RX_DROP_U_SHORT_CMAC = 65575, | |
| + ___RX_DROP_U_SHORT_CMAC256 = 65576, | |
| + ___RX_DROP_U_SHORT_GMAC = 65577, | |
| + ___RX_DROP_U_UNEXPECTED_VLAN_4ADDR = 65578, | |
| + ___RX_DROP_U_UNEXPECTED_STA_4ADDR = 65579, | |
| + ___RX_DROP_U_UNEXPECTED_VLAN_MCAST = 65580, | |
| + ___RX_DROP_U_NOT_PORT_CONTROL = 65581, | |
| + ___RX_DROP_U_UNKNOWN_ACTION_REJECTED = 65582, | |
| +}; | |
| + | |
| enum __sk_action { | |
| __SK_DROP = 0, | |
| __SK_PASS = 1, | |
| @@ -10863,9 +11705,78 @@ | |
| CTYPE_UNIFIED = 3, | |
| }; | |
| -enum _record_type { | |
| - _START_RECORD = 0, | |
| - _COMMIT_RECORD = 1, | |
| +enum _slab_flag_bits { | |
| + _SLAB_CONSISTENCY_CHECKS = 0, | |
| + _SLAB_RED_ZONE = 1, | |
| + _SLAB_POISON = 2, | |
| + _SLAB_KMALLOC = 3, | |
| + _SLAB_HWCACHE_ALIGN = 4, | |
| + _SLAB_CACHE_DMA = 5, | |
| + _SLAB_CACHE_DMA32 = 6, | |
| + _SLAB_STORE_USER = 7, | |
| + _SLAB_PANIC = 8, | |
| + _SLAB_TYPESAFE_BY_RCU = 9, | |
| + _SLAB_TRACE = 10, | |
| + _SLAB_NOLEAKTRACE = 11, | |
| + _SLAB_NO_MERGE = 12, | |
| + _SLAB_FAILSLAB = 13, | |
| + _SLAB_ACCOUNT = 14, | |
| + _SLAB_NO_USER_FLAGS = 15, | |
| + _SLAB_RECLAIM_ACCOUNT = 16, | |
| + _SLAB_OBJECT_POISON = 17, | |
| + _SLAB_CMPXCHG_DOUBLE = 18, | |
| + _SLAB_NO_OBJ_EXT = 19, | |
| + _SLAB_FLAGS_LAST_BIT = 20, | |
| +}; | |
| + | |
| +enum aac_cmd_owner { | |
| + AAC_OWNER_MIDLEVEL = 257, | |
| + AAC_OWNER_LOWLEVEL = 258, | |
| + AAC_OWNER_ERROR_HANDLER = 259, | |
| + AAC_OWNER_FIRMWARE = 262, | |
| +}; | |
| + | |
| +enum aac_log_level { | |
| + LOG_AAC_INIT = 10, | |
| + LOG_AAC_INFORMATIONAL = 20, | |
| + LOG_AAC_WARNING = 30, | |
| + LOG_AAC_LOW_ERROR = 40, | |
| + LOG_AAC_MEDIUM_ERROR = 50, | |
| + LOG_AAC_HIGH_ERROR = 60, | |
| + LOG_AAC_PANIC = 70, | |
| + LOG_AAC_DEBUG = 80, | |
| + LOG_AAC_WINDBG_PRINT = 90, | |
| +}; | |
| + | |
| +enum aac_queue_types { | |
| + HostNormCmdQueue = 0, | |
| + HostHighCmdQueue = 1, | |
| + AdapNormCmdQueue = 2, | |
| + AdapHighCmdQueue = 3, | |
| + HostNormRespQueue = 4, | |
| + HostHighRespQueue = 5, | |
| + AdapNormRespQueue = 6, | |
| + AdapHighRespQueue = 7, | |
| +}; | |
| + | |
| +typedef enum { | |
| + AC_GETDEV_CHANGED = 2048, | |
| + AC_INQ_CHANGED = 1024, | |
| + AC_TRANSFER_NEG = 512, | |
| + AC_LOST_DEVICE = 256, | |
| + AC_FOUND_DEVICE = 128, | |
| + AC_PATH_DEREGISTERED = 64, | |
| + AC_PATH_REGISTERED = 32, | |
| + AC_SENT_BDR = 16, | |
| + AC_SCSI_AEN = 8, | |
| + AC_UNSOL_RESEL = 2, | |
| + AC_BUS_RESET = 1, | |
| +} ac_code; | |
| + | |
| +enum access_coordinate_class { | |
| + ACCESS_COORDINATE_LOCAL = 0, | |
| + ACCESS_COORDINATE_CPU = 1, | |
| + ACCESS_COORDINATE_MAX = 2, | |
| }; | |
| enum acpi_attr_enum { | |
| @@ -10889,6 +11800,16 @@ | |
| ACPI_BUS_DEVICE_TYPE_COUNT = 7, | |
| }; | |
| +enum acpi_cdat_type { | |
| + ACPI_CDAT_TYPE_DSMAS = 0, | |
| + ACPI_CDAT_TYPE_DSLBIS = 1, | |
| + ACPI_CDAT_TYPE_DSMSCIS = 2, | |
| + ACPI_CDAT_TYPE_DSIS = 3, | |
| + ACPI_CDAT_TYPE_DSEMTS = 4, | |
| + ACPI_CDAT_TYPE_SSLBIS = 5, | |
| + ACPI_CDAT_TYPE_RESERVED = 6, | |
| +}; | |
| + | |
| enum acpi_cedt_type { | |
| ACPI_CEDT_TYPE_CHBS = 0, | |
| ACPI_CEDT_TYPE_CFMWS = 1, | |
| @@ -10897,6 +11818,34 @@ | |
| ACPI_CEDT_TYPE_RESERVED = 4, | |
| }; | |
| +enum acpi_device_swnode_dev_props { | |
| + ACPI_DEVICE_SWNODE_DEV_ROTATION = 0, | |
| + ACPI_DEVICE_SWNODE_DEV_CLOCK_FREQUENCY = 1, | |
| + ACPI_DEVICE_SWNODE_DEV_LED_MAX_MICROAMP = 2, | |
| + ACPI_DEVICE_SWNODE_DEV_FLASH_MAX_MICROAMP = 3, | |
| + ACPI_DEVICE_SWNODE_DEV_FLASH_MAX_TIMEOUT_US = 4, | |
| + ACPI_DEVICE_SWNODE_DEV_NUM_OF = 5, | |
| + ACPI_DEVICE_SWNODE_DEV_NUM_ENTRIES = 6, | |
| +}; | |
| + | |
| +enum acpi_device_swnode_ep_props { | |
| + ACPI_DEVICE_SWNODE_EP_REMOTE_EP = 0, | |
| + ACPI_DEVICE_SWNODE_EP_BUS_TYPE = 1, | |
| + ACPI_DEVICE_SWNODE_EP_REG = 2, | |
| + ACPI_DEVICE_SWNODE_EP_CLOCK_LANES = 3, | |
| + ACPI_DEVICE_SWNODE_EP_DATA_LANES = 4, | |
| + ACPI_DEVICE_SWNODE_EP_LANE_POLARITIES = 5, | |
| + ACPI_DEVICE_SWNODE_EP_LINK_FREQUENCIES = 6, | |
| + ACPI_DEVICE_SWNODE_EP_NUM_OF = 7, | |
| + ACPI_DEVICE_SWNODE_EP_NUM_ENTRIES = 8, | |
| +}; | |
| + | |
| +enum acpi_device_swnode_port_props { | |
| + ACPI_DEVICE_SWNODE_PORT_REG = 0, | |
| + ACPI_DEVICE_SWNODE_PORT_NUM_OF = 1, | |
| + ACPI_DEVICE_SWNODE_PORT_NUM_ENTRIES = 2, | |
| +}; | |
| + | |
| enum acpi_dmar_scope_type { | |
| ACPI_DMAR_SCOPE_TYPE_NOT_USED = 0, | |
| ACPI_DMAR_SCOPE_TYPE_ENDPOINT = 1, | |
| @@ -10923,52 +11872,6 @@ | |
| EC_EVENT_COMPLETE = 2, | |
| }; | |
| -enum acpi_einj_actions { | |
| - ACPI_EINJ_BEGIN_OPERATION = 0, | |
| - ACPI_EINJ_GET_TRIGGER_TABLE = 1, | |
| - ACPI_EINJ_SET_ERROR_TYPE = 2, | |
| - ACPI_EINJ_GET_ERROR_TYPE = 3, | |
| - ACPI_EINJ_END_OPERATION = 4, | |
| - ACPI_EINJ_EXECUTE_OPERATION = 5, | |
| - ACPI_EINJ_CHECK_BUSY_STATUS = 6, | |
| - ACPI_EINJ_GET_COMMAND_STATUS = 7, | |
| - ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS = 8, | |
| - ACPI_EINJ_GET_EXECUTE_TIMINGS = 9, | |
| - ACPI_EINJ_ACTION_RESERVED = 10, | |
| - ACPI_EINJ_TRIGGER_ERROR = 255, | |
| -}; | |
| - | |
| -enum acpi_einj_instructions { | |
| - ACPI_EINJ_READ_REGISTER = 0, | |
| - ACPI_EINJ_READ_REGISTER_VALUE = 1, | |
| - ACPI_EINJ_WRITE_REGISTER = 2, | |
| - ACPI_EINJ_WRITE_REGISTER_VALUE = 3, | |
| - ACPI_EINJ_NOOP = 4, | |
| - ACPI_EINJ_FLUSH_CACHELINE = 5, | |
| - ACPI_EINJ_INSTRUCTION_RESERVED = 6, | |
| -}; | |
| - | |
| -enum acpi_erst_actions { | |
| - ACPI_ERST_BEGIN_WRITE = 0, | |
| - ACPI_ERST_BEGIN_READ = 1, | |
| - ACPI_ERST_BEGIN_CLEAR = 2, | |
| - ACPI_ERST_END = 3, | |
| - ACPI_ERST_SET_RECORD_OFFSET = 4, | |
| - ACPI_ERST_EXECUTE_OPERATION = 5, | |
| - ACPI_ERST_CHECK_BUSY_STATUS = 6, | |
| - ACPI_ERST_GET_COMMAND_STATUS = 7, | |
| - ACPI_ERST_GET_RECORD_ID = 8, | |
| - ACPI_ERST_SET_RECORD_ID = 9, | |
| - ACPI_ERST_GET_RECORD_COUNT = 10, | |
| - ACPI_ERST_BEGIN_DUMMY_WRIITE = 11, | |
| - ACPI_ERST_NOT_USED = 12, | |
| - ACPI_ERST_GET_ERROR_RANGE = 13, | |
| - ACPI_ERST_GET_ERROR_LENGTH = 14, | |
| - ACPI_ERST_GET_ERROR_ATTRIBUTES = 15, | |
| - ACPI_ERST_EXECUTE_TIMINGS = 16, | |
| - ACPI_ERST_ACTION_RESERVED = 17, | |
| -}; | |
| - | |
| typedef enum { | |
| OSL_GLOBAL_LOCK_HANDLER = 0, | |
| OSL_NOTIFY_HANDLER = 1, | |
| @@ -10979,38 +11882,6 @@ | |
| OSL_EC_BURST_HANDLER = 6, | |
| } acpi_execute_type; | |
| -enum acpi_hest_notify_types { | |
| - ACPI_HEST_NOTIFY_POLLED = 0, | |
| - ACPI_HEST_NOTIFY_EXTERNAL = 1, | |
| - ACPI_HEST_NOTIFY_LOCAL = 2, | |
| - ACPI_HEST_NOTIFY_SCI = 3, | |
| - ACPI_HEST_NOTIFY_NMI = 4, | |
| - ACPI_HEST_NOTIFY_CMCI = 5, | |
| - ACPI_HEST_NOTIFY_MCE = 6, | |
| - ACPI_HEST_NOTIFY_GPIO = 7, | |
| - ACPI_HEST_NOTIFY_SEA = 8, | |
| - ACPI_HEST_NOTIFY_SEI = 9, | |
| - ACPI_HEST_NOTIFY_GSIV = 10, | |
| - ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED = 11, | |
| - ACPI_HEST_NOTIFY_RESERVED = 12, | |
| -}; | |
| - | |
| -enum acpi_hest_types { | |
| - ACPI_HEST_TYPE_IA32_CHECK = 0, | |
| - ACPI_HEST_TYPE_IA32_CORRECTED_CHECK = 1, | |
| - ACPI_HEST_TYPE_IA32_NMI = 2, | |
| - ACPI_HEST_TYPE_NOT_USED3 = 3, | |
| - ACPI_HEST_TYPE_NOT_USED4 = 4, | |
| - ACPI_HEST_TYPE_NOT_USED5 = 5, | |
| - ACPI_HEST_TYPE_AER_ROOT_PORT = 6, | |
| - ACPI_HEST_TYPE_AER_ENDPOINT = 7, | |
| - ACPI_HEST_TYPE_AER_BRIDGE = 8, | |
| - ACPI_HEST_TYPE_GENERIC_ERROR = 9, | |
| - ACPI_HEST_TYPE_GENERIC_ERROR_V2 = 10, | |
| - ACPI_HEST_TYPE_IA32_DEFERRED_CHECK = 11, | |
| - ACPI_HEST_TYPE_RESERVED = 12, | |
| -}; | |
| - | |
| typedef enum { | |
| ACPI_IMODE_LOAD_PASS1 = 1, | |
| ACPI_IMODE_LOAD_PASS2 = 2, | |
| @@ -11053,7 +11924,10 @@ | |
| ACPI_MADT_TYPE_BIO_PIC = 22, | |
| ACPI_MADT_TYPE_LPC_PIC = 23, | |
| ACPI_MADT_TYPE_RINTC = 24, | |
| - ACPI_MADT_TYPE_RESERVED = 25, | |
| + ACPI_MADT_TYPE_IMSIC = 25, | |
| + ACPI_MADT_TYPE_APLIC = 26, | |
| + ACPI_MADT_TYPE_PLIC = 27, | |
| + ACPI_MADT_TYPE_RESERVED = 28, | |
| ACPI_MADT_TYPE_OEM_RESERVED = 128, | |
| }; | |
| @@ -11074,6 +11948,19 @@ | |
| greater_than_or_equal = 3, | |
| }; | |
| +enum acpi_preferred_pm_profiles { | |
| + PM_UNSPECIFIED = 0, | |
| + PM_DESKTOP = 1, | |
| + PM_MOBILE = 2, | |
| + PM_WORKSTATION = 3, | |
| + PM_ENTERPRISE_SERVER = 4, | |
| + PM_SOHO_SERVER = 5, | |
| + PM_APPLIANCE_PC = 6, | |
| + PM_PERFORMANCE_SERVER = 7, | |
| + PM_TABLET = 8, | |
| + NR_PM_PROFILES = 9, | |
| +}; | |
| + | |
| enum acpi_reconfig_event { | |
| ACPI_RECONFIG_DEVICE_ADD = 0, | |
| ACPI_RECONFIG_DEVICE_REMOVE = 1, | |
| @@ -11103,7 +11990,8 @@ | |
| ACPI_SRAT_TYPE_GIC_ITS_AFFINITY = 4, | |
| ACPI_SRAT_TYPE_GENERIC_AFFINITY = 5, | |
| ACPI_SRAT_TYPE_GENERIC_PORT_AFFINITY = 6, | |
| - ACPI_SRAT_TYPE_RESERVED = 7, | |
| + ACPI_SRAT_TYPE_RINTC_AFFINITY = 7, | |
| + ACPI_SRAT_TYPE_RESERVED = 8, | |
| }; | |
| enum acpi_subtable_type { | |
| @@ -11111,6 +11999,7 @@ | |
| ACPI_SUBTABLE_HMAT = 1, | |
| ACPI_SUBTABLE_PRMT = 2, | |
| ACPI_SUBTABLE_CEDT = 3, | |
| + CDAT_SUBTABLE = 4, | |
| }; | |
| typedef enum { | |
| @@ -11145,6 +12034,295 @@ | |
| AF_VSOCK_TRANSPORT_VIRTIO = 2, | |
| }; | |
| +typedef enum { | |
| + AHC_BUGNONE = 0, | |
| + AHC_TMODE_WIDEODD_BUG = 1, | |
| + AHC_AUTOFLUSH_BUG = 2, | |
| + AHC_CACHETHEN_BUG = 4, | |
| + AHC_CACHETHEN_DIS_BUG = 8, | |
| + AHC_PCI_2_1_RETRY_BUG = 16, | |
| + AHC_PCI_MWI_BUG = 32, | |
| + AHC_SCBCHAN_UPLOAD_BUG = 64, | |
| +} ahc_bug; | |
| + | |
| +typedef enum { | |
| + AHC_NONE = 0, | |
| + AHC_CHIPID_MASK = 255, | |
| + AHC_AIC7770 = 1, | |
| + AHC_AIC7850 = 2, | |
| + AHC_AIC7855 = 3, | |
| + AHC_AIC7859 = 4, | |
| + AHC_AIC7860 = 5, | |
| + AHC_AIC7870 = 6, | |
| + AHC_AIC7880 = 7, | |
| + AHC_AIC7895 = 8, | |
| + AHC_AIC7895C = 9, | |
| + AHC_AIC7890 = 10, | |
| + AHC_AIC7896 = 11, | |
| + AHC_AIC7892 = 12, | |
| + AHC_AIC7899 = 13, | |
| + AHC_VL = 256, | |
| + AHC_EISA = 512, | |
| + AHC_PCI = 1024, | |
| + AHC_BUS_MASK = 3840, | |
| +} ahc_chip; | |
| + | |
| +typedef enum { | |
| + AHC_FENONE = 0, | |
| + AHC_ULTRA = 1, | |
| + AHC_ULTRA2 = 2, | |
| + AHC_WIDE = 4, | |
| + AHC_TWIN = 8, | |
| + AHC_MORE_SRAM = 16, | |
| + AHC_CMD_CHAN = 32, | |
| + AHC_QUEUE_REGS = 64, | |
| + AHC_SG_PRELOAD = 128, | |
| + AHC_SPIOCAP = 256, | |
| + AHC_MULTI_TID = 512, | |
| + AHC_HS_MAILBOX = 1024, | |
| + AHC_DT = 2048, | |
| + AHC_NEW_TERMCTL = 4096, | |
| + AHC_MULTI_FUNC = 8192, | |
| + AHC_LARGE_SCBS = 16384, | |
| + AHC_AUTORATE = 32768, | |
| + AHC_AUTOPAUSE = 65536, | |
| + AHC_TARGETMODE = 131072, | |
| + AHC_MULTIROLE = 262144, | |
| + AHC_REMOVABLE = 524288, | |
| + AHC_HVD = 1048576, | |
| + AHC_AIC7770_FE = 0, | |
| + AHC_AIC7850_FE = 196865, | |
| + AHC_AIC7860_FE = 196865, | |
| + AHC_AIC7870_FE = 196608, | |
| + AHC_AIC7880_FE = 196609, | |
| + AHC_AIC7890_FE = 153330, | |
| + AHC_AIC7892_FE = 253682, | |
| + AHC_AIC7895_FE = 221233, | |
| + AHC_AIC7895C_FE = 221745, | |
| + AHC_AIC7896_FE = 161522, | |
| + AHC_AIC7899_FE = 261874, | |
| +} ahc_feature; | |
| + | |
| +typedef enum { | |
| + AHC_FNONE = 0, | |
| + AHC_PRIMARY_CHANNEL = 3, | |
| + AHC_USEDEFAULTS = 4, | |
| + AHC_SEQUENCER_DEBUG = 8, | |
| + AHC_SHARED_SRAM = 16, | |
| + AHC_LARGE_SEEPROM = 32, | |
| + AHC_RESET_BUS_A = 64, | |
| + AHC_RESET_BUS_B = 128, | |
| + AHC_EXTENDED_TRANS_A = 256, | |
| + AHC_EXTENDED_TRANS_B = 512, | |
| + AHC_TERM_ENB_A = 1024, | |
| + AHC_TERM_ENB_B = 2048, | |
| + AHC_INITIATORROLE = 4096, | |
| + AHC_TARGETROLE = 8192, | |
| + AHC_NEWEEPROM_FMT = 16384, | |
| + AHC_TQINFIFO_BLOCKED = 65536, | |
| + AHC_INT50_SPEEDFLEX = 131072, | |
| + AHC_SCB_BTT = 262144, | |
| + AHC_BIOS_ENABLED = 524288, | |
| + AHC_ALL_INTERRUPTS = 1048576, | |
| + AHC_PAGESCBS = 4194304, | |
| + AHC_EDGE_INTERRUPT = 8388608, | |
| + AHC_39BIT_ADDRESSING = 16777216, | |
| + AHC_LSCBS_ENABLED = 33554432, | |
| + AHC_SCB_CONFIG_USED = 67108864, | |
| + AHC_NO_BIOS_INIT = 134217728, | |
| + AHC_DISABLE_PCI_PERR = 268435456, | |
| + AHC_HAS_TERM_LOGIC = 536870912, | |
| +} ahc_flag; | |
| + | |
| +typedef enum { | |
| + AHC_DEV_FREEZE_TIL_EMPTY = 2, | |
| + AHC_DEV_Q_BASIC = 16, | |
| + AHC_DEV_Q_TAGGED = 32, | |
| + AHC_DEV_PERIODIC_OTAG = 64, | |
| +} ahc_linux_dev_flags; | |
| + | |
| +typedef enum { | |
| + MSG_TYPE_NONE = 0, | |
| + MSG_TYPE_INITIATOR_MSGOUT = 1, | |
| + MSG_TYPE_INITIATOR_MSGIN = 2, | |
| + MSG_TYPE_TARGET_MSGOUT = 3, | |
| + MSG_TYPE_TARGET_MSGIN = 4, | |
| +} ahc_msg_type; | |
| + | |
| +typedef enum { | |
| + AHCMSG_1B = 0, | |
| + AHCMSG_2B = 1, | |
| + AHCMSG_EXT = 2, | |
| +} ahc_msgtype; | |
| + | |
| +typedef enum { | |
| + AHC_NEG_TO_GOAL = 0, | |
| + AHC_NEG_IF_NON_ASYNC = 1, | |
| + AHC_NEG_ALWAYS = 2, | |
| +} ahc_neg_type; | |
| + | |
| +typedef enum { | |
| + AHC_QUEUE_NONE = 0, | |
| + AHC_QUEUE_BASIC = 1, | |
| + AHC_QUEUE_TAGGED = 2, | |
| +} ahc_queue_alg; | |
| + | |
| +typedef enum { | |
| + SEARCH_COMPLETE = 0, | |
| + SEARCH_COUNT = 1, | |
| + SEARCH_REMOVE = 2, | |
| +} ahc_search_action; | |
| + | |
| +typedef enum { | |
| + AHD_BUGNONE = 0, | |
| + AHD_SENT_SCB_UPDATE_BUG = 1, | |
| + AHD_ABORT_LQI_BUG = 2, | |
| + AHD_PKT_BITBUCKET_BUG = 4, | |
| + AHD_LONG_SETIMO_BUG = 8, | |
| + AHD_NLQICRC_DELAYED_BUG = 16, | |
| + AHD_SCSIRST_BUG = 32, | |
| + AHD_PCIX_CHIPRST_BUG = 64, | |
| + AHD_PCIX_MMAPIO_BUG = 128, | |
| + AHD_PCIX_SCBRAM_RD_BUG = 256, | |
| + AHD_PCIX_BUG_MASK = 448, | |
| + AHD_LQO_ATNO_BUG = 512, | |
| + AHD_AUTOFLUSH_BUG = 1024, | |
| + AHD_CLRLQO_AUTOCLR_BUG = 2048, | |
| + AHD_PKTIZED_STATUS_BUG = 4096, | |
| + AHD_PKT_LUN_BUG = 8192, | |
| + AHD_NONPACKFIFO_BUG = 16384, | |
| + AHD_MDFF_WSCBPTR_BUG = 32768, | |
| + AHD_REG_SLOW_SETTLE_BUG = 65536, | |
| + AHD_SET_MODE_BUG = 131072, | |
| + AHD_BUSFREEREV_BUG = 262144, | |
| + AHD_PACED_NEGTABLE_BUG = 524288, | |
| + AHD_LQOOVERRUN_BUG = 1048576, | |
| + AHD_INTCOLLISION_BUG = 2097152, | |
| + AHD_EARLY_REQ_BUG = 4194304, | |
| + AHD_FAINT_LED_BUG = 8388608, | |
| +} ahd_bug; | |
| + | |
| +typedef enum { | |
| + AHD_NONE = 0, | |
| + AHD_CHIPID_MASK = 255, | |
| + AHD_AIC7901 = 1, | |
| + AHD_AIC7902 = 2, | |
| + AHD_AIC7901A = 3, | |
| + AHD_PCI = 256, | |
| + AHD_PCIX = 512, | |
| + AHD_BUS_MASK = 3840, | |
| +} ahd_chip; | |
| + | |
| +typedef enum { | |
| + AHD_FENONE = 0, | |
| + AHD_WIDE = 1, | |
| + AHD_AIC79XXB_SLOWCRC = 2, | |
| + AHD_MULTI_FUNC = 256, | |
| + AHD_TARGETMODE = 4096, | |
| + AHD_MULTIROLE = 8192, | |
| + AHD_RTI = 16384, | |
| + AHD_NEW_IOCELL_OPTS = 32768, | |
| + AHD_NEW_DFCNTRL_OPTS = 65536, | |
| + AHD_FAST_CDB_DELIVERY = 131072, | |
| + AHD_REMOVABLE = 0, | |
| + AHD_AIC7901_FE = 0, | |
| + AHD_AIC7901A_FE = 0, | |
| + AHD_AIC7902_FE = 256, | |
| +} ahd_feature; | |
| + | |
| +typedef enum { | |
| + AHD_FNONE = 0, | |
| + AHD_BOOT_CHANNEL = 1, | |
| + AHD_USEDEFAULTS = 4, | |
| + AHD_SEQUENCER_DEBUG = 8, | |
| + AHD_RESET_BUS_A = 16, | |
| + AHD_EXTENDED_TRANS_A = 32, | |
| + AHD_TERM_ENB_A = 64, | |
| + AHD_SPCHK_ENB_A = 128, | |
| + AHD_STPWLEVEL_A = 256, | |
| + AHD_INITIATORROLE = 512, | |
| + AHD_TARGETROLE = 1024, | |
| + AHD_RESOURCE_SHORTAGE = 2048, | |
| + AHD_TQINFIFO_BLOCKED = 4096, | |
| + AHD_INT50_SPEEDFLEX = 8192, | |
| + AHD_BIOS_ENABLED = 16384, | |
| + AHD_ALL_INTERRUPTS = 32768, | |
| + AHD_39BIT_ADDRESSING = 65536, | |
| + AHD_64BIT_ADDRESSING = 131072, | |
| + AHD_CURRENT_SENSING = 262144, | |
| + AHD_SCB_CONFIG_USED = 524288, | |
| + AHD_HP_BOARD = 1048576, | |
| + AHD_BUS_RESET_ACTIVE = 2097152, | |
| + AHD_UPDATE_PEND_CMDS = 4194304, | |
| + AHD_RUNNING_QOUTFIFO = 8388608, | |
| + AHD_HAD_FIRST_SEL = 16777216, | |
| +} ahd_flag; | |
| + | |
| +typedef enum { | |
| + AHD_DEV_FREEZE_TIL_EMPTY = 2, | |
| + AHD_DEV_Q_BASIC = 16, | |
| + AHD_DEV_Q_TAGGED = 32, | |
| + AHD_DEV_PERIODIC_OTAG = 64, | |
| +} ahd_linux_dev_flags; | |
| + | |
| +typedef enum { | |
| + AHD_MODE_DFF0 = 0, | |
| + AHD_MODE_DFF1 = 1, | |
| + AHD_MODE_CCHAN = 2, | |
| + AHD_MODE_SCSI = 3, | |
| + AHD_MODE_CFG = 4, | |
| + AHD_MODE_UNKNOWN = 5, | |
| +} ahd_mode; | |
| + | |
| +typedef enum { | |
| + MSG_FLAG_NONE = 0, | |
| + MSG_FLAG_EXPECT_PPR_BUSFREE = 1, | |
| + MSG_FLAG_IU_REQ_CHANGED = 2, | |
| + MSG_FLAG_EXPECT_IDE_BUSFREE = 4, | |
| + MSG_FLAG_EXPECT_QASREJ_BUSFREE = 8, | |
| + MSG_FLAG_PACKETIZED = 16, | |
| +} ahd_msg_flags; | |
| + | |
| +typedef enum { | |
| + MSG_TYPE_NONE___2 = 0, | |
| + MSG_TYPE_INITIATOR_MSGOUT___2 = 1, | |
| + MSG_TYPE_INITIATOR_MSGIN___2 = 2, | |
| + MSG_TYPE_TARGET_MSGOUT___2 = 3, | |
| + MSG_TYPE_TARGET_MSGIN___2 = 4, | |
| +} ahd_msg_type; | |
| + | |
| +typedef enum { | |
| + AHDMSG_1B = 0, | |
| + AHDMSG_2B = 1, | |
| + AHDMSG_EXT = 2, | |
| +} ahd_msgtype; | |
| + | |
| +typedef enum { | |
| + AHD_NEG_TO_GOAL = 0, | |
| + AHD_NEG_IF_NON_ASYNC = 1, | |
| + AHD_NEG_ALWAYS = 2, | |
| +} ahd_neg_type; | |
| + | |
| +typedef enum { | |
| + AHD_POWER_STATE_D0 = 0, | |
| + AHD_POWER_STATE_D1 = 1, | |
| + AHD_POWER_STATE_D2 = 2, | |
| + AHD_POWER_STATE_D3 = 3, | |
| +} ahd_power_state; | |
| + | |
| +typedef enum { | |
| + AHD_QUEUE_NONE = 0, | |
| + AHD_QUEUE_BASIC = 1, | |
| + AHD_QUEUE_TAGGED = 2, | |
| +} ahd_queue_alg; | |
| + | |
| +typedef enum { | |
| + SEARCH_COMPLETE___2 = 0, | |
| + SEARCH_COUNT___2 = 1, | |
| + SEARCH_REMOVE___2 = 2, | |
| + SEARCH_PRINT = 3, | |
| +} ahd_search_action; | |
| + | |
| enum alarmtimer_restart { | |
| ALARMTIMER_NORESTART = 0, | |
| ALARMTIMER_RESTART = 1, | |
| @@ -11169,6 +12347,26 @@ | |
| MSR_WRITES_DEFAULT = 2, | |
| }; | |
| +enum alu_dst_ab { | |
| + ALU_DST_A = 0, | |
| + ALU_DST_B = 1, | |
| +}; | |
| + | |
| +enum alu_op { | |
| + ALU_OP_NONE = 0, | |
| + ALU_OP_ADD = 1, | |
| + ALU_OP_NOT = 4, | |
| + ALU_OP_ADD_2B = 5, | |
| + ALU_OP_AND = 8, | |
| + ALU_OP_AND_NOT_A = 12, | |
| + ALU_OP_SUB_C = 13, | |
| + ALU_OP_AND_NOT_B = 16, | |
| + ALU_OP_ADD_C = 17, | |
| + ALU_OP_OR = 20, | |
| + ALU_OP_SUB = 21, | |
| + ALU_OP_XOR = 24, | |
| +}; | |
| + | |
| enum amd_chipset_gen { | |
| NOT_AMD_CHIPSET = 0, | |
| AMD_CHIPSET_SB600 = 1, | |
| @@ -11181,27 +12379,21 @@ | |
| AMD_CHIPSET_UNKNOWN = 8, | |
| }; | |
| -enum amd_iommu_intr_mode_type { | |
| - AMD_IOMMU_GUEST_IR_LEGACY = 0, | |
| - AMD_IOMMU_GUEST_IR_LEGACY_GA = 1, | |
| - AMD_IOMMU_GUEST_IR_VAPIC = 2, | |
| -}; | |
| - | |
| enum amd_pstate_mode { | |
| - AMD_PSTATE_DISABLE = 0, | |
| - AMD_PSTATE_PASSIVE = 1, | |
| - AMD_PSTATE_ACTIVE = 2, | |
| - AMD_PSTATE_GUIDED = 3, | |
| - AMD_PSTATE_MAX = 4, | |
| + AMD_PSTATE_UNDEFINED = 0, | |
| + AMD_PSTATE_DISABLE = 1, | |
| + AMD_PSTATE_PASSIVE = 2, | |
| + AMD_PSTATE_ACTIVE = 3, | |
| + AMD_PSTATE_GUIDED = 4, | |
| + AMD_PSTATE_MAX = 5, | |
| }; | |
| -enum apic_delivery_modes { | |
| - APIC_DELIVERY_MODE_FIXED = 0, | |
| - APIC_DELIVERY_MODE_LOWESTPRIO = 1, | |
| - APIC_DELIVERY_MODE_SMI = 2, | |
| - APIC_DELIVERY_MODE_NMI = 4, | |
| - APIC_DELIVERY_MODE_INIT = 5, | |
| - APIC_DELIVERY_MODE_EXTINT = 7, | |
| +enum aper_size_type { | |
| + U8_APER_SIZE = 0, | |
| + U16_APER_SIZE = 1, | |
| + U32_APER_SIZE = 2, | |
| + LVL2_APER_SIZE = 3, | |
| + FIXED_APER_SIZE = 4, | |
| }; | |
| enum apic_intr_mode_id { | |
| @@ -11311,6 +12503,13 @@ | |
| assoc_array_walk_found_wrong_shortcut = 2, | |
| }; | |
| +enum assoc_status { | |
| + ASSOC_SUCCESS = 0, | |
| + ASSOC_REJECTED = 1, | |
| + ASSOC_TIMEOUT = 2, | |
| + ASSOC_ABANDON = 3, | |
| +}; | |
| + | |
| enum asymmetric_payload_bits { | |
| asym_crypto = 0, | |
| asym_subtype = 1, | |
| @@ -11318,11 +12517,6 @@ | |
| asym_auth = 3, | |
| }; | |
| -enum async_eq_nb_action { | |
| - ASYNC_EQ_IRQ_HANDLER = 0, | |
| - ASYNC_EQ_RECOVER = 1, | |
| -}; | |
| - | |
| enum ata_completion_errors { | |
| AC_ERR_OK = 0, | |
| AC_ERR_DEV = 1, | |
| @@ -11408,7 +12602,9 @@ | |
| AUDIT_NFT_OP_OBJ_RESET = 16, | |
| AUDIT_NFT_OP_FLOWTABLE_REGISTER = 17, | |
| AUDIT_NFT_OP_FLOWTABLE_UNREGISTER = 18, | |
| - AUDIT_NFT_OP_INVALID = 19, | |
| + AUDIT_NFT_OP_SETELEM_RESET = 19, | |
| + AUDIT_NFT_OP_RULE_RESET = 20, | |
| + AUDIT_NFT_OP_INVALID = 21, | |
| }; | |
| enum audit_nlgrps { | |
| @@ -11444,6 +12640,48 @@ | |
| AUDITSC_NVALS = 7, | |
| }; | |
| +enum autofs_notify { | |
| + NFY_NONE = 0, | |
| + NFY_MOUNT = 1, | |
| + NFY_EXPIRE = 2, | |
| +}; | |
| + | |
| +enum avic_ipi_failure_cause { | |
| + AVIC_IPI_FAILURE_INVALID_INT_TYPE = 0, | |
| + AVIC_IPI_FAILURE_TARGET_NOT_RUNNING = 1, | |
| + AVIC_IPI_FAILURE_INVALID_TARGET = 2, | |
| + AVIC_IPI_FAILURE_INVALID_BACKING_PAGE = 3, | |
| + AVIC_IPI_FAILURE_INVALID_IPI_VECTOR = 4, | |
| +}; | |
| + | |
| +enum backlight_notification { | |
| + BACKLIGHT_REGISTERED = 0, | |
| + BACKLIGHT_UNREGISTERED = 1, | |
| +}; | |
| + | |
| +enum backlight_scale { | |
| + BACKLIGHT_SCALE_UNKNOWN = 0, | |
| + BACKLIGHT_SCALE_LINEAR = 1, | |
| + BACKLIGHT_SCALE_NON_LINEAR = 2, | |
| +}; | |
| + | |
| +enum backlight_type { | |
| + BACKLIGHT_RAW = 1, | |
| + BACKLIGHT_PLATFORM = 2, | |
| + BACKLIGHT_FIRMWARE = 3, | |
| + BACKLIGHT_TYPE_MAX = 4, | |
| +}; | |
| + | |
| +enum backlight_update_reason { | |
| + BACKLIGHT_UPDATE_HOTKEY = 0, | |
| + BACKLIGHT_UPDATE_SYSFS = 1, | |
| +}; | |
| + | |
| +typedef enum { | |
| + base_0possible = 0, | |
| + base_1guaranteed = 1, | |
| +} base_directive_e; | |
| + | |
| enum batadv_packettype { | |
| BATADV_IV_OGM = 0, | |
| BATADV_BCAST = 1, | |
| @@ -11471,6 +12709,13 @@ | |
| DROP = 2, | |
| }; | |
| +enum bfs_result { | |
| + BFS_EINVALIDNODE = -2, | |
| + BFS_EQUEUEFULL = -1, | |
| + BFS_RMATCH = 0, | |
| + BFS_RNOMATCH = 1, | |
| +}; | |
| + | |
| enum bh_state_bits { | |
| BH_Uptodate = 0, | |
| BH_Dirty = 1, | |
| @@ -11491,6 +12736,11 @@ | |
| BH_PrivateStart = 16, | |
| }; | |
| +enum bhi_mitigations { | |
| + BHI_MITIGATION_OFF = 0, | |
| + BHI_MITIGATION_ON = 1, | |
| +}; | |
| + | |
| enum bio_merge_status { | |
| BIO_MERGE_OK = 0, | |
| BIO_MERGE_NONE = 1, | |
| @@ -11515,6 +12765,8 @@ | |
| BIP_CTRL_NOCHECK = 4, | |
| BIP_DISK_NOCHECK = 8, | |
| BIP_IP_CHECKSUM = 16, | |
| + BIP_INTEGRITY_USER = 32, | |
| + BIP_COPY_USER = 64, | |
| }; | |
| enum bitmap_page_attr { | |
| @@ -11591,25 +12843,12 @@ | |
| BLK_EH_RESET_TIMER = 1, | |
| }; | |
| -enum blk_integrity_flags { | |
| - BLK_INTEGRITY_VERIFY = 1, | |
| - BLK_INTEGRITY_GENERATE = 2, | |
| - BLK_INTEGRITY_DEVICE_CAPABLE = 4, | |
| - BLK_INTEGRITY_IP_CHECKSUM = 8, | |
| -}; | |
| - | |
| enum blk_unique_id { | |
| BLK_UID_T10 = 1, | |
| BLK_UID_EUI64 = 2, | |
| BLK_UID_NAA = 3, | |
| }; | |
| -enum blk_zoned_model { | |
| - BLK_ZONED_NONE = 0, | |
| - BLK_ZONED_HA = 1, | |
| - BLK_ZONED_HM = 2, | |
| -}; | |
| - | |
| enum blkg_iostat_type { | |
| BLKG_IOSTAT_READ = 0, | |
| BLKG_IOSTAT_WRITE = 1, | |
| @@ -11690,202 +12929,205 @@ | |
| finish_done = 3, | |
| } block_state; | |
| -enum bnxnvm_pkglog_field_index { | |
| - BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0, | |
| - BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1, | |
| - BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2, | |
| - BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3, | |
| - BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4, | |
| - BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5, | |
| - BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6, | |
| -}; | |
| +enum blogic_action { | |
| + BLOGIC_OUTBOX_FREE = 0, | |
| + BLOGIC_MBOX_START = 1, | |
| + BLOGIC_MBOX_ABORT = 2, | |
| +} __attribute__((mode(byte))); | |
| -enum bnxt_dl_param_id { | |
| - BNXT_DEVLINK_PARAM_ID_BASE = 16, | |
| - BNXT_DEVLINK_PARAM_ID_GRE_VER_CHECK = 17, | |
| -}; | |
| +enum blogic_adapter_bus_type { | |
| + BLOGIC_UNKNOWN_BUS = 0, | |
| + BLOGIC_ISA_BUS = 1, | |
| + BLOGIC_EISA_BUS = 2, | |
| + BLOGIC_PCI_BUS = 3, | |
| + BLOGIC_VESA_BUS = 4, | |
| + BLOGIC_MCA_BUS = 5, | |
| +} __attribute__((mode(byte))); | |
| -enum bnxt_dl_version_type { | |
| - BNXT_VERSION_FIXED = 0, | |
| - BNXT_VERSION_RUNNING = 1, | |
| - BNXT_VERSION_STORED = 2, | |
| -}; | |
| +enum blogic_adapter_status { | |
| + BLOGIC_CMD_CMPLT_NORMAL = 0, | |
| + BLOGIC_LINK_CMD_CMPLT = 10, | |
| + BLOGIC_LINK_CMD_CMPLT_FLAG = 11, | |
| + BLOGIC_DATA_UNDERRUN = 12, | |
| + BLOGIC_SELECT_TIMEOUT = 17, | |
| + BLOGIC_DATA_OVERRUN = 18, | |
| + BLOGIC_NOEXPECT_BUSFREE = 19, | |
| + BLOGIC_INVALID_BUSPHASE = 20, | |
| + BLOGIC_INVALID_OUTBOX_CODE = 21, | |
| + BLOGIC_INVALID_CMD_CODE = 22, | |
| + BLOGIC_LINKCCB_BADLUN = 23, | |
| + BLOGIC_BAD_CMD_PARAM = 26, | |
| + BLOGIC_AUTOREQSENSE_FAIL = 27, | |
| + BLOGIC_TAGQUEUE_REJECT = 28, | |
| + BLOGIC_BAD_MSG_RCVD = 29, | |
| + BLOGIC_HW_FAIL = 32, | |
| + BLOGIC_NORESPONSE_TO_ATN = 33, | |
| + BLOGIC_HW_RESET = 34, | |
| + BLOGIC_RST_FROM_OTHERDEV = 35, | |
| + BLOGIC_BAD_RECONNECT = 36, | |
| + BLOGIC_HW_BDR = 37, | |
| + BLOGIC_ABRT_QUEUE = 38, | |
| + BLOGIC_ADAPTER_SW_ERROR = 39, | |
| + BLOGIC_HW_TIMEOUT = 48, | |
| + BLOGIC_PARITY_ERR = 52, | |
| +} __attribute__((mode(byte))); | |
| -enum bnxt_health_remedy { | |
| - REMEDY_DEVLINK_RECOVER = 0, | |
| - REMEDY_POWER_CYCLE_DEVICE = 1, | |
| - REMEDY_POWER_CYCLE_HOST = 2, | |
| - REMEDY_FW_UPDATE = 3, | |
| - REMEDY_HW_REPLACE = 4, | |
| -}; | |
| +enum blogic_adapter_type { | |
| + BLOGIC_MULTIMASTER = 1, | |
| + BLOGIC_FLASHPOINT = 2, | |
| +} __attribute__((mode(byte))); | |
| -enum bnxt_health_severity { | |
| - SEVERITY_NORMAL = 0, | |
| - SEVERITY_WARNING = 1, | |
| - SEVERITY_RECOVERABLE = 2, | |
| - SEVERITY_FATAL = 3, | |
| -}; | |
| +enum blogic_bios_diskgeometry { | |
| + BLOGIC_BIOS_NODISK = 0, | |
| + BLOGIC_BIOS_DISK64x32 = 1, | |
| + BLOGIC_BIOS_DISK128x32 = 2, | |
| + BLOGIC_BIOS_DISK255x63 = 3, | |
| +} __attribute__((mode(byte))); | |
| -enum bnxt_hwrm_chnl { | |
| - BNXT_HWRM_CHNL_CHIMP = 0, | |
| - BNXT_HWRM_CHNL_KONG = 1, | |
| -}; | |
| +enum blogic_ccb_opcode { | |
| + BLOGIC_INITIATOR_CCB = 0, | |
| + BLOGIC_TGT_CCB = 1, | |
| + BLOGIC_INITIATOR_CCB_SG = 2, | |
| + BLOGIC_INITIATOR_CCBB_RESIDUAL = 3, | |
| + BLOGIC_INITIATOR_CCB_SG_RESIDUAL = 4, | |
| + BLOGIC_BDR = 129, | |
| +} __attribute__((mode(byte))); | |
| -enum bnxt_hwrm_ctx_flags { | |
| - BNXT_HWRM_INTERNAL_CTX_OWNED = 1, | |
| - BNXT_HWRM_INTERNAL_RESP_DIRTY = 2, | |
| - BNXT_HWRM_CTX_SILENT = 4, | |
| - BNXT_HWRM_FULL_WAIT = 8, | |
| -}; | |
| +enum blogic_ccb_status { | |
| + BLOGIC_CCB_FREE = 0, | |
| + BLOGIC_CCB_ACTIVE = 1, | |
| + BLOGIC_CCB_COMPLETE = 2, | |
| + BLOGIC_CCB_RESET = 3, | |
| +} __attribute__((mode(byte))); | |
| -enum bnxt_hwrm_wait_state { | |
| - BNXT_HWRM_PENDING = 0, | |
| - BNXT_HWRM_DEFERRED = 1, | |
| - BNXT_HWRM_COMPLETE = 2, | |
| - BNXT_HWRM_CANCELLED = 3, | |
| -}; | |
| +enum blogic_cmplt_code { | |
| + BLOGIC_INBOX_FREE = 0, | |
| + BLOGIC_CMD_COMPLETE_GOOD = 1, | |
| + BLOGIC_CMD_ABORT_BY_HOST = 2, | |
| + BLOGIC_CMD_NOTFOUND = 3, | |
| + BLOGIC_CMD_COMPLETE_ERROR = 4, | |
| + BLOGIC_INVALID_CCB = 5, | |
| +} __attribute__((mode(byte))); | |
| -enum bnxt_link_speed_indices { | |
| - BNXT_LINK_SPEED_UNKNOWN = 0, | |
| - BNXT_LINK_SPEED_100MB_IDX = 1, | |
| - BNXT_LINK_SPEED_1GB_IDX = 2, | |
| - BNXT_LINK_SPEED_10GB_IDX = 3, | |
| - BNXT_LINK_SPEED_25GB_IDX = 4, | |
| - BNXT_LINK_SPEED_40GB_IDX = 5, | |
| - BNXT_LINK_SPEED_50GB_IDX = 6, | |
| - BNXT_LINK_SPEED_100GB_IDX = 7, | |
| - BNXT_LINK_SPEED_200GB_IDX = 8, | |
| - __BNXT_LINK_SPEED_END = 9, | |
| +enum blogic_datadir { | |
| + BLOGIC_UNCHECKED_TX = 0, | |
| + BLOGIC_DATAIN_CHECKED = 1, | |
| + BLOGIC_DATAOUT_CHECKED = 2, | |
| + BLOGIC_NOTX = 3, | |
| }; | |
| -enum bnxt_media_type { | |
| - BNXT_MEDIA_UNKNOWN = 0, | |
| - BNXT_MEDIA_TP = 1, | |
| - BNXT_MEDIA_CR = 2, | |
| - BNXT_MEDIA_SR = 3, | |
| - BNXT_MEDIA_LR_ER_FR = 4, | |
| - BNXT_MEDIA_KR = 5, | |
| - BNXT_MEDIA_KX = 6, | |
| - BNXT_MEDIA_X = 7, | |
| - __BNXT_MEDIA_END = 8, | |
| +enum blogic_isa_ioport { | |
| + BLOGIC_IO_330 = 0, | |
| + BLOGIC_IO_334 = 1, | |
| + BLOGIC_IO_230 = 2, | |
| + BLOGIC_IO_234 = 3, | |
| + BLOGIC_IO_130 = 4, | |
| + BLOGIC_IO_134 = 5, | |
| + BLOGIC_IO_DISABLE = 6, | |
| + BLOGIC_IO_DISABLE2 = 7, | |
| +} __attribute__((mode(byte))); | |
| + | |
| +enum blogic_msglevel { | |
| + BLOGIC_ANNOUNCE_LEVEL = 0, | |
| + BLOGIC_INFO_LEVEL = 1, | |
| + BLOGIC_NOTICE_LEVEL = 2, | |
| + BLOGIC_WARN_LEVEL = 3, | |
| + BLOGIC_ERR_LEVEL = 4, | |
| }; | |
| -enum bnxt_nvm_dir_type { | |
| - BNXT_NVM_SHARED_CFG = 40, | |
| - BNXT_NVM_PORT_CFG = 41, | |
| - BNXT_NVM_FUNC_CFG = 42, | |
| +enum blogic_opcode { | |
| + BLOGIC_TEST_CMP_COMPLETE = 0, | |
| + BLOGIC_INIT_MBOX = 1, | |
| + BLOGIC_EXEC_MBOX_CMD = 2, | |
| + BLOGIC_EXEC_BIOS_CMD = 3, | |
| + BLOGIC_GET_BOARD_ID = 4, | |
| + BLOGIC_ENABLE_OUTBOX_AVAIL_INT = 5, | |
| + BLOGIC_SET_SELECT_TIMEOUT = 6, | |
| + BLOGIC_SET_PREEMPT_TIME = 7, | |
| + BLOGIC_SET_TIMEOFF_BUS = 8, | |
| + BLOGIC_SET_TXRATE = 9, | |
| + BLOGIC_INQ_DEV0TO7 = 10, | |
| + BLOGIC_INQ_CONFIG = 11, | |
| + BLOGIC_TGT_MODE = 12, | |
| + BLOGIC_INQ_SETUPINFO = 13, | |
| + BLOGIC_WRITE_LOCALRAM = 26, | |
| + BLOGIC_READ_LOCALRAM = 27, | |
| + BLOGIC_WRITE_BUSMASTER_FIFO = 28, | |
| + BLOGIC_READ_BUSMASTER_FIFO = 29, | |
| + BLOGIC_ECHO_CMDDATA = 31, | |
| + BLOGIC_ADAPTER_DIAG = 32, | |
| + BLOGIC_SET_OPTIONS = 33, | |
| + BLOGIC_INQ_DEV8TO15 = 35, | |
| + BLOGIC_INQ_DEV = 36, | |
| + BLOGIC_DISABLE_INT = 37, | |
| + BLOGIC_INIT_EXT_MBOX = 129, | |
| + BLOGIC_EXEC_SCS_CMD = 131, | |
| + BLOGIC_INQ_FWVER_D3 = 132, | |
| + BLOGIC_INQ_FWVER_LETTER = 133, | |
| + BLOGIC_INQ_PCI_INFO = 134, | |
| + BLOGIC_INQ_MODELNO = 139, | |
| + BLOGIC_INQ_SYNC_PERIOD = 140, | |
| + BLOGIC_INQ_EXTSETUP = 141, | |
| + BLOGIC_STRICT_RR = 143, | |
| + BLOGIC_STORE_LOCALRAM = 144, | |
| + BLOGIC_FETCH_LOCALRAM = 145, | |
| + BLOGIC_STORE_TO_EEPROM = 146, | |
| + BLOGIC_LOAD_AUTOSCSICODE = 148, | |
| + BLOGIC_MOD_IOADDR = 149, | |
| + BLOGIC_SETCCB_FMT = 150, | |
| + BLOGIC_WRITE_INQBUF = 154, | |
| + BLOGIC_READ_INQBUF = 155, | |
| + BLOGIC_FLASH_LOAD = 167, | |
| + BLOGIC_READ_SCAMDATA = 168, | |
| + BLOGIC_WRITE_SCAMDATA = 169, | |
| }; | |
| -enum bnxt_nvm_directory_type { | |
| - BNX_DIR_TYPE_UNUSED = 0, | |
| - BNX_DIR_TYPE_PKG_LOG = 1, | |
| - BNX_DIR_TYPE_UPDATE = 2, | |
| - BNX_DIR_TYPE_CHIMP_PATCH = 3, | |
| - BNX_DIR_TYPE_BOOTCODE = 4, | |
| - BNX_DIR_TYPE_VPD = 5, | |
| - BNX_DIR_TYPE_EXP_ROM_MBA = 6, | |
| - BNX_DIR_TYPE_AVS = 7, | |
| - BNX_DIR_TYPE_PCIE = 8, | |
| - BNX_DIR_TYPE_PORT_MACRO = 9, | |
| - BNX_DIR_TYPE_APE_FW = 10, | |
| - BNX_DIR_TYPE_APE_PATCH = 11, | |
| - BNX_DIR_TYPE_KONG_FW = 12, | |
| - BNX_DIR_TYPE_KONG_PATCH = 13, | |
| - BNX_DIR_TYPE_BONO_FW = 14, | |
| - BNX_DIR_TYPE_BONO_PATCH = 15, | |
| - BNX_DIR_TYPE_TANG_FW = 16, | |
| - BNX_DIR_TYPE_TANG_PATCH = 17, | |
| - BNX_DIR_TYPE_BOOTCODE_2 = 18, | |
| - BNX_DIR_TYPE_CCM = 19, | |
| - BNX_DIR_TYPE_PCI_CFG = 20, | |
| - BNX_DIR_TYPE_TSCF_UCODE = 21, | |
| - BNX_DIR_TYPE_ISCSI_BOOT = 22, | |
| - BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24, | |
| - BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25, | |
| - BNX_DIR_TYPE_ISCSI_BOOT_CFG6 = 26, | |
| - BNX_DIR_TYPE_EXT_PHY = 27, | |
| - BNX_DIR_TYPE_SHARED_CFG = 40, | |
| - BNX_DIR_TYPE_PORT_CFG = 41, | |
| - BNX_DIR_TYPE_FUNC_CFG = 42, | |
| - BNX_DIR_TYPE_MGMT_CFG = 48, | |
| - BNX_DIR_TYPE_MGMT_DATA = 49, | |
| - BNX_DIR_TYPE_MGMT_WEB_DATA = 50, | |
| - BNX_DIR_TYPE_MGMT_WEB_META = 51, | |
| - BNX_DIR_TYPE_MGMT_EVENT_LOG = 52, | |
| - BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53, | |
| +enum blogic_queuetag { | |
| + BLOGIC_SIMPLETAG = 0, | |
| + BLOGIC_HEADTAG = 1, | |
| + BLOGIC_ORDEREDTAG = 2, | |
| + BLOGIC_RSVDTAG = 3, | |
| }; | |
| +enum blogic_rr_req { | |
| + BLOGIC_AGGRESSIVE_RR = 0, | |
| + BLOGIC_STRICT_RR_MODE = 1, | |
| +} __attribute__((mode(byte))); | |
| + | |
| +enum blogic_setccb_fmt { | |
| + BLOGIC_LEGACY_LUN_CCB = 0, | |
| + BLOGIC_EXT_LUN_CCB = 1, | |
| +} __attribute__((mode(byte))); | |
| + | |
| +enum blogic_tgt_status { | |
| + BLOGIC_OP_GOOD = 0, | |
| + BLOGIC_CHECKCONDITION = 2, | |
| + BLOGIC_DEVBUSY = 8, | |
| +} __attribute__((mode(byte))); | |
| + | |
| enum board_ids { | |
| board_ahci = 0, | |
| - board_ahci_ign_iferr = 1, | |
| - board_ahci_low_power = 2, | |
| + board_ahci_43bit_dma = 1, | |
| + board_ahci_ign_iferr = 2, | |
| board_ahci_no_debounce_delay = 3, | |
| - board_ahci_nomsi = 4, | |
| - board_ahci_noncq = 5, | |
| - board_ahci_nosntf = 6, | |
| - board_ahci_yes_fbs = 7, | |
| - board_ahci_al = 8, | |
| - board_ahci_avn = 9, | |
| - board_ahci_mcp65 = 10, | |
| - board_ahci_mcp77 = 11, | |
| - board_ahci_mcp89 = 12, | |
| - board_ahci_mv = 13, | |
| - board_ahci_sb600 = 14, | |
| - board_ahci_sb700 = 15, | |
| - board_ahci_vt8251 = 16, | |
| - board_ahci_pcs7 = 17, | |
| - board_ahci_mcp_linux = 10, | |
| - board_ahci_mcp67 = 10, | |
| - board_ahci_mcp73 = 10, | |
| - board_ahci_mcp79 = 11, | |
| -}; | |
| - | |
| -enum board_idx { | |
| - BCM57301 = 0, | |
| - BCM57302 = 1, | |
| - BCM57304 = 2, | |
| - BCM57417_NPAR = 3, | |
| - BCM58700 = 4, | |
| - BCM57311 = 5, | |
| - BCM57312 = 6, | |
| - BCM57402 = 7, | |
| - BCM57404 = 8, | |
| - BCM57406 = 9, | |
| - BCM57402_NPAR = 10, | |
| - BCM57407 = 11, | |
| - BCM57412 = 12, | |
| - BCM57414 = 13, | |
| - BCM57416 = 14, | |
| - BCM57417 = 15, | |
| - BCM57412_NPAR = 16, | |
| - BCM57314 = 17, | |
| - BCM57417_SFP = 18, | |
| - BCM57416_SFP = 19, | |
| - BCM57404_NPAR = 20, | |
| - BCM57406_NPAR = 21, | |
| - BCM57407_SFP = 22, | |
| - BCM57407_NPAR = 23, | |
| - BCM57414_NPAR = 24, | |
| - BCM57416_NPAR = 25, | |
| - BCM57452 = 26, | |
| - BCM57454 = 27, | |
| - BCM5745x_NPAR = 28, | |
| - BCM57508 = 29, | |
| - BCM57504 = 30, | |
| - BCM57502 = 31, | |
| - BCM57508_NPAR = 32, | |
| - BCM57504_NPAR = 33, | |
| - BCM57502_NPAR = 34, | |
| - BCM58802 = 35, | |
| - BCM58804 = 36, | |
| - BCM58808 = 37, | |
| - NETXTREME_E_VF = 38, | |
| - NETXTREME_C_VF = 39, | |
| - NETXTREME_S_VF = 40, | |
| - NETXTREME_C_VF_HV = 41, | |
| - NETXTREME_E_VF_HV = 42, | |
| - NETXTREME_E_P5_VF = 43, | |
| - NETXTREME_E_P5_VF_HV = 44, | |
| + board_ahci_no_msi = 4, | |
| + board_ahci_pcs_quirk = 5, | |
| + board_ahci_pcs_quirk_no_devslp = 6, | |
| + board_ahci_pcs_quirk_no_sntf = 7, | |
| + board_ahci_yes_fbs = 8, | |
| + board_ahci_al = 9, | |
| + board_ahci_avn = 10, | |
| + board_ahci_mcp65 = 11, | |
| + board_ahci_mcp77 = 12, | |
| + board_ahci_mcp89 = 13, | |
| + board_ahci_mv = 14, | |
| + board_ahci_sb600 = 15, | |
| + board_ahci_sb700 = 16, | |
| + board_ahci_vt8251 = 17, | |
| + board_ahci_mcp_linux = 11, | |
| + board_ahci_mcp67 = 11, | |
| + board_ahci_mcp73 = 11, | |
| + board_ahci_mcp79 = 12, | |
| }; | |
| enum bp_type_idx { | |
| @@ -11904,6 +13146,10 @@ | |
| BPF_WRITE = 2, | |
| }; | |
| +enum bpf_addr_space_cast { | |
| + BPF_ADDR_SPACE_CAST = 1, | |
| +}; | |
| + | |
| enum bpf_adj_room_mode { | |
| BPF_ADJ_ROOM_NET = 0, | |
| BPF_ADJ_ROOM_MAC = 1, | |
| @@ -11915,38 +13161,44 @@ | |
| ARG_PTR_TO_MAP_KEY = 2, | |
| ARG_PTR_TO_MAP_VALUE = 3, | |
| ARG_PTR_TO_MEM = 4, | |
| - ARG_CONST_SIZE = 5, | |
| - ARG_CONST_SIZE_OR_ZERO = 6, | |
| - ARG_PTR_TO_CTX = 7, | |
| - ARG_ANYTHING = 8, | |
| - ARG_PTR_TO_SPIN_LOCK = 9, | |
| - ARG_PTR_TO_SOCK_COMMON = 10, | |
| - ARG_PTR_TO_INT = 11, | |
| - ARG_PTR_TO_LONG = 12, | |
| - ARG_PTR_TO_SOCKET = 13, | |
| - ARG_PTR_TO_BTF_ID = 14, | |
| - ARG_PTR_TO_RINGBUF_MEM = 15, | |
| - ARG_CONST_ALLOC_SIZE_OR_ZERO = 16, | |
| - ARG_PTR_TO_BTF_ID_SOCK_COMMON = 17, | |
| - ARG_PTR_TO_PERCPU_BTF_ID = 18, | |
| - ARG_PTR_TO_FUNC = 19, | |
| - ARG_PTR_TO_STACK = 20, | |
| - ARG_PTR_TO_CONST_STR = 21, | |
| - ARG_PTR_TO_TIMER = 22, | |
| - ARG_PTR_TO_KPTR = 23, | |
| - ARG_PTR_TO_DYNPTR = 24, | |
| - __BPF_ARG_TYPE_MAX = 25, | |
| + ARG_PTR_TO_ARENA = 5, | |
| + ARG_CONST_SIZE = 6, | |
| + ARG_CONST_SIZE_OR_ZERO = 7, | |
| + ARG_PTR_TO_CTX = 8, | |
| + ARG_ANYTHING = 9, | |
| + ARG_PTR_TO_SPIN_LOCK = 10, | |
| + ARG_PTR_TO_SOCK_COMMON = 11, | |
| + ARG_PTR_TO_INT = 12, | |
| + ARG_PTR_TO_LONG = 13, | |
| + ARG_PTR_TO_SOCKET = 14, | |
| + ARG_PTR_TO_BTF_ID = 15, | |
| + ARG_PTR_TO_RINGBUF_MEM = 16, | |
| + ARG_CONST_ALLOC_SIZE_OR_ZERO = 17, | |
| + ARG_PTR_TO_BTF_ID_SOCK_COMMON = 18, | |
| + ARG_PTR_TO_PERCPU_BTF_ID = 19, | |
| + ARG_PTR_TO_FUNC = 20, | |
| + ARG_PTR_TO_STACK = 21, | |
| + ARG_PTR_TO_CONST_STR = 22, | |
| + ARG_PTR_TO_TIMER = 23, | |
| + ARG_PTR_TO_KPTR = 24, | |
| + ARG_PTR_TO_DYNPTR = 25, | |
| + __BPF_ARG_TYPE_MAX = 26, | |
| ARG_PTR_TO_MAP_VALUE_OR_NULL = 259, | |
| ARG_PTR_TO_MEM_OR_NULL = 260, | |
| - ARG_PTR_TO_CTX_OR_NULL = 263, | |
| - ARG_PTR_TO_SOCKET_OR_NULL = 269, | |
| - ARG_PTR_TO_STACK_OR_NULL = 276, | |
| - ARG_PTR_TO_BTF_ID_OR_NULL = 270, | |
| + ARG_PTR_TO_CTX_OR_NULL = 264, | |
| + ARG_PTR_TO_SOCKET_OR_NULL = 270, | |
| + ARG_PTR_TO_STACK_OR_NULL = 277, | |
| + ARG_PTR_TO_BTF_ID_OR_NULL = 271, | |
| ARG_PTR_TO_UNINIT_MEM = 32772, | |
| ARG_PTR_TO_FIXED_SIZE_MEM = 262148, | |
| __BPF_ARG_TYPE_LIMIT = 33554431, | |
| }; | |
| +enum bpf_async_type { | |
| + BPF_ASYNC_TYPE_TIMER = 0, | |
| + BPF_ASYNC_TYPE_WQ = 1, | |
| +}; | |
| + | |
| enum bpf_attach_type { | |
| BPF_CGROUP_INET_INGRESS = 0, | |
| BPF_CGROUP_INET_EGRESS = 1, | |
| @@ -12004,7 +13256,8 @@ | |
| BPF_CGROUP_UNIX_GETSOCKNAME = 53, | |
| BPF_NETKIT_PRIMARY = 54, | |
| BPF_NETKIT_PEER = 55, | |
| - __MAX_BPF_ATTACH_TYPE = 56, | |
| + BPF_TRACE_KPROBE_SESSION = 56, | |
| + __MAX_BPF_ATTACH_TYPE = 57, | |
| }; | |
| enum bpf_audit { | |
| @@ -12013,6 +13266,17 @@ | |
| BPF_AUDIT_MAX = 2, | |
| }; | |
| +enum bpf_cap_tlv_type { | |
| + NFP_BPF_CAP_TYPE_FUNC = 1, | |
| + NFP_BPF_CAP_TYPE_ADJUST_HEAD = 2, | |
| + NFP_BPF_CAP_TYPE_MAPS = 3, | |
| + NFP_BPF_CAP_TYPE_RANDOM = 4, | |
| + NFP_BPF_CAP_TYPE_QUEUE_SELECT = 5, | |
| + NFP_BPF_CAP_TYPE_ADJUST_TAIL = 6, | |
| + NFP_BPF_CAP_TYPE_ABI_VERSION = 7, | |
| + NFP_BPF_CAP_TYPE_CMSG_MULTI_ENT = 8, | |
| +}; | |
| + | |
| enum bpf_cgroup_iter_order { | |
| BPF_CGROUP_ITER_ORDER_UNSPEC = 0, | |
| BPF_CGROUP_ITER_SELF_ONLY = 1, | |
| @@ -12079,6 +13343,10 @@ | |
| __MAX_BPF_CMD = 37, | |
| }; | |
| +enum bpf_cond_pseudo_jmp { | |
| + BPF_MAY_GOTO = 0, | |
| +}; | |
| + | |
| enum bpf_core_relo_kind { | |
| BPF_CORE_FIELD_BYTE_OFFSET = 0, | |
| BPF_CORE_FIELD_BYTE_SIZE = 1, | |
| @@ -12103,6 +13371,11 @@ | |
| BPF_DYNPTR_TYPE_XDP = 4, | |
| }; | |
| +enum bpf_fou_encap_type { | |
| + FOU_BPF_ENCAP_FOU = 0, | |
| + FOU_BPF_ENCAP_GUE = 1, | |
| +}; | |
| + | |
| enum bpf_func_id { | |
| BPF_FUNC_unspec = 0, | |
| BPF_FUNC_map_lookup_elem = 1, | |
| @@ -12359,7 +13632,8 @@ | |
| BPF_LINK_TYPE_TCX = 11, | |
| BPF_LINK_TYPE_UPROBE_MULTI = 12, | |
| BPF_LINK_TYPE_NETKIT = 13, | |
| - __MAX_BPF_LINK_TYPE = 14, | |
| + BPF_LINK_TYPE_SOCKMAP = 14, | |
| + __MAX_BPF_LINK_TYPE = 15, | |
| }; | |
| enum bpf_lru_list_type { | |
| @@ -12412,7 +13686,8 @@ | |
| BPF_MAP_TYPE_BLOOM_FILTER = 30, | |
| BPF_MAP_TYPE_USER_RINGBUF = 31, | |
| BPF_MAP_TYPE_CGRP_STORAGE = 32, | |
| - __MAX_BPF_MAP_TYPE = 33, | |
| + BPF_MAP_TYPE_ARENA = 33, | |
| + __MAX_BPF_MAP_TYPE = 34, | |
| }; | |
| enum bpf_netdev_command { | |
| @@ -12498,10 +13773,11 @@ | |
| PTR_TO_XDP_SOCK = 15, | |
| PTR_TO_BTF_ID = 16, | |
| PTR_TO_MEM = 17, | |
| - PTR_TO_BUF = 18, | |
| - PTR_TO_FUNC = 19, | |
| - CONST_PTR_TO_DYNPTR = 20, | |
| - __BPF_REG_TYPE_MAX = 21, | |
| + PTR_TO_ARENA = 18, | |
| + PTR_TO_BUF = 19, | |
| + PTR_TO_FUNC = 20, | |
| + CONST_PTR_TO_DYNPTR = 21, | |
| + __BPF_REG_TYPE_MAX = 22, | |
| PTR_TO_MAP_VALUE_OR_NULL = 260, | |
| PTR_TO_SOCKET_OR_NULL = 267, | |
| PTR_TO_SOCK_COMMON_OR_NULL = 268, | |
| @@ -12636,11 +13912,58 @@ | |
| __MAX_XDP_MODE = 3, | |
| }; | |
| +enum br_boolopt_id { | |
| + BR_BOOLOPT_NO_LL_LEARN = 0, | |
| + BR_BOOLOPT_MCAST_VLAN_SNOOPING = 1, | |
| + BR_BOOLOPT_MST_ENABLE = 2, | |
| + BR_BOOLOPT_MAX = 3, | |
| +}; | |
| + | |
| +enum br_ctx_signal_state { | |
| + BR_CSS_NONE = 2, | |
| +}; | |
| + | |
| +enum br_ev_pip { | |
| + BR_EV_PIP_UNCOND = 0, | |
| + BR_EV_PIP_COND = 1, | |
| +}; | |
| + | |
| +enum br_mask { | |
| + BR_BEQ = 0, | |
| + BR_BNE = 1, | |
| + BR_BMI = 2, | |
| + BR_BHS = 4, | |
| + BR_BCC = 5, | |
| + BR_BLO = 5, | |
| + BR_BGE = 8, | |
| + BR_BLT = 9, | |
| + BR_UNC = 24, | |
| +}; | |
| + | |
| +enum br_pkt_type { | |
| + BR_PKT_UNICAST = 0, | |
| + BR_PKT_MULTICAST = 1, | |
| + BR_PKT_BROADCAST = 2, | |
| +}; | |
| + | |
| +enum bss_compare_mode { | |
| + BSS_CMP_REGULAR = 0, | |
| + BSS_CMP_HIDE_ZLEN = 1, | |
| + BSS_CMP_HIDE_NUL = 2, | |
| +}; | |
| + | |
| +enum bss_param_flags { | |
| + BSS_PARAM_FLAGS_CTS_PROT = 1, | |
| + BSS_PARAM_FLAGS_SHORT_PREAMBLE = 2, | |
| + BSS_PARAM_FLAGS_SHORT_SLOT_TIME = 4, | |
| +}; | |
| + | |
| enum btf_arg_tag { | |
| ARG_TAG_CTX = 1, | |
| ARG_TAG_NONNULL = 2, | |
| ARG_TAG_TRUSTED = 4, | |
| ARG_TAG_NULLABLE = 8, | |
| + ARG_TAG_ARENA = 16, | |
| }; | |
| enum btf_field_type { | |
| @@ -12657,6 +13980,7 @@ | |
| BPF_GRAPH_NODE = 320, | |
| BPF_GRAPH_ROOT = 160, | |
| BPF_REFCOUNT = 512, | |
| + BPF_WORKQUEUE = 1024, | |
| }; | |
| enum btf_func_linkage { | |
| @@ -12679,7 +14003,8 @@ | |
| BTF_KFUNC_HOOK_SOCKET_FILTER = 10, | |
| BTF_KFUNC_HOOK_LWT = 11, | |
| BTF_KFUNC_HOOK_NETFILTER = 12, | |
| - BTF_KFUNC_HOOK_MAX = 13, | |
| + BTF_KFUNC_HOOK_KPROBE = 13, | |
| + BTF_KFUNC_HOOK_MAX = 14, | |
| }; | |
| enum btrfs_block_group_flags { | |
| @@ -12692,6 +14017,7 @@ | |
| BLOCK_GROUP_FLAG_ZONED_DATA_RELOC = 6, | |
| BLOCK_GROUP_FLAG_NEEDS_FREE_SPACE = 7, | |
| BLOCK_GROUP_FLAG_SEQUENTIAL_ZONE = 8, | |
| + BLOCK_GROUP_FLAG_NEW = 9, | |
| }; | |
| enum btrfs_block_group_size_class { | |
| @@ -12747,6 +14073,13 @@ | |
| BTRFS_DELAYED_DELETION_ITEM = 1, | |
| }; | |
| +enum btrfs_delayed_ref_action { | |
| + BTRFS_ADD_DELAYED_REF = 1, | |
| + BTRFS_DROP_DELAYED_REF = 2, | |
| + BTRFS_ADD_DELAYED_EXTENT = 3, | |
| + BTRFS_UPDATE_DELAYED_HEAD = 4, | |
| +} __attribute__((mode(byte))); | |
| + | |
| enum btrfs_delayed_ref_flags { | |
| BTRFS_DELAYED_REFS_FLUSHING = 0, | |
| }; | |
| @@ -12854,6 +14187,13 @@ | |
| BTRFS_NESTING_MAX = 8, | |
| }; | |
| +enum btrfs_lockdep_trans_states { | |
| + BTRFS_LOCKDEP_TRANS_COMMIT_PREP = 0, | |
| + BTRFS_LOCKDEP_TRANS_UNBLOCKED = 1, | |
| + BTRFS_LOCKDEP_TRANS_SUPER_COMMITTED = 2, | |
| + BTRFS_LOCKDEP_TRANS_COMPLETED = 3, | |
| +}; | |
| + | |
| enum btrfs_loop_type { | |
| LOOP_CACHING_NOWAIT = 0, | |
| LOOP_CACHING_WAIT = 1, | |
| @@ -12866,8 +14206,7 @@ | |
| enum btrfs_map_op { | |
| BTRFS_MAP_READ = 0, | |
| BTRFS_MAP_WRITE = 1, | |
| - BTRFS_MAP_DISCARD = 2, | |
| - BTRFS_MAP_GET_READ_MIRRORS = 3, | |
| + BTRFS_MAP_GET_READ_MIRRORS = 2, | |
| }; | |
| enum btrfs_mod_log_op { | |
| @@ -12910,7 +14249,6 @@ | |
| BTRFS_RBIO_WRITE = 0, | |
| BTRFS_RBIO_READ_REBUILD = 1, | |
| BTRFS_RBIO_PARITY_SCRUB = 2, | |
| - BTRFS_RBIO_REBUILD_MISSING = 3, | |
| }; | |
| enum btrfs_read_policy { | |
| @@ -12923,7 +14261,7 @@ | |
| BTRFS_REF_DATA = 1, | |
| BTRFS_REF_METADATA = 2, | |
| BTRFS_REF_LAST = 3, | |
| -}; | |
| +} __attribute__((mode(byte))); | |
| enum btrfs_reserve_flush_enum { | |
| BTRFS_RESERVE_NO_FLUSH = 0, | |
| @@ -12988,12 +14326,27 @@ | |
| enum btrfs_trans_state { | |
| TRANS_STATE_RUNNING = 0, | |
| - TRANS_STATE_COMMIT_START = 1, | |
| - TRANS_STATE_COMMIT_DOING = 2, | |
| - TRANS_STATE_UNBLOCKED = 3, | |
| - TRANS_STATE_SUPER_COMMITTED = 4, | |
| - TRANS_STATE_COMPLETED = 5, | |
| - TRANS_STATE_MAX = 6, | |
| + TRANS_STATE_COMMIT_PREP = 1, | |
| + TRANS_STATE_COMMIT_START = 2, | |
| + TRANS_STATE_COMMIT_DOING = 3, | |
| + TRANS_STATE_UNBLOCKED = 4, | |
| + TRANS_STATE_SUPER_COMMITTED = 5, | |
| + TRANS_STATE_COMPLETED = 6, | |
| + TRANS_STATE_MAX = 7, | |
| +}; | |
| + | |
| +enum btrfs_tree_block_status { | |
| + BTRFS_TREE_BLOCK_CLEAN = 0, | |
| + BTRFS_TREE_BLOCK_INVALID_NRITEMS = 1, | |
| + BTRFS_TREE_BLOCK_INVALID_PARENT_KEY = 2, | |
| + BTRFS_TREE_BLOCK_BAD_KEY_ORDER = 3, | |
| + BTRFS_TREE_BLOCK_INVALID_LEVEL = 4, | |
| + BTRFS_TREE_BLOCK_INVALID_FREE_SPACE = 5, | |
| + BTRFS_TREE_BLOCK_INVALID_OFFSETS = 6, | |
| + BTRFS_TREE_BLOCK_INVALID_BLOCKPTR = 7, | |
| + BTRFS_TREE_BLOCK_INVALID_ITEM = 8, | |
| + BTRFS_TREE_BLOCK_INVALID_OWNER = 9, | |
| + BTRFS_TREE_BLOCK_WRITTEN_NOT_SET = 10, | |
| }; | |
| enum btrfs_trim_state { | |
| @@ -13019,6 +14372,11 @@ | |
| BUS_NOTIFY_DRIVER_NOT_BOUND = 7, | |
| }; | |
| +typedef enum { | |
| + BUS_SPACE_MEMIO = 0, | |
| + BUS_SPACE_PIO = 1, | |
| +} bus_space_tag_t; | |
| + | |
| enum cable_info_err { | |
| CABLE_INF_INV_PORT = 1, | |
| CABLE_INF_OP_NOSUP = 2, | |
| @@ -13031,6 +14389,13 @@ | |
| CABLE_INF_I2C_BUSY = 9, | |
| }; | |
| +enum cache_tag_type { | |
| + CACHE_TAG_IOTLB = 0, | |
| + CACHE_TAG_DEVTLB = 1, | |
| + CACHE_TAG_NESTING_IOTLB = 2, | |
| + CACHE_TAG_NESTING_DEVTLB = 3, | |
| +}; | |
| + | |
| enum cache_type { | |
| CACHE_TYPE_NOCACHE = 0, | |
| CACHE_TYPE_INST = 1, | |
| @@ -13039,6 +14404,40 @@ | |
| CACHE_TYPE_UNIFIED = 4, | |
| }; | |
| +typedef enum { | |
| + CAM_REQ_INPROG = 0, | |
| + CAM_REQ_CMP = 1, | |
| + CAM_REQ_ABORTED = 2, | |
| + CAM_UA_ABORT = 3, | |
| + CAM_REQ_CMP_ERR = 4, | |
| + CAM_BUSY = 5, | |
| + CAM_REQ_INVALID = 6, | |
| + CAM_PATH_INVALID = 7, | |
| + CAM_SEL_TIMEOUT = 8, | |
| + CAM_CMD_TIMEOUT = 9, | |
| + CAM_SCSI_STATUS_ERROR = 10, | |
| + CAM_SCSI_BUS_RESET = 11, | |
| + CAM_UNCOR_PARITY = 12, | |
| + CAM_AUTOSENSE_FAIL = 13, | |
| + CAM_NO_HBA = 14, | |
| + CAM_DATA_RUN_ERR = 15, | |
| + CAM_UNEXP_BUSFREE = 16, | |
| + CAM_SEQUENCE_FAIL = 17, | |
| + CAM_CCB_LEN_ERR = 18, | |
| + CAM_PROVIDE_FAIL = 19, | |
| + CAM_BDR_SENT = 20, | |
| + CAM_REQ_TERMIO = 21, | |
| + CAM_UNREC_HBA_ERROR = 22, | |
| + CAM_REQ_TOO_BIG = 23, | |
| + CAM_UA_TERMIO = 24, | |
| + CAM_MSG_REJECT_REC = 25, | |
| + CAM_DEV_NOT_THERE = 26, | |
| + CAM_RESRC_UNAVAIL = 27, | |
| + CAM_REQUEUE_REQ = 28, | |
| + CAM_DEV_QFRZN = 64, | |
| + CAM_STATUS_MASK = 63, | |
| +} cam_status; | |
| + | |
| enum cap_audit_type { | |
| CAP_AUDIT_STATIC_DMAR = 0, | |
| CAP_AUDIT_STATIC_IRQR = 1, | |
| @@ -13054,6 +14453,7 @@ | |
| CC_ATTR_GUEST_UNROLL_STRING_IO = 4, | |
| CC_ATTR_GUEST_SEV_SNP = 5, | |
| CC_ATTR_HOTPLUG_DISABLED = 6, | |
| + CC_ATTR_HOST_SEV_SNP = 7, | |
| }; | |
| enum cc_vendor { | |
| @@ -13075,6 +14475,68 @@ | |
| __DCB_ATTR_CEE_MAX = 9, | |
| }; | |
| +enum cfg80211_assoc_req_flags { | |
| + ASSOC_REQ_DISABLE_HT = 1, | |
| + ASSOC_REQ_DISABLE_VHT = 2, | |
| + ASSOC_REQ_USE_RRM = 4, | |
| + CONNECT_REQ_EXTERNAL_AUTH_SUPPORT = 8, | |
| + ASSOC_REQ_DISABLE_HE = 16, | |
| + ASSOC_REQ_DISABLE_EHT = 32, | |
| + CONNECT_REQ_MLO_SUPPORT = 64, | |
| + ASSOC_REQ_SPP_AMSDU = 128, | |
| +}; | |
| + | |
| +enum cfg80211_bss_frame_type { | |
| + CFG80211_BSS_FTYPE_UNKNOWN = 0, | |
| + CFG80211_BSS_FTYPE_BEACON = 1, | |
| + CFG80211_BSS_FTYPE_PRESP = 2, | |
| + CFG80211_BSS_FTYPE_S1G_BEACON = 3, | |
| +}; | |
| + | |
| +enum cfg80211_connect_params_changed { | |
| + UPDATE_ASSOC_IES = 1, | |
| + UPDATE_FILS_ERP_INFO = 2, | |
| + UPDATE_AUTH_TYPE = 4, | |
| +}; | |
| + | |
| +enum cfg80211_event_type { | |
| + EVENT_CONNECT_RESULT = 0, | |
| + EVENT_ROAMED = 1, | |
| + EVENT_DISCONNECTED = 2, | |
| + EVENT_IBSS_JOINED = 3, | |
| + EVENT_STOPPED = 4, | |
| + EVENT_PORT_AUTHORIZED = 5, | |
| +}; | |
| + | |
| +enum cfg80211_nan_conf_changes { | |
| + CFG80211_NAN_CONF_CHANGED_PREF = 1, | |
| + CFG80211_NAN_CONF_CHANGED_BANDS = 2, | |
| +}; | |
| + | |
| +enum cfg80211_rnr_iter_ret { | |
| + RNR_ITER_CONTINUE = 0, | |
| + RNR_ITER_BREAK = 1, | |
| + RNR_ITER_ERROR = 2, | |
| +}; | |
| + | |
| +enum cfg80211_signal_type { | |
| + CFG80211_SIGNAL_TYPE_NONE = 0, | |
| + CFG80211_SIGNAL_TYPE_MBM = 1, | |
| + CFG80211_SIGNAL_TYPE_UNSPEC = 2, | |
| +}; | |
| + | |
| +enum cfg80211_station_type { | |
| + CFG80211_STA_AP_CLIENT = 0, | |
| + CFG80211_STA_AP_CLIENT_UNASSOC = 1, | |
| + CFG80211_STA_AP_MLME_CLIENT = 2, | |
| + CFG80211_STA_AP_STA = 3, | |
| + CFG80211_STA_IBSS = 4, | |
| + CFG80211_STA_TDLS_PEER_SETUP = 5, | |
| + CFG80211_STA_TDLS_PEER_ACTIVE = 6, | |
| + CFG80211_STA_MESH_PEER_KERNEL = 7, | |
| + CFG80211_STA_MESH_PEER_USER = 8, | |
| +}; | |
| + | |
| enum cfi_mode { | |
| CFI_DEFAULT = 0, | |
| CFI_OFF = 1, | |
| @@ -13082,10 +14544,6 @@ | |
| CFI_FINEIBT = 3, | |
| }; | |
| -enum cfile_flags { | |
| - CFILE_HIDDEN = 1, | |
| -}; | |
| - | |
| enum cgroup1_param { | |
| Opt_all = 0, | |
| Opt_clone_children = 1, | |
| @@ -13163,10 +14621,8 @@ | |
| freezer_cgrp_id = 6, | |
| net_cls_cgrp_id = 7, | |
| perf_event_cgrp_id = 8, | |
| - net_prio_cgrp_id = 9, | |
| - hugetlb_cgrp_id = 10, | |
| - pids_cgrp_id = 11, | |
| - CGROUP_SUBSYS_COUNT = 12, | |
| + hugetlb_cgrp_id = 9, | |
| + CGROUP_SUBSYS_COUNT = 10, | |
| }; | |
| enum chacha_constants { | |
| @@ -13176,91 +14632,9 @@ | |
| CHACHA_CONSTANT_TE_K = 1797285236, | |
| }; | |
| -enum chips { | |
| - adm1023 = 0, | |
| - adm1032 = 1, | |
| - adt7461 = 2, | |
| - adt7461a = 3, | |
| - adt7481 = 4, | |
| - g781 = 5, | |
| - lm84 = 6, | |
| - lm90 = 7, | |
| - lm99 = 8, | |
| - max1617 = 9, | |
| - max6642 = 10, | |
| - max6646 = 11, | |
| - max6648 = 12, | |
| - max6654 = 13, | |
| - max6657 = 14, | |
| - max6659 = 15, | |
| - max6680 = 16, | |
| - max6696 = 17, | |
| - nct210 = 18, | |
| - nct72 = 19, | |
| - ne1618 = 20, | |
| - sa56004 = 21, | |
| - tmp451 = 22, | |
| - tmp461 = 23, | |
| - w83l771 = 24, | |
| -}; | |
| - | |
| -enum chips___2 { | |
| - max6581 = 0, | |
| - max6602 = 1, | |
| - max6622 = 2, | |
| - max6636 = 3, | |
| - max6689 = 4, | |
| - max6693 = 5, | |
| - max6694 = 6, | |
| - max6697 = 7, | |
| - max6698 = 8, | |
| - max6699 = 9, | |
| -}; | |
| - | |
| -enum chips___3 { | |
| - tmp421 = 0, | |
| - tmp422 = 1, | |
| - tmp423 = 2, | |
| - tmp441 = 3, | |
| - tmp442 = 4, | |
| -}; | |
| - | |
| -enum chips___4 { | |
| - tps53647 = 0, | |
| - tps53667 = 1, | |
| - tps53676 = 2, | |
| - tps53679 = 3, | |
| - tps53681 = 4, | |
| - tps53688 = 5, | |
| -}; | |
| - | |
| -enum chips___5 { | |
| - ucd9000 = 0, | |
| - ucd90120 = 1, | |
| - ucd90124 = 2, | |
| - ucd90160 = 3, | |
| - ucd90320 = 4, | |
| - ucd9090 = 5, | |
| - ucd90910 = 6, | |
| -}; | |
| - | |
| -typedef enum { | |
| - AD_CHURN_MONITOR = 0, | |
| - AD_CHURN = 1, | |
| - AD_NO_CHURN = 2, | |
| -} churn_state_t; | |
| - | |
| -enum class_map_type { | |
| - DD_CLASS_TYPE_DISJOINT_BITS = 0, | |
| - DD_CLASS_TYPE_LEVEL_NUM = 1, | |
| - DD_CLASS_TYPE_DISJOINT_NAMES = 2, | |
| - DD_CLASS_TYPE_LEVEL_NAMES = 3, | |
| -}; | |
| - | |
| -enum class_stat_type { | |
| - ZS_OBJS_ALLOCATED = 12, | |
| - ZS_OBJS_INUSE = 13, | |
| - NR_CLASS_STAT_TYPES = 14, | |
| +enum chipset_type { | |
| + NOT_SUPPORTED = 0, | |
| + SUPPORTED = 1, | |
| }; | |
| enum cleanup_prefix_rt_t { | |
| @@ -13269,6 +14643,12 @@ | |
| CLEANUP_PREFIX_RT_EXPIRE = 2, | |
| }; | |
| +enum clear_nexus_phase { | |
| + NEXUS_PHASE_PRE = 0, | |
| + NEXUS_PHASE_POST = 1, | |
| + NEXUS_PHASE_RESUME = 2, | |
| +}; | |
| + | |
| enum clear_refs_types { | |
| CLEAR_REFS_ALL = 1, | |
| CLEAR_REFS_ANON = 2, | |
| @@ -13289,7 +14669,44 @@ | |
| enum clocksource_ids { | |
| CSID_GENERIC = 0, | |
| CSID_ARM_ARCH_COUNTER = 1, | |
| - CSID_MAX = 2, | |
| + CSID_X86_TSC_EARLY = 2, | |
| + CSID_X86_TSC = 3, | |
| + CSID_X86_KVM_CLK = 4, | |
| + CSID_MAX = 5, | |
| +}; | |
| + | |
| +enum closure_state { | |
| + CLOSURE_BITS_START = 67108864, | |
| + CLOSURE_DESTRUCTOR = 67108864, | |
| + CLOSURE_WAITING = 268435456, | |
| + CLOSURE_RUNNING = 1073741824, | |
| +}; | |
| + | |
| +enum cmd_ctx_swap { | |
| + CMD_CTX_SWAP = 0, | |
| + CMD_CTX_SWAP_DEFER1 = 1, | |
| + CMD_CTX_SWAP_DEFER2 = 2, | |
| + CMD_CTX_NO_SWAP = 3, | |
| +}; | |
| + | |
| +enum cmd_mode { | |
| + CMD_MODE_40b_AB = 0, | |
| + CMD_MODE_40b_BA = 1, | |
| + CMD_MODE_32b = 4, | |
| +}; | |
| + | |
| +enum cmd_tgt_map { | |
| + CMD_TGT_READ8 = 0, | |
| + CMD_TGT_WRITE8_SWAP = 1, | |
| + CMD_TGT_WRITE32_SWAP = 2, | |
| + CMD_TGT_READ32 = 3, | |
| + CMD_TGT_READ32_LE = 4, | |
| + CMD_TGT_READ32_SWAP = 5, | |
| + CMD_TGT_READ_LE = 6, | |
| + CMD_TGT_READ_SWAP_LE = 7, | |
| + CMD_TGT_ADD = 8, | |
| + CMD_TGT_ADD_IMM = 9, | |
| + __CMD_TGT_MAP_SIZE = 10, | |
| }; | |
| typedef enum { | |
| @@ -13343,6 +14760,8 @@ | |
| CON_ANYTIME = 16, | |
| CON_BRL = 32, | |
| CON_EXTENDED = 64, | |
| + CON_SUSPENDED = 128, | |
| + CON_NBCON = 256, | |
| }; | |
| enum context { | |
| @@ -13351,26 +14770,6 @@ | |
| IN_KERNEL_RECOV = 3, | |
| }; | |
| -enum cookie_mac_state { | |
| - INVALID_MAC = 0, | |
| - VALID_MAC_BUT_NO_COOKIE = 1, | |
| - VALID_MAC_WITH_COOKIE_BUT_RATELIMITED = 2, | |
| - VALID_MAC_WITH_COOKIE = 3, | |
| -}; | |
| - | |
| -enum cookie_values { | |
| - COOKIE_SECRET_MAX_AGE = 120, | |
| - COOKIE_SECRET_LATENCY = 5, | |
| - COOKIE_NONCE_LEN = 24, | |
| - COOKIE_LEN = 16, | |
| -}; | |
| - | |
| -enum counter_values { | |
| - COUNTER_BITS_TOTAL = 8192, | |
| - COUNTER_REDUNDANT_BITS = 64, | |
| - COUNTER_WINDOW_SIZE = 8128, | |
| -}; | |
| - | |
| enum cpa_warn { | |
| CPA_CONFLICT = 0, | |
| CPA_PROTECT = 1, | |
| @@ -13419,28 +14818,13 @@ | |
| NOMINAL_FREQ = 20, | |
| }; | |
| -enum cpu_cftype_id { | |
| - CPU_CFTYPE_WEIGHT = 0, | |
| - CPU_CFTYPE_WEIGHT_NICE = 1, | |
| - CPU_CFTYPE_IDLE = 2, | |
| - CPU_CFTYPE_MAX = 3, | |
| - CPU_CFTYPE_MAX_BURST = 4, | |
| - CPU_CFTYPE_CNT = 5, | |
| -}; | |
| - | |
| enum cpu_idle_type { | |
| - CPU_IDLE = 0, | |
| - CPU_NOT_IDLE = 1, | |
| + __CPU_NOT_IDLE = 0, | |
| + CPU_IDLE = 1, | |
| CPU_NEWLY_IDLE = 2, | |
| CPU_MAX_IDLE_TYPES = 3, | |
| }; | |
| -enum cpu_mitigations { | |
| - CPU_MITIGATIONS_OFF = 0, | |
| - CPU_MITIGATIONS_AUTO = 1, | |
| - CPU_MITIGATIONS_AUTO_NOSMT = 2, | |
| -}; | |
| - | |
| enum cpu_usage_stat { | |
| CPUTIME_USER = 0, | |
| CPUTIME_NICE = 1, | |
| @@ -13452,12 +14836,8 @@ | |
| CPUTIME_STEAL = 7, | |
| CPUTIME_GUEST = 8, | |
| CPUTIME_GUEST_NICE = 9, | |
| - NR_STATS = 10, | |
| -}; | |
| - | |
| -enum cpu_util_type { | |
| - FREQUENCY_UTIL = 0, | |
| - ENERGY_UTIL = 1, | |
| + CPUTIME_FORCEIDLE = 10, | |
| + NR_STATS = 11, | |
| }; | |
| enum cpuacct_stat_index { | |
| @@ -13490,185 +14870,186 @@ | |
| CPUHP_PERF_POWER = 5, | |
| CPUHP_PERF_SUPERH = 6, | |
| CPUHP_X86_HPET_DEAD = 7, | |
| - CPUHP_X86_APB_DEAD = 8, | |
| - CPUHP_X86_MCE_DEAD = 9, | |
| - CPUHP_VIRT_NET_DEAD = 10, | |
| - CPUHP_IBMVNIC_DEAD = 11, | |
| - CPUHP_SLUB_DEAD = 12, | |
| - CPUHP_DEBUG_OBJ_DEAD = 13, | |
| - CPUHP_MM_WRITEBACK_DEAD = 14, | |
| - CPUHP_MM_DEMOTION_DEAD = 15, | |
| - CPUHP_MM_VMSTAT_DEAD = 16, | |
| - CPUHP_SOFTIRQ_DEAD = 17, | |
| - CPUHP_NET_MVNETA_DEAD = 18, | |
| - CPUHP_CPUIDLE_DEAD = 19, | |
| - CPUHP_ARM64_FPSIMD_DEAD = 20, | |
| - CPUHP_ARM_OMAP_WAKE_DEAD = 21, | |
| - CPUHP_IRQ_POLL_DEAD = 22, | |
| - CPUHP_BLOCK_SOFTIRQ_DEAD = 23, | |
| - CPUHP_BIO_DEAD = 24, | |
| - CPUHP_ACPI_CPUDRV_DEAD = 25, | |
| - CPUHP_S390_PFAULT_DEAD = 26, | |
| - CPUHP_BLK_MQ_DEAD = 27, | |
| - CPUHP_FS_BUFF_DEAD = 28, | |
| - CPUHP_PRINTK_DEAD = 29, | |
| - CPUHP_MM_MEMCQ_DEAD = 30, | |
| - CPUHP_XFS_DEAD = 31, | |
| - CPUHP_PERCPU_CNT_DEAD = 32, | |
| - CPUHP_RADIX_DEAD = 33, | |
| - CPUHP_PAGE_ALLOC = 34, | |
| - CPUHP_NET_DEV_DEAD = 35, | |
| - CPUHP_PCI_XGENE_DEAD = 36, | |
| - CPUHP_IOMMU_IOVA_DEAD = 37, | |
| - CPUHP_LUSTRE_CFS_DEAD = 38, | |
| - CPUHP_AP_ARM_CACHE_B15_RAC_DEAD = 39, | |
| - CPUHP_PADATA_DEAD = 40, | |
| - CPUHP_AP_DTPM_CPU_DEAD = 41, | |
| - CPUHP_RANDOM_PREPARE = 42, | |
| - CPUHP_WORKQUEUE_PREP = 43, | |
| - CPUHP_POWER_NUMA_PREPARE = 44, | |
| - CPUHP_HRTIMERS_PREPARE = 45, | |
| - CPUHP_PROFILE_PREPARE = 46, | |
| - CPUHP_X2APIC_PREPARE = 47, | |
| - CPUHP_SMPCFD_PREPARE = 48, | |
| - CPUHP_RELAY_PREPARE = 49, | |
| - CPUHP_SLAB_PREPARE = 50, | |
| - CPUHP_MD_RAID5_PREPARE = 51, | |
| - CPUHP_RCUTREE_PREP = 52, | |
| - CPUHP_CPUIDLE_COUPLED_PREPARE = 53, | |
| - CPUHP_POWERPC_PMAC_PREPARE = 54, | |
| - CPUHP_POWERPC_MMU_CTX_PREPARE = 55, | |
| - CPUHP_XEN_PREPARE = 56, | |
| - CPUHP_XEN_EVTCHN_PREPARE = 57, | |
| - CPUHP_ARM_SHMOBILE_SCU_PREPARE = 58, | |
| - CPUHP_SH_SH3X_PREPARE = 59, | |
| - CPUHP_NET_FLOW_PREPARE = 60, | |
| - CPUHP_TOPOLOGY_PREPARE = 61, | |
| - CPUHP_NET_IUCV_PREPARE = 62, | |
| - CPUHP_ARM_BL_PREPARE = 63, | |
| - CPUHP_TRACE_RB_PREPARE = 64, | |
| - CPUHP_MM_ZS_PREPARE = 65, | |
| - CPUHP_MM_ZSWP_POOL_PREPARE = 66, | |
| - CPUHP_KVM_PPC_BOOK3S_PREPARE = 67, | |
| - CPUHP_ZCOMP_PREPARE = 68, | |
| - CPUHP_TIMERS_PREPARE = 69, | |
| - CPUHP_MIPS_SOC_PREPARE = 70, | |
| - CPUHP_BP_PREPARE_DYN = 71, | |
| - CPUHP_BP_PREPARE_DYN_END = 91, | |
| - CPUHP_BRINGUP_CPU = 92, | |
| - CPUHP_AP_IDLE_DEAD = 93, | |
| - CPUHP_AP_OFFLINE = 94, | |
| - CPUHP_AP_CACHECTRL_STARTING = 95, | |
| - CPUHP_AP_SCHED_STARTING = 96, | |
| - CPUHP_AP_RCUTREE_DYING = 97, | |
| - CPUHP_AP_CPU_PM_STARTING = 98, | |
| - CPUHP_AP_IRQ_GIC_STARTING = 99, | |
| - CPUHP_AP_IRQ_HIP04_STARTING = 100, | |
| - CPUHP_AP_IRQ_APPLE_AIC_STARTING = 101, | |
| - CPUHP_AP_IRQ_ARMADA_XP_STARTING = 102, | |
| - CPUHP_AP_IRQ_BCM2836_STARTING = 103, | |
| - CPUHP_AP_IRQ_MIPS_GIC_STARTING = 104, | |
| - CPUHP_AP_IRQ_RISCV_STARTING = 105, | |
| - CPUHP_AP_IRQ_LOONGARCH_STARTING = 106, | |
| - CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING = 107, | |
| - CPUHP_AP_ARM_MVEBU_COHERENCY = 108, | |
| - CPUHP_AP_MICROCODE_LOADER = 109, | |
| - CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING = 110, | |
| - CPUHP_AP_PERF_X86_STARTING = 111, | |
| - CPUHP_AP_PERF_X86_AMD_IBS_STARTING = 112, | |
| - CPUHP_AP_PERF_X86_CQM_STARTING = 113, | |
| - CPUHP_AP_PERF_X86_CSTATE_STARTING = 114, | |
| - CPUHP_AP_PERF_XTENSA_STARTING = 115, | |
| - CPUHP_AP_MIPS_OP_LOONGSON3_STARTING = 116, | |
| - CPUHP_AP_ARM_VFP_STARTING = 117, | |
| - CPUHP_AP_ARM64_DEBUG_MONITORS_STARTING = 118, | |
| - CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING = 119, | |
| - CPUHP_AP_PERF_ARM_ACPI_STARTING = 120, | |
| - CPUHP_AP_PERF_ARM_STARTING = 121, | |
| - CPUHP_AP_PERF_RISCV_STARTING = 122, | |
| - CPUHP_AP_ARM_L2X0_STARTING = 123, | |
| - CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING = 124, | |
| - CPUHP_AP_ARM_ARCH_TIMER_STARTING = 125, | |
| - CPUHP_AP_ARM_GLOBAL_TIMER_STARTING = 126, | |
| - CPUHP_AP_JCORE_TIMER_STARTING = 127, | |
| - CPUHP_AP_ARM_TWD_STARTING = 128, | |
| - CPUHP_AP_QCOM_TIMER_STARTING = 129, | |
| - CPUHP_AP_TEGRA_TIMER_STARTING = 130, | |
| - CPUHP_AP_ARMADA_TIMER_STARTING = 131, | |
| - CPUHP_AP_MARCO_TIMER_STARTING = 132, | |
| - CPUHP_AP_MIPS_GIC_TIMER_STARTING = 133, | |
| - CPUHP_AP_ARC_TIMER_STARTING = 134, | |
| - CPUHP_AP_RISCV_TIMER_STARTING = 135, | |
| - CPUHP_AP_CLINT_TIMER_STARTING = 136, | |
| - CPUHP_AP_CSKY_TIMER_STARTING = 137, | |
| - CPUHP_AP_TI_GP_TIMER_STARTING = 138, | |
| - CPUHP_AP_HYPERV_TIMER_STARTING = 139, | |
| - CPUHP_AP_DUMMY_TIMER_STARTING = 140, | |
| - CPUHP_AP_ARM_XEN_STARTING = 141, | |
| - CPUHP_AP_ARM_CORESIGHT_STARTING = 142, | |
| - CPUHP_AP_ARM_CORESIGHT_CTI_STARTING = 143, | |
| - CPUHP_AP_ARM64_ISNDEP_STARTING = 144, | |
| - CPUHP_AP_SMPCFD_DYING = 145, | |
| - CPUHP_AP_X86_TBOOT_DYING = 146, | |
| - CPUHP_AP_ARM_CACHE_B15_RAC_DYING = 147, | |
| - CPUHP_AP_ONLINE = 148, | |
| - CPUHP_TEARDOWN_CPU = 149, | |
| - CPUHP_AP_ONLINE_IDLE = 150, | |
| - CPUHP_AP_HYPERV_ONLINE = 151, | |
| - CPUHP_AP_KVM_ONLINE = 152, | |
| - CPUHP_AP_SCHED_WAIT_EMPTY = 153, | |
| - CPUHP_AP_SMPBOOT_THREADS = 154, | |
| - CPUHP_AP_X86_VDSO_VMA_ONLINE = 155, | |
| - CPUHP_AP_IRQ_AFFINITY_ONLINE = 156, | |
| - CPUHP_AP_BLK_MQ_ONLINE = 157, | |
| - CPUHP_AP_ARM_MVEBU_SYNC_CLOCKS = 158, | |
| - CPUHP_AP_X86_INTEL_EPB_ONLINE = 159, | |
| - CPUHP_AP_PERF_ONLINE = 160, | |
| - CPUHP_AP_PERF_X86_ONLINE = 161, | |
| - CPUHP_AP_PERF_X86_UNCORE_ONLINE = 162, | |
| - CPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE = 163, | |
| - CPUHP_AP_PERF_X86_AMD_POWER_ONLINE = 164, | |
| - CPUHP_AP_PERF_X86_RAPL_ONLINE = 165, | |
| - CPUHP_AP_PERF_X86_CQM_ONLINE = 166, | |
| - CPUHP_AP_PERF_X86_CSTATE_ONLINE = 167, | |
| - CPUHP_AP_PERF_X86_IDXD_ONLINE = 168, | |
| - CPUHP_AP_PERF_S390_CF_ONLINE = 169, | |
| - CPUHP_AP_PERF_S390_SF_ONLINE = 170, | |
| - CPUHP_AP_PERF_ARM_CCI_ONLINE = 171, | |
| - CPUHP_AP_PERF_ARM_CCN_ONLINE = 172, | |
| - CPUHP_AP_PERF_ARM_HISI_CPA_ONLINE = 173, | |
| - CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE = 174, | |
| - CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE = 175, | |
| - CPUHP_AP_PERF_ARM_HISI_L3_ONLINE = 176, | |
| - CPUHP_AP_PERF_ARM_HISI_PA_ONLINE = 177, | |
| - CPUHP_AP_PERF_ARM_HISI_SLLC_ONLINE = 178, | |
| - CPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE = 179, | |
| - CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE = 180, | |
| - CPUHP_AP_PERF_ARM_L2X0_ONLINE = 181, | |
| - CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE = 182, | |
| - CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE = 183, | |
| - CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE = 184, | |
| - CPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE = 185, | |
| - CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE = 186, | |
| - CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE = 187, | |
| - CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE = 188, | |
| - CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE = 189, | |
| - CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE = 190, | |
| - CPUHP_AP_PERF_POWERPC_HV_24x7_ONLINE = 191, | |
| - CPUHP_AP_PERF_POWERPC_HV_GPCI_ONLINE = 192, | |
| - CPUHP_AP_PERF_CSKY_ONLINE = 193, | |
| - CPUHP_AP_WATCHDOG_ONLINE = 194, | |
| - CPUHP_AP_WORKQUEUE_ONLINE = 195, | |
| - CPUHP_AP_RANDOM_ONLINE = 196, | |
| - CPUHP_AP_RCUTREE_ONLINE = 197, | |
| - CPUHP_AP_BASE_CACHEINFO_ONLINE = 198, | |
| - CPUHP_AP_ONLINE_DYN = 199, | |
| - CPUHP_AP_ONLINE_DYN_END = 229, | |
| - CPUHP_AP_MM_DEMOTION_ONLINE = 230, | |
| - CPUHP_AP_X86_HPET_ONLINE = 231, | |
| - CPUHP_AP_X86_KVM_CLK_ONLINE = 232, | |
| - CPUHP_AP_ACTIVE = 233, | |
| - CPUHP_ONLINE = 234, | |
| + CPUHP_X86_MCE_DEAD = 8, | |
| + CPUHP_VIRT_NET_DEAD = 9, | |
| + CPUHP_IBMVNIC_DEAD = 10, | |
| + CPUHP_SLUB_DEAD = 11, | |
| + CPUHP_DEBUG_OBJ_DEAD = 12, | |
| + CPUHP_MM_WRITEBACK_DEAD = 13, | |
| + CPUHP_MM_VMSTAT_DEAD = 14, | |
| + CPUHP_SOFTIRQ_DEAD = 15, | |
| + CPUHP_NET_MVNETA_DEAD = 16, | |
| + CPUHP_CPUIDLE_DEAD = 17, | |
| + CPUHP_ARM64_FPSIMD_DEAD = 18, | |
| + CPUHP_ARM_OMAP_WAKE_DEAD = 19, | |
| + CPUHP_IRQ_POLL_DEAD = 20, | |
| + CPUHP_BLOCK_SOFTIRQ_DEAD = 21, | |
| + CPUHP_BIO_DEAD = 22, | |
| + CPUHP_ACPI_CPUDRV_DEAD = 23, | |
| + CPUHP_S390_PFAULT_DEAD = 24, | |
| + CPUHP_BLK_MQ_DEAD = 25, | |
| + CPUHP_FS_BUFF_DEAD = 26, | |
| + CPUHP_PRINTK_DEAD = 27, | |
| + CPUHP_MM_MEMCQ_DEAD = 28, | |
| + CPUHP_PERCPU_CNT_DEAD = 29, | |
| + CPUHP_RADIX_DEAD = 30, | |
| + CPUHP_PAGE_ALLOC = 31, | |
| + CPUHP_NET_DEV_DEAD = 32, | |
| + CPUHP_PCI_XGENE_DEAD = 33, | |
| + CPUHP_IOMMU_IOVA_DEAD = 34, | |
| + CPUHP_AP_ARM_CACHE_B15_RAC_DEAD = 35, | |
| + CPUHP_PADATA_DEAD = 36, | |
| + CPUHP_AP_DTPM_CPU_DEAD = 37, | |
| + CPUHP_RANDOM_PREPARE = 38, | |
| + CPUHP_WORKQUEUE_PREP = 39, | |
| + CPUHP_POWER_NUMA_PREPARE = 40, | |
| + CPUHP_HRTIMERS_PREPARE = 41, | |
| + CPUHP_PROFILE_PREPARE = 42, | |
| + CPUHP_X2APIC_PREPARE = 43, | |
| + CPUHP_SMPCFD_PREPARE = 44, | |
| + CPUHP_RELAY_PREPARE = 45, | |
| + CPUHP_MD_RAID5_PREPARE = 46, | |
| + CPUHP_RCUTREE_PREP = 47, | |
| + CPUHP_CPUIDLE_COUPLED_PREPARE = 48, | |
| + CPUHP_POWERPC_PMAC_PREPARE = 49, | |
| + CPUHP_POWERPC_MMU_CTX_PREPARE = 50, | |
| + CPUHP_XEN_PREPARE = 51, | |
| + CPUHP_XEN_EVTCHN_PREPARE = 52, | |
| + CPUHP_ARM_SHMOBILE_SCU_PREPARE = 53, | |
| + CPUHP_SH_SH3X_PREPARE = 54, | |
| + CPUHP_TOPOLOGY_PREPARE = 55, | |
| + CPUHP_NET_IUCV_PREPARE = 56, | |
| + CPUHP_ARM_BL_PREPARE = 57, | |
| + CPUHP_TRACE_RB_PREPARE = 58, | |
| + CPUHP_MM_ZS_PREPARE = 59, | |
| + CPUHP_MM_ZSWP_POOL_PREPARE = 60, | |
| + CPUHP_KVM_PPC_BOOK3S_PREPARE = 61, | |
| + CPUHP_ZCOMP_PREPARE = 62, | |
| + CPUHP_TIMERS_PREPARE = 63, | |
| + CPUHP_MIPS_SOC_PREPARE = 64, | |
| + CPUHP_BP_PREPARE_DYN = 65, | |
| + CPUHP_BP_PREPARE_DYN_END = 85, | |
| + CPUHP_BP_KICK_AP = 86, | |
| + CPUHP_BRINGUP_CPU = 87, | |
| + CPUHP_AP_IDLE_DEAD = 88, | |
| + CPUHP_AP_OFFLINE = 89, | |
| + CPUHP_AP_CACHECTRL_STARTING = 90, | |
| + CPUHP_AP_SCHED_STARTING = 91, | |
| + CPUHP_AP_RCUTREE_DYING = 92, | |
| + CPUHP_AP_CPU_PM_STARTING = 93, | |
| + CPUHP_AP_IRQ_GIC_STARTING = 94, | |
| + CPUHP_AP_IRQ_HIP04_STARTING = 95, | |
| + CPUHP_AP_IRQ_APPLE_AIC_STARTING = 96, | |
| + CPUHP_AP_IRQ_ARMADA_XP_STARTING = 97, | |
| + CPUHP_AP_IRQ_BCM2836_STARTING = 98, | |
| + CPUHP_AP_IRQ_MIPS_GIC_STARTING = 99, | |
| + CPUHP_AP_IRQ_LOONGARCH_STARTING = 100, | |
| + CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING = 101, | |
| + CPUHP_AP_IRQ_RISCV_IMSIC_STARTING = 102, | |
| + CPUHP_AP_ARM_MVEBU_COHERENCY = 103, | |
| + CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING = 104, | |
| + CPUHP_AP_PERF_X86_STARTING = 105, | |
| + CPUHP_AP_PERF_X86_AMD_IBS_STARTING = 106, | |
| + CPUHP_AP_PERF_X86_CSTATE_STARTING = 107, | |
| + CPUHP_AP_PERF_XTENSA_STARTING = 108, | |
| + CPUHP_AP_ARM_VFP_STARTING = 109, | |
| + CPUHP_AP_ARM64_DEBUG_MONITORS_STARTING = 110, | |
| + CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING = 111, | |
| + CPUHP_AP_PERF_ARM_ACPI_STARTING = 112, | |
| + CPUHP_AP_PERF_ARM_STARTING = 113, | |
| + CPUHP_AP_PERF_RISCV_STARTING = 114, | |
| + CPUHP_AP_ARM_L2X0_STARTING = 115, | |
| + CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING = 116, | |
| + CPUHP_AP_ARM_ARCH_TIMER_STARTING = 117, | |
| + CPUHP_AP_ARM_ARCH_TIMER_EVTSTRM_STARTING = 118, | |
| + CPUHP_AP_ARM_GLOBAL_TIMER_STARTING = 119, | |
| + CPUHP_AP_JCORE_TIMER_STARTING = 120, | |
| + CPUHP_AP_ARM_TWD_STARTING = 121, | |
| + CPUHP_AP_QCOM_TIMER_STARTING = 122, | |
| + CPUHP_AP_TEGRA_TIMER_STARTING = 123, | |
| + CPUHP_AP_ARMADA_TIMER_STARTING = 124, | |
| + CPUHP_AP_MIPS_GIC_TIMER_STARTING = 125, | |
| + CPUHP_AP_ARC_TIMER_STARTING = 126, | |
| + CPUHP_AP_RISCV_TIMER_STARTING = 127, | |
| + CPUHP_AP_CLINT_TIMER_STARTING = 128, | |
| + CPUHP_AP_CSKY_TIMER_STARTING = 129, | |
| + CPUHP_AP_TI_GP_TIMER_STARTING = 130, | |
| + CPUHP_AP_HYPERV_TIMER_STARTING = 131, | |
| + CPUHP_AP_DUMMY_TIMER_STARTING = 132, | |
| + CPUHP_AP_ARM_XEN_STARTING = 133, | |
| + CPUHP_AP_ARM_XEN_RUNSTATE_STARTING = 134, | |
| + CPUHP_AP_ARM_CORESIGHT_STARTING = 135, | |
| + CPUHP_AP_ARM_CORESIGHT_CTI_STARTING = 136, | |
| + CPUHP_AP_ARM64_ISNDEP_STARTING = 137, | |
| + CPUHP_AP_SMPCFD_DYING = 138, | |
| + CPUHP_AP_HRTIMERS_DYING = 139, | |
| + CPUHP_AP_TICK_DYING = 140, | |
| + CPUHP_AP_X86_TBOOT_DYING = 141, | |
| + CPUHP_AP_ARM_CACHE_B15_RAC_DYING = 142, | |
| + CPUHP_AP_ONLINE = 143, | |
| + CPUHP_TEARDOWN_CPU = 144, | |
| + CPUHP_AP_ONLINE_IDLE = 145, | |
| + CPUHP_AP_HYPERV_ONLINE = 146, | |
| + CPUHP_AP_KVM_ONLINE = 147, | |
| + CPUHP_AP_SCHED_WAIT_EMPTY = 148, | |
| + CPUHP_AP_SMPBOOT_THREADS = 149, | |
| + CPUHP_AP_IRQ_AFFINITY_ONLINE = 150, | |
| + CPUHP_AP_BLK_MQ_ONLINE = 151, | |
| + CPUHP_AP_ARM_MVEBU_SYNC_CLOCKS = 152, | |
| + CPUHP_AP_X86_INTEL_EPB_ONLINE = 153, | |
| + CPUHP_AP_PERF_ONLINE = 154, | |
| + CPUHP_AP_PERF_X86_ONLINE = 155, | |
| + CPUHP_AP_PERF_X86_UNCORE_ONLINE = 156, | |
| + CPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE = 157, | |
| + CPUHP_AP_PERF_X86_AMD_POWER_ONLINE = 158, | |
| + CPUHP_AP_PERF_X86_RAPL_ONLINE = 159, | |
| + CPUHP_AP_PERF_X86_CSTATE_ONLINE = 160, | |
| + CPUHP_AP_PERF_S390_CF_ONLINE = 161, | |
| + CPUHP_AP_PERF_S390_SF_ONLINE = 162, | |
| + CPUHP_AP_PERF_ARM_CCI_ONLINE = 163, | |
| + CPUHP_AP_PERF_ARM_CCN_ONLINE = 164, | |
| + CPUHP_AP_PERF_ARM_HISI_CPA_ONLINE = 165, | |
| + CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE = 166, | |
| + CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE = 167, | |
| + CPUHP_AP_PERF_ARM_HISI_L3_ONLINE = 168, | |
| + CPUHP_AP_PERF_ARM_HISI_PA_ONLINE = 169, | |
| + CPUHP_AP_PERF_ARM_HISI_SLLC_ONLINE = 170, | |
| + CPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE = 171, | |
| + CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE = 172, | |
| + CPUHP_AP_PERF_ARM_L2X0_ONLINE = 173, | |
| + CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE = 174, | |
| + CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE = 175, | |
| + CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE = 176, | |
| + CPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE = 177, | |
| + CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE = 178, | |
| + CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE = 179, | |
| + CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE = 180, | |
| + CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE = 181, | |
| + CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE = 182, | |
| + CPUHP_AP_PERF_POWERPC_HV_24x7_ONLINE = 183, | |
| + CPUHP_AP_PERF_POWERPC_HV_GPCI_ONLINE = 184, | |
| + CPUHP_AP_PERF_CSKY_ONLINE = 185, | |
| + CPUHP_AP_TMIGR_ONLINE = 186, | |
| + CPUHP_AP_WATCHDOG_ONLINE = 187, | |
| + CPUHP_AP_WORKQUEUE_ONLINE = 188, | |
| + CPUHP_AP_RANDOM_ONLINE = 189, | |
| + CPUHP_AP_RCUTREE_ONLINE = 190, | |
| + CPUHP_AP_BASE_CACHEINFO_ONLINE = 191, | |
| + CPUHP_AP_ONLINE_DYN = 192, | |
| + CPUHP_AP_ONLINE_DYN_END = 232, | |
| + CPUHP_AP_X86_HPET_ONLINE = 233, | |
| + CPUHP_AP_X86_KVM_CLK_ONLINE = 234, | |
| + CPUHP_AP_ACTIVE = 235, | |
| + CPUHP_ONLINE = 236, | |
| +}; | |
| + | |
| +enum cpuhp_sync_state { | |
| + SYNC_STATE_DEAD = 0, | |
| + SYNC_STATE_KICKED = 1, | |
| + SYNC_STATE_SHOULD_DIE = 2, | |
| + SYNC_STATE_ALIVE = 3, | |
| + SYNC_STATE_SHOULD_ONLINE = 4, | |
| + SYNC_STATE_ONLINE = 5, | |
| }; | |
| enum cpuid_leafs { | |
| @@ -13693,6 +15074,8 @@ | |
| CPUID_7_EDX = 18, | |
| CPUID_8000_001F_EAX = 19, | |
| CPUID_8000_0021_EAX = 20, | |
| + CPUID_LNX_5 = 21, | |
| + NR_CPUID_WORDS = 22, | |
| }; | |
| enum cpuid_regs_idx { | |
| @@ -13709,16 +15092,19 @@ | |
| FILE_EFFECTIVE_CPULIST = 3, | |
| FILE_EFFECTIVE_MEMLIST = 4, | |
| FILE_SUBPARTS_CPULIST = 5, | |
| - FILE_CPU_EXCLUSIVE = 6, | |
| - FILE_MEM_EXCLUSIVE = 7, | |
| - FILE_MEM_HARDWALL = 8, | |
| - FILE_SCHED_LOAD_BALANCE = 9, | |
| - FILE_PARTITION_ROOT = 10, | |
| - FILE_SCHED_RELAX_DOMAIN_LEVEL = 11, | |
| - FILE_MEMORY_PRESSURE_ENABLED = 12, | |
| - FILE_MEMORY_PRESSURE = 13, | |
| - FILE_SPREAD_PAGE = 14, | |
| - FILE_SPREAD_SLAB = 15, | |
| + FILE_EXCLUSIVE_CPULIST = 6, | |
| + FILE_EFFECTIVE_XCPULIST = 7, | |
| + FILE_ISOLATED_CPULIST = 8, | |
| + FILE_CPU_EXCLUSIVE = 9, | |
| + FILE_MEM_EXCLUSIVE = 10, | |
| + FILE_MEM_HARDWALL = 11, | |
| + FILE_SCHED_LOAD_BALANCE = 12, | |
| + FILE_PARTITION_ROOT = 13, | |
| + FILE_SCHED_RELAX_DOMAIN_LEVEL = 14, | |
| + FILE_MEMORY_PRESSURE_ENABLED = 15, | |
| + FILE_MEMORY_PRESSURE = 16, | |
| + FILE_SPREAD_PAGE = 17, | |
| + FILE_SPREAD_SLAB = 18, | |
| } cpuset_filetype_t; | |
| typedef enum { | |
| @@ -13775,113 +15161,58 @@ | |
| CRB_DRV_STS_COMPLETE = 1, | |
| }; | |
| -enum ctx_state { | |
| - CONTEXT_DISABLED = -1, | |
| - CONTEXT_KERNEL = 0, | |
| - CONTEXT_IDLE = 1, | |
| - CONTEXT_USER = 2, | |
| - CONTEXT_GUEST = 3, | |
| - CONTEXT_MAX = 4, | |
| -}; | |
| - | |
| -enum curve25519_lengths { | |
| - CURVE25519_KEY_SIZE = 32, | |
| -}; | |
| - | |
| -enum cxl_config_state { | |
| - CXL_CONFIG_IDLE = 0, | |
| - CXL_CONFIG_INTERLEAVE_ACTIVE = 1, | |
| - CXL_CONFIG_ACTIVE = 2, | |
| - CXL_CONFIG_RESET_PENDING = 3, | |
| - CXL_CONFIG_COMMIT = 4, | |
| -}; | |
| - | |
| -enum cxl_decoder_mode { | |
| - CXL_DECODER_NONE = 0, | |
| - CXL_DECODER_RAM = 1, | |
| - CXL_DECODER_PMEM = 2, | |
| - CXL_DECODER_MIXED = 3, | |
| - CXL_DECODER_DEAD = 4, | |
| -}; | |
| - | |
| -enum cxl_decoder_state { | |
| - CXL_DECODER_STATE_MANUAL = 0, | |
| - CXL_DECODER_STATE_AUTO = 1, | |
| -}; | |
| - | |
| -enum cxl_decoder_type { | |
| - CXL_DECODER_ACCELERATOR = 2, | |
| - CXL_DECODER_EXPANDER = 3, | |
| -}; | |
| - | |
| -enum cxl_event_int_mode { | |
| - CXL_INT_NONE = 0, | |
| - CXL_INT_MSI_MSIX = 1, | |
| - CXL_INT_FW = 2, | |
| +enum criteria { | |
| + CR_POWER2_ALIGNED = 0, | |
| + CR_GOAL_LEN_FAST = 1, | |
| + CR_BEST_AVAIL_LEN = 2, | |
| + CR_GOAL_LEN_SLOW = 3, | |
| + CR_ANY_FREE = 4, | |
| + EXT4_MB_NUM_CRS = 5, | |
| }; | |
| -enum cxl_event_log_type { | |
| - CXL_EVENT_TYPE_INFO = 0, | |
| - CXL_EVENT_TYPE_WARN = 1, | |
| - CXL_EVENT_TYPE_FAIL = 2, | |
| - CXL_EVENT_TYPE_FATAL = 3, | |
| - CXL_EVENT_TYPE_MAX = 4, | |
| +enum ct_dccp_roles { | |
| + CT_DCCP_ROLE_CLIENT = 0, | |
| + CT_DCCP_ROLE_SERVER = 1, | |
| + __CT_DCCP_ROLE_MAX = 2, | |
| }; | |
| -enum cxl_opcode { | |
| - CXL_MBOX_OP_INVALID = 0, | |
| - CXL_MBOX_OP_RAW = 0, | |
| - CXL_MBOX_OP_GET_EVENT_RECORD = 256, | |
| - CXL_MBOX_OP_CLEAR_EVENT_RECORD = 257, | |
| - CXL_MBOX_OP_GET_EVT_INT_POLICY = 258, | |
| - CXL_MBOX_OP_SET_EVT_INT_POLICY = 259, | |
| - CXL_MBOX_OP_GET_FW_INFO = 512, | |
| - CXL_MBOX_OP_ACTIVATE_FW = 514, | |
| - CXL_MBOX_OP_SET_TIMESTAMP = 769, | |
| - CXL_MBOX_OP_GET_SUPPORTED_LOGS = 1024, | |
| - CXL_MBOX_OP_GET_LOG = 1025, | |
| - CXL_MBOX_OP_IDENTIFY = 16384, | |
| - CXL_MBOX_OP_GET_PARTITION_INFO = 16640, | |
| - CXL_MBOX_OP_SET_PARTITION_INFO = 16641, | |
| - CXL_MBOX_OP_GET_LSA = 16642, | |
| - CXL_MBOX_OP_SET_LSA = 16643, | |
| - CXL_MBOX_OP_GET_HEALTH_INFO = 16896, | |
| - CXL_MBOX_OP_GET_ALERT_CONFIG = 16897, | |
| - CXL_MBOX_OP_SET_ALERT_CONFIG = 16898, | |
| - CXL_MBOX_OP_GET_SHUTDOWN_STATE = 16899, | |
| - CXL_MBOX_OP_SET_SHUTDOWN_STATE = 16900, | |
| - CXL_MBOX_OP_GET_POISON = 17152, | |
| - CXL_MBOX_OP_INJECT_POISON = 17153, | |
| - CXL_MBOX_OP_CLEAR_POISON = 17154, | |
| - CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 17155, | |
| - CXL_MBOX_OP_SCAN_MEDIA = 17156, | |
| - CXL_MBOX_OP_GET_SCAN_MEDIA = 17157, | |
| - CXL_MBOX_OP_GET_SECURITY_STATE = 17664, | |
| - CXL_MBOX_OP_SET_PASSPHRASE = 17665, | |
| - CXL_MBOX_OP_DISABLE_PASSPHRASE = 17666, | |
| - CXL_MBOX_OP_UNLOCK = 17667, | |
| - CXL_MBOX_OP_FREEZE_SECURITY = 17668, | |
| - CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 17669, | |
| - CXL_MBOX_OP_MAX = 65536, | |
| +enum ct_dccp_states { | |
| + CT_DCCP_NONE = 0, | |
| + CT_DCCP_REQUEST = 1, | |
| + CT_DCCP_RESPOND = 2, | |
| + CT_DCCP_PARTOPEN = 3, | |
| + CT_DCCP_OPEN = 4, | |
| + CT_DCCP_CLOSEREQ = 5, | |
| + CT_DCCP_CLOSING = 6, | |
| + CT_DCCP_TIMEWAIT = 7, | |
| + CT_DCCP_IGNORE = 8, | |
| + CT_DCCP_INVALID = 9, | |
| + __CT_DCCP_MAX = 10, | |
| }; | |
| -enum cxl_poison_trace_type { | |
| - CXL_POISON_TRACE_LIST = 0, | |
| - CXL_POISON_TRACE_INJECT = 1, | |
| - CXL_POISON_TRACE_CLEAR = 2, | |
| +enum cti_port_type { | |
| + CTI_PORT_TYPE_NONE = 0, | |
| + CTI_PORT_TYPE_RS232 = 1, | |
| + CTI_PORT_TYPE_RS422_485 = 2, | |
| + CTI_PORT_TYPE_RS232_422_485_HW = 3, | |
| + CTI_PORT_TYPE_RS232_422_485_SW = 4, | |
| + CTI_PORT_TYPE_RS232_422_485_4B = 5, | |
| + CTI_PORT_TYPE_RS232_422_485_2B = 6, | |
| + CTI_PORT_TYPE_MAX = 7, | |
| }; | |
| -enum cxl_rcrb { | |
| - CXL_RCRB_DOWNSTREAM = 0, | |
| - CXL_RCRB_UPSTREAM = 1, | |
| +enum ctx_state { | |
| + CONTEXT_DISABLED = -1, | |
| + CONTEXT_KERNEL = 0, | |
| + CONTEXT_IDLE = 1, | |
| + CONTEXT_USER = 2, | |
| + CONTEXT_GUEST = 3, | |
| + CONTEXT_MAX = 4, | |
| }; | |
| -enum cxl_regloc_type { | |
| - CXL_REGLOC_RBI_EMPTY = 0, | |
| - CXL_REGLOC_RBI_COMPONENT = 1, | |
| - CXL_REGLOC_RBI_VIRT = 2, | |
| - CXL_REGLOC_RBI_MEMDEV = 3, | |
| - CXL_REGLOC_RBI_TYPES = 4, | |
| +enum d_real_type { | |
| + D_REAL_DATA = 0, | |
| + D_REAL_METADATA = 1, | |
| }; | |
| enum d_walk_ret { | |
| @@ -13900,35 +15231,6 @@ | |
| DATA_FMT_UINT = 5, | |
| }; | |
| -enum dax_access_mode { | |
| - DAX_ACCESS = 0, | |
| - DAX_RECOVERY_WRITE = 1, | |
| -}; | |
| - | |
| -enum dax_device_flags { | |
| - DAXDEV_ALIVE = 0, | |
| - DAXDEV_WRITE_CACHE = 1, | |
| - DAXDEV_SYNC = 2, | |
| - DAXDEV_NOCACHE = 3, | |
| - DAXDEV_NOMC = 4, | |
| -}; | |
| - | |
| -enum dax_driver_type { | |
| - DAXDRV_KMEM_TYPE = 0, | |
| - DAXDRV_DEVICE_TYPE = 1, | |
| -}; | |
| - | |
| -enum dax_wake_mode { | |
| - WAKE_ALL = 0, | |
| - WAKE_NEXT = 1, | |
| -}; | |
| - | |
| -enum dbg_rsc_type { | |
| - MLX5_DBG_RSC_QP = 0, | |
| - MLX5_DBG_RSC_EQ = 1, | |
| - MLX5_DBG_RSC_CQ = 2, | |
| -}; | |
| - | |
| enum dcb_general_attr_values { | |
| DCB_ATTR_VALUE_UNDEFINED = 255, | |
| }; | |
| @@ -14132,6 +15434,36 @@ | |
| DCB_TC_ATTR_PARAM_MAX = 5, | |
| }; | |
| +enum dccp_pkt_type { | |
| + DCCP_PKT_REQUEST = 0, | |
| + DCCP_PKT_RESPONSE = 1, | |
| + DCCP_PKT_DATA = 2, | |
| + DCCP_PKT_ACK = 3, | |
| + DCCP_PKT_DATAACK = 4, | |
| + DCCP_PKT_CLOSEREQ = 5, | |
| + DCCP_PKT_CLOSE = 6, | |
| + DCCP_PKT_RESET = 7, | |
| + DCCP_PKT_SYNC = 8, | |
| + DCCP_PKT_SYNCACK = 9, | |
| + DCCP_PKT_INVALID = 10, | |
| +}; | |
| + | |
| +enum dccp_state { | |
| + DCCP_OPEN = 1, | |
| + DCCP_REQUESTING = 2, | |
| + DCCP_LISTEN = 10, | |
| + DCCP_RESPOND = 3, | |
| + DCCP_ACTIVE_CLOSEREQ = 4, | |
| + DCCP_PASSIVE_CLOSE = 8, | |
| + DCCP_CLOSING = 11, | |
| + DCCP_TIME_WAIT = 6, | |
| + DCCP_CLOSED = 7, | |
| + DCCP_NEW_SYN_RECV = 12, | |
| + DCCP_PARTOPEN = 14, | |
| + DCCP_PASSIVE_CLOSEREQ = 15, | |
| + DCCP_MAX_STATES = 16, | |
| +}; | |
| + | |
| enum dd_data_dir { | |
| DD_READ = 0, | |
| DD_WRITE = 1, | |
| @@ -14149,6 +15481,16 @@ | |
| DENTRY_D_LOCK_NESTED = 1, | |
| }; | |
| +enum depot_counter_id { | |
| + DEPOT_COUNTER_REFD_ALLOCS = 0, | |
| + DEPOT_COUNTER_REFD_FREES = 1, | |
| + DEPOT_COUNTER_REFD_INUSE = 2, | |
| + DEPOT_COUNTER_FREELIST_SIZE = 3, | |
| + DEPOT_COUNTER_PERSIST_COUNT = 4, | |
| + DEPOT_COUNTER_PERSIST_BYTES = 5, | |
| + DEPOT_COUNTER_COUNT = 6, | |
| +}; | |
| + | |
| enum desc_state { | |
| desc_miss = -1, | |
| desc_reserved = 0, | |
| @@ -14180,17 +15522,6 @@ | |
| DEV_PROP_REF = 5, | |
| }; | |
| -enum dev_type { | |
| - DEV_UNKNOWN = 0, | |
| - DEV_X1 = 1, | |
| - DEV_X2 = 2, | |
| - DEV_X4 = 3, | |
| - DEV_X8 = 4, | |
| - DEV_X16 = 5, | |
| - DEV_X32 = 6, | |
| - DEV_X64 = 7, | |
| -}; | |
| - | |
| enum devcg_behavior { | |
| DEVCG_DEFAULT_NONE = 0, | |
| DEVCG_DEFAULT_ALLOW = 1, | |
| @@ -14235,6 +15566,12 @@ | |
| DEVICE_REMOVABLE = 3, | |
| }; | |
| +enum devkmsg_log_bits { | |
| + __DEVKMSG_LOG_BIT_ON = 0, | |
| + __DEVKMSG_LOG_BIT_OFF = 1, | |
| + __DEVKMSG_LOG_BIT_LOCK = 2, | |
| +}; | |
| + | |
| enum devkmsg_log_masks { | |
| DEVKMSG_LOG_MASK_ON = 1, | |
| DEVKMSG_LOG_MASK_OFF = 2, | |
| @@ -14527,19 +15864,38 @@ | |
| DEVLINK_CMD_LINECARD_DEL = 81, | |
| DEVLINK_CMD_SELFTESTS_GET = 82, | |
| DEVLINK_CMD_SELFTESTS_RUN = 83, | |
| - __DEVLINK_CMD_MAX = 84, | |
| - DEVLINK_CMD_MAX = 83, | |
| + DEVLINK_CMD_NOTIFY_FILTER_SET = 84, | |
| + __DEVLINK_CMD_MAX = 85, | |
| + DEVLINK_CMD_MAX = 84, | |
| }; | |
| enum devlink_dpipe_action_type { | |
| DEVLINK_DPIPE_ACTION_TYPE_FIELD_MODIFY = 0, | |
| }; | |
| +enum devlink_dpipe_field_ethernet_id { | |
| + DEVLINK_DPIPE_FIELD_ETHERNET_DST_MAC = 0, | |
| +}; | |
| + | |
| +enum devlink_dpipe_field_ipv4_id { | |
| + DEVLINK_DPIPE_FIELD_IPV4_DST_IP = 0, | |
| +}; | |
| + | |
| +enum devlink_dpipe_field_ipv6_id { | |
| + DEVLINK_DPIPE_FIELD_IPV6_DST_IP = 0, | |
| +}; | |
| + | |
| enum devlink_dpipe_field_mapping_type { | |
| DEVLINK_DPIPE_FIELD_MAPPING_TYPE_NONE = 0, | |
| DEVLINK_DPIPE_FIELD_MAPPING_TYPE_IFINDEX = 1, | |
| }; | |
| +enum devlink_dpipe_header_id { | |
| + DEVLINK_DPIPE_HEADER_ETHERNET = 0, | |
| + DEVLINK_DPIPE_HEADER_IPV4 = 1, | |
| + DEVLINK_DPIPE_HEADER_IPV6 = 2, | |
| +}; | |
| + | |
| enum devlink_dpipe_match_type { | |
| DEVLINK_DPIPE_MATCH_TYPE_FIELD_EXACT = 0, | |
| }; | |
| @@ -14588,6 +15944,13 @@ | |
| DEVLINK_PARAM_CMODE_MAX = 2, | |
| }; | |
| +enum devlink_param_fw_load_policy_value { | |
| + DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER = 0, | |
| + DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH = 1, | |
| + DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DISK = 2, | |
| + DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_UNKNOWN = 3, | |
| +}; | |
| + | |
| enum devlink_param_generic_id { | |
| DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET = 0, | |
| DEVLINK_PARAM_GENERIC_ID_MAX_MACS = 1, | |
| @@ -14610,6 +15973,13 @@ | |
| DEVLINK_PARAM_GENERIC_ID_MAX = 16, | |
| }; | |
| +enum devlink_param_reset_dev_on_drv_probe_value { | |
| + DEVLINK_PARAM_RESET_DEV_ON_DRV_PROBE_VALUE_UNKNOWN = 0, | |
| + DEVLINK_PARAM_RESET_DEV_ON_DRV_PROBE_VALUE_ALWAYS = 1, | |
| + DEVLINK_PARAM_RESET_DEV_ON_DRV_PROBE_VALUE_NEVER = 2, | |
| + DEVLINK_PARAM_RESET_DEV_ON_DRV_PROBE_VALUE_DISK = 3, | |
| +}; | |
| + | |
| enum devlink_param_type { | |
| DEVLINK_PARAM_TYPE_U8 = 0, | |
| DEVLINK_PARAM_TYPE_U16 = 1, | |
| @@ -14632,7 +16002,9 @@ | |
| enum devlink_port_fn_attr_cap { | |
| DEVLINK_PORT_FN_ATTR_CAP_ROCE_BIT = 0, | |
| DEVLINK_PORT_FN_ATTR_CAP_MIGRATABLE_BIT = 1, | |
| - __DEVLINK_PORT_FN_ATTR_CAPS_MAX = 2, | |
| + DEVLINK_PORT_FN_ATTR_CAP_IPSEC_CRYPTO_BIT = 2, | |
| + DEVLINK_PORT_FN_ATTR_CAP_IPSEC_PACKET_BIT = 3, | |
| + __DEVLINK_PORT_FN_ATTR_CAPS_MAX = 4, | |
| }; | |
| enum devlink_port_fn_opstate { | |
| @@ -14651,8 +16023,10 @@ | |
| DEVLINK_PORT_FN_ATTR_STATE = 2, | |
| DEVLINK_PORT_FN_ATTR_OPSTATE = 3, | |
| DEVLINK_PORT_FN_ATTR_CAPS = 4, | |
| - __DEVLINK_PORT_FUNCTION_ATTR_MAX = 5, | |
| - DEVLINK_PORT_FUNCTION_ATTR_MAX = 4, | |
| + DEVLINK_PORT_FN_ATTR_DEVLINK = 5, | |
| + DEVLINK_PORT_FN_ATTR_MAX_IO_EQS = 6, | |
| + __DEVLINK_PORT_FUNCTION_ATTR_MAX = 7, | |
| + DEVLINK_PORT_FUNCTION_ATTR_MAX = 6, | |
| }; | |
| enum devlink_port_type { | |
| @@ -14917,11 +16291,18 @@ | |
| DIRENT_HTREE = 3, | |
| } dirblock_type_t; | |
| -enum dispatch_to_local_dsq_ret { | |
| - DTL_DISPATCHED = 0, | |
| - DTL_LOST = 1, | |
| - DTL_NOT_LOCAL = 2, | |
| - DTL_INVALID = 3, | |
| +enum discover_event { | |
| + DISCE_DISCOVER_DOMAIN = 0, | |
| + DISCE_REVALIDATE_DOMAIN = 1, | |
| + DISCE_SUSPEND = 2, | |
| + DISCE_RESUME = 3, | |
| + DISC_NUM_EVENTS = 4, | |
| +}; | |
| + | |
| +enum dl_bw_request { | |
| + dl_bw_req_check_overflow = 0, | |
| + dl_bw_req_alloc = 1, | |
| + dl_bw_req_free = 2, | |
| }; | |
| enum dl_dev_state { | |
| @@ -14931,20 +16312,6 @@ | |
| DL_DEV_UNBINDING = 3, | |
| }; | |
| -enum dm_io_mem_type { | |
| - DM_IO_PAGE_LIST = 0, | |
| - DM_IO_BIO = 1, | |
| - DM_IO_VMA = 2, | |
| - DM_IO_KMEM = 3, | |
| -}; | |
| - | |
| -enum dm_queue_mode { | |
| - DM_TYPE_NONE = 0, | |
| - DM_TYPE_BIO_BASED = 1, | |
| - DM_TYPE_REQUEST_BASED = 2, | |
| - DM_TYPE_DAX_BIO_BASED = 3, | |
| -}; | |
| - | |
| enum dma_ctrl_flags { | |
| DMA_PREP_INTERRUPT = 1, | |
| DMA_CTRL_ACK = 2, | |
| @@ -14971,12 +16338,26 @@ | |
| DESC_METADATA_ENGINE = 2, | |
| }; | |
| +enum dma_fence_flag_bits { | |
| + DMA_FENCE_FLAG_SIGNALED_BIT = 0, | |
| + DMA_FENCE_FLAG_TIMESTAMP_BIT = 1, | |
| + DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT = 2, | |
| + DMA_FENCE_FLAG_USER_BITS = 3, | |
| +}; | |
| + | |
| enum dma_residue_granularity { | |
| DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0, | |
| DMA_RESIDUE_GRANULARITY_SEGMENT = 1, | |
| DMA_RESIDUE_GRANULARITY_BURST = 2, | |
| }; | |
| +enum dma_resv_usage { | |
| + DMA_RESV_USAGE_KERNEL = 0, | |
| + DMA_RESV_USAGE_WRITE = 1, | |
| + DMA_RESV_USAGE_READ = 2, | |
| + DMA_RESV_USAGE_BOOKKEEP = 3, | |
| +}; | |
| + | |
| enum dma_slave_buswidth { | |
| DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, | |
| DMA_SLAVE_BUSWIDTH_1_BYTE = 1, | |
| @@ -15138,10 +16519,28 @@ | |
| DMI_OEM_STRING = 24, | |
| }; | |
| +enum dns_lookup_status { | |
| + DNS_LOOKUP_NOT_DONE = 0, | |
| + DNS_LOOKUP_GOOD = 1, | |
| + DNS_LOOKUP_GOOD_WITH_BAD = 2, | |
| + DNS_LOOKUP_BAD = 3, | |
| + DNS_LOOKUP_GOT_NOT_FOUND = 4, | |
| + DNS_LOOKUP_GOT_LOCAL_FAILURE = 5, | |
| + DNS_LOOKUP_GOT_TEMP_FAILURE = 6, | |
| + DNS_LOOKUP_GOT_NS_FAILURE = 7, | |
| + NR__dns_lookup_status = 8, | |
| +}; | |
| + | |
| enum dns_payload_content_type { | |
| DNS_PAYLOAD_IS_SERVER_LIST = 0, | |
| }; | |
| +enum dock_callback_type { | |
| + DOCK_CALL_HANDLER = 0, | |
| + DOCK_CALL_FIXUP = 1, | |
| + DOCK_CALL_UEVENT = 2, | |
| +}; | |
| + | |
| enum dpm_order { | |
| DPM_ORDER_NONE = 0, | |
| DPM_ORDER_DEV_AFTER_PARENT = 1, | |
| @@ -15168,143 +16567,6 @@ | |
| DYNEVENT_TYPE_NONE = 3, | |
| }; | |
| -enum e1000_1000t_rx_status { | |
| - e1000_1000t_rx_status_not_ok = 0, | |
| - e1000_1000t_rx_status_ok = 1, | |
| - e1000_1000t_rx_status_undefined = 255, | |
| -}; | |
| - | |
| -enum e1000_bus_speed { | |
| - e1000_bus_speed_unknown = 0, | |
| - e1000_bus_speed_33 = 1, | |
| - e1000_bus_speed_66 = 2, | |
| - e1000_bus_speed_100 = 3, | |
| - e1000_bus_speed_120 = 4, | |
| - e1000_bus_speed_133 = 5, | |
| - e1000_bus_speed_2500 = 6, | |
| - e1000_bus_speed_5000 = 7, | |
| - e1000_bus_speed_reserved = 8, | |
| -}; | |
| - | |
| -enum e1000_bus_type { | |
| - e1000_bus_type_unknown = 0, | |
| - e1000_bus_type_pci = 1, | |
| - e1000_bus_type_pcix = 2, | |
| - e1000_bus_type_pci_express = 3, | |
| - e1000_bus_type_reserved = 4, | |
| -}; | |
| - | |
| -enum e1000_bus_width { | |
| - e1000_bus_width_unknown = 0, | |
| - e1000_bus_width_pcie_x1 = 1, | |
| - e1000_bus_width_pcie_x2 = 2, | |
| - e1000_bus_width_pcie_x4 = 4, | |
| - e1000_bus_width_pcie_x8 = 8, | |
| - e1000_bus_width_32 = 9, | |
| - e1000_bus_width_64 = 10, | |
| - e1000_bus_width_reserved = 11, | |
| -}; | |
| - | |
| -enum e1000_fc_mode { | |
| - e1000_fc_none = 0, | |
| - e1000_fc_rx_pause = 1, | |
| - e1000_fc_tx_pause = 2, | |
| - e1000_fc_full = 3, | |
| - e1000_fc_default = 255, | |
| -}; | |
| - | |
| -enum e1000_mac_type { | |
| - e1000_undefined = 0, | |
| - e1000_82575 = 1, | |
| - e1000_82576 = 2, | |
| - e1000_82580 = 3, | |
| - e1000_i350 = 4, | |
| - e1000_i354 = 5, | |
| - e1000_i210 = 6, | |
| - e1000_i211 = 7, | |
| - e1000_num_macs = 8, | |
| -}; | |
| - | |
| -enum e1000_media_type { | |
| - e1000_media_type_unknown = 0, | |
| - e1000_media_type_copper = 1, | |
| - e1000_media_type_fiber = 2, | |
| - e1000_media_type_internal_serdes = 3, | |
| - e1000_num_media_types = 4, | |
| -}; | |
| - | |
| -enum e1000_mng_mode { | |
| - e1000_mng_mode_none = 0, | |
| - e1000_mng_mode_asf = 1, | |
| - e1000_mng_mode_pt = 2, | |
| - e1000_mng_mode_ipmi = 3, | |
| - e1000_mng_mode_host_if_only = 4, | |
| -}; | |
| - | |
| -enum e1000_ms_type { | |
| - e1000_ms_hw_default = 0, | |
| - e1000_ms_force_master = 1, | |
| - e1000_ms_force_slave = 2, | |
| - e1000_ms_auto = 3, | |
| -}; | |
| - | |
| -enum e1000_nvm_override { | |
| - e1000_nvm_override_none = 0, | |
| - e1000_nvm_override_spi_small = 1, | |
| - e1000_nvm_override_spi_large = 2, | |
| -}; | |
| - | |
| -enum e1000_nvm_type { | |
| - e1000_nvm_unknown = 0, | |
| - e1000_nvm_none = 1, | |
| - e1000_nvm_eeprom_spi = 2, | |
| - e1000_nvm_flash_hw = 3, | |
| - e1000_nvm_invm = 4, | |
| - e1000_nvm_flash_sw = 5, | |
| -}; | |
| - | |
| -enum e1000_phy_type { | |
| - e1000_phy_unknown = 0, | |
| - e1000_phy_none = 1, | |
| - e1000_phy_m88 = 2, | |
| - e1000_phy_igp = 3, | |
| - e1000_phy_igp_2 = 4, | |
| - e1000_phy_gg82563 = 5, | |
| - e1000_phy_igp_3 = 6, | |
| - e1000_phy_ife = 7, | |
| - e1000_phy_82580 = 8, | |
| - e1000_phy_i210 = 9, | |
| - e1000_phy_bcm54616 = 10, | |
| -}; | |
| - | |
| -enum e1000_rev_polarity { | |
| - e1000_rev_polarity_normal = 0, | |
| - e1000_rev_polarity_reversed = 1, | |
| - e1000_rev_polarity_undefined = 255, | |
| -}; | |
| - | |
| -enum e1000_ring_flags_t { | |
| - IGB_RING_FLAG_RX_3K_BUFFER = 0, | |
| - IGB_RING_FLAG_RX_BUILD_SKB_ENABLED = 1, | |
| - IGB_RING_FLAG_RX_SCTP_CSUM = 2, | |
| - IGB_RING_FLAG_RX_LB_VLAN_BSWAP = 3, | |
| - IGB_RING_FLAG_TX_CTX_IDX = 4, | |
| - IGB_RING_FLAG_TX_DETECT_HANG = 5, | |
| -}; | |
| - | |
| -enum e1000_smart_speed { | |
| - e1000_smart_speed_default = 0, | |
| - e1000_smart_speed_on = 1, | |
| - e1000_smart_speed_off = 2, | |
| -}; | |
| - | |
| -enum e1000_state_t { | |
| - __IGB_TESTING = 0, | |
| - __IGB_RESETTING = 1, | |
| - __IGB_DOWN = 2, | |
| - __IGB_PTP_TX_IN_PROGRESS = 3, | |
| -}; | |
| - | |
| enum e820_type { | |
| E820_TYPE_RAM = 1, | |
| E820_TYPE_RESERVED = 2, | |
| @@ -15336,27 +16598,6 @@ | |
| ECC_DIALECT_SAFECURVE = 2, | |
| }; | |
| -enum edac_mc_layer_type { | |
| - EDAC_MC_LAYER_BRANCH = 0, | |
| - EDAC_MC_LAYER_CHANNEL = 1, | |
| - EDAC_MC_LAYER_SLOT = 2, | |
| - EDAC_MC_LAYER_CHIP_SELECT = 3, | |
| - EDAC_MC_LAYER_ALL_MEM = 4, | |
| -}; | |
| - | |
| -enum edac_type { | |
| - EDAC_UNKNOWN = 0, | |
| - EDAC_NONE = 1, | |
| - EDAC_RESERVED = 2, | |
| - EDAC_PARITY = 3, | |
| - EDAC_EC = 4, | |
| - EDAC_SECDED = 5, | |
| - EDAC_S2ECD2ED = 6, | |
| - EDAC_S4ECD4ED = 7, | |
| - EDAC_S8ECD8ED = 8, | |
| - EDAC_S16ECD16ED = 9, | |
| -}; | |
| - | |
| enum efi_rts_ids { | |
| EFI_NONE = 0, | |
| EFI_GET_TIME = 1, | |
| @@ -15371,6 +16612,7 @@ | |
| EFI_RESET_SYSTEM = 10, | |
| EFI_UPDATE_CAPSULE = 11, | |
| EFI_QUERY_CAPSULE_CAPS = 12, | |
| + EFI_ACPI_PRM_HANDLER = 13, | |
| }; | |
| enum efi_secureboot_mode { | |
| @@ -15380,29 +16622,6 @@ | |
| efi_secureboot_mode_enabled = 3, | |
| }; | |
| -enum ehci_hrtimer_event { | |
| - EHCI_HRTIMER_POLL_ASS = 0, | |
| - EHCI_HRTIMER_POLL_PSS = 1, | |
| - EHCI_HRTIMER_POLL_DEAD = 2, | |
| - EHCI_HRTIMER_UNLINK_INTR = 3, | |
| - EHCI_HRTIMER_FREE_ITDS = 4, | |
| - EHCI_HRTIMER_ACTIVE_UNLINK = 5, | |
| - EHCI_HRTIMER_START_UNLINK_INTR = 6, | |
| - EHCI_HRTIMER_ASYNC_UNLINKS = 7, | |
| - EHCI_HRTIMER_IAA_WATCHDOG = 8, | |
| - EHCI_HRTIMER_DISABLE_PERIODIC = 9, | |
| - EHCI_HRTIMER_DISABLE_ASYNC = 10, | |
| - EHCI_HRTIMER_IO_WATCHDOG = 11, | |
| - EHCI_HRTIMER_NUM_EVENTS = 12, | |
| -}; | |
| - | |
| -enum ehci_rh_state { | |
| - EHCI_RH_HALTED = 0, | |
| - EHCI_RH_SUSPENDED = 1, | |
| - EHCI_RH_RUNNING = 2, | |
| - EHCI_RH_STOPPING = 3, | |
| -}; | |
| - | |
| enum elv_merge { | |
| ELEVATOR_NO_MERGE = 0, | |
| ELEVATOR_FRONT_MERGE = 1, | |
| @@ -15424,6 +16643,14 @@ | |
| } endCondition_directive; | |
| enum energy_perf_value_index { | |
| + EPB_INDEX_PERFORMANCE = 0, | |
| + EPB_INDEX_BALANCE_PERFORMANCE = 1, | |
| + EPB_INDEX_NORMAL = 2, | |
| + EPB_INDEX_BALANCE_POWERSAVE = 3, | |
| + EPB_INDEX_POWERSAVE = 4, | |
| +}; | |
| + | |
| +enum energy_perf_value_index___2 { | |
| EPP_INDEX_DEFAULT = 0, | |
| EPP_INDEX_PERFORMANCE = 1, | |
| EPP_INDEX_BALANCE_PERFORMANCE = 2, | |
| @@ -15431,21 +16658,10 @@ | |
| EPP_INDEX_POWERSAVE = 4, | |
| }; | |
| -enum err_codes { | |
| - DECODE_OK = 0, | |
| - ERR_NODE = -1, | |
| - ERR_CSROW = -2, | |
| - ERR_CHANNEL = -3, | |
| - ERR_SYND = -4, | |
| - ERR_NORM_ADDR = -5, | |
| -}; | |
| - | |
| -enum err_types { | |
| - ERR_TYPE_CACHE = 0, | |
| - ERR_TYPE_TLB = 1, | |
| - ERR_TYPE_BUS = 2, | |
| - ERR_TYPE_MS = 3, | |
| - N_ERR_TYPES = 4, | |
| +enum environment_cap { | |
| + ENVIRON_ANY = 0, | |
| + ENVIRON_INDOOR = 1, | |
| + ENVIRON_OUTDOOR = 2, | |
| }; | |
| enum error_detector { | |
| @@ -15454,13 +16670,34 @@ | |
| ERROR_DETECTOR_WARN = 2, | |
| }; | |
| -enum es_result { | |
| - ES_OK = 0, | |
| - ES_UNSUPPORTED = 1, | |
| - ES_VMM_ERROR = 2, | |
| - ES_DECODE_FAILED = 3, | |
| - ES_EXCEPTION = 4, | |
| - ES_RETRY = 5, | |
| +enum erspan_bso { | |
| + BSO_NOERROR = 0, | |
| + BSO_SHORT = 1, | |
| + BSO_OVERSIZED = 2, | |
| + BSO_BAD = 3, | |
| +}; | |
| + | |
| +enum erspan_encap_type { | |
| + ERSPAN_ENCAP_NOVLAN = 0, | |
| + ERSPAN_ENCAP_ISL = 1, | |
| + ERSPAN_ENCAP_8021Q = 2, | |
| + ERSPAN_ENCAP_INFRAME = 3, | |
| +}; | |
| + | |
| +enum ethtool_c33_pse_admin_state { | |
| + ETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN = 1, | |
| + ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED = 2, | |
| + ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED = 3, | |
| +}; | |
| + | |
| +enum ethtool_c33_pse_pw_d_status { | |
| + ETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN = 1, | |
| + ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED = 2, | |
| + ETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING = 3, | |
| + ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING = 4, | |
| + ETHTOOL_C33_PSE_PW_D_STATUS_TEST = 5, | |
| + ETHTOOL_C33_PSE_PW_D_STATUS_FAULT = 6, | |
| + ETHTOOL_C33_PSE_PW_D_STATUS_OTHERFAULT = 7, | |
| }; | |
| enum ethtool_fec_config_bits { | |
| @@ -15480,10 +16717,6 @@ | |
| ETH_FLAG_RXHASH = 268435456, | |
| }; | |
| -enum ethtool_flash_op_type { | |
| - ETHTOOL_FLASH_ALL_REGIONS = 0, | |
| -}; | |
| - | |
| enum ethtool_header_flags { | |
| ETHTOOL_FLAG_COMPACT_BITSETS = 1, | |
| ETHTOOL_FLAG_OMIT_REPLY = 2, | |
| @@ -15703,24 +16936,10 @@ | |
| }; | |
| enum ethtool_report { | |
| - SUPPORTED = 0, | |
| + SUPPORTED___2 = 0, | |
| ADVERTISED = 1, | |
| }; | |
| -enum ethtool_reset_flags { | |
| - ETH_RESET_MGMT = 1, | |
| - ETH_RESET_IRQ = 2, | |
| - ETH_RESET_DMA = 4, | |
| - ETH_RESET_FILTER = 8, | |
| - ETH_RESET_OFFLOAD = 16, | |
| - ETH_RESET_MAC = 32, | |
| - ETH_RESET_PHY = 64, | |
| - ETH_RESET_RAM = 128, | |
| - ETH_RESET_AP = 256, | |
| - ETH_RESET_DEDICATED = 65535, | |
| - ETH_RESET_ALL = 4294967295, | |
| -}; | |
| - | |
| enum ethtool_sfeatures_retval_bits { | |
| ETHTOOL_F_UNSUPPORTED__BIT = 0, | |
| ETHTOOL_F_WISH__BIT = 1, | |
| @@ -15758,6 +16977,7 @@ | |
| ETHTOOL_RING_USE_TX_PUSH = 4, | |
| ETHTOOL_RING_USE_RX_PUSH = 8, | |
| ETHTOOL_RING_USE_TX_PUSH_BUF_LEN = 16, | |
| + ETHTOOL_RING_USE_TCP_DATA_SPLIT = 32, | |
| }; | |
| enum ethtool_test_flags { | |
| @@ -15788,6 +17008,7 @@ | |
| EVENT_PINNED = 2, | |
| EVENT_TIME = 4, | |
| EVENT_CPU = 8, | |
| + EVENT_CGROUP = 16, | |
| EVENT_ALL = 3, | |
| }; | |
| @@ -15801,11 +17022,92 @@ | |
| IMA_XATTR_LAST = 7, | |
| }; | |
| +enum evmcs_ctrl_type { | |
| + EVMCS_EXIT_CTRLS = 0, | |
| + EVMCS_ENTRY_CTRLS = 1, | |
| + EVMCS_EXEC_CTRL = 2, | |
| + EVMCS_2NDEXEC = 3, | |
| + EVMCS_3RDEXEC = 4, | |
| + EVMCS_PINCTRL = 5, | |
| + EVMCS_VMFUNC = 6, | |
| + NR_EVMCS_CTRLS = 7, | |
| +}; | |
| + | |
| +enum evmcs_revision { | |
| + EVMCSv1_LEGACY = 0, | |
| + NR_EVMCS_REVISIONS = 1, | |
| +}; | |
| + | |
| +enum ex_phy_state { | |
| + PHY_EMPTY = 0, | |
| + PHY_VACANT = 1, | |
| + PHY_NOT_PRESENT = 2, | |
| + PHY_DEVICE_DISCOVERED = 3, | |
| +}; | |
| + | |
| +enum exact_level { | |
| + NOT_EXACT = 0, | |
| + EXACT = 1, | |
| + RANGE_WITHIN = 2, | |
| +}; | |
| + | |
| enum exception { | |
| EXCP_CONTEXT = 1, | |
| NO_EXCP = 2, | |
| }; | |
| +enum exception_stack_ordering { | |
| + ESTACK_DF = 0, | |
| + ESTACK_NMI = 1, | |
| + ESTACK_DB = 2, | |
| + ESTACK_MCE = 3, | |
| + ESTACK_VC = 4, | |
| + ESTACK_VC2 = 5, | |
| + N_EXCEPTION_STACKS = 6, | |
| +}; | |
| + | |
| +enum exec_status { | |
| + SAS_SAM_STAT_GOOD = 0, | |
| + SAS_SAM_STAT_BUSY = 8, | |
| + SAS_SAM_STAT_TASK_ABORTED = 64, | |
| + SAS_SAM_STAT_CHECK_CONDITION = 2, | |
| + SAS_DEV_NO_RESPONSE = 128, | |
| + SAS_DATA_UNDERRUN = 129, | |
| + SAS_DATA_OVERRUN = 130, | |
| + SAS_INTERRUPTED = 131, | |
| + SAS_QUEUE_FULL = 132, | |
| + SAS_DEVICE_UNKNOWN = 133, | |
| + SAS_OPEN_REJECT = 134, | |
| + SAS_OPEN_TO = 135, | |
| + SAS_PROTO_RESPONSE = 136, | |
| + SAS_PHY_DOWN = 137, | |
| + SAS_NAK_R_ERR = 138, | |
| + SAS_PENDING = 139, | |
| + SAS_ABORTED_TASK = 140, | |
| +}; | |
| + | |
| +enum execmem_range_flags { | |
| + EXECMEM_KASAN_SHADOW = 1, | |
| +}; | |
| + | |
| +enum execmem_type { | |
| + EXECMEM_DEFAULT = 0, | |
| + EXECMEM_MODULE_TEXT = 0, | |
| + EXECMEM_KPROBES = 1, | |
| + EXECMEM_FTRACE = 2, | |
| + EXECMEM_BPF = 3, | |
| + EXECMEM_MODULE_DATA = 4, | |
| + EXECMEM_TYPE_MAX = 5, | |
| +}; | |
| + | |
| +enum exit_fastpath_completion { | |
| + EXIT_FASTPATH_NONE = 0, | |
| + EXIT_FASTPATH_REENTER_GUEST = 1, | |
| + EXIT_FASTPATH_EXIT_HANDLED = 2, | |
| +}; | |
| + | |
| +typedef enum exit_fastpath_completion fastpath_t; | |
| + | |
| typedef enum { | |
| EXT4_IGET_NORMAL = 0, | |
| EXT4_IGET_SPECIAL = 1, | |
| @@ -15841,16 +17143,6 @@ | |
| FAIL_DUP_MOD_LOAD = 1, | |
| }; | |
| -enum fanotify_event_type { | |
| - FANOTIFY_EVENT_TYPE_FID = 0, | |
| - FANOTIFY_EVENT_TYPE_FID_NAME = 1, | |
| - FANOTIFY_EVENT_TYPE_PATH = 2, | |
| - FANOTIFY_EVENT_TYPE_PATH_PERM = 3, | |
| - FANOTIFY_EVENT_TYPE_OVERFLOW = 4, | |
| - FANOTIFY_EVENT_TYPE_FS_ERROR = 5, | |
| - __FANOTIFY_EVENT_TYPE_NUM = 6, | |
| -}; | |
| - | |
| enum fault_flag { | |
| FAULT_FLAG_WRITE = 1, | |
| FAULT_FLAG_MKWRITE = 2, | |
| @@ -15883,6 +17175,106 @@ | |
| all = 2, | |
| }; | |
| +enum fc_fpin_congn_event_types { | |
| + FPIN_CONGN_CLEAR = 0, | |
| + FPIN_CONGN_LOST_CREDIT = 1, | |
| + FPIN_CONGN_CREDIT_STALL = 2, | |
| + FPIN_CONGN_OVERSUBSCRIPTION = 3, | |
| + FPIN_CONGN_DEVICE_SPEC = 15, | |
| +}; | |
| + | |
| +enum fc_fpin_deli_event_types { | |
| + FPIN_DELI_UNKNOWN = 0, | |
| + FPIN_DELI_TIMEOUT = 1, | |
| + FPIN_DELI_UNABLE_TO_ROUTE = 2, | |
| + FPIN_DELI_DEVICE_SPEC = 15, | |
| +}; | |
| + | |
| +enum fc_fpin_li_event_types { | |
| + FPIN_LI_UNKNOWN = 0, | |
| + FPIN_LI_LINK_FAILURE = 1, | |
| + FPIN_LI_LOSS_OF_SYNC = 2, | |
| + FPIN_LI_LOSS_OF_SIG = 3, | |
| + FPIN_LI_PRIM_SEQ_ERR = 4, | |
| + FPIN_LI_INVALID_TX_WD = 5, | |
| + FPIN_LI_INVALID_CRC = 6, | |
| + FPIN_LI_DEVICE_SPEC = 15, | |
| +}; | |
| + | |
| +enum fc_host_event_code { | |
| + FCH_EVT_LIP = 1, | |
| + FCH_EVT_LINKUP = 2, | |
| + FCH_EVT_LINKDOWN = 3, | |
| + FCH_EVT_LIPRESET = 4, | |
| + FCH_EVT_RSCN = 5, | |
| + FCH_EVT_ADAPTER_CHANGE = 259, | |
| + FCH_EVT_PORT_UNKNOWN = 512, | |
| + FCH_EVT_PORT_OFFLINE = 513, | |
| + FCH_EVT_PORT_ONLINE = 514, | |
| + FCH_EVT_PORT_FABRIC = 516, | |
| + FCH_EVT_LINK_UNKNOWN = 1280, | |
| + FCH_EVT_LINK_FPIN = 1281, | |
| + FCH_EVT_LINK_FPIN_ACK = 1282, | |
| + FCH_EVT_VENDOR_UNIQUE = 65535, | |
| +}; | |
| + | |
| +enum fc_ls_tlv_dtag { | |
| + ELS_DTAG_LS_REQ_INFO = 1, | |
| + ELS_DTAG_LNK_FAULT_CAP = 65549, | |
| + ELS_DTAG_CG_SIGNAL_CAP = 65551, | |
| + ELS_DTAG_LNK_INTEGRITY = 131073, | |
| + ELS_DTAG_DELIVERY = 131074, | |
| + ELS_DTAG_PEER_CONGEST = 131075, | |
| + ELS_DTAG_CONGESTION = 131076, | |
| + ELS_DTAG_FPIN_REGISTER = 196609, | |
| +}; | |
| + | |
| +enum fc_port_state { | |
| + FC_PORTSTATE_UNKNOWN = 0, | |
| + FC_PORTSTATE_NOTPRESENT = 1, | |
| + FC_PORTSTATE_ONLINE = 2, | |
| + FC_PORTSTATE_OFFLINE = 3, | |
| + FC_PORTSTATE_BLOCKED = 4, | |
| + FC_PORTSTATE_BYPASSED = 5, | |
| + FC_PORTSTATE_DIAGNOSTICS = 6, | |
| + FC_PORTSTATE_LINKDOWN = 7, | |
| + FC_PORTSTATE_ERROR = 8, | |
| + FC_PORTSTATE_LOOPBACK = 9, | |
| + FC_PORTSTATE_DELETED = 10, | |
| + FC_PORTSTATE_MARGINAL = 11, | |
| +}; | |
| + | |
| +enum fc_port_type { | |
| + FC_PORTTYPE_UNKNOWN = 0, | |
| + FC_PORTTYPE_OTHER = 1, | |
| + FC_PORTTYPE_NOTPRESENT = 2, | |
| + FC_PORTTYPE_NPORT = 3, | |
| + FC_PORTTYPE_NLPORT = 4, | |
| + FC_PORTTYPE_LPORT = 5, | |
| + FC_PORTTYPE_PTP = 6, | |
| + FC_PORTTYPE_NPIV = 7, | |
| +}; | |
| + | |
| +enum fc_tgtid_binding_type { | |
| + FC_TGTID_BIND_NONE = 0, | |
| + FC_TGTID_BIND_BY_WWPN = 1, | |
| + FC_TGTID_BIND_BY_WWNN = 2, | |
| + FC_TGTID_BIND_BY_ID = 3, | |
| +}; | |
| + | |
| +enum fc_vport_state { | |
| + FC_VPORT_UNKNOWN = 0, | |
| + FC_VPORT_ACTIVE = 1, | |
| + FC_VPORT_DISABLED = 2, | |
| + FC_VPORT_LINKDOWN = 3, | |
| + FC_VPORT_INITIALIZING = 4, | |
| + FC_VPORT_NO_FABRIC_SUPP = 5, | |
| + FC_VPORT_NO_FABRIC_RSCS = 6, | |
| + FC_VPORT_FABRIC_LOGOUT = 7, | |
| + FC_VPORT_FABRIC_REJ_WWN = 8, | |
| + FC_VPORT_FAILED = 9, | |
| +}; | |
| + | |
| enum fetch_op { | |
| FETCH_OP_NOP = 0, | |
| FETCH_OP_REG = 1, | |
| @@ -15894,19 +17286,21 @@ | |
| FETCH_OP_ARG = 7, | |
| FETCH_OP_FOFFS = 8, | |
| FETCH_OP_DATA = 9, | |
| - FETCH_OP_DEREF = 10, | |
| - FETCH_OP_UDEREF = 11, | |
| - FETCH_OP_ST_RAW = 12, | |
| - FETCH_OP_ST_MEM = 13, | |
| - FETCH_OP_ST_UMEM = 14, | |
| - FETCH_OP_ST_STRING = 15, | |
| - FETCH_OP_ST_USTRING = 16, | |
| - FETCH_OP_ST_SYMSTR = 17, | |
| - FETCH_OP_MOD_BF = 18, | |
| - FETCH_OP_LP_ARRAY = 19, | |
| - FETCH_OP_TP_ARG = 20, | |
| - FETCH_OP_END = 21, | |
| - FETCH_NOP_SYMBOL = 22, | |
| + FETCH_OP_EDATA = 10, | |
| + FETCH_OP_DEREF = 11, | |
| + FETCH_OP_UDEREF = 12, | |
| + FETCH_OP_ST_RAW = 13, | |
| + FETCH_OP_ST_MEM = 14, | |
| + FETCH_OP_ST_UMEM = 15, | |
| + FETCH_OP_ST_STRING = 16, | |
| + FETCH_OP_ST_USTRING = 17, | |
| + FETCH_OP_ST_SYMSTR = 18, | |
| + FETCH_OP_ST_EDATA = 19, | |
| + FETCH_OP_MOD_BF = 20, | |
| + FETCH_OP_LP_ARRAY = 21, | |
| + FETCH_OP_TP_ARG = 22, | |
| + FETCH_OP_END = 23, | |
| + FETCH_NOP_SYMBOL = 24, | |
| }; | |
| enum fib6_walk_state { | |
| @@ -15930,6 +17324,32 @@ | |
| FIB_EVENT_VIF_DEL = 9, | |
| }; | |
| +enum fib_xfer_state { | |
| + HostOwned = 1, | |
| + AdapterOwned = 2, | |
| + FibInitialized = 4, | |
| + FibEmpty = 8, | |
| + AllocatedFromPool = 16, | |
| + SentFromHost = 32, | |
| + SentFromAdapter = 64, | |
| + ResponseExpected = 128, | |
| + NoResponseExpected = 256, | |
| + AdapterProcessed = 512, | |
| + HostProcessed = 1024, | |
| + HighPriority = 2048, | |
| + NormalPriority = 4096, | |
| + Async = 8192, | |
| + AsyncIo = 8192, | |
| + PageFileIo = 16384, | |
| + ShutdownRequest = 32768, | |
| + LazyWrite = 65536, | |
| + AdapterMicroFib = 131072, | |
| + BIOSFibPath = 262144, | |
| + FastResponseCapable = 524288, | |
| + ApiFib = 1048576, | |
| + NoMoreAifDataAvailable = 2097152, | |
| +}; | |
| + | |
| enum fid_type { | |
| FILEID_ROOT = 0, | |
| FILEID_INO32_GEN = 1, | |
| @@ -15943,7 +17363,11 @@ | |
| FILEID_NILFS_WITH_PARENT = 98, | |
| FILEID_FAT_WITHOUT_PARENT = 113, | |
| FILEID_FAT_WITH_PARENT = 114, | |
| + FILEID_INO64_GEN = 129, | |
| + FILEID_INO64_GEN_PARENT = 130, | |
| FILEID_LUSTRE = 151, | |
| + FILEID_BCACHEFS_WITHOUT_PARENT = 177, | |
| + FILEID_BCACHEFS_WITH_PARENT = 178, | |
| FILEID_KERNFS = 254, | |
| FILEID_INVALID = 255, | |
| }; | |
| @@ -15970,27 +17394,34 @@ | |
| enum filter_pred_fn { | |
| FILTER_PRED_FN_NOP = 0, | |
| FILTER_PRED_FN_64 = 1, | |
| - FILTER_PRED_FN_S64 = 2, | |
| - FILTER_PRED_FN_U64 = 3, | |
| - FILTER_PRED_FN_32 = 4, | |
| - FILTER_PRED_FN_S32 = 5, | |
| - FILTER_PRED_FN_U32 = 6, | |
| - FILTER_PRED_FN_16 = 7, | |
| - FILTER_PRED_FN_S16 = 8, | |
| - FILTER_PRED_FN_U16 = 9, | |
| - FILTER_PRED_FN_8 = 10, | |
| - FILTER_PRED_FN_S8 = 11, | |
| - FILTER_PRED_FN_U8 = 12, | |
| - FILTER_PRED_FN_COMM = 13, | |
| - FILTER_PRED_FN_STRING = 14, | |
| - FILTER_PRED_FN_STRLOC = 15, | |
| - FILTER_PRED_FN_STRRELLOC = 16, | |
| - FILTER_PRED_FN_PCHAR_USER = 17, | |
| - FILTER_PRED_FN_PCHAR = 18, | |
| - FILTER_PRED_FN_CPU = 19, | |
| - FILTER_PRED_FN_FUNCTION = 20, | |
| - FILTER_PRED_FN_ = 21, | |
| - FILTER_PRED_TEST_VISITED = 22, | |
| + FILTER_PRED_FN_64_CPUMASK = 2, | |
| + FILTER_PRED_FN_S64 = 3, | |
| + FILTER_PRED_FN_U64 = 4, | |
| + FILTER_PRED_FN_32 = 5, | |
| + FILTER_PRED_FN_32_CPUMASK = 6, | |
| + FILTER_PRED_FN_S32 = 7, | |
| + FILTER_PRED_FN_U32 = 8, | |
| + FILTER_PRED_FN_16 = 9, | |
| + FILTER_PRED_FN_16_CPUMASK = 10, | |
| + FILTER_PRED_FN_S16 = 11, | |
| + FILTER_PRED_FN_U16 = 12, | |
| + FILTER_PRED_FN_8 = 13, | |
| + FILTER_PRED_FN_8_CPUMASK = 14, | |
| + FILTER_PRED_FN_S8 = 15, | |
| + FILTER_PRED_FN_U8 = 16, | |
| + FILTER_PRED_FN_COMM = 17, | |
| + FILTER_PRED_FN_STRING = 18, | |
| + FILTER_PRED_FN_STRLOC = 19, | |
| + FILTER_PRED_FN_STRRELLOC = 20, | |
| + FILTER_PRED_FN_PCHAR_USER = 21, | |
| + FILTER_PRED_FN_PCHAR = 22, | |
| + FILTER_PRED_FN_CPU = 23, | |
| + FILTER_PRED_FN_CPU_CPUMASK = 24, | |
| + FILTER_PRED_FN_CPUMASK = 25, | |
| + FILTER_PRED_FN_CPUMASK_CPU = 26, | |
| + FILTER_PRED_FN_FUNCTION = 27, | |
| + FILTER_PRED_FN_ = 28, | |
| + FILTER_PRED_TEST_VISITED = 29, | |
| }; | |
| enum fit_type { | |
| @@ -16008,9 +17439,7 @@ | |
| FIX_APIC_BASE = 514, | |
| FIX_IO_APIC_BASE_0 = 515, | |
| FIX_IO_APIC_BASE_END = 642, | |
| - FIX_APEI_GHES_IRQ = 643, | |
| - FIX_APEI_GHES_NMI = 644, | |
| - __end_of_permanent_fixed_addresses = 645, | |
| + __end_of_permanent_fixed_addresses = 643, | |
| FIX_BTMAP_END = 1024, | |
| FIX_BTMAP_BEGIN = 1535, | |
| FIX_TBOOT_BASE = 1536, | |
| @@ -16032,11 +17461,11 @@ | |
| Candidate = 11, | |
| Journal = 12, | |
| ClusterRemove = 13, | |
| - RemoveSynchronized = 14, | |
| - ExternalBbl = 15, | |
| - FailFast = 16, | |
| - LastDev = 17, | |
| - CollisionCheck = 18, | |
| + ExternalBbl = 14, | |
| + FailFast = 15, | |
| + LastDev = 16, | |
| + CollisionCheck = 17, | |
| + Nonrot = 18, | |
| }; | |
| enum flow_action_hw_stats { | |
| @@ -16047,6 +17476,13 @@ | |
| FLOW_ACTION_HW_STATS_DONT_CARE = 7, | |
| }; | |
| +enum flow_action_hw_stats_bit { | |
| + FLOW_ACTION_HW_STATS_IMMEDIATE_BIT = 0, | |
| + FLOW_ACTION_HW_STATS_DELAYED_BIT = 1, | |
| + FLOW_ACTION_HW_STATS_DISABLED_BIT = 2, | |
| + FLOW_ACTION_HW_STATS_NUM_BITS = 3, | |
| +}; | |
| + | |
| enum flow_action_id { | |
| FLOW_ACTION_ACCEPT = 0, | |
| FLOW_ACTION_DROP = 1, | |
| @@ -16157,7 +17593,9 @@ | |
| FLOW_DISSECTOR_KEY_NUM_OF_VLANS = 28, | |
| FLOW_DISSECTOR_KEY_PPPOE = 29, | |
| FLOW_DISSECTOR_KEY_L2TPV3 = 30, | |
| - FLOW_DISSECTOR_KEY_MAX = 31, | |
| + FLOW_DISSECTOR_KEY_CFM = 31, | |
| + FLOW_DISSECTOR_KEY_IPSEC = 32, | |
| + FLOW_DISSECTOR_KEY_MAX = 33, | |
| }; | |
| enum flowlabel_reflect { | |
| @@ -16166,37 +17604,6 @@ | |
| FLOWLABEL_REFLECT_ICMPV6_ECHO_REPLIES = 4, | |
| }; | |
| -typedef enum { | |
| - FL_READY = 0, | |
| - FL_STATUS = 1, | |
| - FL_CFI_QUERY = 2, | |
| - FL_JEDEC_QUERY = 3, | |
| - FL_ERASING = 4, | |
| - FL_ERASE_SUSPENDING = 5, | |
| - FL_ERASE_SUSPENDED = 6, | |
| - FL_WRITING = 7, | |
| - FL_WRITING_TO_BUFFER = 8, | |
| - FL_OTP_WRITE = 9, | |
| - FL_WRITE_SUSPENDING = 10, | |
| - FL_WRITE_SUSPENDED = 11, | |
| - FL_PM_SUSPENDED = 12, | |
| - FL_SYNCING = 13, | |
| - FL_UNLOADING = 14, | |
| - FL_LOCKING = 15, | |
| - FL_UNLOCKING = 16, | |
| - FL_POINT = 17, | |
| - FL_XIP_WHILE_ERASING = 18, | |
| - FL_XIP_WHILE_WRITING = 19, | |
| - FL_SHUTDOWN = 20, | |
| - FL_READING = 21, | |
| - FL_CACHEDPRG = 22, | |
| - FL_RESETTING = 23, | |
| - FL_OTPING = 24, | |
| - FL_PREPARING_ERASE = 25, | |
| - FL_VERIFYING_ERASE = 26, | |
| - FL_UNKNOWN = 27, | |
| -} flstate_t; | |
| - | |
| enum folio_references { | |
| FOLIOREF_RECLAIM = 0, | |
| FOLIOREF_RECLAIM_CLEAN = 1, | |
| @@ -16226,6 +17633,12 @@ | |
| FORMAT_TYPE_PTRDIFF = 18, | |
| }; | |
| +enum freeze_holder { | |
| + FREEZE_HOLDER_KERNEL = 1, | |
| + FREEZE_HOLDER_USERSPACE = 2, | |
| + FREEZE_MAY_NEST = 4, | |
| +}; | |
| + | |
| enum freezer_state_flags { | |
| CGROUP_FREEZER_ONLINE = 1, | |
| CGROUP_FREEZING_SELF = 2, | |
| @@ -16255,51 +17668,6 @@ | |
| FS_CONTEXT_FOR_RECONFIGURE = 2, | |
| }; | |
| -enum fs_flow_table_op_mod { | |
| - FS_FT_OP_MOD_NORMAL = 0, | |
| - FS_FT_OP_MOD_LAG_DEMUX = 1, | |
| -}; | |
| - | |
| -enum fs_flow_table_type { | |
| - FS_FT_NIC_RX = 0, | |
| - FS_FT_NIC_TX = 1, | |
| - FS_FT_ESW_EGRESS_ACL = 2, | |
| - FS_FT_ESW_INGRESS_ACL = 3, | |
| - FS_FT_FDB = 4, | |
| - FS_FT_SNIFFER_RX = 5, | |
| - FS_FT_SNIFFER_TX = 6, | |
| - FS_FT_RDMA_RX = 7, | |
| - FS_FT_RDMA_TX = 8, | |
| - FS_FT_PORT_SEL = 9, | |
| - FS_FT_MAX_TYPE = 9, | |
| -}; | |
| - | |
| -enum fs_fte_status { | |
| - FS_FTE_STATUS_EXISTING = 1, | |
| -}; | |
| - | |
| -enum fs_i_lock_class { | |
| - FS_LOCK_GRANDPARENT = 0, | |
| - FS_LOCK_PARENT = 1, | |
| - FS_LOCK_CHILD = 2, | |
| -}; | |
| - | |
| -enum fs_node_type { | |
| - FS_TYPE_NAMESPACE = 0, | |
| - FS_TYPE_PRIO = 1, | |
| - FS_TYPE_PRIO_CHAINS = 2, | |
| - FS_TYPE_FLOW_TABLE = 3, | |
| - FS_TYPE_FLOW_GROUP = 4, | |
| - FS_TYPE_FLOW_ENTRY = 5, | |
| - FS_TYPE_FLOW_DEST = 6, | |
| -}; | |
| - | |
| -enum fs_udp_type { | |
| - FS_IPV4_UDP = 0, | |
| - FS_IPV6_UDP = 1, | |
| - FS_UDP_NUM_TYPES = 2, | |
| -}; | |
| - | |
| enum fs_value_type { | |
| fs_value_is_undefined = 0, | |
| fs_value_is_flag = 1, | |
| @@ -16309,6 +17677,33 @@ | |
| fs_value_is_file = 5, | |
| }; | |
| +enum fscache_cache_state { | |
| + FSCACHE_CACHE_IS_NOT_PRESENT = 0, | |
| + FSCACHE_CACHE_IS_PREPARING = 1, | |
| + FSCACHE_CACHE_IS_ACTIVE = 2, | |
| + FSCACHE_CACHE_GOT_IOERROR = 3, | |
| + FSCACHE_CACHE_IS_WITHDRAWN = 4, | |
| +}; | |
| + | |
| +enum fscache_cookie_state { | |
| + FSCACHE_COOKIE_STATE_QUIESCENT = 0, | |
| + FSCACHE_COOKIE_STATE_LOOKING_UP = 1, | |
| + FSCACHE_COOKIE_STATE_CREATING = 2, | |
| + FSCACHE_COOKIE_STATE_ACTIVE = 3, | |
| + FSCACHE_COOKIE_STATE_INVALIDATING = 4, | |
| + FSCACHE_COOKIE_STATE_FAILED = 5, | |
| + FSCACHE_COOKIE_STATE_LRU_DISCARDING = 6, | |
| + FSCACHE_COOKIE_STATE_WITHDRAWING = 7, | |
| + FSCACHE_COOKIE_STATE_RELINQUISHING = 8, | |
| + FSCACHE_COOKIE_STATE_DROPPED = 9, | |
| +} __attribute__((mode(byte))); | |
| + | |
| +enum fscache_want_state { | |
| + FSCACHE_WANT_PARAMS = 0, | |
| + FSCACHE_WANT_WRITE = 1, | |
| + FSCACHE_WANT_READ = 2, | |
| +}; | |
| + | |
| enum fsconfig_command { | |
| FSCONFIG_SET_FLAG = 0, | |
| FSCONFIG_SET_STRING = 1, | |
| @@ -16318,6 +17713,7 @@ | |
| FSCONFIG_SET_FD = 5, | |
| FSCONFIG_CMD_CREATE = 6, | |
| FSCONFIG_CMD_RECONFIGURE = 7, | |
| + FSCONFIG_CMD_CREATE_EXCL = 8, | |
| }; | |
| enum fsl_mc_pool_type { | |
| @@ -16330,11 +17726,17 @@ | |
| enum fsnotify_data_type { | |
| FSNOTIFY_EVENT_NONE = 0, | |
| - FSNOTIFY_EVENT_FILE_RANGE = 1, | |
| - FSNOTIFY_EVENT_PATH = 2, | |
| - FSNOTIFY_EVENT_INODE = 3, | |
| - FSNOTIFY_EVENT_DENTRY = 4, | |
| - FSNOTIFY_EVENT_ERROR = 5, | |
| + FSNOTIFY_EVENT_PATH = 1, | |
| + FSNOTIFY_EVENT_INODE = 2, | |
| + FSNOTIFY_EVENT_DENTRY = 3, | |
| + FSNOTIFY_EVENT_ERROR = 4, | |
| +}; | |
| + | |
| +enum fsnotify_group_prio { | |
| + FSNOTIFY_PRIO_NORMAL = 0, | |
| + FSNOTIFY_PRIO_CONTENT = 1, | |
| + FSNOTIFY_PRIO_PRE_CONTENT = 2, | |
| + __FSNOTIFY_PRIO_NUM = 3, | |
| }; | |
| enum fsnotify_iter_type { | |
| @@ -16367,6 +17769,7 @@ | |
| DUMP_NONE = 0, | |
| DUMP_ALL = 1, | |
| DUMP_ORIG = 2, | |
| + DUMP_PARAM = 3, | |
| }; | |
| enum ftrace_ops_cmd { | |
| @@ -16375,14 +17778,6 @@ | |
| FTRACE_OPS_CMD_DISABLE_SHARE_IPMODIFY_PEER = 2, | |
| }; | |
| -enum fullness_group { | |
| - ZS_INUSE_RATIO_0 = 0, | |
| - ZS_INUSE_RATIO_10 = 1, | |
| - ZS_INUSE_RATIO_99 = 10, | |
| - ZS_INUSE_RATIO_100 = 11, | |
| - NR_FULLNESS_GROUPS = 12, | |
| -}; | |
| - | |
| enum futex_access { | |
| FUTEX_READ = 0, | |
| FUTEX_WRITE = 1, | |
| @@ -16406,6 +17801,14 @@ | |
| FW_STATUS_ABORTED = 3, | |
| }; | |
| +enum fwdb_flags { | |
| + FWDB_FLAG_NO_OFDM = 1, | |
| + FWDB_FLAG_NO_OUTDOOR = 2, | |
| + FWDB_FLAG_DFS = 4, | |
| + FWDB_FLAG_NO_IR = 8, | |
| + FWDB_FLAG_AUTO_BW = 16, | |
| +}; | |
| + | |
| enum gcry_mpi_constants { | |
| MPI_C_ZERO = 0, | |
| MPI_C_ONE = 1, | |
| @@ -16446,12 +17849,6 @@ | |
| GENL_DONT_VALIDATE_DUMP_STRICT = 4, | |
| }; | |
| -enum get_ksm_page_flags { | |
| - GET_KSM_PAGE_NOLOCK = 0, | |
| - GET_KSM_PAGE_LOCK = 1, | |
| - GET_KSM_PAGE_TRYLOCK = 2, | |
| -}; | |
| - | |
| enum gpio_lookup_flags { | |
| GPIO_ACTIVE_HIGH = 0, | |
| GPIO_ACTIVE_LOW = 1, | |
| @@ -16526,9 +17923,10 @@ | |
| group_has_spare = 0, | |
| group_fully_busy = 1, | |
| group_misfit_task = 2, | |
| - group_asym_packing = 3, | |
| - group_imbalanced = 4, | |
| - group_overloaded = 5, | |
| + group_smt_balance = 3, | |
| + group_asym_packing = 4, | |
| + group_imbalanced = 5, | |
| + group_overloaded = 6, | |
| }; | |
| enum handshake_auth { | |
| @@ -16571,7 +17969,10 @@ | |
| HASH_ALGO_SM3_256 = 17, | |
| HASH_ALGO_STREEBOG_256 = 18, | |
| HASH_ALGO_STREEBOG_512 = 19, | |
| - HASH_ALGO__LAST = 20, | |
| + HASH_ALGO_SHA3_256 = 20, | |
| + HASH_ALGO_SHA3_384 = 21, | |
| + HASH_ALGO_SHA3_512 = 22, | |
| + HASH_ALGO__LAST = 23, | |
| }; | |
| enum hctx_type { | |
| @@ -16581,6 +17982,188 @@ | |
| HCTX_MAX_TYPES = 3, | |
| }; | |
| +enum hdmi_3d_structure { | |
| + HDMI_3D_STRUCTURE_INVALID = -1, | |
| + HDMI_3D_STRUCTURE_FRAME_PACKING = 0, | |
| + HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE = 1, | |
| + HDMI_3D_STRUCTURE_LINE_ALTERNATIVE = 2, | |
| + HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL = 3, | |
| + HDMI_3D_STRUCTURE_L_DEPTH = 4, | |
| + HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH = 5, | |
| + HDMI_3D_STRUCTURE_TOP_AND_BOTTOM = 6, | |
| + HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF = 8, | |
| +}; | |
| + | |
| +enum hdmi_active_aspect { | |
| + HDMI_ACTIVE_ASPECT_16_9_TOP = 2, | |
| + HDMI_ACTIVE_ASPECT_14_9_TOP = 3, | |
| + HDMI_ACTIVE_ASPECT_16_9_CENTER = 4, | |
| + HDMI_ACTIVE_ASPECT_PICTURE = 8, | |
| + HDMI_ACTIVE_ASPECT_4_3 = 9, | |
| + HDMI_ACTIVE_ASPECT_16_9 = 10, | |
| + HDMI_ACTIVE_ASPECT_14_9 = 11, | |
| + HDMI_ACTIVE_ASPECT_4_3_SP_14_9 = 13, | |
| + HDMI_ACTIVE_ASPECT_16_9_SP_14_9 = 14, | |
| + HDMI_ACTIVE_ASPECT_16_9_SP_4_3 = 15, | |
| +}; | |
| + | |
| +enum hdmi_audio_coding_type { | |
| + HDMI_AUDIO_CODING_TYPE_STREAM = 0, | |
| + HDMI_AUDIO_CODING_TYPE_PCM = 1, | |
| + HDMI_AUDIO_CODING_TYPE_AC3 = 2, | |
| + HDMI_AUDIO_CODING_TYPE_MPEG1 = 3, | |
| + HDMI_AUDIO_CODING_TYPE_MP3 = 4, | |
| + HDMI_AUDIO_CODING_TYPE_MPEG2 = 5, | |
| + HDMI_AUDIO_CODING_TYPE_AAC_LC = 6, | |
| + HDMI_AUDIO_CODING_TYPE_DTS = 7, | |
| + HDMI_AUDIO_CODING_TYPE_ATRAC = 8, | |
| + HDMI_AUDIO_CODING_TYPE_DSD = 9, | |
| + HDMI_AUDIO_CODING_TYPE_EAC3 = 10, | |
| + HDMI_AUDIO_CODING_TYPE_DTS_HD = 11, | |
| + HDMI_AUDIO_CODING_TYPE_MLP = 12, | |
| + HDMI_AUDIO_CODING_TYPE_DST = 13, | |
| + HDMI_AUDIO_CODING_TYPE_WMA_PRO = 14, | |
| + HDMI_AUDIO_CODING_TYPE_CXT = 15, | |
| +}; | |
| + | |
| +enum hdmi_audio_coding_type_ext { | |
| + HDMI_AUDIO_CODING_TYPE_EXT_CT = 0, | |
| + HDMI_AUDIO_CODING_TYPE_EXT_HE_AAC = 1, | |
| + HDMI_AUDIO_CODING_TYPE_EXT_HE_AAC_V2 = 2, | |
| + HDMI_AUDIO_CODING_TYPE_EXT_MPEG_SURROUND = 3, | |
| + HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC = 4, | |
| + HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_V2 = 5, | |
| + HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC = 6, | |
| + HDMI_AUDIO_CODING_TYPE_EXT_DRA = 7, | |
| + HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_SURROUND = 8, | |
| + HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC_SURROUND = 10, | |
| +}; | |
| + | |
| +enum hdmi_audio_sample_frequency { | |
| + HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM = 0, | |
| + HDMI_AUDIO_SAMPLE_FREQUENCY_32000 = 1, | |
| + HDMI_AUDIO_SAMPLE_FREQUENCY_44100 = 2, | |
| + HDMI_AUDIO_SAMPLE_FREQUENCY_48000 = 3, | |
| + HDMI_AUDIO_SAMPLE_FREQUENCY_88200 = 4, | |
| + HDMI_AUDIO_SAMPLE_FREQUENCY_96000 = 5, | |
| + HDMI_AUDIO_SAMPLE_FREQUENCY_176400 = 6, | |
| + HDMI_AUDIO_SAMPLE_FREQUENCY_192000 = 7, | |
| +}; | |
| + | |
| +enum hdmi_audio_sample_size { | |
| + HDMI_AUDIO_SAMPLE_SIZE_STREAM = 0, | |
| + HDMI_AUDIO_SAMPLE_SIZE_16 = 1, | |
| + HDMI_AUDIO_SAMPLE_SIZE_20 = 2, | |
| + HDMI_AUDIO_SAMPLE_SIZE_24 = 3, | |
| +}; | |
| + | |
| +enum hdmi_colorimetry { | |
| + HDMI_COLORIMETRY_NONE = 0, | |
| + HDMI_COLORIMETRY_ITU_601 = 1, | |
| + HDMI_COLORIMETRY_ITU_709 = 2, | |
| + HDMI_COLORIMETRY_EXTENDED = 3, | |
| +}; | |
| + | |
| +enum hdmi_colorspace { | |
| + HDMI_COLORSPACE_RGB = 0, | |
| + HDMI_COLORSPACE_YUV422 = 1, | |
| + HDMI_COLORSPACE_YUV444 = 2, | |
| + HDMI_COLORSPACE_YUV420 = 3, | |
| + HDMI_COLORSPACE_RESERVED4 = 4, | |
| + HDMI_COLORSPACE_RESERVED5 = 5, | |
| + HDMI_COLORSPACE_RESERVED6 = 6, | |
| + HDMI_COLORSPACE_IDO_DEFINED = 7, | |
| +}; | |
| + | |
| +enum hdmi_content_type { | |
| + HDMI_CONTENT_TYPE_GRAPHICS = 0, | |
| + HDMI_CONTENT_TYPE_PHOTO = 1, | |
| + HDMI_CONTENT_TYPE_CINEMA = 2, | |
| + HDMI_CONTENT_TYPE_GAME = 3, | |
| +}; | |
| + | |
| +enum hdmi_eotf { | |
| + HDMI_EOTF_TRADITIONAL_GAMMA_SDR = 0, | |
| + HDMI_EOTF_TRADITIONAL_GAMMA_HDR = 1, | |
| + HDMI_EOTF_SMPTE_ST2084 = 2, | |
| + HDMI_EOTF_BT_2100_HLG = 3, | |
| +}; | |
| + | |
| +enum hdmi_extended_colorimetry { | |
| + HDMI_EXTENDED_COLORIMETRY_XV_YCC_601 = 0, | |
| + HDMI_EXTENDED_COLORIMETRY_XV_YCC_709 = 1, | |
| + HDMI_EXTENDED_COLORIMETRY_S_YCC_601 = 2, | |
| + HDMI_EXTENDED_COLORIMETRY_OPYCC_601 = 3, | |
| + HDMI_EXTENDED_COLORIMETRY_OPRGB = 4, | |
| + HDMI_EXTENDED_COLORIMETRY_BT2020_CONST_LUM = 5, | |
| + HDMI_EXTENDED_COLORIMETRY_BT2020 = 6, | |
| + HDMI_EXTENDED_COLORIMETRY_RESERVED = 7, | |
| +}; | |
| + | |
| +enum hdmi_infoframe_type { | |
| + HDMI_INFOFRAME_TYPE_VENDOR = 129, | |
| + HDMI_INFOFRAME_TYPE_AVI = 130, | |
| + HDMI_INFOFRAME_TYPE_SPD = 131, | |
| + HDMI_INFOFRAME_TYPE_AUDIO = 132, | |
| + HDMI_INFOFRAME_TYPE_DRM = 135, | |
| +}; | |
| + | |
| +enum hdmi_metadata_type { | |
| + HDMI_STATIC_METADATA_TYPE1 = 0, | |
| +}; | |
| + | |
| +enum hdmi_nups { | |
| + HDMI_NUPS_UNKNOWN = 0, | |
| + HDMI_NUPS_HORIZONTAL = 1, | |
| + HDMI_NUPS_VERTICAL = 2, | |
| + HDMI_NUPS_BOTH = 3, | |
| +}; | |
| + | |
| +enum hdmi_picture_aspect { | |
| + HDMI_PICTURE_ASPECT_NONE = 0, | |
| + HDMI_PICTURE_ASPECT_4_3 = 1, | |
| + HDMI_PICTURE_ASPECT_16_9 = 2, | |
| + HDMI_PICTURE_ASPECT_64_27 = 3, | |
| + HDMI_PICTURE_ASPECT_256_135 = 4, | |
| + HDMI_PICTURE_ASPECT_RESERVED = 5, | |
| +}; | |
| + | |
| +enum hdmi_quantization_range { | |
| + HDMI_QUANTIZATION_RANGE_DEFAULT = 0, | |
| + HDMI_QUANTIZATION_RANGE_LIMITED = 1, | |
| + HDMI_QUANTIZATION_RANGE_FULL = 2, | |
| + HDMI_QUANTIZATION_RANGE_RESERVED = 3, | |
| +}; | |
| + | |
| +enum hdmi_scan_mode { | |
| + HDMI_SCAN_MODE_NONE = 0, | |
| + HDMI_SCAN_MODE_OVERSCAN = 1, | |
| + HDMI_SCAN_MODE_UNDERSCAN = 2, | |
| + HDMI_SCAN_MODE_RESERVED = 3, | |
| +}; | |
| + | |
| +enum hdmi_spd_sdi { | |
| + HDMI_SPD_SDI_UNKNOWN = 0, | |
| + HDMI_SPD_SDI_DSTB = 1, | |
| + HDMI_SPD_SDI_DVDP = 2, | |
| + HDMI_SPD_SDI_DVHS = 3, | |
| + HDMI_SPD_SDI_HDDVR = 4, | |
| + HDMI_SPD_SDI_DVC = 5, | |
| + HDMI_SPD_SDI_DSC = 6, | |
| + HDMI_SPD_SDI_VCD = 7, | |
| + HDMI_SPD_SDI_GAME = 8, | |
| + HDMI_SPD_SDI_PC = 9, | |
| + HDMI_SPD_SDI_BD = 10, | |
| + HDMI_SPD_SDI_SACD = 11, | |
| + HDMI_SPD_SDI_HDDVD = 12, | |
| + HDMI_SPD_SDI_PMP = 13, | |
| +}; | |
| + | |
| +enum hdmi_ycc_quantization_range { | |
| + HDMI_YCC_QUANTIZATION_RANGE_LIMITED = 0, | |
| + HDMI_YCC_QUANTIZATION_RANGE_FULL = 1, | |
| +}; | |
| + | |
| enum header_fields { | |
| HDR_PCR = 0, | |
| HDR_DIGEST = 1, | |
| @@ -16589,10 +18172,11 @@ | |
| HDR__LAST = 4, | |
| }; | |
| -enum hest_status { | |
| - HEST_ENABLED = 0, | |
| - HEST_DISABLED = 1, | |
| - HEST_NOT_FOUND = 2, | |
| +enum hid_bpf_prog_type { | |
| + HID_BPF_PROG_TYPE_UNDEF = -1, | |
| + HID_BPF_PROG_TYPE_DEVICE_EVENT = 0, | |
| + HID_BPF_PROG_TYPE_RDESC_FIXUP = 1, | |
| + HID_BPF_PROG_TYPE_MAX = 2, | |
| }; | |
| enum hid_class_request { | |
| @@ -16617,18 +18201,6 @@ | |
| HID_TYPE_USBNONE = 2, | |
| }; | |
| -enum hk_flags { | |
| - HK_FLAG_TIMER = 1, | |
| - HK_FLAG_RCU = 2, | |
| - HK_FLAG_MISC = 4, | |
| - HK_FLAG_SCHED = 8, | |
| - HK_FLAG_TICK = 16, | |
| - HK_FLAG_DOMAIN = 32, | |
| - HK_FLAG_WQ = 64, | |
| - HK_FLAG_MANAGED_IRQ = 128, | |
| - HK_FLAG_KTHREAD = 256, | |
| -}; | |
| - | |
| enum hk_type { | |
| HK_TYPE_TIMER = 0, | |
| HK_TYPE_RCU = 1, | |
| @@ -16666,6 +18238,18 @@ | |
| HPX_CFG_MAX = 5, | |
| }; | |
| +enum hpx_type3_dev_type { | |
| + HPX_TYPE_ENDPOINT = 1, | |
| + HPX_TYPE_LEG_END = 2, | |
| + HPX_TYPE_RC_END = 4, | |
| + HPX_TYPE_RC_EC = 8, | |
| + HPX_TYPE_ROOT_PORT = 16, | |
| + HPX_TYPE_UPSTREAM = 32, | |
| + HPX_TYPE_DOWNSTREAM = 64, | |
| + HPX_TYPE_PCI_BRIDGE = 128, | |
| + HPX_TYPE_PCIE_BRIDGE = 256, | |
| +}; | |
| + | |
| enum hpx_type3_fn_type { | |
| HPX_FN_NORMAL = 1, | |
| HPX_FN_SRIOV_PHYS = 2, | |
| @@ -16674,6 +18258,7 @@ | |
| enum hr_flags_bits { | |
| HANDSHAKE_F_REQ_COMPLETED = 0, | |
| + HANDSHAKE_F_REQ_SESSION = 1, | |
| }; | |
| enum hrtimer_base_type { | |
| @@ -16711,6 +18296,14 @@ | |
| HRTIMER_RESTART = 1, | |
| }; | |
| +enum hsm_task_states { | |
| + HSM_ST_IDLE = 0, | |
| + HSM_ST_FIRST = 1, | |
| + HSM_ST = 2, | |
| + HSM_ST_LAST = 3, | |
| + HSM_ST_ERR = 4, | |
| +}; | |
| + | |
| enum hub_activation_type { | |
| HUB_INIT = 0, | |
| HUB_INIT2 = 1, | |
| @@ -16753,13 +18346,13 @@ | |
| }; | |
| enum hugetlb_param { | |
| - Opt_gid___4 = 0, | |
| + Opt_gid___5 = 0, | |
| Opt_min_size = 1, | |
| - Opt_mode___3 = 2, | |
| + Opt_mode___4 = 2, | |
| Opt_nr_inodes = 3, | |
| Opt_pagesize = 4, | |
| Opt_size = 5, | |
| - Opt_uid___4 = 6, | |
| + Opt_uid___5 = 6, | |
| }; | |
| enum hugetlbfs_size_type { | |
| @@ -16768,6 +18361,36 @@ | |
| SIZE_PERCENT = 2, | |
| }; | |
| +enum hv_isolation_type { | |
| + HV_ISOLATION_TYPE_NONE = 0, | |
| + HV_ISOLATION_TYPE_VBS = 1, | |
| + HV_ISOLATION_TYPE_SNP = 2, | |
| + HV_ISOLATION_TYPE_TDX = 3, | |
| +}; | |
| + | |
| +enum hv_message_type { | |
| + HVMSG_NONE = 0, | |
| + HVMSG_UNMAPPED_GPA = 2147483648, | |
| + HVMSG_GPA_INTERCEPT = 2147483649, | |
| + HVMSG_TIMER_EXPIRED = 2147483664, | |
| + HVMSG_INVALID_VP_REGISTER_VALUE = 2147483680, | |
| + HVMSG_UNRECOVERABLE_EXCEPTION = 2147483681, | |
| + HVMSG_UNSUPPORTED_FEATURE = 2147483682, | |
| + HVMSG_EVENTLOG_BUFFERCOMPLETE = 2147483712, | |
| + HVMSG_X64_IOPORT_INTERCEPT = 2147549184, | |
| + HVMSG_X64_MSR_INTERCEPT = 2147549185, | |
| + HVMSG_X64_CPUID_INTERCEPT = 2147549186, | |
| + HVMSG_X64_EXCEPTION_INTERCEPT = 2147549187, | |
| + HVMSG_X64_APIC_EOI = 2147549188, | |
| + HVMSG_X64_LEGACY_FP_ERROR = 2147549189, | |
| +}; | |
| + | |
| +enum hv_tlb_flush_fifos { | |
| + HV_L1_TLB_FLUSH_FIFO = 0, | |
| + HV_L2_TLB_FLUSH_FIFO = 1, | |
| + HV_NR_TLB_FLUSH_FIFOS = 2, | |
| +}; | |
| + | |
| enum hv_tsc_page_status { | |
| HV_TSC_PAGE_UNSET = 0, | |
| HV_TSC_PAGE_GUEST_CHANGED = 1, | |
| @@ -16797,6 +18420,7 @@ | |
| hwmon_chip_in_samples = 9, | |
| hwmon_chip_power_samples = 10, | |
| hwmon_chip_temp_samples = 11, | |
| + hwmon_chip_beep_enable = 12, | |
| }; | |
| enum hwmon_curr_attributes { | |
| @@ -16818,6 +18442,7 @@ | |
| hwmon_curr_crit_alarm = 15, | |
| hwmon_curr_rated_min = 16, | |
| hwmon_curr_rated_max = 17, | |
| + hwmon_curr_beep = 18, | |
| }; | |
| enum hwmon_energy_attributes { | |
| @@ -16839,6 +18464,7 @@ | |
| hwmon_fan_min_alarm = 9, | |
| hwmon_fan_max_alarm = 10, | |
| hwmon_fan_fault = 11, | |
| + hwmon_fan_beep = 12, | |
| }; | |
| enum hwmon_humidity_attributes { | |
| @@ -16853,6 +18479,8 @@ | |
| hwmon_humidity_fault = 8, | |
| hwmon_humidity_rated_min = 9, | |
| hwmon_humidity_rated_max = 10, | |
| + hwmon_humidity_min_alarm = 11, | |
| + hwmon_humidity_max_alarm = 12, | |
| }; | |
| enum hwmon_in_attributes { | |
| @@ -16874,6 +18502,13 @@ | |
| hwmon_in_crit_alarm = 15, | |
| hwmon_in_rated_min = 16, | |
| hwmon_in_rated_max = 17, | |
| + hwmon_in_beep = 18, | |
| + hwmon_in_fault = 19, | |
| +}; | |
| + | |
| +enum hwmon_intrusion_attributes { | |
| + hwmon_intrusion_alarm = 0, | |
| + hwmon_intrusion_beep = 1, | |
| }; | |
| enum hwmon_power_attributes { | |
| @@ -16910,6 +18545,14 @@ | |
| hwmon_power_rated_max = 30, | |
| }; | |
| +enum hwmon_pwm_attributes { | |
| + hwmon_pwm_input = 0, | |
| + hwmon_pwm_enable = 1, | |
| + hwmon_pwm_mode = 2, | |
| + hwmon_pwm_freq = 3, | |
| + hwmon_pwm_auto_channels_temp = 4, | |
| +}; | |
| + | |
| enum hwmon_sensor_types { | |
| hwmon_chip = 0, | |
| hwmon_temp = 1, | |
| @@ -16952,6 +18595,17 @@ | |
| hwmon_temp_reset_history = 24, | |
| hwmon_temp_rated_min = 25, | |
| hwmon_temp_rated_max = 26, | |
| + hwmon_temp_beep = 27, | |
| +}; | |
| + | |
| +enum hwparam_type { | |
| + hwparam_ioport = 0, | |
| + hwparam_iomem = 1, | |
| + hwparam_ioport_or_iomem = 2, | |
| + hwparam_irq = 3, | |
| + hwparam_dma = 4, | |
| + hwparam_dma_addr = 5, | |
| + hwparam_other = 6, | |
| }; | |
| enum hwtstamp_flags { | |
| @@ -16980,6 +18634,11 @@ | |
| __HWTSTAMP_FILTER_CNT = 16, | |
| }; | |
| +enum hwtstamp_source { | |
| + HWTSTAMP_SOURCE_NETDEV = 0, | |
| + HWTSTAMP_SOURCE_PHYLIB = 1, | |
| +}; | |
| + | |
| enum hwtstamp_tx_types { | |
| HWTSTAMP_TX_OFF = 0, | |
| HWTSTAMP_TX_ON = 1, | |
| @@ -16988,19 +18647,17 @@ | |
| __HWTSTAMP_TX_CNT = 4, | |
| }; | |
| -enum hybrid_pmu_type { | |
| - hybrid_big = 64, | |
| - hybrid_small = 32, | |
| - hybrid_big_small = 96, | |
| -}; | |
| - | |
| -enum i2c_alert_protocol { | |
| - I2C_PROTOCOL_SMBUS_ALERT = 0, | |
| - I2C_PROTOCOL_SMBUS_HOST_NOTIFY = 1, | |
| +enum hybrid_cpu_type { | |
| + HYBRID_INTEL_NONE = 0, | |
| + HYBRID_INTEL_ATOM = 32, | |
| + HYBRID_INTEL_CORE = 64, | |
| }; | |
| -enum i2c_driver_flags { | |
| - I2C_DRV_ACPI_WAIVE_D0_PROBE = 1, | |
| +enum hybrid_pmu_type { | |
| + not_hybrid = 0, | |
| + hybrid_small = 1, | |
| + hybrid_big = 2, | |
| + hybrid_big_small = 3, | |
| }; | |
| enum i8042_controller_reset_mode { | |
| @@ -17194,12 +18851,155 @@ | |
| IB_T10DIF_CSUM = 1, | |
| }; | |
| +enum ib_uverbs_access_flags { | |
| + IB_UVERBS_ACCESS_LOCAL_WRITE = 1, | |
| + IB_UVERBS_ACCESS_REMOTE_WRITE = 2, | |
| + IB_UVERBS_ACCESS_REMOTE_READ = 4, | |
| + IB_UVERBS_ACCESS_REMOTE_ATOMIC = 8, | |
| + IB_UVERBS_ACCESS_MW_BIND = 16, | |
| + IB_UVERBS_ACCESS_ZERO_BASED = 32, | |
| + IB_UVERBS_ACCESS_ON_DEMAND = 64, | |
| + IB_UVERBS_ACCESS_HUGETLB = 128, | |
| + IB_UVERBS_ACCESS_FLUSH_GLOBAL = 256, | |
| + IB_UVERBS_ACCESS_FLUSH_PERSISTENT = 512, | |
| + IB_UVERBS_ACCESS_RELAXED_ORDERING = 1048576, | |
| + IB_UVERBS_ACCESS_OPTIONAL_RANGE = 1072693248, | |
| +}; | |
| + | |
| enum ib_uverbs_advise_mr_advice { | |
| IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH = 0, | |
| IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE = 1, | |
| IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT = 2, | |
| }; | |
| +enum ib_uverbs_create_qp_mask { | |
| + IB_UVERBS_CREATE_QP_MASK_IND_TABLE = 1, | |
| +}; | |
| + | |
| +enum ib_uverbs_gid_type { | |
| + IB_UVERBS_GID_TYPE_IB = 0, | |
| + IB_UVERBS_GID_TYPE_ROCE_V1 = 1, | |
| + IB_UVERBS_GID_TYPE_ROCE_V2 = 2, | |
| +}; | |
| + | |
| +enum ib_uverbs_qp_create_flags { | |
| + IB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 2, | |
| + IB_UVERBS_QP_CREATE_SCATTER_FCS = 256, | |
| + IB_UVERBS_QP_CREATE_CVLAN_STRIPPING = 512, | |
| + IB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING = 2048, | |
| + IB_UVERBS_QP_CREATE_SQ_SIG_ALL = 4096, | |
| +}; | |
| + | |
| +enum ib_uverbs_qp_type { | |
| + IB_UVERBS_QPT_RC = 2, | |
| + IB_UVERBS_QPT_UC = 3, | |
| + IB_UVERBS_QPT_UD = 4, | |
| + IB_UVERBS_QPT_RAW_PACKET = 8, | |
| + IB_UVERBS_QPT_XRC_INI = 9, | |
| + IB_UVERBS_QPT_XRC_TGT = 10, | |
| + IB_UVERBS_QPT_DRIVER = 255, | |
| +}; | |
| + | |
| +enum ib_uverbs_raw_packet_caps { | |
| + IB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING = 1, | |
| + IB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS = 2, | |
| + IB_UVERBS_RAW_PACKET_CAP_IP_CSUM = 4, | |
| + IB_UVERBS_RAW_PACKET_CAP_DELAY_DROP = 8, | |
| +}; | |
| + | |
| +enum ib_uverbs_srq_type { | |
| + IB_UVERBS_SRQT_BASIC = 0, | |
| + IB_UVERBS_SRQT_XRC = 1, | |
| + IB_UVERBS_SRQT_TM = 2, | |
| +}; | |
| + | |
| +enum ib_uverbs_wc_opcode { | |
| + IB_UVERBS_WC_SEND = 0, | |
| + IB_UVERBS_WC_RDMA_WRITE = 1, | |
| + IB_UVERBS_WC_RDMA_READ = 2, | |
| + IB_UVERBS_WC_COMP_SWAP = 3, | |
| + IB_UVERBS_WC_FETCH_ADD = 4, | |
| + IB_UVERBS_WC_BIND_MW = 5, | |
| + IB_UVERBS_WC_LOCAL_INV = 6, | |
| + IB_UVERBS_WC_TSO = 7, | |
| + IB_UVERBS_WC_FLUSH = 8, | |
| + IB_UVERBS_WC_ATOMIC_WRITE = 9, | |
| +}; | |
| + | |
| +enum ib_uverbs_wq_flags { | |
| + IB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING = 1, | |
| + IB_UVERBS_WQ_FLAGS_SCATTER_FCS = 2, | |
| + IB_UVERBS_WQ_FLAGS_DELAY_DROP = 4, | |
| + IB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING = 8, | |
| +}; | |
| + | |
| +enum ib_uverbs_wq_type { | |
| + IB_UVERBS_WQT_RQ = 0, | |
| +}; | |
| + | |
| +enum ib_uverbs_wr_opcode { | |
| + IB_UVERBS_WR_RDMA_WRITE = 0, | |
| + IB_UVERBS_WR_RDMA_WRITE_WITH_IMM = 1, | |
| + IB_UVERBS_WR_SEND = 2, | |
| + IB_UVERBS_WR_SEND_WITH_IMM = 3, | |
| + IB_UVERBS_WR_RDMA_READ = 4, | |
| + IB_UVERBS_WR_ATOMIC_CMP_AND_SWP = 5, | |
| + IB_UVERBS_WR_ATOMIC_FETCH_AND_ADD = 6, | |
| + IB_UVERBS_WR_LOCAL_INV = 7, | |
| + IB_UVERBS_WR_BIND_MW = 8, | |
| + IB_UVERBS_WR_SEND_WITH_INV = 9, | |
| + IB_UVERBS_WR_TSO = 10, | |
| + IB_UVERBS_WR_RDMA_READ_WITH_INV = 11, | |
| + IB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = 12, | |
| + IB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13, | |
| + IB_UVERBS_WR_FLUSH = 14, | |
| + IB_UVERBS_WR_ATOMIC_WRITE = 15, | |
| +}; | |
| + | |
| +enum ib_uverbs_write_cmds { | |
| + IB_USER_VERBS_CMD_GET_CONTEXT = 0, | |
| + IB_USER_VERBS_CMD_QUERY_DEVICE = 1, | |
| + IB_USER_VERBS_CMD_QUERY_PORT = 2, | |
| + IB_USER_VERBS_CMD_ALLOC_PD = 3, | |
| + IB_USER_VERBS_CMD_DEALLOC_PD = 4, | |
| + IB_USER_VERBS_CMD_CREATE_AH = 5, | |
| + IB_USER_VERBS_CMD_MODIFY_AH = 6, | |
| + IB_USER_VERBS_CMD_QUERY_AH = 7, | |
| + IB_USER_VERBS_CMD_DESTROY_AH = 8, | |
| + IB_USER_VERBS_CMD_REG_MR = 9, | |
| + IB_USER_VERBS_CMD_REG_SMR = 10, | |
| + IB_USER_VERBS_CMD_REREG_MR = 11, | |
| + IB_USER_VERBS_CMD_QUERY_MR = 12, | |
| + IB_USER_VERBS_CMD_DEREG_MR = 13, | |
| + IB_USER_VERBS_CMD_ALLOC_MW = 14, | |
| + IB_USER_VERBS_CMD_BIND_MW = 15, | |
| + IB_USER_VERBS_CMD_DEALLOC_MW = 16, | |
| + IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL = 17, | |
| + IB_USER_VERBS_CMD_CREATE_CQ = 18, | |
| + IB_USER_VERBS_CMD_RESIZE_CQ = 19, | |
| + IB_USER_VERBS_CMD_DESTROY_CQ = 20, | |
| + IB_USER_VERBS_CMD_POLL_CQ = 21, | |
| + IB_USER_VERBS_CMD_PEEK_CQ = 22, | |
| + IB_USER_VERBS_CMD_REQ_NOTIFY_CQ = 23, | |
| + IB_USER_VERBS_CMD_CREATE_QP = 24, | |
| + IB_USER_VERBS_CMD_QUERY_QP = 25, | |
| + IB_USER_VERBS_CMD_MODIFY_QP = 26, | |
| + IB_USER_VERBS_CMD_DESTROY_QP = 27, | |
| + IB_USER_VERBS_CMD_POST_SEND = 28, | |
| + IB_USER_VERBS_CMD_POST_RECV = 29, | |
| + IB_USER_VERBS_CMD_ATTACH_MCAST = 30, | |
| + IB_USER_VERBS_CMD_DETACH_MCAST = 31, | |
| + IB_USER_VERBS_CMD_CREATE_SRQ = 32, | |
| + IB_USER_VERBS_CMD_MODIFY_SRQ = 33, | |
| + IB_USER_VERBS_CMD_QUERY_SRQ = 34, | |
| + IB_USER_VERBS_CMD_DESTROY_SRQ = 35, | |
| + IB_USER_VERBS_CMD_POST_SRQ_RECV = 36, | |
| + IB_USER_VERBS_CMD_OPEN_XRCD = 37, | |
| + IB_USER_VERBS_CMD_CLOSE_XRCD = 38, | |
| + IB_USER_VERBS_CMD_CREATE_XSRQ = 39, | |
| + IB_USER_VERBS_CMD_OPEN_QP = 40, | |
| +}; | |
| + | |
| enum ib_wc_opcode { | |
| IB_WC_SEND = 0, | |
| IB_WC_RDMA_WRITE = 1, | |
| @@ -17300,11 +19100,6 @@ | |
| IB_MTU_4096___2 = 5, | |
| }; | |
| -enum id_action { | |
| - ID_REMOVE = 0, | |
| - ID_ADD = 1, | |
| -}; | |
| - | |
| enum idle_boot_override { | |
| IDLE_NO_OVERRIDE = 0, | |
| IDLE_HALT = 1, | |
| @@ -17312,188 +19107,1373 @@ | |
| IDLE_POLL = 3, | |
| }; | |
| -enum ieee_attrs { | |
| - DCB_ATTR_IEEE_UNSPEC = 0, | |
| - DCB_ATTR_IEEE_ETS = 1, | |
| - DCB_ATTR_IEEE_PFC = 2, | |
| - DCB_ATTR_IEEE_APP_TABLE = 3, | |
| - DCB_ATTR_IEEE_PEER_ETS = 4, | |
| - DCB_ATTR_IEEE_PEER_PFC = 5, | |
| - DCB_ATTR_IEEE_PEER_APP = 6, | |
| - DCB_ATTR_IEEE_MAXRATE = 7, | |
| - DCB_ATTR_IEEE_QCN = 8, | |
| - DCB_ATTR_IEEE_QCN_STATS = 9, | |
| - DCB_ATTR_DCB_BUFFER = 10, | |
| - DCB_ATTR_DCB_APP_TRUST_TABLE = 11, | |
| - DCB_ATTR_DCB_REWR_TABLE = 12, | |
| - __DCB_ATTR_IEEE_MAX = 13, | |
| +enum ieee80211_ac_numbers { | |
| + IEEE80211_AC_VO = 0, | |
| + IEEE80211_AC_VI = 1, | |
| + IEEE80211_AC_BE = 2, | |
| + IEEE80211_AC_BK = 3, | |
| }; | |
| -enum ieee_attrs_app { | |
| - DCB_ATTR_IEEE_APP_UNSPEC = 0, | |
| - DCB_ATTR_IEEE_APP = 1, | |
| - DCB_ATTR_DCB_APP = 2, | |
| - __DCB_ATTR_IEEE_APP_MAX = 3, | |
| +enum ieee80211_agg_stop_reason { | |
| + AGG_STOP_DECLINED = 0, | |
| + AGG_STOP_LOCAL_REQUEST = 1, | |
| + AGG_STOP_PEER_REQUEST = 2, | |
| + AGG_STOP_DESTROY_STA = 3, | |
| }; | |
| -enum igb_diagnostics_results { | |
| - TEST_REG = 0, | |
| - TEST_EEP = 1, | |
| - TEST_IRQ = 2, | |
| - TEST_LOOP = 3, | |
| - TEST_LINK = 4, | |
| +enum ieee80211_ampdu_mlme_action { | |
| + IEEE80211_AMPDU_RX_START = 0, | |
| + IEEE80211_AMPDU_RX_STOP = 1, | |
| + IEEE80211_AMPDU_TX_START = 2, | |
| + IEEE80211_AMPDU_TX_STOP_CONT = 3, | |
| + IEEE80211_AMPDU_TX_STOP_FLUSH = 4, | |
| + IEEE80211_AMPDU_TX_STOP_FLUSH_CONT = 5, | |
| + IEEE80211_AMPDU_TX_OPERATIONAL = 6, | |
| }; | |
| -enum igb_filter_match_flags { | |
| - IGB_FILTER_FLAG_ETHER_TYPE = 1, | |
| - IGB_FILTER_FLAG_VLAN_TCI = 2, | |
| - IGB_FILTER_FLAG_SRC_MAC_ADDR = 4, | |
| - IGB_FILTER_FLAG_DST_MAC_ADDR = 8, | |
| +enum ieee80211_ap_reg_power { | |
| + IEEE80211_REG_UNSET_AP = 0, | |
| + IEEE80211_REG_LPI_AP = 1, | |
| + IEEE80211_REG_SP_AP = 2, | |
| + IEEE80211_REG_VLP_AP = 3, | |
| + IEEE80211_REG_AP_POWER_AFTER_LAST = 4, | |
| + IEEE80211_REG_AP_POWER_MAX = 3, | |
| }; | |
| -enum igb_tx_buf_type { | |
| - IGB_TYPE_SKB = 0, | |
| - IGB_TYPE_XDP = 1, | |
| +enum ieee80211_back_actioncode { | |
| + WLAN_ACTION_ADDBA_REQ = 0, | |
| + WLAN_ACTION_ADDBA_RESP = 1, | |
| + WLAN_ACTION_DELBA = 2, | |
| }; | |
| -enum igb_tx_flags { | |
| - IGB_TX_FLAGS_VLAN = 1, | |
| - IGB_TX_FLAGS_TSO = 2, | |
| - IGB_TX_FLAGS_TSTAMP = 4, | |
| - IGB_TX_FLAGS_IPV4 = 16, | |
| - IGB_TX_FLAGS_CSUM = 32, | |
| +enum ieee80211_back_parties { | |
| + WLAN_BACK_RECIPIENT = 0, | |
| + WLAN_BACK_INITIATOR = 1, | |
| }; | |
| -enum ii_ids { | |
| - II_MEM = 0, | |
| - II_RESV = 1, | |
| - II_IO = 2, | |
| - II_GEN = 3, | |
| +enum ieee80211_bss_corrupt_data_flags { | |
| + IEEE80211_BSS_CORRUPT_BEACON = 1, | |
| + IEEE80211_BSS_CORRUPT_PROBE_RESP = 2, | |
| }; | |
| -enum iio_available_type { | |
| - IIO_AVAIL_LIST = 0, | |
| - IIO_AVAIL_RANGE = 1, | |
| +enum ieee80211_bss_type { | |
| + IEEE80211_BSS_TYPE_ESS = 0, | |
| + IEEE80211_BSS_TYPE_PBSS = 1, | |
| + IEEE80211_BSS_TYPE_IBSS = 2, | |
| + IEEE80211_BSS_TYPE_MBSS = 3, | |
| + IEEE80211_BSS_TYPE_ANY = 4, | |
| }; | |
| -enum iio_buffer_direction { | |
| - IIO_BUFFER_DIRECTION_IN = 0, | |
| - IIO_BUFFER_DIRECTION_OUT = 1, | |
| +enum ieee80211_bss_valid_data_flags { | |
| + IEEE80211_BSS_VALID_WMM = 2, | |
| + IEEE80211_BSS_VALID_RATES = 4, | |
| + IEEE80211_BSS_VALID_ERP = 8, | |
| }; | |
| -enum iio_chan_info_enum { | |
| - IIO_CHAN_INFO_RAW = 0, | |
| - IIO_CHAN_INFO_PROCESSED = 1, | |
| - IIO_CHAN_INFO_SCALE = 2, | |
| - IIO_CHAN_INFO_OFFSET = 3, | |
| - IIO_CHAN_INFO_CALIBSCALE = 4, | |
| - IIO_CHAN_INFO_CALIBBIAS = 5, | |
| - IIO_CHAN_INFO_PEAK = 6, | |
| - IIO_CHAN_INFO_PEAK_SCALE = 7, | |
| - IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW = 8, | |
| - IIO_CHAN_INFO_AVERAGE_RAW = 9, | |
| - IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY = 10, | |
| - IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY = 11, | |
| - IIO_CHAN_INFO_SAMP_FREQ = 12, | |
| - IIO_CHAN_INFO_FREQUENCY = 13, | |
| - IIO_CHAN_INFO_PHASE = 14, | |
| - IIO_CHAN_INFO_HARDWAREGAIN = 15, | |
| - IIO_CHAN_INFO_HYSTERESIS = 16, | |
| - IIO_CHAN_INFO_HYSTERESIS_RELATIVE = 17, | |
| - IIO_CHAN_INFO_INT_TIME = 18, | |
| - IIO_CHAN_INFO_ENABLE = 19, | |
| - IIO_CHAN_INFO_CALIBHEIGHT = 20, | |
| - IIO_CHAN_INFO_CALIBWEIGHT = 21, | |
| - IIO_CHAN_INFO_DEBOUNCE_COUNT = 22, | |
| - IIO_CHAN_INFO_DEBOUNCE_TIME = 23, | |
| - IIO_CHAN_INFO_CALIBEMISSIVITY = 24, | |
| - IIO_CHAN_INFO_OVERSAMPLING_RATIO = 25, | |
| - IIO_CHAN_INFO_THERMOCOUPLE_TYPE = 26, | |
| - IIO_CHAN_INFO_CALIBAMBIENT = 27, | |
| - IIO_CHAN_INFO_ZEROPOINT = 28, | |
| +enum ieee80211_category { | |
| + WLAN_CATEGORY_SPECTRUM_MGMT = 0, | |
| + WLAN_CATEGORY_QOS = 1, | |
| + WLAN_CATEGORY_DLS = 2, | |
| + WLAN_CATEGORY_BACK = 3, | |
| + WLAN_CATEGORY_PUBLIC = 4, | |
| + WLAN_CATEGORY_RADIO_MEASUREMENT = 5, | |
| + WLAN_CATEGORY_FAST_BBS_TRANSITION = 6, | |
| + WLAN_CATEGORY_HT = 7, | |
| + WLAN_CATEGORY_SA_QUERY = 8, | |
| + WLAN_CATEGORY_PROTECTED_DUAL_OF_ACTION = 9, | |
| + WLAN_CATEGORY_WNM = 10, | |
| + WLAN_CATEGORY_WNM_UNPROTECTED = 11, | |
| + WLAN_CATEGORY_TDLS = 12, | |
| + WLAN_CATEGORY_MESH_ACTION = 13, | |
| + WLAN_CATEGORY_MULTIHOP_ACTION = 14, | |
| + WLAN_CATEGORY_SELF_PROTECTED = 15, | |
| + WLAN_CATEGORY_DMG = 16, | |
| + WLAN_CATEGORY_WMM = 17, | |
| + WLAN_CATEGORY_FST = 18, | |
| + WLAN_CATEGORY_UNPROT_DMG = 20, | |
| + WLAN_CATEGORY_VHT = 21, | |
| + WLAN_CATEGORY_S1G = 22, | |
| + WLAN_CATEGORY_PROTECTED_EHT = 37, | |
| + WLAN_CATEGORY_VENDOR_SPECIFIC_PROTECTED = 126, | |
| + WLAN_CATEGORY_VENDOR_SPECIFIC = 127, | |
| }; | |
| -enum iio_chan_type { | |
| - IIO_VOLTAGE = 0, | |
| - IIO_CURRENT = 1, | |
| - IIO_POWER = 2, | |
| - IIO_ACCEL = 3, | |
| - IIO_ANGL_VEL = 4, | |
| - IIO_MAGN = 5, | |
| - IIO_LIGHT = 6, | |
| - IIO_INTENSITY = 7, | |
| - IIO_PROXIMITY = 8, | |
| - IIO_TEMP = 9, | |
| - IIO_INCLI = 10, | |
| - IIO_ROT = 11, | |
| - IIO_ANGL = 12, | |
| - IIO_TIMESTAMP = 13, | |
| - IIO_CAPACITANCE = 14, | |
| - IIO_ALTVOLTAGE = 15, | |
| - IIO_CCT = 16, | |
| - IIO_PRESSURE = 17, | |
| - IIO_HUMIDITYRELATIVE = 18, | |
| - IIO_ACTIVITY = 19, | |
| - IIO_STEPS = 20, | |
| - IIO_ENERGY = 21, | |
| - IIO_DISTANCE = 22, | |
| - IIO_VELOCITY = 23, | |
| - IIO_CONCENTRATION = 24, | |
| - IIO_RESISTANCE = 25, | |
| - IIO_PH = 26, | |
| - IIO_UVINDEX = 27, | |
| - IIO_ELECTRICALCONDUCTIVITY = 28, | |
| - IIO_COUNT = 29, | |
| - IIO_INDEX = 30, | |
| - IIO_GRAVITY = 31, | |
| - IIO_POSITIONRELATIVE = 32, | |
| - IIO_PHASE = 33, | |
| - IIO_MASSCONCENTRATION = 34, | |
| +enum ieee80211_chanctx_change { | |
| + IEEE80211_CHANCTX_CHANGE_WIDTH = 1, | |
| + IEEE80211_CHANCTX_CHANGE_RX_CHAINS = 2, | |
| + IEEE80211_CHANCTX_CHANGE_RADAR = 4, | |
| + IEEE80211_CHANCTX_CHANGE_CHANNEL = 8, | |
| + IEEE80211_CHANCTX_CHANGE_MIN_WIDTH = 16, | |
| + IEEE80211_CHANCTX_CHANGE_AP = 32, | |
| + IEEE80211_CHANCTX_CHANGE_PUNCTURING = 64, | |
| }; | |
| -enum iio_endian { | |
| - IIO_CPU = 0, | |
| - IIO_BE = 1, | |
| - IIO_LE = 2, | |
| +enum ieee80211_chanctx_mode { | |
| + IEEE80211_CHANCTX_SHARED = 0, | |
| + IEEE80211_CHANCTX_EXCLUSIVE = 1, | |
| }; | |
| -enum iio_event_direction { | |
| - IIO_EV_DIR_EITHER = 0, | |
| - IIO_EV_DIR_RISING = 1, | |
| - IIO_EV_DIR_FALLING = 2, | |
| - IIO_EV_DIR_NONE = 3, | |
| - IIO_EV_DIR_SINGLETAP = 4, | |
| - IIO_EV_DIR_DOUBLETAP = 5, | |
| +enum ieee80211_chanctx_replace_state { | |
| + IEEE80211_CHANCTX_REPLACE_NONE = 0, | |
| + IEEE80211_CHANCTX_WILL_BE_REPLACED = 1, | |
| + IEEE80211_CHANCTX_REPLACES_OTHER = 2, | |
| }; | |
| -enum iio_event_info { | |
| - IIO_EV_INFO_ENABLE = 0, | |
| - IIO_EV_INFO_VALUE = 1, | |
| - IIO_EV_INFO_HYSTERESIS = 2, | |
| - IIO_EV_INFO_PERIOD = 3, | |
| - IIO_EV_INFO_HIGH_PASS_FILTER_3DB = 4, | |
| - IIO_EV_INFO_LOW_PASS_FILTER_3DB = 5, | |
| - IIO_EV_INFO_TIMEOUT = 6, | |
| - IIO_EV_INFO_RESET_TIMEOUT = 7, | |
| - IIO_EV_INFO_TAP2_MIN_DELAY = 8, | |
| +enum ieee80211_chanctx_switch_mode { | |
| + CHANCTX_SWMODE_REASSIGN_VIF = 0, | |
| + CHANCTX_SWMODE_SWAP_CONTEXTS = 1, | |
| }; | |
| -enum iio_event_type { | |
| - IIO_EV_TYPE_THRESH = 0, | |
| - IIO_EV_TYPE_MAG = 1, | |
| - IIO_EV_TYPE_ROC = 2, | |
| - IIO_EV_TYPE_THRESH_ADAPTIVE = 3, | |
| - IIO_EV_TYPE_MAG_ADAPTIVE = 4, | |
| - IIO_EV_TYPE_CHANGE = 5, | |
| - IIO_EV_TYPE_MAG_REFERENCED = 6, | |
| - IIO_EV_TYPE_GESTURE = 7, | |
| +enum ieee80211_channel_flags { | |
| + IEEE80211_CHAN_DISABLED = 1, | |
| + IEEE80211_CHAN_NO_IR = 2, | |
| + IEEE80211_CHAN_PSD = 4, | |
| + IEEE80211_CHAN_RADAR = 8, | |
| + IEEE80211_CHAN_NO_HT40PLUS = 16, | |
| + IEEE80211_CHAN_NO_HT40MINUS = 32, | |
| + IEEE80211_CHAN_NO_OFDM = 64, | |
| + IEEE80211_CHAN_NO_80MHZ = 128, | |
| + IEEE80211_CHAN_NO_160MHZ = 256, | |
| + IEEE80211_CHAN_INDOOR_ONLY = 512, | |
| + IEEE80211_CHAN_IR_CONCURRENT = 1024, | |
| + IEEE80211_CHAN_NO_20MHZ = 2048, | |
| + IEEE80211_CHAN_NO_10MHZ = 4096, | |
| + IEEE80211_CHAN_NO_HE = 8192, | |
| + IEEE80211_CHAN_1MHZ = 16384, | |
| + IEEE80211_CHAN_2MHZ = 32768, | |
| + IEEE80211_CHAN_4MHZ = 65536, | |
| + IEEE80211_CHAN_8MHZ = 131072, | |
| + IEEE80211_CHAN_16MHZ = 262144, | |
| + IEEE80211_CHAN_NO_320MHZ = 524288, | |
| + IEEE80211_CHAN_NO_EHT = 1048576, | |
| + IEEE80211_CHAN_DFS_CONCURRENT = 2097152, | |
| + IEEE80211_CHAN_NO_6GHZ_VLP_CLIENT = 4194304, | |
| + IEEE80211_CHAN_NO_6GHZ_AFC_CLIENT = 8388608, | |
| + IEEE80211_CHAN_CAN_MONITOR = 16777216, | |
| }; | |
| -enum iio_shared_by { | |
| - IIO_SEPARATE = 0, | |
| - IIO_SHARED_BY_TYPE = 1, | |
| - IIO_SHARED_BY_DIR = 2, | |
| - IIO_SHARED_BY_ALL = 3, | |
| +enum ieee80211_conf_changed { | |
| + IEEE80211_CONF_CHANGE_SMPS = 2, | |
| + IEEE80211_CONF_CHANGE_LISTEN_INTERVAL = 4, | |
| + IEEE80211_CONF_CHANGE_MONITOR = 8, | |
| + IEEE80211_CONF_CHANGE_PS = 16, | |
| + IEEE80211_CONF_CHANGE_POWER = 32, | |
| + IEEE80211_CONF_CHANGE_CHANNEL = 64, | |
| + IEEE80211_CONF_CHANGE_RETRY_LIMITS = 128, | |
| + IEEE80211_CONF_CHANGE_IDLE = 256, | |
| +}; | |
| + | |
| +enum ieee80211_conf_flags { | |
| + IEEE80211_CONF_MONITOR = 1, | |
| + IEEE80211_CONF_PS = 2, | |
| + IEEE80211_CONF_IDLE = 4, | |
| + IEEE80211_CONF_OFFCHANNEL = 8, | |
| +}; | |
| + | |
| +enum ieee80211_conn_bw_limit { | |
| + IEEE80211_CONN_BW_LIMIT_20 = 0, | |
| + IEEE80211_CONN_BW_LIMIT_40 = 1, | |
| + IEEE80211_CONN_BW_LIMIT_80 = 2, | |
| + IEEE80211_CONN_BW_LIMIT_160 = 3, | |
| + IEEE80211_CONN_BW_LIMIT_320 = 4, | |
| +}; | |
| + | |
| +enum ieee80211_conn_mode { | |
| + IEEE80211_CONN_MODE_S1G = 0, | |
| + IEEE80211_CONN_MODE_LEGACY = 1, | |
| + IEEE80211_CONN_MODE_HT = 2, | |
| + IEEE80211_CONN_MODE_VHT = 3, | |
| + IEEE80211_CONN_MODE_HE = 4, | |
| + IEEE80211_CONN_MODE_EHT = 5, | |
| +}; | |
| + | |
| +enum ieee80211_edmg_bw_config { | |
| + IEEE80211_EDMG_BW_CONFIG_4 = 4, | |
| + IEEE80211_EDMG_BW_CONFIG_5 = 5, | |
| + IEEE80211_EDMG_BW_CONFIG_6 = 6, | |
| + IEEE80211_EDMG_BW_CONFIG_7 = 7, | |
| + IEEE80211_EDMG_BW_CONFIG_8 = 8, | |
| + IEEE80211_EDMG_BW_CONFIG_9 = 9, | |
| + IEEE80211_EDMG_BW_CONFIG_10 = 10, | |
| + IEEE80211_EDMG_BW_CONFIG_11 = 11, | |
| + IEEE80211_EDMG_BW_CONFIG_12 = 12, | |
| + IEEE80211_EDMG_BW_CONFIG_13 = 13, | |
| + IEEE80211_EDMG_BW_CONFIG_14 = 14, | |
| + IEEE80211_EDMG_BW_CONFIG_15 = 15, | |
| +}; | |
| + | |
| +enum ieee80211_eid { | |
| + WLAN_EID_SSID = 0, | |
| + WLAN_EID_SUPP_RATES = 1, | |
| + WLAN_EID_FH_PARAMS = 2, | |
| + WLAN_EID_DS_PARAMS = 3, | |
| + WLAN_EID_CF_PARAMS = 4, | |
| + WLAN_EID_TIM = 5, | |
| + WLAN_EID_IBSS_PARAMS = 6, | |
| + WLAN_EID_COUNTRY = 7, | |
| + WLAN_EID_REQUEST = 10, | |
| + WLAN_EID_QBSS_LOAD = 11, | |
| + WLAN_EID_EDCA_PARAM_SET = 12, | |
| + WLAN_EID_TSPEC = 13, | |
| + WLAN_EID_TCLAS = 14, | |
| + WLAN_EID_SCHEDULE = 15, | |
| + WLAN_EID_CHALLENGE = 16, | |
| + WLAN_EID_PWR_CONSTRAINT = 32, | |
| + WLAN_EID_PWR_CAPABILITY = 33, | |
| + WLAN_EID_TPC_REQUEST = 34, | |
| + WLAN_EID_TPC_REPORT = 35, | |
| + WLAN_EID_SUPPORTED_CHANNELS = 36, | |
| + WLAN_EID_CHANNEL_SWITCH = 37, | |
| + WLAN_EID_MEASURE_REQUEST = 38, | |
| + WLAN_EID_MEASURE_REPORT = 39, | |
| + WLAN_EID_QUIET = 40, | |
| + WLAN_EID_IBSS_DFS = 41, | |
| + WLAN_EID_ERP_INFO = 42, | |
| + WLAN_EID_TS_DELAY = 43, | |
| + WLAN_EID_TCLAS_PROCESSING = 44, | |
| + WLAN_EID_HT_CAPABILITY = 45, | |
| + WLAN_EID_QOS_CAPA = 46, | |
| + WLAN_EID_RSN = 48, | |
| + WLAN_EID_802_15_COEX = 49, | |
| + WLAN_EID_EXT_SUPP_RATES = 50, | |
| + WLAN_EID_AP_CHAN_REPORT = 51, | |
| + WLAN_EID_NEIGHBOR_REPORT = 52, | |
| + WLAN_EID_RCPI = 53, | |
| + WLAN_EID_MOBILITY_DOMAIN = 54, | |
| + WLAN_EID_FAST_BSS_TRANSITION = 55, | |
| + WLAN_EID_TIMEOUT_INTERVAL = 56, | |
| + WLAN_EID_RIC_DATA = 57, | |
| + WLAN_EID_DSE_REGISTERED_LOCATION = 58, | |
| + WLAN_EID_SUPPORTED_REGULATORY_CLASSES = 59, | |
| + WLAN_EID_EXT_CHANSWITCH_ANN = 60, | |
| + WLAN_EID_HT_OPERATION = 61, | |
| + WLAN_EID_SECONDARY_CHANNEL_OFFSET = 62, | |
| + WLAN_EID_BSS_AVG_ACCESS_DELAY = 63, | |
| + WLAN_EID_ANTENNA_INFO = 64, | |
| + WLAN_EID_RSNI = 65, | |
| + WLAN_EID_MEASUREMENT_PILOT_TX_INFO = 66, | |
| + WLAN_EID_BSS_AVAILABLE_CAPACITY = 67, | |
| + WLAN_EID_BSS_AC_ACCESS_DELAY = 68, | |
| + WLAN_EID_TIME_ADVERTISEMENT = 69, | |
| + WLAN_EID_RRM_ENABLED_CAPABILITIES = 70, | |
| + WLAN_EID_MULTIPLE_BSSID = 71, | |
| + WLAN_EID_BSS_COEX_2040 = 72, | |
| + WLAN_EID_BSS_INTOLERANT_CHL_REPORT = 73, | |
| + WLAN_EID_OVERLAP_BSS_SCAN_PARAM = 74, | |
| + WLAN_EID_RIC_DESCRIPTOR = 75, | |
| + WLAN_EID_MMIE = 76, | |
| + WLAN_EID_ASSOC_COMEBACK_TIME = 77, | |
| + WLAN_EID_EVENT_REQUEST = 78, | |
| + WLAN_EID_EVENT_REPORT = 79, | |
| + WLAN_EID_DIAGNOSTIC_REQUEST = 80, | |
| + WLAN_EID_DIAGNOSTIC_REPORT = 81, | |
| + WLAN_EID_LOCATION_PARAMS = 82, | |
| + WLAN_EID_NON_TX_BSSID_CAP = 83, | |
| + WLAN_EID_SSID_LIST = 84, | |
| + WLAN_EID_MULTI_BSSID_IDX = 85, | |
| + WLAN_EID_FMS_DESCRIPTOR = 86, | |
| + WLAN_EID_FMS_REQUEST = 87, | |
| + WLAN_EID_FMS_RESPONSE = 88, | |
| + WLAN_EID_QOS_TRAFFIC_CAPA = 89, | |
| + WLAN_EID_BSS_MAX_IDLE_PERIOD = 90, | |
| + WLAN_EID_TSF_REQUEST = 91, | |
| + WLAN_EID_TSF_RESPOSNE = 92, | |
| + WLAN_EID_WNM_SLEEP_MODE = 93, | |
| + WLAN_EID_TIM_BCAST_REQ = 94, | |
| + WLAN_EID_TIM_BCAST_RESP = 95, | |
| + WLAN_EID_COLL_IF_REPORT = 96, | |
| + WLAN_EID_CHANNEL_USAGE = 97, | |
| + WLAN_EID_TIME_ZONE = 98, | |
| + WLAN_EID_DMS_REQUEST = 99, | |
| + WLAN_EID_DMS_RESPONSE = 100, | |
| + WLAN_EID_LINK_ID = 101, | |
| + WLAN_EID_WAKEUP_SCHEDUL = 102, | |
| + WLAN_EID_CHAN_SWITCH_TIMING = 104, | |
| + WLAN_EID_PTI_CONTROL = 105, | |
| + WLAN_EID_PU_BUFFER_STATUS = 106, | |
| + WLAN_EID_INTERWORKING = 107, | |
| + WLAN_EID_ADVERTISEMENT_PROTOCOL = 108, | |
| + WLAN_EID_EXPEDITED_BW_REQ = 109, | |
| + WLAN_EID_QOS_MAP_SET = 110, | |
| + WLAN_EID_ROAMING_CONSORTIUM = 111, | |
| + WLAN_EID_EMERGENCY_ALERT = 112, | |
| + WLAN_EID_MESH_CONFIG = 113, | |
| + WLAN_EID_MESH_ID = 114, | |
| + WLAN_EID_LINK_METRIC_REPORT = 115, | |
| + WLAN_EID_CONGESTION_NOTIFICATION = 116, | |
| + WLAN_EID_PEER_MGMT = 117, | |
| + WLAN_EID_CHAN_SWITCH_PARAM = 118, | |
| + WLAN_EID_MESH_AWAKE_WINDOW = 119, | |
| + WLAN_EID_BEACON_TIMING = 120, | |
| + WLAN_EID_MCCAOP_SETUP_REQ = 121, | |
| + WLAN_EID_MCCAOP_SETUP_RESP = 122, | |
| + WLAN_EID_MCCAOP_ADVERT = 123, | |
| + WLAN_EID_MCCAOP_TEARDOWN = 124, | |
| + WLAN_EID_GANN = 125, | |
| + WLAN_EID_RANN = 126, | |
| + WLAN_EID_EXT_CAPABILITY = 127, | |
| + WLAN_EID_PREQ = 130, | |
| + WLAN_EID_PREP = 131, | |
| + WLAN_EID_PERR = 132, | |
| + WLAN_EID_PXU = 137, | |
| + WLAN_EID_PXUC = 138, | |
| + WLAN_EID_AUTH_MESH_PEER_EXCH = 139, | |
| + WLAN_EID_MIC = 140, | |
| + WLAN_EID_DESTINATION_URI = 141, | |
| + WLAN_EID_UAPSD_COEX = 142, | |
| + WLAN_EID_WAKEUP_SCHEDULE = 143, | |
| + WLAN_EID_EXT_SCHEDULE = 144, | |
| + WLAN_EID_STA_AVAILABILITY = 145, | |
| + WLAN_EID_DMG_TSPEC = 146, | |
| + WLAN_EID_DMG_AT = 147, | |
| + WLAN_EID_DMG_CAP = 148, | |
| + WLAN_EID_CISCO_VENDOR_SPECIFIC = 150, | |
| + WLAN_EID_DMG_OPERATION = 151, | |
| + WLAN_EID_DMG_BSS_PARAM_CHANGE = 152, | |
| + WLAN_EID_DMG_BEAM_REFINEMENT = 153, | |
| + WLAN_EID_CHANNEL_MEASURE_FEEDBACK = 154, | |
| + WLAN_EID_AWAKE_WINDOW = 157, | |
| + WLAN_EID_MULTI_BAND = 158, | |
| + WLAN_EID_ADDBA_EXT = 159, | |
| + WLAN_EID_NEXT_PCP_LIST = 160, | |
| + WLAN_EID_PCP_HANDOVER = 161, | |
| + WLAN_EID_DMG_LINK_MARGIN = 162, | |
| + WLAN_EID_SWITCHING_STREAM = 163, | |
| + WLAN_EID_SESSION_TRANSITION = 164, | |
| + WLAN_EID_DYN_TONE_PAIRING_REPORT = 165, | |
| + WLAN_EID_CLUSTER_REPORT = 166, | |
| + WLAN_EID_RELAY_CAP = 167, | |
| + WLAN_EID_RELAY_XFER_PARAM_SET = 168, | |
| + WLAN_EID_BEAM_LINK_MAINT = 169, | |
| + WLAN_EID_MULTIPLE_MAC_ADDR = 170, | |
| + WLAN_EID_U_PID = 171, | |
| + WLAN_EID_DMG_LINK_ADAPT_ACK = 172, | |
| + WLAN_EID_MCCAOP_ADV_OVERVIEW = 174, | |
| + WLAN_EID_QUIET_PERIOD_REQ = 175, | |
| + WLAN_EID_QUIET_PERIOD_RESP = 177, | |
| + WLAN_EID_EPAC_POLICY = 182, | |
| + WLAN_EID_CLISTER_TIME_OFF = 183, | |
| + WLAN_EID_INTER_AC_PRIO = 184, | |
| + WLAN_EID_SCS_DESCRIPTOR = 185, | |
| + WLAN_EID_QLOAD_REPORT = 186, | |
| + WLAN_EID_HCCA_TXOP_UPDATE_COUNT = 187, | |
| + WLAN_EID_HL_STREAM_ID = 188, | |
| + WLAN_EID_GCR_GROUP_ADDR = 189, | |
| + WLAN_EID_ANTENNA_SECTOR_ID_PATTERN = 190, | |
| + WLAN_EID_VHT_CAPABILITY = 191, | |
| + WLAN_EID_VHT_OPERATION = 192, | |
| + WLAN_EID_EXTENDED_BSS_LOAD = 193, | |
| + WLAN_EID_WIDE_BW_CHANNEL_SWITCH = 194, | |
| + WLAN_EID_TX_POWER_ENVELOPE = 195, | |
| + WLAN_EID_CHANNEL_SWITCH_WRAPPER = 196, | |
| + WLAN_EID_AID = 197, | |
| + WLAN_EID_QUIET_CHANNEL = 198, | |
| + WLAN_EID_OPMODE_NOTIF = 199, | |
| + WLAN_EID_REDUCED_NEIGHBOR_REPORT = 201, | |
| + WLAN_EID_AID_REQUEST = 210, | |
| + WLAN_EID_AID_RESPONSE = 211, | |
| + WLAN_EID_S1G_BCN_COMPAT = 213, | |
| + WLAN_EID_S1G_SHORT_BCN_INTERVAL = 214, | |
| + WLAN_EID_S1G_TWT = 216, | |
| + WLAN_EID_S1G_CAPABILITIES = 217, | |
| + WLAN_EID_VENDOR_SPECIFIC = 221, | |
| + WLAN_EID_QOS_PARAMETER = 222, | |
| + WLAN_EID_S1G_OPERATION = 232, | |
| + WLAN_EID_CAG_NUMBER = 237, | |
| + WLAN_EID_AP_CSN = 239, | |
| + WLAN_EID_FILS_INDICATION = 240, | |
| + WLAN_EID_DILS = 241, | |
| + WLAN_EID_FRAGMENT = 242, | |
| + WLAN_EID_RSNX = 244, | |
| + WLAN_EID_EXTENSION = 255, | |
| +}; | |
| + | |
| +enum ieee80211_eid_ext { | |
| + WLAN_EID_EXT_ASSOC_DELAY_INFO = 1, | |
| + WLAN_EID_EXT_FILS_REQ_PARAMS = 2, | |
| + WLAN_EID_EXT_FILS_KEY_CONFIRM = 3, | |
| + WLAN_EID_EXT_FILS_SESSION = 4, | |
| + WLAN_EID_EXT_FILS_HLP_CONTAINER = 5, | |
| + WLAN_EID_EXT_FILS_IP_ADDR_ASSIGN = 6, | |
| + WLAN_EID_EXT_KEY_DELIVERY = 7, | |
| + WLAN_EID_EXT_FILS_WRAPPED_DATA = 8, | |
| + WLAN_EID_EXT_FILS_PUBLIC_KEY = 12, | |
| + WLAN_EID_EXT_FILS_NONCE = 13, | |
| + WLAN_EID_EXT_FUTURE_CHAN_GUIDANCE = 14, | |
| + WLAN_EID_EXT_HE_CAPABILITY = 35, | |
| + WLAN_EID_EXT_HE_OPERATION = 36, | |
| + WLAN_EID_EXT_UORA = 37, | |
| + WLAN_EID_EXT_HE_MU_EDCA = 38, | |
| + WLAN_EID_EXT_HE_SPR = 39, | |
| + WLAN_EID_EXT_NDP_FEEDBACK_REPORT_PARAMSET = 41, | |
| + WLAN_EID_EXT_BSS_COLOR_CHG_ANN = 42, | |
| + WLAN_EID_EXT_QUIET_TIME_PERIOD_SETUP = 43, | |
| + WLAN_EID_EXT_ESS_REPORT = 45, | |
| + WLAN_EID_EXT_OPS = 46, | |
| + WLAN_EID_EXT_HE_BSS_LOAD = 47, | |
| + WLAN_EID_EXT_MAX_CHANNEL_SWITCH_TIME = 52, | |
| + WLAN_EID_EXT_MULTIPLE_BSSID_CONFIGURATION = 55, | |
| + WLAN_EID_EXT_NON_INHERITANCE = 56, | |
| + WLAN_EID_EXT_KNOWN_BSSID = 57, | |
| + WLAN_EID_EXT_SHORT_SSID_LIST = 58, | |
| + WLAN_EID_EXT_HE_6GHZ_CAPA = 59, | |
| + WLAN_EID_EXT_UL_MU_POWER_CAPA = 60, | |
| + WLAN_EID_EXT_EHT_OPERATION = 106, | |
| + WLAN_EID_EXT_EHT_MULTI_LINK = 107, | |
| + WLAN_EID_EXT_EHT_CAPABILITY = 108, | |
| + WLAN_EID_EXT_TID_TO_LINK_MAPPING = 109, | |
| + WLAN_EID_EXT_BANDWIDTH_INDICATION = 135, | |
| +}; | |
| + | |
| +enum ieee80211_elems_parse_error { | |
| + IEEE80211_PARSE_ERR_INVALID_END = 1, | |
| + IEEE80211_PARSE_ERR_DUP_ELEM = 2, | |
| + IEEE80211_PARSE_ERR_BAD_ELEM_SIZE = 4, | |
| + IEEE80211_PARSE_ERR_UNEXPECTED_ELEM = 8, | |
| + IEEE80211_PARSE_ERR_DUP_NEST_ML_BASIC = 16, | |
| +}; | |
| + | |
| +enum ieee80211_encrypt { | |
| + ENCRYPT_NO = 0, | |
| + ENCRYPT_MGMT = 1, | |
| + ENCRYPT_DATA = 2, | |
| +}; | |
| + | |
| +enum ieee80211_event_type { | |
| + RSSI_EVENT = 0, | |
| + MLME_EVENT = 1, | |
| + BAR_RX_EVENT = 2, | |
| + BA_FRAME_TIMEOUT = 3, | |
| +}; | |
| + | |
| +enum ieee80211_filter_flags { | |
| + FIF_ALLMULTI = 2, | |
| + FIF_FCSFAIL = 4, | |
| + FIF_PLCPFAIL = 8, | |
| + FIF_BCN_PRBRESP_PROMISC = 16, | |
| + FIF_CONTROL = 32, | |
| + FIF_OTHER_BSS = 64, | |
| + FIF_PSPOLL = 128, | |
| + FIF_PROBE_REQ = 256, | |
| + FIF_MCAST_ACTION = 512, | |
| +}; | |
| + | |
| +enum ieee80211_frame_release_type { | |
| + IEEE80211_FRAME_RELEASE_PSPOLL = 0, | |
| + IEEE80211_FRAME_RELEASE_UAPSD = 1, | |
| +}; | |
| + | |
| +enum ieee80211_he_mcs_support { | |
| + IEEE80211_HE_MCS_SUPPORT_0_7 = 0, | |
| + IEEE80211_HE_MCS_SUPPORT_0_9 = 1, | |
| + IEEE80211_HE_MCS_SUPPORT_0_11 = 2, | |
| + IEEE80211_HE_MCS_NOT_SUPPORTED = 3, | |
| +}; | |
| + | |
| +enum ieee80211_ht_actioncode { | |
| + WLAN_HT_ACTION_NOTIFY_CHANWIDTH = 0, | |
| + WLAN_HT_ACTION_SMPS = 1, | |
| + WLAN_HT_ACTION_PSMP = 2, | |
| + WLAN_HT_ACTION_PCO_PHASE = 3, | |
| + WLAN_HT_ACTION_CSI = 4, | |
| + WLAN_HT_ACTION_NONCOMPRESSED_BF = 5, | |
| + WLAN_HT_ACTION_COMPRESSED_BF = 6, | |
| + WLAN_HT_ACTION_ASEL_IDX_FEEDBACK = 7, | |
| +}; | |
| + | |
| +enum ieee80211_ht_chanwidth_values { | |
| + IEEE80211_HT_CHANWIDTH_20MHZ = 0, | |
| + IEEE80211_HT_CHANWIDTH_ANY = 1, | |
| +}; | |
| + | |
| +enum ieee80211_hw_flags { | |
| + IEEE80211_HW_HAS_RATE_CONTROL = 0, | |
| + IEEE80211_HW_RX_INCLUDES_FCS = 1, | |
| + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING = 2, | |
| + IEEE80211_HW_SIGNAL_UNSPEC = 3, | |
| + IEEE80211_HW_SIGNAL_DBM = 4, | |
| + IEEE80211_HW_NEED_DTIM_BEFORE_ASSOC = 5, | |
| + IEEE80211_HW_SPECTRUM_MGMT = 6, | |
| + IEEE80211_HW_AMPDU_AGGREGATION = 7, | |
| + IEEE80211_HW_SUPPORTS_PS = 8, | |
| + IEEE80211_HW_PS_NULLFUNC_STACK = 9, | |
| + IEEE80211_HW_SUPPORTS_DYNAMIC_PS = 10, | |
| + IEEE80211_HW_MFP_CAPABLE = 11, | |
| + IEEE80211_HW_WANT_MONITOR_VIF = 12, | |
| + IEEE80211_HW_NO_AUTO_VIF = 13, | |
| + IEEE80211_HW_SW_CRYPTO_CONTROL = 14, | |
| + IEEE80211_HW_SUPPORT_FAST_XMIT = 15, | |
| + IEEE80211_HW_REPORTS_TX_ACK_STATUS = 16, | |
| + IEEE80211_HW_CONNECTION_MONITOR = 17, | |
| + IEEE80211_HW_QUEUE_CONTROL = 18, | |
| + IEEE80211_HW_SUPPORTS_PER_STA_GTK = 19, | |
| + IEEE80211_HW_AP_LINK_PS = 20, | |
| + IEEE80211_HW_TX_AMPDU_SETUP_IN_HW = 21, | |
| + IEEE80211_HW_SUPPORTS_RC_TABLE = 22, | |
| + IEEE80211_HW_P2P_DEV_ADDR_FOR_INTF = 23, | |
| + IEEE80211_HW_TIMING_BEACON_ONLY = 24, | |
| + IEEE80211_HW_SUPPORTS_HT_CCK_RATES = 25, | |
| + IEEE80211_HW_CHANCTX_STA_CSA = 26, | |
| + IEEE80211_HW_SUPPORTS_CLONED_SKBS = 27, | |
| + IEEE80211_HW_SINGLE_SCAN_ON_ALL_BANDS = 28, | |
| + IEEE80211_HW_TDLS_WIDER_BW = 29, | |
| + IEEE80211_HW_SUPPORTS_AMSDU_IN_AMPDU = 30, | |
| + IEEE80211_HW_BEACON_TX_STATUS = 31, | |
| + IEEE80211_HW_NEEDS_UNIQUE_STA_ADDR = 32, | |
| + IEEE80211_HW_SUPPORTS_REORDERING_BUFFER = 33, | |
| + IEEE80211_HW_USES_RSS = 34, | |
| + IEEE80211_HW_TX_AMSDU = 35, | |
| + IEEE80211_HW_TX_FRAG_LIST = 36, | |
| + IEEE80211_HW_REPORTS_LOW_ACK = 37, | |
| + IEEE80211_HW_SUPPORTS_TX_FRAG = 38, | |
| + IEEE80211_HW_SUPPORTS_TDLS_BUFFER_STA = 39, | |
| + IEEE80211_HW_DEAUTH_NEED_MGD_TX_PREP = 40, | |
| + IEEE80211_HW_DOESNT_SUPPORT_QOS_NDP = 41, | |
| + IEEE80211_HW_BUFF_MMPDU_TXQ = 42, | |
| + IEEE80211_HW_SUPPORTS_VHT_EXT_NSS_BW = 43, | |
| + IEEE80211_HW_STA_MMPDU_TXQ = 44, | |
| + IEEE80211_HW_TX_STATUS_NO_AMPDU_LEN = 45, | |
| + IEEE80211_HW_SUPPORTS_MULTI_BSSID = 46, | |
| + IEEE80211_HW_SUPPORTS_ONLY_HE_MULTI_BSSID = 47, | |
| + IEEE80211_HW_AMPDU_KEYBORDER_SUPPORT = 48, | |
| + IEEE80211_HW_SUPPORTS_TX_ENCAP_OFFLOAD = 49, | |
| + IEEE80211_HW_SUPPORTS_RX_DECAP_OFFLOAD = 50, | |
| + IEEE80211_HW_SUPPORTS_CONC_MON_RX_DECAP = 51, | |
| + IEEE80211_HW_DETECTS_COLOR_COLLISION = 52, | |
| + IEEE80211_HW_MLO_MCAST_MULTI_LINK_TX = 53, | |
| + IEEE80211_HW_DISALLOW_PUNCTURING = 54, | |
| + IEEE80211_HW_DISALLOW_PUNCTURING_5GHZ = 55, | |
| + IEEE80211_HW_HANDLES_QUIET_CSA = 56, | |
| + NUM_IEEE80211_HW_FLAGS = 57, | |
| +}; | |
| + | |
| +enum ieee80211_idle_options { | |
| + WLAN_IDLE_OPTIONS_PROTECTED_KEEP_ALIVE = 1, | |
| +}; | |
| + | |
| +enum ieee80211_interface_iteration_flags { | |
| + IEEE80211_IFACE_ITER_NORMAL = 0, | |
| + IEEE80211_IFACE_ITER_RESUME_ALL = 1, | |
| + IEEE80211_IFACE_ITER_ACTIVE = 2, | |
| + IEEE80211_IFACE_SKIP_SDATA_NOT_IN_DRIVER = 4, | |
| +}; | |
| + | |
| +enum ieee80211_internal_key_flags { | |
| + KEY_FLAG_UPLOADED_TO_HARDWARE = 1, | |
| + KEY_FLAG_TAINTED = 2, | |
| +}; | |
| + | |
| +enum ieee80211_internal_tkip_state { | |
| + TKIP_STATE_NOT_INIT = 0, | |
| + TKIP_STATE_PHASE1_DONE = 1, | |
| + TKIP_STATE_PHASE1_HW_UPLOADED = 2, | |
| +}; | |
| + | |
| +enum ieee80211_key_flags { | |
| + IEEE80211_KEY_FLAG_GENERATE_IV_MGMT = 1, | |
| + IEEE80211_KEY_FLAG_GENERATE_IV = 2, | |
| + IEEE80211_KEY_FLAG_GENERATE_MMIC = 4, | |
| + IEEE80211_KEY_FLAG_PAIRWISE = 8, | |
| + IEEE80211_KEY_FLAG_SW_MGMT_TX = 16, | |
| + IEEE80211_KEY_FLAG_PUT_IV_SPACE = 32, | |
| + IEEE80211_KEY_FLAG_RX_MGMT = 64, | |
| + IEEE80211_KEY_FLAG_RESERVE_TAILROOM = 128, | |
| + IEEE80211_KEY_FLAG_PUT_MIC_SPACE = 256, | |
| + IEEE80211_KEY_FLAG_NO_AUTO_TX = 512, | |
| + IEEE80211_KEY_FLAG_GENERATE_MMIE = 1024, | |
| + IEEE80211_KEY_FLAG_SPP_AMSDU = 2048, | |
| +}; | |
| + | |
| +enum ieee80211_key_len { | |
| + WLAN_KEY_LEN_WEP40 = 5, | |
| + WLAN_KEY_LEN_WEP104 = 13, | |
| + WLAN_KEY_LEN_CCMP = 16, | |
| + WLAN_KEY_LEN_CCMP_256 = 32, | |
| + WLAN_KEY_LEN_TKIP = 32, | |
| + WLAN_KEY_LEN_AES_CMAC = 16, | |
| + WLAN_KEY_LEN_SMS4 = 32, | |
| + WLAN_KEY_LEN_GCMP = 16, | |
| + WLAN_KEY_LEN_GCMP_256 = 32, | |
| + WLAN_KEY_LEN_BIP_CMAC_256 = 32, | |
| + WLAN_KEY_LEN_BIP_GMAC_128 = 16, | |
| + WLAN_KEY_LEN_BIP_GMAC_256 = 32, | |
| +}; | |
| + | |
| +enum ieee80211_max_queues { | |
| + IEEE80211_MAX_QUEUES = 16, | |
| + IEEE80211_MAX_QUEUE_MAP = 65535, | |
| +}; | |
| + | |
| +enum ieee80211_mesh_path_metric { | |
| + IEEE80211_PATH_METRIC_AIRTIME = 1, | |
| + IEEE80211_PATH_METRIC_VENDOR = 255, | |
| +}; | |
| + | |
| +enum ieee80211_mesh_path_protocol { | |
| + IEEE80211_PATH_PROTOCOL_HWMP = 1, | |
| + IEEE80211_PATH_PROTOCOL_VENDOR = 255, | |
| +}; | |
| + | |
| +enum ieee80211_mesh_sync_method { | |
| + IEEE80211_SYNC_METHOD_NEIGHBOR_OFFSET = 1, | |
| + IEEE80211_SYNC_METHOD_VENDOR = 255, | |
| +}; | |
| + | |
| +enum ieee80211_mle_subelems { | |
| + IEEE80211_MLE_SUBELEM_PER_STA_PROFILE = 0, | |
| + IEEE80211_MLE_SUBELEM_FRAGMENT = 254, | |
| +}; | |
| + | |
| +enum ieee80211_mlme_event_data { | |
| + AUTH_EVENT = 0, | |
| + ASSOC_EVENT = 1, | |
| + DEAUTH_RX_EVENT = 2, | |
| + DEAUTH_TX_EVENT = 3, | |
| +}; | |
| + | |
| +enum ieee80211_mlme_event_status { | |
| + MLME_SUCCESS = 0, | |
| + MLME_DENIED = 1, | |
| + MLME_TIMEOUT = 2, | |
| +}; | |
| + | |
| +enum ieee80211_neg_ttlm_res { | |
| + NEG_TTLM_RES_ACCEPT = 0, | |
| + NEG_TTLM_RES_REJECT = 1, | |
| + NEG_TTLM_RES_SUGGEST_PREFERRED = 2, | |
| +}; | |
| + | |
| +enum ieee80211_offload_flags { | |
| + IEEE80211_OFFLOAD_ENCAP_ENABLED = 1, | |
| + IEEE80211_OFFLOAD_ENCAP_4ADDR = 2, | |
| + IEEE80211_OFFLOAD_DECAP_ENABLED = 4, | |
| +}; | |
| + | |
| +enum ieee80211_p2p_attr_id { | |
| + IEEE80211_P2P_ATTR_STATUS = 0, | |
| + IEEE80211_P2P_ATTR_MINOR_REASON = 1, | |
| + IEEE80211_P2P_ATTR_CAPABILITY = 2, | |
| + IEEE80211_P2P_ATTR_DEVICE_ID = 3, | |
| + IEEE80211_P2P_ATTR_GO_INTENT = 4, | |
| + IEEE80211_P2P_ATTR_GO_CONFIG_TIMEOUT = 5, | |
| + IEEE80211_P2P_ATTR_LISTEN_CHANNEL = 6, | |
| + IEEE80211_P2P_ATTR_GROUP_BSSID = 7, | |
| + IEEE80211_P2P_ATTR_EXT_LISTEN_TIMING = 8, | |
| + IEEE80211_P2P_ATTR_INTENDED_IFACE_ADDR = 9, | |
| + IEEE80211_P2P_ATTR_MANAGABILITY = 10, | |
| + IEEE80211_P2P_ATTR_CHANNEL_LIST = 11, | |
| + IEEE80211_P2P_ATTR_ABSENCE_NOTICE = 12, | |
| + IEEE80211_P2P_ATTR_DEVICE_INFO = 13, | |
| + IEEE80211_P2P_ATTR_GROUP_INFO = 14, | |
| + IEEE80211_P2P_ATTR_GROUP_ID = 15, | |
| + IEEE80211_P2P_ATTR_INTERFACE = 16, | |
| + IEEE80211_P2P_ATTR_OPER_CHANNEL = 17, | |
| + IEEE80211_P2P_ATTR_INVITE_FLAGS = 18, | |
| + IEEE80211_P2P_ATTR_VENDOR_SPECIFIC = 221, | |
| + IEEE80211_P2P_ATTR_MAX = 222, | |
| +}; | |
| + | |
| +enum ieee80211_packet_rx_flags { | |
| + IEEE80211_RX_AMSDU = 8, | |
| + IEEE80211_RX_MALFORMED_ACTION_FRM = 16, | |
| + IEEE80211_RX_DEFERRED_RELEASE = 32, | |
| +}; | |
| + | |
| +enum ieee80211_privacy { | |
| + IEEE80211_PRIVACY_ON = 0, | |
| + IEEE80211_PRIVACY_OFF = 1, | |
| + IEEE80211_PRIVACY_ANY = 2, | |
| +}; | |
| + | |
| +enum ieee80211_protected_eht_actioncode { | |
| + WLAN_PROTECTED_EHT_ACTION_TTLM_REQ = 0, | |
| + WLAN_PROTECTED_EHT_ACTION_TTLM_RES = 1, | |
| + WLAN_PROTECTED_EHT_ACTION_TTLM_TEARDOWN = 2, | |
| +}; | |
| + | |
| +enum ieee80211_pub_actioncode { | |
| + WLAN_PUB_ACTION_20_40_BSS_COEX = 0, | |
| + WLAN_PUB_ACTION_DSE_ENABLEMENT = 1, | |
| + WLAN_PUB_ACTION_DSE_DEENABLEMENT = 2, | |
| + WLAN_PUB_ACTION_DSE_REG_LOC_ANN = 3, | |
| + WLAN_PUB_ACTION_EXT_CHANSW_ANN = 4, | |
| + WLAN_PUB_ACTION_DSE_MSMT_REQ = 5, | |
| + WLAN_PUB_ACTION_DSE_MSMT_RESP = 6, | |
| + WLAN_PUB_ACTION_MSMT_PILOT = 7, | |
| + WLAN_PUB_ACTION_DSE_PC = 8, | |
| + WLAN_PUB_ACTION_VENDOR_SPECIFIC = 9, | |
| + WLAN_PUB_ACTION_GAS_INITIAL_REQ = 10, | |
| + WLAN_PUB_ACTION_GAS_INITIAL_RESP = 11, | |
| + WLAN_PUB_ACTION_GAS_COMEBACK_REQ = 12, | |
| + WLAN_PUB_ACTION_GAS_COMEBACK_RESP = 13, | |
| + WLAN_PUB_ACTION_TDLS_DISCOVER_RES = 14, | |
| + WLAN_PUB_ACTION_LOC_TRACK_NOTI = 15, | |
| + WLAN_PUB_ACTION_QAB_REQUEST_FRAME = 16, | |
| + WLAN_PUB_ACTION_QAB_RESPONSE_FRAME = 17, | |
| + WLAN_PUB_ACTION_QMF_POLICY = 18, | |
| + WLAN_PUB_ACTION_QMF_POLICY_CHANGE = 19, | |
| + WLAN_PUB_ACTION_QLOAD_REQUEST = 20, | |
| + WLAN_PUB_ACTION_QLOAD_REPORT = 21, | |
| + WLAN_PUB_ACTION_HCCA_TXOP_ADVERT = 22, | |
| + WLAN_PUB_ACTION_HCCA_TXOP_RESPONSE = 23, | |
| + WLAN_PUB_ACTION_PUBLIC_KEY = 24, | |
| + WLAN_PUB_ACTION_CHANNEL_AVAIL_QUERY = 25, | |
| + WLAN_PUB_ACTION_CHANNEL_SCHEDULE_MGMT = 26, | |
| + WLAN_PUB_ACTION_CONTACT_VERI_SIGNAL = 27, | |
| + WLAN_PUB_ACTION_GDD_ENABLEMENT_REQ = 28, | |
| + WLAN_PUB_ACTION_GDD_ENABLEMENT_RESP = 29, | |
| + WLAN_PUB_ACTION_NETWORK_CHANNEL_CONTROL = 30, | |
| + WLAN_PUB_ACTION_WHITE_SPACE_MAP_ANN = 31, | |
| + WLAN_PUB_ACTION_FTM_REQUEST = 32, | |
| + WLAN_PUB_ACTION_FTM_RESPONSE = 33, | |
| + WLAN_PUB_ACTION_FILS_DISCOVERY = 34, | |
| +}; | |
| + | |
| +enum ieee80211_radiotap_ampdu_flags { | |
| + IEEE80211_RADIOTAP_AMPDU_REPORT_ZEROLEN = 1, | |
| + IEEE80211_RADIOTAP_AMPDU_IS_ZEROLEN = 2, | |
| + IEEE80211_RADIOTAP_AMPDU_LAST_KNOWN = 4, | |
| + IEEE80211_RADIOTAP_AMPDU_IS_LAST = 8, | |
| + IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_ERR = 16, | |
| + IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN = 32, | |
| + IEEE80211_RADIOTAP_AMPDU_EOF = 64, | |
| + IEEE80211_RADIOTAP_AMPDU_EOF_KNOWN = 128, | |
| +}; | |
| + | |
| +enum ieee80211_radiotap_channel_flags { | |
| + IEEE80211_CHAN_CCK = 32, | |
| + IEEE80211_CHAN_OFDM = 64, | |
| + IEEE80211_CHAN_2GHZ = 128, | |
| + IEEE80211_CHAN_5GHZ = 256, | |
| + IEEE80211_CHAN_DYN = 1024, | |
| + IEEE80211_CHAN_HALF = 16384, | |
| + IEEE80211_CHAN_QUARTER = 32768, | |
| +}; | |
| + | |
| +enum ieee80211_radiotap_flags { | |
| + IEEE80211_RADIOTAP_F_CFP = 1, | |
| + IEEE80211_RADIOTAP_F_SHORTPRE = 2, | |
| + IEEE80211_RADIOTAP_F_WEP = 4, | |
| + IEEE80211_RADIOTAP_F_FRAG = 8, | |
| + IEEE80211_RADIOTAP_F_FCS = 16, | |
| + IEEE80211_RADIOTAP_F_DATAPAD = 32, | |
| + IEEE80211_RADIOTAP_F_BADFCS = 64, | |
| +}; | |
| + | |
| +enum ieee80211_radiotap_he_bits { | |
| + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MASK = 3, | |
| + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU = 0, | |
| + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_EXT_SU = 1, | |
| + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU = 2, | |
| + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG = 3, | |
| + IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN = 4, | |
| + IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN = 8, | |
| + IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN = 16, | |
| + IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN = 32, | |
| + IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN = 64, | |
| + IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN = 128, | |
| + IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN = 256, | |
| + IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN = 512, | |
| + IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN = 1024, | |
| + IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE2_KNOWN = 2048, | |
| + IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE3_KNOWN = 4096, | |
| + IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE4_KNOWN = 8192, | |
| + IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN = 16384, | |
| + IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN = 32768, | |
| + IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_KNOWN = 1, | |
| + IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN = 2, | |
| + IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN = 4, | |
| + IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN = 8, | |
| + IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN = 16, | |
| + IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN = 32, | |
| + IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN = 64, | |
| + IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN = 128, | |
| + IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET = 16128, | |
| + IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET_KNOWN = 16384, | |
| + IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_SEC = 32768, | |
| + IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR = 63, | |
| + IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE = 64, | |
| + IEEE80211_RADIOTAP_HE_DATA3_UL_DL = 128, | |
| + IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS = 3840, | |
| + IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM = 4096, | |
| + IEEE80211_RADIOTAP_HE_DATA3_CODING = 8192, | |
| + IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG = 16384, | |
| + IEEE80211_RADIOTAP_HE_DATA3_STBC = 32768, | |
| + IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE = 15, | |
| + IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID = 32752, | |
| + IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE1 = 15, | |
| + IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE2 = 240, | |
| + IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE3 = 3840, | |
| + IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE4 = 61440, | |
| + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC = 15, | |
| + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_20MHZ = 0, | |
| + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_40MHZ = 1, | |
| + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_80MHZ = 2, | |
| + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_160MHZ = 3, | |
| + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_26T = 4, | |
| + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_52T = 5, | |
| + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_106T = 6, | |
| + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_242T = 7, | |
| + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_484T = 8, | |
| + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_996T = 9, | |
| + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_2x996T = 10, | |
| + IEEE80211_RADIOTAP_HE_DATA5_GI = 48, | |
| + IEEE80211_RADIOTAP_HE_DATA5_GI_0_8 = 0, | |
| + IEEE80211_RADIOTAP_HE_DATA5_GI_1_6 = 1, | |
| + IEEE80211_RADIOTAP_HE_DATA5_GI_3_2 = 2, | |
| + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE = 192, | |
| + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_UNKNOWN = 0, | |
| + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_1X = 1, | |
| + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_2X = 2, | |
| + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_4X = 3, | |
| + IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS = 1792, | |
| + IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD = 12288, | |
| + IEEE80211_RADIOTAP_HE_DATA5_TXBF = 16384, | |
| + IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG = 32768, | |
| + IEEE80211_RADIOTAP_HE_DATA6_NSTS = 15, | |
| + IEEE80211_RADIOTAP_HE_DATA6_DOPPLER = 16, | |
| + IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_KNOWN = 32, | |
| + IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW = 192, | |
| + IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_20MHZ = 0, | |
| + IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_40MHZ = 1, | |
| + IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_80MHZ = 2, | |
| + IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_160MHZ = 3, | |
| + IEEE80211_RADIOTAP_HE_DATA6_TXOP = 32512, | |
| + IEEE80211_RADIOTAP_HE_DATA6_MIDAMBLE_PDCTY = 32768, | |
| +}; | |
| + | |
| +enum ieee80211_radiotap_mcs_flags { | |
| + IEEE80211_RADIOTAP_MCS_BW_MASK = 3, | |
| + IEEE80211_RADIOTAP_MCS_BW_20 = 0, | |
| + IEEE80211_RADIOTAP_MCS_BW_40 = 1, | |
| + IEEE80211_RADIOTAP_MCS_BW_20L = 2, | |
| + IEEE80211_RADIOTAP_MCS_BW_20U = 3, | |
| + IEEE80211_RADIOTAP_MCS_SGI = 4, | |
| + IEEE80211_RADIOTAP_MCS_FMT_GF = 8, | |
| + IEEE80211_RADIOTAP_MCS_FEC_LDPC = 16, | |
| + IEEE80211_RADIOTAP_MCS_STBC_MASK = 96, | |
| + IEEE80211_RADIOTAP_MCS_STBC_1 = 1, | |
| + IEEE80211_RADIOTAP_MCS_STBC_2 = 2, | |
| + IEEE80211_RADIOTAP_MCS_STBC_3 = 3, | |
| + IEEE80211_RADIOTAP_MCS_STBC_SHIFT = 5, | |
| +}; | |
| + | |
| +enum ieee80211_radiotap_mcs_have { | |
| + IEEE80211_RADIOTAP_MCS_HAVE_BW = 1, | |
| + IEEE80211_RADIOTAP_MCS_HAVE_MCS = 2, | |
| + IEEE80211_RADIOTAP_MCS_HAVE_GI = 4, | |
| + IEEE80211_RADIOTAP_MCS_HAVE_FMT = 8, | |
| + IEEE80211_RADIOTAP_MCS_HAVE_FEC = 16, | |
| + IEEE80211_RADIOTAP_MCS_HAVE_STBC = 32, | |
| +}; | |
| + | |
| +enum ieee80211_radiotap_presence { | |
| + IEEE80211_RADIOTAP_TSFT = 0, | |
| + IEEE80211_RADIOTAP_FLAGS = 1, | |
| + IEEE80211_RADIOTAP_RATE = 2, | |
| + IEEE80211_RADIOTAP_CHANNEL = 3, | |
| + IEEE80211_RADIOTAP_FHSS = 4, | |
| + IEEE80211_RADIOTAP_DBM_ANTSIGNAL = 5, | |
| + IEEE80211_RADIOTAP_DBM_ANTNOISE = 6, | |
| + IEEE80211_RADIOTAP_LOCK_QUALITY = 7, | |
| + IEEE80211_RADIOTAP_TX_ATTENUATION = 8, | |
| + IEEE80211_RADIOTAP_DB_TX_ATTENUATION = 9, | |
| + IEEE80211_RADIOTAP_DBM_TX_POWER = 10, | |
| + IEEE80211_RADIOTAP_ANTENNA = 11, | |
| + IEEE80211_RADIOTAP_DB_ANTSIGNAL = 12, | |
| + IEEE80211_RADIOTAP_DB_ANTNOISE = 13, | |
| + IEEE80211_RADIOTAP_RX_FLAGS = 14, | |
| + IEEE80211_RADIOTAP_TX_FLAGS = 15, | |
| + IEEE80211_RADIOTAP_RTS_RETRIES = 16, | |
| + IEEE80211_RADIOTAP_DATA_RETRIES = 17, | |
| + IEEE80211_RADIOTAP_MCS = 19, | |
| + IEEE80211_RADIOTAP_AMPDU_STATUS = 20, | |
| + IEEE80211_RADIOTAP_VHT = 21, | |
| + IEEE80211_RADIOTAP_TIMESTAMP = 22, | |
| + IEEE80211_RADIOTAP_HE = 23, | |
| + IEEE80211_RADIOTAP_HE_MU = 24, | |
| + IEEE80211_RADIOTAP_ZERO_LEN_PSDU = 26, | |
| + IEEE80211_RADIOTAP_LSIG = 27, | |
| + IEEE80211_RADIOTAP_TLV = 28, | |
| + IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE = 29, | |
| + IEEE80211_RADIOTAP_VENDOR_NAMESPACE = 30, | |
| + IEEE80211_RADIOTAP_EXT = 31, | |
| + IEEE80211_RADIOTAP_EHT_USIG = 33, | |
| + IEEE80211_RADIOTAP_EHT = 34, | |
| +}; | |
| + | |
| +enum ieee80211_radiotap_rx_flags { | |
| + IEEE80211_RADIOTAP_F_RX_BADPLCP = 2, | |
| +}; | |
| + | |
| +enum ieee80211_radiotap_timestamp_flags { | |
| + IEEE80211_RADIOTAP_TIMESTAMP_FLAG_64BIT = 0, | |
| + IEEE80211_RADIOTAP_TIMESTAMP_FLAG_32BIT = 1, | |
| + IEEE80211_RADIOTAP_TIMESTAMP_FLAG_ACCURACY = 2, | |
| +}; | |
| + | |
| +enum ieee80211_radiotap_tx_flags { | |
| + IEEE80211_RADIOTAP_F_TX_FAIL = 1, | |
| + IEEE80211_RADIOTAP_F_TX_CTS = 2, | |
| + IEEE80211_RADIOTAP_F_TX_RTS = 4, | |
| + IEEE80211_RADIOTAP_F_TX_NOACK = 8, | |
| + IEEE80211_RADIOTAP_F_TX_NOSEQNO = 16, | |
| + IEEE80211_RADIOTAP_F_TX_ORDER = 32, | |
| +}; | |
| + | |
| +enum ieee80211_radiotap_vht_coding { | |
| + IEEE80211_RADIOTAP_CODING_LDPC_USER0 = 1, | |
| + IEEE80211_RADIOTAP_CODING_LDPC_USER1 = 2, | |
| + IEEE80211_RADIOTAP_CODING_LDPC_USER2 = 4, | |
| + IEEE80211_RADIOTAP_CODING_LDPC_USER3 = 8, | |
| +}; | |
| + | |
| +enum ieee80211_radiotap_vht_flags { | |
| + IEEE80211_RADIOTAP_VHT_FLAG_STBC = 1, | |
| + IEEE80211_RADIOTAP_VHT_FLAG_TXOP_PS_NA = 2, | |
| + IEEE80211_RADIOTAP_VHT_FLAG_SGI = 4, | |
| + IEEE80211_RADIOTAP_VHT_FLAG_SGI_NSYM_M10_9 = 8, | |
| + IEEE80211_RADIOTAP_VHT_FLAG_LDPC_EXTRA_OFDM_SYM = 16, | |
| + IEEE80211_RADIOTAP_VHT_FLAG_BEAMFORMED = 32, | |
| +}; | |
| + | |
| +enum ieee80211_radiotap_vht_known { | |
| + IEEE80211_RADIOTAP_VHT_KNOWN_STBC = 1, | |
| + IEEE80211_RADIOTAP_VHT_KNOWN_TXOP_PS_NA = 2, | |
| + IEEE80211_RADIOTAP_VHT_KNOWN_GI = 4, | |
| + IEEE80211_RADIOTAP_VHT_KNOWN_SGI_NSYM_DIS = 8, | |
| + IEEE80211_RADIOTAP_VHT_KNOWN_LDPC_EXTRA_OFDM_SYM = 16, | |
| + IEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED = 32, | |
| + IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH = 64, | |
| + IEEE80211_RADIOTAP_VHT_KNOWN_GROUP_ID = 128, | |
| + IEEE80211_RADIOTAP_VHT_KNOWN_PARTIAL_AID = 256, | |
| +}; | |
| + | |
| +enum ieee80211_rate_control_changed { | |
| + IEEE80211_RC_BW_CHANGED = 1, | |
| + IEEE80211_RC_SMPS_CHANGED = 2, | |
| + IEEE80211_RC_SUPP_RATES_CHANGED = 4, | |
| + IEEE80211_RC_NSS_CHANGED = 8, | |
| +}; | |
| + | |
| +enum ieee80211_rate_flags { | |
| + IEEE80211_RATE_SHORT_PREAMBLE = 1, | |
| + IEEE80211_RATE_MANDATORY_A = 2, | |
| + IEEE80211_RATE_MANDATORY_B = 4, | |
| + IEEE80211_RATE_MANDATORY_G = 8, | |
| + IEEE80211_RATE_ERP_G = 16, | |
| + IEEE80211_RATE_SUPPORTS_5MHZ = 32, | |
| + IEEE80211_RATE_SUPPORTS_10MHZ = 64, | |
| +}; | |
| + | |
| +enum ieee80211_reasoncode { | |
| + WLAN_REASON_UNSPECIFIED = 1, | |
| + WLAN_REASON_PREV_AUTH_NOT_VALID = 2, | |
| + WLAN_REASON_DEAUTH_LEAVING = 3, | |
| + WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY = 4, | |
| + WLAN_REASON_DISASSOC_AP_BUSY = 5, | |
| + WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA = 6, | |
| + WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA = 7, | |
| + WLAN_REASON_DISASSOC_STA_HAS_LEFT = 8, | |
| + WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH = 9, | |
| + WLAN_REASON_DISASSOC_BAD_POWER = 10, | |
| + WLAN_REASON_DISASSOC_BAD_SUPP_CHAN = 11, | |
| + WLAN_REASON_INVALID_IE = 13, | |
| + WLAN_REASON_MIC_FAILURE = 14, | |
| + WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT = 15, | |
| + WLAN_REASON_GROUP_KEY_HANDSHAKE_TIMEOUT = 16, | |
| + WLAN_REASON_IE_DIFFERENT = 17, | |
| + WLAN_REASON_INVALID_GROUP_CIPHER = 18, | |
| + WLAN_REASON_INVALID_PAIRWISE_CIPHER = 19, | |
| + WLAN_REASON_INVALID_AKMP = 20, | |
| + WLAN_REASON_UNSUPP_RSN_VERSION = 21, | |
| + WLAN_REASON_INVALID_RSN_IE_CAP = 22, | |
| + WLAN_REASON_IEEE8021X_FAILED = 23, | |
| + WLAN_REASON_CIPHER_SUITE_REJECTED = 24, | |
| + WLAN_REASON_TDLS_TEARDOWN_UNREACHABLE = 25, | |
| + WLAN_REASON_TDLS_TEARDOWN_UNSPECIFIED = 26, | |
| + WLAN_REASON_DISASSOC_UNSPECIFIED_QOS = 32, | |
| + WLAN_REASON_DISASSOC_QAP_NO_BANDWIDTH = 33, | |
| + WLAN_REASON_DISASSOC_LOW_ACK = 34, | |
| + WLAN_REASON_DISASSOC_QAP_EXCEED_TXOP = 35, | |
| + WLAN_REASON_QSTA_LEAVE_QBSS = 36, | |
| + WLAN_REASON_QSTA_NOT_USE = 37, | |
| + WLAN_REASON_QSTA_REQUIRE_SETUP = 38, | |
| + WLAN_REASON_QSTA_TIMEOUT = 39, | |
| + WLAN_REASON_QSTA_CIPHER_NOT_SUPP = 45, | |
| + WLAN_REASON_MESH_PEER_CANCELED = 52, | |
| + WLAN_REASON_MESH_MAX_PEERS = 53, | |
| + WLAN_REASON_MESH_CONFIG = 54, | |
| + WLAN_REASON_MESH_CLOSE = 55, | |
| + WLAN_REASON_MESH_MAX_RETRIES = 56, | |
| + WLAN_REASON_MESH_CONFIRM_TIMEOUT = 57, | |
| + WLAN_REASON_MESH_INVALID_GTK = 58, | |
| + WLAN_REASON_MESH_INCONSISTENT_PARAM = 59, | |
| + WLAN_REASON_MESH_INVALID_SECURITY = 60, | |
| + WLAN_REASON_MESH_PATH_ERROR = 61, | |
| + WLAN_REASON_MESH_PATH_NOFORWARD = 62, | |
| + WLAN_REASON_MESH_PATH_DEST_UNREACHABLE = 63, | |
| + WLAN_REASON_MAC_EXISTS_IN_MBSS = 64, | |
| + WLAN_REASON_MESH_CHAN_REGULATORY = 65, | |
| + WLAN_REASON_MESH_CHAN = 66, | |
| +}; | |
| + | |
| +enum ieee80211_reconfig_type { | |
| + IEEE80211_RECONFIG_TYPE_RESTART = 0, | |
| + IEEE80211_RECONFIG_TYPE_SUSPEND = 1, | |
| +}; | |
| + | |
| +enum ieee80211_regd_source { | |
| + REGD_SOURCE_INTERNAL_DB = 0, | |
| + REGD_SOURCE_CRDA = 1, | |
| + REGD_SOURCE_CACHED = 2, | |
| +}; | |
| + | |
| +enum ieee80211_regulatory_flags { | |
| + REGULATORY_CUSTOM_REG = 1, | |
| + REGULATORY_STRICT_REG = 2, | |
| + REGULATORY_DISABLE_BEACON_HINTS = 4, | |
| + REGULATORY_COUNTRY_IE_FOLLOW_POWER = 8, | |
| + REGULATORY_COUNTRY_IE_IGNORE = 16, | |
| + REGULATORY_ENABLE_RELAX_NO_IR = 32, | |
| + REGULATORY_WIPHY_SELF_MANAGED = 128, | |
| +}; | |
| + | |
| +enum ieee80211_roc_type { | |
| + IEEE80211_ROC_TYPE_NORMAL = 0, | |
| + IEEE80211_ROC_TYPE_MGMT_TX = 1, | |
| +}; | |
| + | |
| +enum ieee80211_rssi_event_data { | |
| + RSSI_EVENT_HIGH = 0, | |
| + RSSI_EVENT_LOW = 1, | |
| +}; | |
| + | |
| +enum ieee80211_rx_flags { | |
| + IEEE80211_RX_CMNTR = 1, | |
| + IEEE80211_RX_BEACON_REPORTED = 2, | |
| +}; | |
| + | |
| +enum ieee80211_s1g_actioncode { | |
| + WLAN_S1G_AID_SWITCH_REQUEST = 0, | |
| + WLAN_S1G_AID_SWITCH_RESPONSE = 1, | |
| + WLAN_S1G_SYNC_CONTROL = 2, | |
| + WLAN_S1G_STA_INFO_ANNOUNCE = 3, | |
| + WLAN_S1G_EDCA_PARAM_SET = 4, | |
| + WLAN_S1G_EL_OPERATION = 5, | |
| + WLAN_S1G_TWT_SETUP = 6, | |
| + WLAN_S1G_TWT_TEARDOWN = 7, | |
| + WLAN_S1G_SECT_GROUP_ID_LIST = 8, | |
| + WLAN_S1G_SECT_ID_FEEDBACK = 9, | |
| + WLAN_S1G_TWT_INFORMATION = 11, | |
| +}; | |
| + | |
| +enum ieee80211_s1g_chanwidth { | |
| + IEEE80211_S1G_CHANWIDTH_1MHZ = 0, | |
| + IEEE80211_S1G_CHANWIDTH_2MHZ = 1, | |
| + IEEE80211_S1G_CHANWIDTH_4MHZ = 3, | |
| + IEEE80211_S1G_CHANWIDTH_8MHZ = 7, | |
| + IEEE80211_S1G_CHANWIDTH_16MHZ = 15, | |
| +}; | |
| + | |
| +enum ieee80211_sa_query_action { | |
| + WLAN_ACTION_SA_QUERY_REQUEST = 0, | |
| + WLAN_ACTION_SA_QUERY_RESPONSE = 1, | |
| +}; | |
| + | |
| +enum ieee80211_sdata_state_bits { | |
| + SDATA_STATE_RUNNING = 0, | |
| + SDATA_STATE_OFFCHANNEL = 1, | |
| + SDATA_STATE_OFFCHANNEL_BEACON_STOPPED = 2, | |
| +}; | |
| + | |
| +enum ieee80211_self_protected_actioncode { | |
| + WLAN_SP_RESERVED = 0, | |
| + WLAN_SP_MESH_PEERING_OPEN = 1, | |
| + WLAN_SP_MESH_PEERING_CONFIRM = 2, | |
| + WLAN_SP_MESH_PEERING_CLOSE = 3, | |
| + WLAN_SP_MGK_INFORM = 4, | |
| + WLAN_SP_MGK_ACK = 5, | |
| +}; | |
| + | |
| +enum ieee80211_smps_mode { | |
| + IEEE80211_SMPS_AUTOMATIC = 0, | |
| + IEEE80211_SMPS_OFF = 1, | |
| + IEEE80211_SMPS_STATIC = 2, | |
| + IEEE80211_SMPS_DYNAMIC = 3, | |
| + IEEE80211_SMPS_NUM_MODES = 4, | |
| +}; | |
| + | |
| +enum ieee80211_spectrum_mgmt_actioncode { | |
| + WLAN_ACTION_SPCT_MSR_REQ = 0, | |
| + WLAN_ACTION_SPCT_MSR_RPRT = 1, | |
| + WLAN_ACTION_SPCT_TPC_REQ = 2, | |
| + WLAN_ACTION_SPCT_TPC_RPRT = 3, | |
| + WLAN_ACTION_SPCT_CHL_SWITCH = 4, | |
| +}; | |
| + | |
| +enum ieee80211_sta_flags { | |
| + IEEE80211_STA_CONNECTION_POLL = 2, | |
| + IEEE80211_STA_CONTROL_PORT = 4, | |
| + IEEE80211_STA_MFP_ENABLED = 64, | |
| + IEEE80211_STA_UAPSD_ENABLED = 128, | |
| + IEEE80211_STA_NULLFUNC_ACKED = 256, | |
| + IEEE80211_STA_ENABLE_RRM = 32768, | |
| +}; | |
| + | |
| +enum ieee80211_sta_info_flags { | |
| + WLAN_STA_AUTH = 0, | |
| + WLAN_STA_ASSOC = 1, | |
| + WLAN_STA_PS_STA = 2, | |
| + WLAN_STA_AUTHORIZED = 3, | |
| + WLAN_STA_SHORT_PREAMBLE = 4, | |
| + WLAN_STA_WDS = 5, | |
| + WLAN_STA_CLEAR_PS_FILT = 6, | |
| + WLAN_STA_MFP = 7, | |
| + WLAN_STA_BLOCK_BA = 8, | |
| + WLAN_STA_PS_DRIVER = 9, | |
| + WLAN_STA_PSPOLL = 10, | |
| + WLAN_STA_TDLS_PEER = 11, | |
| + WLAN_STA_TDLS_PEER_AUTH = 12, | |
| + WLAN_STA_TDLS_INITIATOR = 13, | |
| + WLAN_STA_TDLS_CHAN_SWITCH = 14, | |
| + WLAN_STA_TDLS_OFF_CHANNEL = 15, | |
| + WLAN_STA_TDLS_WIDER_BW = 16, | |
| + WLAN_STA_UAPSD = 17, | |
| + WLAN_STA_SP = 18, | |
| + WLAN_STA_4ADDR_EVENT = 19, | |
| + WLAN_STA_INSERTED = 20, | |
| + WLAN_STA_RATE_CONTROL = 21, | |
| + WLAN_STA_TOFFSET_KNOWN = 22, | |
| + WLAN_STA_MPSP_OWNER = 23, | |
| + WLAN_STA_MPSP_RECIPIENT = 24, | |
| + WLAN_STA_PS_DELIVER = 25, | |
| + WLAN_STA_USES_ENCRYPTION = 26, | |
| + WLAN_STA_DECAP_OFFLOAD = 27, | |
| + NUM_WLAN_STA_FLAGS = 28, | |
| +}; | |
| + | |
| +enum ieee80211_sta_rx_bandwidth { | |
| + IEEE80211_STA_RX_BW_20 = 0, | |
| + IEEE80211_STA_RX_BW_40 = 1, | |
| + IEEE80211_STA_RX_BW_80 = 2, | |
| + IEEE80211_STA_RX_BW_160 = 3, | |
| + IEEE80211_STA_RX_BW_320 = 4, | |
| +}; | |
| + | |
| +enum ieee80211_sta_state { | |
| + IEEE80211_STA_NOTEXIST = 0, | |
| + IEEE80211_STA_NONE = 1, | |
| + IEEE80211_STA_AUTH = 2, | |
| + IEEE80211_STA_ASSOC = 3, | |
| + IEEE80211_STA_AUTHORIZED = 4, | |
| +}; | |
| + | |
| +enum ieee80211_status_data { | |
| + IEEE80211_STATUS_TYPE_MASK = 15, | |
| + IEEE80211_STATUS_TYPE_INVALID = 0, | |
| + IEEE80211_STATUS_TYPE_SMPS = 1, | |
| + IEEE80211_STATUS_TYPE_NEG_TTLM = 2, | |
| + IEEE80211_STATUS_SUBDATA_MASK = 8176, | |
| +}; | |
| + | |
| +enum ieee80211_statuscode { | |
| + WLAN_STATUS_SUCCESS = 0, | |
| + WLAN_STATUS_UNSPECIFIED_FAILURE = 1, | |
| + WLAN_STATUS_CAPS_UNSUPPORTED = 10, | |
| + WLAN_STATUS_REASSOC_NO_ASSOC = 11, | |
| + WLAN_STATUS_ASSOC_DENIED_UNSPEC = 12, | |
| + WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG = 13, | |
| + WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION = 14, | |
| + WLAN_STATUS_CHALLENGE_FAIL = 15, | |
| + WLAN_STATUS_AUTH_TIMEOUT = 16, | |
| + WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA = 17, | |
| + WLAN_STATUS_ASSOC_DENIED_RATES = 18, | |
| + WLAN_STATUS_ASSOC_DENIED_NOSHORTPREAMBLE = 19, | |
| + WLAN_STATUS_ASSOC_DENIED_NOPBCC = 20, | |
| + WLAN_STATUS_ASSOC_DENIED_NOAGILITY = 21, | |
| + WLAN_STATUS_ASSOC_DENIED_NOSPECTRUM = 22, | |
| + WLAN_STATUS_ASSOC_REJECTED_BAD_POWER = 23, | |
| + WLAN_STATUS_ASSOC_REJECTED_BAD_SUPP_CHAN = 24, | |
| + WLAN_STATUS_ASSOC_DENIED_NOSHORTTIME = 25, | |
| + WLAN_STATUS_ASSOC_DENIED_NODSSSOFDM = 26, | |
| + WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY = 30, | |
| + WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION = 31, | |
| + WLAN_STATUS_INVALID_IE = 40, | |
| + WLAN_STATUS_INVALID_GROUP_CIPHER = 41, | |
| + WLAN_STATUS_INVALID_PAIRWISE_CIPHER = 42, | |
| + WLAN_STATUS_INVALID_AKMP = 43, | |
| + WLAN_STATUS_UNSUPP_RSN_VERSION = 44, | |
| + WLAN_STATUS_INVALID_RSN_IE_CAP = 45, | |
| + WLAN_STATUS_CIPHER_SUITE_REJECTED = 46, | |
| + WLAN_STATUS_UNSPECIFIED_QOS = 32, | |
| + WLAN_STATUS_ASSOC_DENIED_NOBANDWIDTH = 33, | |
| + WLAN_STATUS_ASSOC_DENIED_LOWACK = 34, | |
| + WLAN_STATUS_ASSOC_DENIED_UNSUPP_QOS = 35, | |
| + WLAN_STATUS_REQUEST_DECLINED = 37, | |
| + WLAN_STATUS_INVALID_QOS_PARAM = 38, | |
| + WLAN_STATUS_CHANGE_TSPEC = 39, | |
| + WLAN_STATUS_WAIT_TS_DELAY = 47, | |
| + WLAN_STATUS_NO_DIRECT_LINK = 48, | |
| + WLAN_STATUS_STA_NOT_PRESENT = 49, | |
| + WLAN_STATUS_STA_NOT_QSTA = 50, | |
| + WLAN_STATUS_ANTI_CLOG_REQUIRED = 76, | |
| + WLAN_STATUS_FCG_NOT_SUPP = 78, | |
| + WLAN_STATUS_STA_NO_TBTT = 78, | |
| + WLAN_STATUS_REJECTED_WITH_SUGGESTED_CHANGES = 39, | |
| + WLAN_STATUS_REJECTED_FOR_DELAY_PERIOD = 47, | |
| + WLAN_STATUS_REJECT_WITH_SCHEDULE = 83, | |
| + WLAN_STATUS_PENDING_ADMITTING_FST_SESSION = 86, | |
| + WLAN_STATUS_PERFORMING_FST_NOW = 87, | |
| + WLAN_STATUS_PENDING_GAP_IN_BA_WINDOW = 88, | |
| + WLAN_STATUS_REJECT_U_PID_SETTING = 89, | |
| + WLAN_STATUS_REJECT_DSE_BAND = 96, | |
| + WLAN_STATUS_DENIED_WITH_SUGGESTED_BAND_AND_CHANNEL = 99, | |
| + WLAN_STATUS_DENIED_DUE_TO_SPECTRUM_MANAGEMENT = 103, | |
| + WLAN_STATUS_FILS_AUTHENTICATION_FAILURE = 108, | |
| + WLAN_STATUS_UNKNOWN_AUTHENTICATION_SERVER = 109, | |
| + WLAN_STATUS_SAE_HASH_TO_ELEMENT = 126, | |
| + WLAN_STATUS_SAE_PK = 127, | |
| + WLAN_STATUS_DENIED_TID_TO_LINK_MAPPING = 133, | |
| + WLAN_STATUS_PREF_TID_TO_LINK_MAPPING_SUGGESTED = 134, | |
| +}; | |
| + | |
| +enum ieee80211_sub_if_data_flags { | |
| + IEEE80211_SDATA_ALLMULTI = 1, | |
| + IEEE80211_SDATA_DONT_BRIDGE_PACKETS = 8, | |
| + IEEE80211_SDATA_DISCONNECT_RESUME = 16, | |
| + IEEE80211_SDATA_IN_DRIVER = 32, | |
| + IEEE80211_SDATA_DISCONNECT_HW_RESTART = 64, | |
| +}; | |
| + | |
| +enum ieee80211_tdls_actioncode { | |
| + WLAN_TDLS_SETUP_REQUEST = 0, | |
| + WLAN_TDLS_SETUP_RESPONSE = 1, | |
| + WLAN_TDLS_SETUP_CONFIRM = 2, | |
| + WLAN_TDLS_TEARDOWN = 3, | |
| + WLAN_TDLS_PEER_TRAFFIC_INDICATION = 4, | |
| + WLAN_TDLS_CHANNEL_SWITCH_REQUEST = 5, | |
| + WLAN_TDLS_CHANNEL_SWITCH_RESPONSE = 6, | |
| + WLAN_TDLS_PEER_PSM_REQUEST = 7, | |
| + WLAN_TDLS_PEER_PSM_RESPONSE = 8, | |
| + WLAN_TDLS_PEER_TRAFFIC_RESPONSE = 9, | |
| + WLAN_TDLS_DISCOVERY_REQUEST = 10, | |
| +}; | |
| + | |
| +enum ieee80211_timeout_interval_type { | |
| + WLAN_TIMEOUT_REASSOC_DEADLINE = 1, | |
| + WLAN_TIMEOUT_KEY_LIFETIME = 2, | |
| + WLAN_TIMEOUT_ASSOC_COMEBACK = 3, | |
| +}; | |
| + | |
| +enum ieee80211_tpt_led_trigger_flags { | |
| + IEEE80211_TPT_LEDTRIG_FL_RADIO = 1, | |
| + IEEE80211_TPT_LEDTRIG_FL_WORK = 2, | |
| + IEEE80211_TPT_LEDTRIG_FL_CONNECTED = 4, | |
| +}; | |
| + | |
| +enum ieee80211_twt_setup_cmd { | |
| + TWT_SETUP_CMD_REQUEST = 0, | |
| + TWT_SETUP_CMD_SUGGEST = 1, | |
| + TWT_SETUP_CMD_DEMAND = 2, | |
| + TWT_SETUP_CMD_GROUPING = 3, | |
| + TWT_SETUP_CMD_ACCEPT = 4, | |
| + TWT_SETUP_CMD_ALTERNATE = 5, | |
| + TWT_SETUP_CMD_DICTATE = 6, | |
| + TWT_SETUP_CMD_REJECT = 7, | |
| +}; | |
| + | |
| +enum ieee80211_unprotected_wnm_actioncode { | |
| + WLAN_UNPROTECTED_WNM_ACTION_TIM = 0, | |
| + WLAN_UNPROTECTED_WNM_ACTION_TIMING_MEASUREMENT_RESPONSE = 1, | |
| +}; | |
| + | |
| +enum ieee80211_vht_actioncode { | |
| + WLAN_VHT_ACTION_COMPRESSED_BF = 0, | |
| + WLAN_VHT_ACTION_GROUPID_MGMT = 1, | |
| + WLAN_VHT_ACTION_OPMODE_NOTIF = 2, | |
| +}; | |
| + | |
| +enum ieee80211_vht_chanwidth { | |
| + IEEE80211_VHT_CHANWIDTH_USE_HT = 0, | |
| + IEEE80211_VHT_CHANWIDTH_80MHZ = 1, | |
| + IEEE80211_VHT_CHANWIDTH_160MHZ = 2, | |
| + IEEE80211_VHT_CHANWIDTH_80P80MHZ = 3, | |
| +}; | |
| + | |
| +enum ieee80211_vht_mcs_support { | |
| + IEEE80211_VHT_MCS_SUPPORT_0_7 = 0, | |
| + IEEE80211_VHT_MCS_SUPPORT_0_8 = 1, | |
| + IEEE80211_VHT_MCS_SUPPORT_0_9 = 2, | |
| + IEEE80211_VHT_MCS_NOT_SUPPORTED = 3, | |
| +}; | |
| + | |
| +enum ieee80211_vht_opmode_bits { | |
| + IEEE80211_OPMODE_NOTIF_CHANWIDTH_MASK = 3, | |
| + IEEE80211_OPMODE_NOTIF_CHANWIDTH_20MHZ = 0, | |
| + IEEE80211_OPMODE_NOTIF_CHANWIDTH_40MHZ = 1, | |
| + IEEE80211_OPMODE_NOTIF_CHANWIDTH_80MHZ = 2, | |
| + IEEE80211_OPMODE_NOTIF_CHANWIDTH_160MHZ = 3, | |
| + IEEE80211_OPMODE_NOTIF_BW_160_80P80 = 4, | |
| + IEEE80211_OPMODE_NOTIF_RX_NSS_MASK = 112, | |
| + IEEE80211_OPMODE_NOTIF_RX_NSS_SHIFT = 4, | |
| + IEEE80211_OPMODE_NOTIF_RX_NSS_TYPE_BF = 128, | |
| +}; | |
| + | |
| +enum ieee80211_vif_flags { | |
| + IEEE80211_VIF_BEACON_FILTER = 1, | |
| + IEEE80211_VIF_SUPPORTS_CQM_RSSI = 2, | |
| + IEEE80211_VIF_SUPPORTS_UAPSD = 4, | |
| + IEEE80211_VIF_GET_NOA_UPDATE = 8, | |
| + IEEE80211_VIF_EML_ACTIVE = 16, | |
| + IEEE80211_VIF_IGNORE_OFDMA_WIDER_BW = 32, | |
| +}; | |
| + | |
| +enum ieee_attrs { | |
| + DCB_ATTR_IEEE_UNSPEC = 0, | |
| + DCB_ATTR_IEEE_ETS = 1, | |
| + DCB_ATTR_IEEE_PFC = 2, | |
| + DCB_ATTR_IEEE_APP_TABLE = 3, | |
| + DCB_ATTR_IEEE_PEER_ETS = 4, | |
| + DCB_ATTR_IEEE_PEER_PFC = 5, | |
| + DCB_ATTR_IEEE_PEER_APP = 6, | |
| + DCB_ATTR_IEEE_MAXRATE = 7, | |
| + DCB_ATTR_IEEE_QCN = 8, | |
| + DCB_ATTR_IEEE_QCN_STATS = 9, | |
| + DCB_ATTR_DCB_BUFFER = 10, | |
| + DCB_ATTR_DCB_APP_TRUST_TABLE = 11, | |
| + DCB_ATTR_DCB_REWR_TABLE = 12, | |
| + __DCB_ATTR_IEEE_MAX = 13, | |
| +}; | |
| + | |
| +enum ieee_attrs_app { | |
| + DCB_ATTR_IEEE_APP_UNSPEC = 0, | |
| + DCB_ATTR_IEEE_APP = 1, | |
| + DCB_ATTR_DCB_APP = 2, | |
| + __DCB_ATTR_IEEE_APP_MAX = 3, | |
| +}; | |
| + | |
| +enum ifla_geneve_df { | |
| + GENEVE_DF_UNSET = 0, | |
| + GENEVE_DF_SET = 1, | |
| + GENEVE_DF_INHERIT = 2, | |
| + __GENEVE_DF_END = 3, | |
| + GENEVE_DF_MAX = 2, | |
| +}; | |
| + | |
| +enum ifla_vxlan_df { | |
| + VXLAN_DF_UNSET = 0, | |
| + VXLAN_DF_SET = 1, | |
| + VXLAN_DF_INHERIT = 2, | |
| + __VXLAN_DF_END = 3, | |
| + VXLAN_DF_MAX = 2, | |
| +}; | |
| + | |
| +enum ifla_vxlan_label_policy { | |
| + VXLAN_LABEL_FIXED = 0, | |
| + VXLAN_LABEL_INHERIT = 1, | |
| + __VXLAN_LABEL_END = 2, | |
| + VXLAN_LABEL_MAX = 1, | |
| }; | |
| enum ima_fs_flags { | |
| @@ -17527,6 +20507,18 @@ | |
| IMA_SHOW_ASCII = 3, | |
| }; | |
| +enum immed_shift { | |
| + IMMED_SHIFT_0B = 0, | |
| + IMMED_SHIFT_1B = 1, | |
| + IMMED_SHIFT_2B = 2, | |
| +}; | |
| + | |
| +enum immed_width { | |
| + IMMED_WIDTH_ALL = 0, | |
| + IMMED_WIDTH_BYTE = 1, | |
| + IMMED_WIDTH_WORD = 2, | |
| +}; | |
| + | |
| enum in6_addr_gen_mode { | |
| IN6_ADDR_GEN_MODE_EUI64 = 0, | |
| IN6_ADDR_GEN_MODE_NONE = 1, | |
| @@ -17534,17 +20526,13 @@ | |
| IN6_ADDR_GEN_MODE_RANDOM = 3, | |
| }; | |
| -enum index_hashtable_type { | |
| - INDEX_HASHTABLE_HANDSHAKE = 1, | |
| - INDEX_HASHTABLE_KEYPAIR = 2, | |
| -}; | |
| - | |
| enum inet_csk_ack_state_t { | |
| ICSK_ACK_SCHED = 1, | |
| ICSK_ACK_TIMER = 2, | |
| ICSK_ACK_PUSHED = 4, | |
| ICSK_ACK_PUSHED2 = 8, | |
| ICSK_ACK_NOW = 16, | |
| + ICSK_ACK_NOMEM = 32, | |
| }; | |
| typedef enum { | |
| @@ -17645,18 +20633,14 @@ | |
| INTEL_EXCL_EXCLUSIVE = 2, | |
| }; | |
| -enum io_pgtable_fmt { | |
| - ARM_32_LPAE_S1 = 0, | |
| - ARM_32_LPAE_S2 = 1, | |
| - ARM_64_LPAE_S1 = 2, | |
| - ARM_64_LPAE_S2 = 3, | |
| - ARM_V7S = 4, | |
| - ARM_MALI_LPAE = 5, | |
| - AMD_IOMMU_V1 = 6, | |
| - AMD_IOMMU_V2 = 7, | |
| - APPLE_DART = 8, | |
| - APPLE_DART2 = 9, | |
| - IO_PGTABLE_NUM_FMTS = 10, | |
| +enum intercept_words { | |
| + INTERCEPT_CR = 0, | |
| + INTERCEPT_DR = 1, | |
| + INTERCEPT_EXCEPTION = 2, | |
| + INTERCEPT_WORD3 = 3, | |
| + INTERCEPT_WORD4 = 4, | |
| + INTERCEPT_WORD5 = 5, | |
| + MAX_INTERCEPT = 6, | |
| }; | |
| enum io_uring_cmd_flags { | |
| @@ -17672,6 +20656,11 @@ | |
| IO_URING_F_COMPAT = 4096, | |
| }; | |
| +enum io_uring_msg_ring_flags { | |
| + IORING_MSG_DATA = 0, | |
| + IORING_MSG_SEND_FD = 1, | |
| +}; | |
| + | |
| enum io_uring_op { | |
| IORING_OP_NOP = 0, | |
| IORING_OP_READV = 1, | |
| @@ -17728,7 +20717,71 @@ | |
| IORING_OP_FUTEX_WAKE = 52, | |
| IORING_OP_FUTEX_WAITV = 53, | |
| IORING_OP_FIXED_FD_INSTALL = 54, | |
| - IORING_OP_LAST = 55, | |
| + IORING_OP_FTRUNCATE = 55, | |
| + IORING_OP_LAST = 56, | |
| +}; | |
| + | |
| +enum io_uring_register_op { | |
| + IORING_REGISTER_BUFFERS = 0, | |
| + IORING_UNREGISTER_BUFFERS = 1, | |
| + IORING_REGISTER_FILES = 2, | |
| + IORING_UNREGISTER_FILES = 3, | |
| + IORING_REGISTER_EVENTFD = 4, | |
| + IORING_UNREGISTER_EVENTFD = 5, | |
| + IORING_REGISTER_FILES_UPDATE = 6, | |
| + IORING_REGISTER_EVENTFD_ASYNC = 7, | |
| + IORING_REGISTER_PROBE = 8, | |
| + IORING_REGISTER_PERSONALITY = 9, | |
| + IORING_UNREGISTER_PERSONALITY = 10, | |
| + IORING_REGISTER_RESTRICTIONS = 11, | |
| + IORING_REGISTER_ENABLE_RINGS = 12, | |
| + IORING_REGISTER_FILES2 = 13, | |
| + IORING_REGISTER_FILES_UPDATE2 = 14, | |
| + IORING_REGISTER_BUFFERS2 = 15, | |
| + IORING_REGISTER_BUFFERS_UPDATE = 16, | |
| + IORING_REGISTER_IOWQ_AFF = 17, | |
| + IORING_UNREGISTER_IOWQ_AFF = 18, | |
| + IORING_REGISTER_IOWQ_MAX_WORKERS = 19, | |
| + IORING_REGISTER_RING_FDS = 20, | |
| + IORING_UNREGISTER_RING_FDS = 21, | |
| + IORING_REGISTER_PBUF_RING = 22, | |
| + IORING_UNREGISTER_PBUF_RING = 23, | |
| + IORING_REGISTER_SYNC_CANCEL = 24, | |
| + IORING_REGISTER_FILE_ALLOC_RANGE = 25, | |
| + IORING_REGISTER_PBUF_STATUS = 26, | |
| + IORING_REGISTER_NAPI = 27, | |
| + IORING_UNREGISTER_NAPI = 28, | |
| + IORING_REGISTER_LAST = 29, | |
| + IORING_REGISTER_USE_REGISTERED_RING = 2147483648, | |
| +}; | |
| + | |
| +enum io_uring_register_pbuf_ring_flags { | |
| + IOU_PBUF_RING_MMAP = 1, | |
| +}; | |
| + | |
| +enum io_uring_register_restriction_op { | |
| + IORING_RESTRICTION_REGISTER_OP = 0, | |
| + IORING_RESTRICTION_SQE_OP = 1, | |
| + IORING_RESTRICTION_SQE_FLAGS_ALLOWED = 2, | |
| + IORING_RESTRICTION_SQE_FLAGS_REQUIRED = 3, | |
| + IORING_RESTRICTION_LAST = 4, | |
| +}; | |
| + | |
| +enum io_uring_socket_op { | |
| + SOCKET_URING_OP_SIOCINQ = 0, | |
| + SOCKET_URING_OP_SIOCOUTQ = 1, | |
| + SOCKET_URING_OP_GETSOCKOPT = 2, | |
| + SOCKET_URING_OP_SETSOCKOPT = 3, | |
| +}; | |
| + | |
| +enum io_uring_sqe_flags_bit { | |
| + IOSQE_FIXED_FILE_BIT = 0, | |
| + IOSQE_IO_DRAIN_BIT = 1, | |
| + IOSQE_IO_LINK_BIT = 2, | |
| + IOSQE_IO_HARDLINK_BIT = 3, | |
| + IOSQE_ASYNC_BIT = 4, | |
| + IOSQE_BUFFER_SELECT_BIT = 5, | |
| + IOSQE_CQE_SKIP_SUCCESS_BIT = 6, | |
| }; | |
| enum io_wq_cancel { | |
| @@ -17737,6 +20790,25 @@ | |
| IO_WQ_CANCEL_NOTFOUND = 2, | |
| }; | |
| +enum io_wq_type { | |
| + IO_WQ_BOUND = 0, | |
| + IO_WQ_UNBOUND = 1, | |
| +}; | |
| + | |
| +enum ioam6_event_attr { | |
| + IOAM6_EVENT_ATTR_UNSPEC = 0, | |
| + IOAM6_EVENT_ATTR_TRACE_NAMESPACE = 1, | |
| + IOAM6_EVENT_ATTR_TRACE_NODELEN = 2, | |
| + IOAM6_EVENT_ATTR_TRACE_TYPE = 3, | |
| + IOAM6_EVENT_ATTR_TRACE_DATA = 4, | |
| + __IOAM6_EVENT_ATTR_MAX = 5, | |
| +}; | |
| + | |
| +enum ioam6_event_type { | |
| + IOAM6_EVENT_UNSPEC = 0, | |
| + IOAM6_EVENT_TRACE = 1, | |
| +}; | |
| + | |
| enum ioapic_domain_type { | |
| IOAPIC_DOMAIN_INVALID = 0, | |
| IOAPIC_DOMAIN_LEGACY = 1, | |
| @@ -17751,17 +20823,13 @@ | |
| IOAT_INTX = 3, | |
| }; | |
| -enum ioc_running { | |
| - IOC_IDLE = 0, | |
| - IOC_RUNNING = 1, | |
| - IOC_STOP = 2, | |
| -}; | |
| - | |
| enum iommu_cap { | |
| IOMMU_CAP_CACHE_COHERENCY = 0, | |
| IOMMU_CAP_NOEXEC = 1, | |
| IOMMU_CAP_PRE_BOOT_PROTECTION = 2, | |
| IOMMU_CAP_ENFORCE_CACHE_COHERENCY = 3, | |
| + IOMMU_CAP_DEFERRED_FLUSH = 4, | |
| + IOMMU_CAP_DIRTY_TRACKING = 5, | |
| }; | |
| enum iommu_dev_features { | |
| @@ -17774,28 +20842,37 @@ | |
| IOMMU_DMA_MSI_COOKIE = 1, | |
| }; | |
| -enum iommu_fault_type { | |
| - IOMMU_FAULT_DMA_UNRECOV = 1, | |
| - IOMMU_FAULT_PAGE_REQ = 2, | |
| +enum iommu_dma_queue_type { | |
| + IOMMU_DMA_OPTS_PER_CPU_QUEUE = 0, | |
| + IOMMU_DMA_OPTS_SINGLE_QUEUE = 1, | |
| }; | |
| -enum iommu_init_state { | |
| - IOMMU_START_STATE = 0, | |
| - IOMMU_IVRS_DETECTED = 1, | |
| - IOMMU_ACPI_FINISHED = 2, | |
| - IOMMU_ENABLED = 3, | |
| - IOMMU_PCI_INIT = 4, | |
| - IOMMU_INTERRUPTS_EN = 5, | |
| - IOMMU_INITIALIZED = 6, | |
| - IOMMU_NOT_FOUND = 7, | |
| - IOMMU_INIT_ERROR = 8, | |
| - IOMMU_CMDLINE_DISABLED = 9, | |
| +enum iommu_hw_info_type { | |
| + IOMMU_HW_INFO_TYPE_NONE = 0, | |
| + IOMMU_HW_INFO_TYPE_INTEL_VTD = 1, | |
| }; | |
| -enum iommu_page_response_code { | |
| - IOMMU_PAGE_RESP_SUCCESS = 0, | |
| - IOMMU_PAGE_RESP_INVALID = 1, | |
| - IOMMU_PAGE_RESP_FAILURE = 2, | |
| +enum iommu_hw_info_vtd_flags { | |
| + IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 = 1, | |
| +}; | |
| + | |
| +enum iommu_hwpt_data_type { | |
| + IOMMU_HWPT_DATA_NONE = 0, | |
| + IOMMU_HWPT_DATA_VTD_S1 = 1, | |
| +}; | |
| + | |
| +enum iommu_hwpt_invalidate_data_type { | |
| + IOMMU_HWPT_INVALIDATE_DATA_VTD_S1 = 0, | |
| +}; | |
| + | |
| +enum iommu_hwpt_vtd_s1_flags { | |
| + IOMMU_VTD_S1_SRE = 1, | |
| + IOMMU_VTD_S1_EAFE = 2, | |
| + IOMMU_VTD_S1_WPE = 4, | |
| +}; | |
| + | |
| +enum iommu_hwpt_vtd_s1_invalidate_flags { | |
| + IOMMU_VTD_INV_FLAGS_LEAF = 1, | |
| }; | |
| enum iommu_resv_type { | |
| @@ -17806,6 +20883,11 @@ | |
| IOMMU_RESV_SW_MSI = 4, | |
| }; | |
| +enum iommufd_hwpt_alloc_flags { | |
| + IOMMU_HWPT_ALLOC_NEST_PARENT = 1, | |
| + IOMMU_HWPT_ALLOC_DIRTY_TRACKING = 2, | |
| +}; | |
| + | |
| enum ip6_defrag_users { | |
| IP6_DEFRAG_LOCAL_DELIVER = 0, | |
| IP6_DEFRAG_CONNTRACK_IN = 1, | |
| @@ -17822,6 +20904,28 @@ | |
| IP_CT_DIR_MAX = 2, | |
| }; | |
| +enum ip_conntrack_events { | |
| + IPCT_NEW = 0, | |
| + IPCT_RELATED = 1, | |
| + IPCT_DESTROY = 2, | |
| + IPCT_REPLY = 3, | |
| + IPCT_ASSURED = 4, | |
| + IPCT_PROTOINFO = 5, | |
| + IPCT_HELPER = 6, | |
| + IPCT_MARK = 7, | |
| + IPCT_SEQADJ = 8, | |
| + IPCT_NATSEQADJ = 8, | |
| + IPCT_SECMARK = 9, | |
| + IPCT_LABEL = 10, | |
| + IPCT_SYNPROXY = 11, | |
| + __IPCT_MAX = 12, | |
| +}; | |
| + | |
| +enum ip_conntrack_expect_events { | |
| + IPEXP_NEW = 0, | |
| + IPEXP_DESTROY = 1, | |
| +}; | |
| + | |
| enum ip_conntrack_info { | |
| IP_CT_ESTABLISHED = 0, | |
| IP_CT_RELATED = 1, | |
| @@ -17890,48 +20994,6 @@ | |
| IP_DEFRAG_MACVLAN = 196614, | |
| }; | |
| -enum ip_set_ext_id { | |
| - IPSET_EXT_ID_COUNTER = 0, | |
| - IPSET_EXT_ID_TIMEOUT = 1, | |
| - IPSET_EXT_ID_SKBINFO = 2, | |
| - IPSET_EXT_ID_COMMENT = 3, | |
| - IPSET_EXT_ID_MAX = 4, | |
| -}; | |
| - | |
| -enum ip_set_extension { | |
| - IPSET_EXT_BIT_TIMEOUT = 0, | |
| - IPSET_EXT_TIMEOUT = 1, | |
| - IPSET_EXT_BIT_COUNTER = 1, | |
| - IPSET_EXT_COUNTER = 2, | |
| - IPSET_EXT_BIT_COMMENT = 2, | |
| - IPSET_EXT_COMMENT = 4, | |
| - IPSET_EXT_BIT_SKBINFO = 3, | |
| - IPSET_EXT_SKBINFO = 8, | |
| - IPSET_EXT_BIT_DESTROY = 7, | |
| - IPSET_EXT_DESTROY = 128, | |
| -}; | |
| - | |
| -enum ip_set_feature { | |
| - IPSET_TYPE_IP_FLAG = 0, | |
| - IPSET_TYPE_IP = 1, | |
| - IPSET_TYPE_PORT_FLAG = 1, | |
| - IPSET_TYPE_PORT = 2, | |
| - IPSET_TYPE_MAC_FLAG = 2, | |
| - IPSET_TYPE_MAC = 4, | |
| - IPSET_TYPE_IP2_FLAG = 3, | |
| - IPSET_TYPE_IP2 = 8, | |
| - IPSET_TYPE_NAME_FLAG = 4, | |
| - IPSET_TYPE_NAME = 16, | |
| - IPSET_TYPE_IFACE_FLAG = 5, | |
| - IPSET_TYPE_IFACE = 32, | |
| - IPSET_TYPE_MARK_FLAG = 6, | |
| - IPSET_TYPE_MARK = 64, | |
| - IPSET_TYPE_NOMATCH_FLAG = 7, | |
| - IPSET_TYPE_NOMATCH = 128, | |
| - IPSET_DUMP_LAST_FLAG = 8, | |
| - IPSET_DUMP_LAST = 256, | |
| -}; | |
| - | |
| enum ipmi_addr_space { | |
| IPMI_IO_ADDR_SPACE = 0, | |
| IPMI_MEM_ADDR_SPACE = 1, | |
| @@ -17955,131 +21017,6 @@ | |
| IPMI_PLAT_IF_SSIF = 1, | |
| }; | |
| -enum ipset_adt { | |
| - IPSET_ADD = 0, | |
| - IPSET_DEL = 1, | |
| - IPSET_TEST = 2, | |
| - IPSET_ADT_MAX = 3, | |
| - IPSET_CREATE = 3, | |
| - IPSET_CADT_MAX = 4, | |
| -}; | |
| - | |
| -enum ipset_cadt_flags { | |
| - IPSET_FLAG_BIT_BEFORE = 0, | |
| - IPSET_FLAG_BEFORE = 1, | |
| - IPSET_FLAG_BIT_PHYSDEV = 1, | |
| - IPSET_FLAG_PHYSDEV = 2, | |
| - IPSET_FLAG_BIT_NOMATCH = 2, | |
| - IPSET_FLAG_NOMATCH = 4, | |
| - IPSET_FLAG_BIT_WITH_COUNTERS = 3, | |
| - IPSET_FLAG_WITH_COUNTERS = 8, | |
| - IPSET_FLAG_BIT_WITH_COMMENT = 4, | |
| - IPSET_FLAG_WITH_COMMENT = 16, | |
| - IPSET_FLAG_BIT_WITH_FORCEADD = 5, | |
| - IPSET_FLAG_WITH_FORCEADD = 32, | |
| - IPSET_FLAG_BIT_WITH_SKBINFO = 6, | |
| - IPSET_FLAG_WITH_SKBINFO = 64, | |
| - IPSET_FLAG_BIT_IFACE_WILDCARD = 7, | |
| - IPSET_FLAG_IFACE_WILDCARD = 128, | |
| - IPSET_FLAG_CADT_MAX = 15, | |
| -}; | |
| - | |
| -enum ipset_cmd { | |
| - IPSET_CMD_NONE = 0, | |
| - IPSET_CMD_PROTOCOL = 1, | |
| - IPSET_CMD_CREATE = 2, | |
| - IPSET_CMD_DESTROY = 3, | |
| - IPSET_CMD_FLUSH = 4, | |
| - IPSET_CMD_RENAME = 5, | |
| - IPSET_CMD_SWAP = 6, | |
| - IPSET_CMD_LIST = 7, | |
| - IPSET_CMD_SAVE = 8, | |
| - IPSET_CMD_ADD = 9, | |
| - IPSET_CMD_DEL = 10, | |
| - IPSET_CMD_TEST = 11, | |
| - IPSET_CMD_HEADER = 12, | |
| - IPSET_CMD_TYPE = 13, | |
| - IPSET_CMD_GET_BYNAME = 14, | |
| - IPSET_CMD_GET_BYINDEX = 15, | |
| - IPSET_MSG_MAX = 16, | |
| - IPSET_CMD_RESTORE = 16, | |
| - IPSET_CMD_HELP = 17, | |
| - IPSET_CMD_VERSION = 18, | |
| - IPSET_CMD_QUIT = 19, | |
| - IPSET_CMD_MAX = 20, | |
| - IPSET_CMD_COMMIT = 20, | |
| -}; | |
| - | |
| -enum ipset_cmd_flags { | |
| - IPSET_FLAG_BIT_EXIST = 0, | |
| - IPSET_FLAG_EXIST = 1, | |
| - IPSET_FLAG_BIT_LIST_SETNAME = 1, | |
| - IPSET_FLAG_LIST_SETNAME = 2, | |
| - IPSET_FLAG_BIT_LIST_HEADER = 2, | |
| - IPSET_FLAG_LIST_HEADER = 4, | |
| - IPSET_FLAG_BIT_SKIP_COUNTER_UPDATE = 3, | |
| - IPSET_FLAG_SKIP_COUNTER_UPDATE = 8, | |
| - IPSET_FLAG_BIT_SKIP_SUBCOUNTER_UPDATE = 4, | |
| - IPSET_FLAG_SKIP_SUBCOUNTER_UPDATE = 16, | |
| - IPSET_FLAG_BIT_MATCH_COUNTERS = 5, | |
| - IPSET_FLAG_MATCH_COUNTERS = 32, | |
| - IPSET_FLAG_BIT_RETURN_NOMATCH = 7, | |
| - IPSET_FLAG_RETURN_NOMATCH = 128, | |
| - IPSET_FLAG_BIT_MAP_SKBMARK = 8, | |
| - IPSET_FLAG_MAP_SKBMARK = 256, | |
| - IPSET_FLAG_BIT_MAP_SKBPRIO = 9, | |
| - IPSET_FLAG_MAP_SKBPRIO = 512, | |
| - IPSET_FLAG_BIT_MAP_SKBQUEUE = 10, | |
| - IPSET_FLAG_MAP_SKBQUEUE = 1024, | |
| - IPSET_FLAG_CMD_MAX = 15, | |
| -}; | |
| - | |
| -enum ipset_create_flags { | |
| - IPSET_CREATE_FLAG_BIT_FORCEADD = 0, | |
| - IPSET_CREATE_FLAG_FORCEADD = 1, | |
| - IPSET_CREATE_FLAG_BIT_BUCKETSIZE = 1, | |
| - IPSET_CREATE_FLAG_BUCKETSIZE = 2, | |
| - IPSET_CREATE_FLAG_BIT_MAX = 7, | |
| -}; | |
| - | |
| -enum ipset_errno { | |
| - IPSET_ERR_PRIVATE = 4096, | |
| - IPSET_ERR_PROTOCOL = 4097, | |
| - IPSET_ERR_FIND_TYPE = 4098, | |
| - IPSET_ERR_MAX_SETS = 4099, | |
| - IPSET_ERR_BUSY = 4100, | |
| - IPSET_ERR_EXIST_SETNAME2 = 4101, | |
| - IPSET_ERR_TYPE_MISMATCH = 4102, | |
| - IPSET_ERR_EXIST = 4103, | |
| - IPSET_ERR_INVALID_CIDR = 4104, | |
| - IPSET_ERR_INVALID_NETMASK = 4105, | |
| - IPSET_ERR_INVALID_FAMILY = 4106, | |
| - IPSET_ERR_TIMEOUT = 4107, | |
| - IPSET_ERR_REFERENCED = 4108, | |
| - IPSET_ERR_IPADDR_IPV4 = 4109, | |
| - IPSET_ERR_IPADDR_IPV6 = 4110, | |
| - IPSET_ERR_COUNTER = 4111, | |
| - IPSET_ERR_COMMENT = 4112, | |
| - IPSET_ERR_INVALID_MARKMASK = 4113, | |
| - IPSET_ERR_SKBINFO = 4114, | |
| - IPSET_ERR_BITMASK_NETMASK_EXCL = 4115, | |
| - IPSET_ERR_TYPE_SPECIFIC = 4352, | |
| -}; | |
| - | |
| -typedef enum { | |
| - IPVL_IPV6 = 0, | |
| - IPVL_ICMPV6 = 1, | |
| - IPVL_IPV4 = 2, | |
| - IPVL_ARP = 3, | |
| -} ipvl_hdr_type; | |
| - | |
| -enum ipvlan_mode { | |
| - IPVLAN_MODE_L2 = 0, | |
| - IPVLAN_MODE_L3 = 1, | |
| - IPVLAN_MODE_L3S = 2, | |
| - IPVLAN_MODE_MAX = 3, | |
| -}; | |
| - | |
| enum irq_alloc_type { | |
| X86_IRQ_ALLOC_TYPE_IOAPIC = 1, | |
| X86_IRQ_ALLOC_TYPE_HPET = 2, | |
| @@ -18106,7 +21043,8 @@ | |
| DOMAIN_BUS_PCI_DEVICE_MSIX = 12, | |
| DOMAIN_BUS_DMAR = 13, | |
| DOMAIN_BUS_AMDVI = 14, | |
| - DOMAIN_BUS_PCI_DEVICE_IMS = 15, | |
| + DOMAIN_BUS_DEVICE_MSI = 15, | |
| + DOMAIN_BUS_WIRED_TO_MSI = 16, | |
| }; | |
| enum irq_gc_flags { | |
| @@ -18141,6 +21079,12 @@ | |
| typedef enum irqreturn irqreturn_t; | |
| +enum isofs_file_format { | |
| + isofs_file_normal = 0, | |
| + isofs_file_sparse = 1, | |
| + isofs_file_compressed = 2, | |
| +}; | |
| + | |
| typedef enum { | |
| ISOLATE_ABORT = 0, | |
| ISOLATE_NONE = 1, | |
| @@ -18148,13 +21092,12 @@ | |
| } isolate_migrate_t; | |
| enum iter_type { | |
| - ITER_IOVEC = 0, | |
| - ITER_KVEC = 1, | |
| + ITER_UBUF = 0, | |
| + ITER_IOVEC = 1, | |
| ITER_BVEC = 2, | |
| - ITER_PIPE = 3, | |
| + ITER_KVEC = 3, | |
| ITER_XARRAY = 4, | |
| ITER_DISCARD = 5, | |
| - ITER_UBUF = 6, | |
| }; | |
| enum ixgbe_atr_flow_type { | |
| @@ -18168,6 +21111,17 @@ | |
| IXGBE_ATR_FLOW_TYPE_SCTPV6 = 7, | |
| }; | |
| +enum ixgbe_boards { | |
| + board_82598 = 0, | |
| + board_82599 = 1, | |
| + board_X540 = 2, | |
| + board_X550 = 3, | |
| + board_X550EM_x = 4, | |
| + board_x550em_x_fw = 5, | |
| + board_x550em_a = 6, | |
| + board_x550em_a_fw = 7, | |
| +}; | |
| + | |
| enum ixgbe_bus_speed { | |
| ixgbe_bus_speed_unknown = 0, | |
| ixgbe_bus_speed_33 = 33, | |
| @@ -18350,6 +21304,8 @@ | |
| ixgbe_sfp_type_1g_sx_core1 = 12, | |
| ixgbe_sfp_type_1g_lx_core0 = 13, | |
| ixgbe_sfp_type_1g_lx_core1 = 14, | |
| + ixgbe_sfp_type_1g_bx_core0 = 15, | |
| + ixgbe_sfp_type_1g_bx_core1 = 16, | |
| ixgbe_sfp_type_not_present = 65534, | |
| ixgbe_sfp_type_unknown = 65535, | |
| }; | |
| @@ -18539,32 +21495,6 @@ | |
| KEY_IS_POSITIVE = 1, | |
| }; | |
| -enum kfence_counter_id { | |
| - KFENCE_COUNTER_ALLOCATED = 0, | |
| - KFENCE_COUNTER_ALLOCS = 1, | |
| - KFENCE_COUNTER_FREES = 2, | |
| - KFENCE_COUNTER_ZOMBIES = 3, | |
| - KFENCE_COUNTER_BUGS = 4, | |
| - KFENCE_COUNTER_SKIP_INCOMPAT = 5, | |
| - KFENCE_COUNTER_SKIP_CAPACITY = 6, | |
| - KFENCE_COUNTER_SKIP_COVERED = 7, | |
| - KFENCE_COUNTER_COUNT = 8, | |
| -}; | |
| - | |
| -enum kfence_error_type { | |
| - KFENCE_ERROR_OOB = 0, | |
| - KFENCE_ERROR_UAF = 1, | |
| - KFENCE_ERROR_CORRUPTION = 2, | |
| - KFENCE_ERROR_INVALID = 3, | |
| - KFENCE_ERROR_INVALID_FREE = 4, | |
| -}; | |
| - | |
| -enum kfence_object_state { | |
| - KFENCE_OBJECT_UNUSED = 0, | |
| - KFENCE_OBJECT_ALLOCATED = 1, | |
| - KFENCE_OBJECT_FREED = 2, | |
| -}; | |
| - | |
| enum kfunc_ptr_arg_type { | |
| KF_ARG_PTR_TO_CTX = 0, | |
| KF_ARG_PTR_TO_ALLOC_BTF_ID = 1, | |
| @@ -18581,10 +21511,14 @@ | |
| KF_ARG_PTR_TO_RB_NODE = 12, | |
| KF_ARG_PTR_TO_NULL = 13, | |
| KF_ARG_PTR_TO_CONST_STR = 14, | |
| + KF_ARG_PTR_TO_MAP = 15, | |
| + KF_ARG_PTR_TO_WORKQUEUE = 16, | |
| }; | |
| enum kmalloc_cache_type { | |
| KMALLOC_NORMAL = 0, | |
| + KMALLOC_RANDOM_START = 0, | |
| + KMALLOC_RANDOM_END = 0, | |
| KMALLOC_RECLAIM = 1, | |
| KMALLOC_DMA = 2, | |
| KMALLOC_CGROUP = 3, | |
| @@ -18623,6 +21557,17 @@ | |
| SLOT_USED = 2, | |
| }; | |
| +enum ksm_advisor_type { | |
| + KSM_ADVISOR_NONE = 0, | |
| + KSM_ADVISOR_SCAN_TIME = 1, | |
| +}; | |
| + | |
| +enum ksm_get_folio_flags { | |
| + KSM_GET_FOLIO_NOLOCK = 0, | |
| + KSM_GET_FOLIO_LOCK = 1, | |
| + KSM_GET_FOLIO_TRYLOCK = 2, | |
| +}; | |
| + | |
| enum kvm_apic_logical_mode { | |
| KVM_APIC_MODE_SW_DISABLED = 0, | |
| KVM_APIC_MODE_XAPIC_CLUSTER = 1, | |
| @@ -18631,12 +21576,117 @@ | |
| KVM_APIC_MODE_MAP_DISABLED = 4, | |
| }; | |
| +enum kvm_apicv_inhibit { | |
| + APICV_INHIBIT_REASON_DISABLE = 0, | |
| + APICV_INHIBIT_REASON_HYPERV = 1, | |
| + APICV_INHIBIT_REASON_ABSENT = 2, | |
| + APICV_INHIBIT_REASON_BLOCKIRQ = 3, | |
| + APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED = 4, | |
| + APICV_INHIBIT_REASON_APIC_ID_MODIFIED = 5, | |
| + APICV_INHIBIT_REASON_APIC_BASE_MODIFIED = 6, | |
| + APICV_INHIBIT_REASON_NESTED = 7, | |
| + APICV_INHIBIT_REASON_IRQWIN = 8, | |
| + APICV_INHIBIT_REASON_PIT_REINJ = 9, | |
| + APICV_INHIBIT_REASON_SEV = 10, | |
| + APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED = 11, | |
| +}; | |
| + | |
| +enum kvm_bus { | |
| + KVM_MMIO_BUS = 0, | |
| + KVM_PIO_BUS = 1, | |
| + KVM_VIRTIO_CCW_NOTIFY_BUS = 2, | |
| + KVM_FAST_MMIO_BUS = 3, | |
| + KVM_NR_BUSES = 4, | |
| +}; | |
| + | |
| +enum kvm_device_type { | |
| + KVM_DEV_TYPE_FSL_MPIC_20 = 1, | |
| + KVM_DEV_TYPE_FSL_MPIC_42 = 2, | |
| + KVM_DEV_TYPE_XICS = 3, | |
| + KVM_DEV_TYPE_VFIO = 4, | |
| + KVM_DEV_TYPE_ARM_VGIC_V2 = 5, | |
| + KVM_DEV_TYPE_FLIC = 6, | |
| + KVM_DEV_TYPE_ARM_VGIC_V3 = 7, | |
| + KVM_DEV_TYPE_ARM_VGIC_ITS = 8, | |
| + KVM_DEV_TYPE_XIVE = 9, | |
| + KVM_DEV_TYPE_ARM_PV_TIME = 10, | |
| + KVM_DEV_TYPE_RISCV_AIA = 11, | |
| + KVM_DEV_TYPE_MAX = 12, | |
| +}; | |
| + | |
| +enum kvm_governed_features { | |
| + KVM_GOVERNED_X86_FEATURE_GBPAGES = 0, | |
| + KVM_GOVERNED_X86_FEATURE_XSAVES = 1, | |
| + KVM_GOVERNED_X86_FEATURE_VMX = 2, | |
| + KVM_GOVERNED_X86_FEATURE_NRIPS = 3, | |
| + KVM_GOVERNED_X86_FEATURE_TSCRATEMSR = 4, | |
| + KVM_GOVERNED_X86_FEATURE_V_VMSAVE_VMLOAD = 5, | |
| + KVM_GOVERNED_X86_FEATURE_LBRV = 6, | |
| + KVM_GOVERNED_X86_FEATURE_PAUSEFILTER = 7, | |
| + KVM_GOVERNED_X86_FEATURE_PFTHRESHOLD = 8, | |
| + KVM_GOVERNED_X86_FEATURE_VGIF = 9, | |
| + KVM_GOVERNED_X86_FEATURE_VNMI = 10, | |
| + KVM_GOVERNED_X86_FEATURE_LAM = 11, | |
| + KVM_NR_GOVERNED_FEATURES = 12, | |
| +}; | |
| + | |
| +enum kvm_intr_type { | |
| + KVM_HANDLING_IRQ = 1, | |
| + KVM_HANDLING_NMI = 2, | |
| +}; | |
| + | |
| enum kvm_irqchip_mode { | |
| KVM_IRQCHIP_NONE = 0, | |
| KVM_IRQCHIP_KERNEL = 1, | |
| KVM_IRQCHIP_SPLIT = 2, | |
| }; | |
| +enum kvm_mr_change { | |
| + KVM_MR_CREATE = 0, | |
| + KVM_MR_DELETE = 1, | |
| + KVM_MR_MOVE = 2, | |
| + KVM_MR_FLAGS_ONLY = 3, | |
| +}; | |
| + | |
| +enum kvm_only_cpuid_leafs { | |
| + CPUID_12_EAX = 22, | |
| + CPUID_7_1_EDX = 23, | |
| + CPUID_8000_0007_EDX = 24, | |
| + CPUID_8000_0022_EAX = 25, | |
| + CPUID_7_2_EDX = 26, | |
| + NR_KVM_CPU_CAPS = 27, | |
| + NKVMCAPINTS = 5, | |
| +}; | |
| + | |
| +enum kvm_reg { | |
| + VCPU_REGS_RAX = 0, | |
| + VCPU_REGS_RCX = 1, | |
| + VCPU_REGS_RDX = 2, | |
| + VCPU_REGS_RBX = 3, | |
| + VCPU_REGS_RSP = 4, | |
| + VCPU_REGS_RBP = 5, | |
| + VCPU_REGS_RSI = 6, | |
| + VCPU_REGS_RDI = 7, | |
| + VCPU_REGS_R8 = 8, | |
| + VCPU_REGS_R9 = 9, | |
| + VCPU_REGS_R10 = 10, | |
| + VCPU_REGS_R11 = 11, | |
| + VCPU_REGS_R12 = 12, | |
| + VCPU_REGS_R13 = 13, | |
| + VCPU_REGS_R14 = 14, | |
| + VCPU_REGS_R15 = 15, | |
| + VCPU_REGS_RIP = 16, | |
| + NR_VCPU_REGS = 17, | |
| + VCPU_EXREG_PDPTR = 17, | |
| + VCPU_EXREG_CR0 = 18, | |
| + VCPU_EXREG_CR3 = 19, | |
| + VCPU_EXREG_CR4 = 20, | |
| + VCPU_EXREG_RFLAGS = 21, | |
| + VCPU_EXREG_SEGMENTS = 22, | |
| + VCPU_EXREG_EXIT_INFO_1 = 23, | |
| + VCPU_EXREG_EXIT_INFO_2 = 24, | |
| +}; | |
| + | |
| enum kvm_stat_kind { | |
| KVM_STAT_VM = 0, | |
| KVM_STAT_VCPU = 1, | |
| @@ -18656,6 +21706,13 @@ | |
| L1TF_MITIGATION_FULL_FORCE = 5, | |
| }; | |
| +enum l2tp_debug_flags { | |
| + L2TP_MSG_DEBUG = 1, | |
| + L2TP_MSG_CONTROL = 2, | |
| + L2TP_MSG_SEQ = 4, | |
| + L2TP_MSG_DATA = 8, | |
| +}; | |
| + | |
| enum l3mdev_type { | |
| L3MDEV_TYPE_UNSPEC = 0, | |
| L3MDEV_TYPE_VRF = 1, | |
| @@ -18668,24 +21725,43 @@ | |
| LABEL_PENDING = 2, | |
| }; | |
| -enum latency_range { | |
| - lowest_latency = 0, | |
| - low_latency = 1, | |
| - bulk_latency = 2, | |
| - latency_invalid = 255, | |
| +enum lapic_lvt_entry { | |
| + LVT_TIMER = 0, | |
| + LVT_THERMAL_MONITOR = 1, | |
| + LVT_PERFORMANCE_COUNTER = 2, | |
| + LVT_LINT0 = 3, | |
| + LVT_LINT1 = 4, | |
| + LVT_ERROR = 5, | |
| + LVT_CMCI = 6, | |
| + KVM_APIC_MAX_NR_LVT_ENTRIES = 7, | |
| +}; | |
| + | |
| +enum lapic_mode { | |
| + LAPIC_MODE_DISABLED = 0, | |
| + LAPIC_MODE_INVALID = 1024, | |
| + LAPIC_MODE_XAPIC = 2048, | |
| + LAPIC_MODE_X2APIC = 3072, | |
| +}; | |
| + | |
| +enum latency_count { | |
| + COUNTS_10e2 = 0, | |
| + COUNTS_10e3 = 1, | |
| + COUNTS_10e4 = 2, | |
| + COUNTS_10e5 = 3, | |
| + COUNTS_10e6 = 4, | |
| + COUNTS_10e7 = 5, | |
| + COUNTS_10e8_plus = 6, | |
| + COUNTS_MIN = 7, | |
| + COUNTS_MAX = 8, | |
| + COUNTS_SUM = 9, | |
| + COUNTS_NUM = 10, | |
| }; | |
| enum latency_type { | |
| DMAR_LATENCY_INV_IOTLB = 0, | |
| DMAR_LATENCY_INV_DEVTLB = 1, | |
| DMAR_LATENCY_INV_IEC = 2, | |
| - DMAR_LATENCY_PRQ = 3, | |
| - DMAR_LATENCY_NUM = 4, | |
| -}; | |
| - | |
| -enum layout_break_reason { | |
| - BREAK_WRITE = 0, | |
| - BREAK_UNMAP = 1, | |
| + DMAR_LATENCY_NUM = 3, | |
| }; | |
| enum led_brightness { | |
| @@ -18707,62 +21783,107 @@ | |
| LEGACY_FS_INDIVIDUAL_PARAMS = 2, | |
| }; | |
| -enum ll_ids { | |
| - LL_RESV = 0, | |
| - LL_L1 = 1, | |
| - LL_L2 = 2, | |
| - LL_LG = 3, | |
| +enum lg_g15_led_type { | |
| + LG_G15_KBD_BRIGHTNESS = 0, | |
| + LG_G15_LCD_BRIGHTNESS = 1, | |
| + LG_G15_BRIGHTNESS_MAX = 2, | |
| + LG_G15_MACRO_PRESET1 = 2, | |
| + LG_G15_MACRO_PRESET2 = 3, | |
| + LG_G15_MACRO_PRESET3 = 4, | |
| + LG_G15_MACRO_RECORD = 5, | |
| + LG_G15_LED_MAX = 6, | |
| }; | |
| -enum lm75_type { | |
| - adt75 = 0, | |
| - at30ts74 = 1, | |
| - ds1775 = 2, | |
| - ds75 = 3, | |
| - ds7505 = 4, | |
| - g751 = 5, | |
| - lm75 = 6, | |
| - lm75a = 7, | |
| - lm75b = 8, | |
| - max6625 = 9, | |
| - max6626 = 10, | |
| - max31725 = 11, | |
| - mcp980x = 12, | |
| - pct2075 = 13, | |
| - stds75 = 14, | |
| - stlm75 = 15, | |
| - tcn75 = 16, | |
| - tmp100 = 17, | |
| - tmp101 = 18, | |
| - tmp105 = 19, | |
| - tmp112 = 20, | |
| - tmp175 = 21, | |
| - tmp275 = 22, | |
| - tmp75 = 23, | |
| - tmp75b = 24, | |
| - tmp75c = 25, | |
| - tmp1075 = 26, | |
| +enum lg_g15_model { | |
| + LG_G15 = 0, | |
| + LG_G15_V2 = 1, | |
| + LG_G510 = 2, | |
| + LG_G510_USB_AUDIO = 3, | |
| + LG_Z10 = 4, | |
| }; | |
| -enum lm90_temp_reg_index { | |
| - LOCAL_LOW = 0, | |
| - LOCAL_HIGH = 1, | |
| - LOCAL_CRIT = 2, | |
| - REMOTE_CRIT = 3, | |
| - LOCAL_EMERG = 4, | |
| - REMOTE_EMERG = 5, | |
| - REMOTE2_CRIT = 6, | |
| - REMOTE2_EMERG = 7, | |
| - REMOTE_TEMP = 8, | |
| - REMOTE_LOW = 9, | |
| - REMOTE_HIGH = 10, | |
| - REMOTE_OFFSET = 11, | |
| - LOCAL_TEMP = 12, | |
| - REMOTE2_TEMP = 13, | |
| - REMOTE2_LOW = 14, | |
| - REMOTE2_HIGH = 15, | |
| - REMOTE2_OFFSET = 16, | |
| - TEMP_REG_NUM = 17, | |
| +enum linux_mptcp_mib_field { | |
| + MPTCP_MIB_NUM = 0, | |
| + MPTCP_MIB_MPCAPABLEPASSIVE = 1, | |
| + MPTCP_MIB_MPCAPABLEACTIVE = 2, | |
| + MPTCP_MIB_MPCAPABLEACTIVEACK = 3, | |
| + MPTCP_MIB_MPCAPABLEPASSIVEACK = 4, | |
| + MPTCP_MIB_MPCAPABLEPASSIVEFALLBACK = 5, | |
| + MPTCP_MIB_MPCAPABLEACTIVEFALLBACK = 6, | |
| + MPTCP_MIB_TOKENFALLBACKINIT = 7, | |
| + MPTCP_MIB_RETRANSSEGS = 8, | |
| + MPTCP_MIB_JOINNOTOKEN = 9, | |
| + MPTCP_MIB_JOINSYNRX = 10, | |
| + MPTCP_MIB_JOINSYNACKRX = 11, | |
| + MPTCP_MIB_JOINSYNACKMAC = 12, | |
| + MPTCP_MIB_JOINACKRX = 13, | |
| + MPTCP_MIB_JOINACKMAC = 14, | |
| + MPTCP_MIB_DSSNOMATCH = 15, | |
| + MPTCP_MIB_INFINITEMAPTX = 16, | |
| + MPTCP_MIB_INFINITEMAPRX = 17, | |
| + MPTCP_MIB_DSSTCPMISMATCH = 18, | |
| + MPTCP_MIB_DATACSUMERR = 19, | |
| + MPTCP_MIB_OFOQUEUETAIL = 20, | |
| + MPTCP_MIB_OFOQUEUE = 21, | |
| + MPTCP_MIB_OFOMERGE = 22, | |
| + MPTCP_MIB_NODSSWINDOW = 23, | |
| + MPTCP_MIB_DUPDATA = 24, | |
| + MPTCP_MIB_ADDADDR = 25, | |
| + MPTCP_MIB_ADDADDRTX = 26, | |
| + MPTCP_MIB_ADDADDRTXDROP = 27, | |
| + MPTCP_MIB_ECHOADD = 28, | |
| + MPTCP_MIB_ECHOADDTX = 29, | |
| + MPTCP_MIB_ECHOADDTXDROP = 30, | |
| + MPTCP_MIB_PORTADD = 31, | |
| + MPTCP_MIB_ADDADDRDROP = 32, | |
| + MPTCP_MIB_JOINPORTSYNRX = 33, | |
| + MPTCP_MIB_JOINPORTSYNACKRX = 34, | |
| + MPTCP_MIB_JOINPORTACKRX = 35, | |
| + MPTCP_MIB_MISMATCHPORTSYNRX = 36, | |
| + MPTCP_MIB_MISMATCHPORTACKRX = 37, | |
| + MPTCP_MIB_RMADDR = 38, | |
| + MPTCP_MIB_RMADDRDROP = 39, | |
| + MPTCP_MIB_RMADDRTX = 40, | |
| + MPTCP_MIB_RMADDRTXDROP = 41, | |
| + MPTCP_MIB_RMSUBFLOW = 42, | |
| + MPTCP_MIB_MPPRIOTX = 43, | |
| + MPTCP_MIB_MPPRIORX = 44, | |
| + MPTCP_MIB_MPFAILTX = 45, | |
| + MPTCP_MIB_MPFAILRX = 46, | |
| + MPTCP_MIB_MPFASTCLOSETX = 47, | |
| + MPTCP_MIB_MPFASTCLOSERX = 48, | |
| + MPTCP_MIB_MPRSTTX = 49, | |
| + MPTCP_MIB_MPRSTRX = 50, | |
| + MPTCP_MIB_RCVPRUNED = 51, | |
| + MPTCP_MIB_SUBFLOWSTALE = 52, | |
| + MPTCP_MIB_SUBFLOWRECOVER = 53, | |
| + MPTCP_MIB_SNDWNDSHARED = 54, | |
| + MPTCP_MIB_RCVWNDSHARED = 55, | |
| + MPTCP_MIB_RCVWNDCONFLICTUPDATE = 56, | |
| + MPTCP_MIB_RCVWNDCONFLICT = 57, | |
| + MPTCP_MIB_CURRESTAB = 58, | |
| + __MPTCP_MIB_MAX = 59, | |
| +}; | |
| + | |
| +enum lock_usage_bit { | |
| + LOCK_USED_IN_HARDIRQ = 0, | |
| + LOCK_USED_IN_HARDIRQ_READ = 1, | |
| + LOCK_ENABLED_HARDIRQ = 2, | |
| + LOCK_ENABLED_HARDIRQ_READ = 3, | |
| + LOCK_USED_IN_SOFTIRQ = 4, | |
| + LOCK_USED_IN_SOFTIRQ_READ = 5, | |
| + LOCK_ENABLED_SOFTIRQ = 6, | |
| + LOCK_ENABLED_SOFTIRQ_READ = 7, | |
| + LOCK_USED = 8, | |
| + LOCK_USED_READ = 9, | |
| + LOCK_USAGE_STATES = 10, | |
| +}; | |
| + | |
| +enum lockdep_lock_type { | |
| + LD_LOCK_NORMAL = 0, | |
| + LD_LOCK_PERCPU = 1, | |
| + LD_LOCK_WAIT_OVERRIDE = 2, | |
| + LD_LOCK_MAX = 3, | |
| }; | |
| enum lockdep_ok { | |
| @@ -18770,6 +21891,15 @@ | |
| LOCKDEP_NOW_UNRELIABLE = 1, | |
| }; | |
| +enum lockdep_wait_type { | |
| + LD_WAIT_INV = 0, | |
| + LD_WAIT_FREE = 1, | |
| + LD_WAIT_SPIN = 2, | |
| + LD_WAIT_CONFIG = 3, | |
| + LD_WAIT_SLEEP = 4, | |
| + LD_WAIT_MAX = 5, | |
| +}; | |
| + | |
| enum lockdown_reason { | |
| LOCKDOWN_NONE = 0, | |
| LOCKDOWN_MODULE_SIGNATURE = 1, | |
| @@ -18803,12 +21933,6 @@ | |
| LOCKDOWN_CONFIDENTIALITY_MAX = 29, | |
| }; | |
| -enum loglevel_source { | |
| - LLS_GLOBAL = 0, | |
| - LLS_LOCAL = 1, | |
| - LLS_IGNORE_LOGLEVEL = 2, | |
| -}; | |
| - | |
| enum lru_list { | |
| LRU_INACTIVE_ANON = 0, | |
| LRU_ACTIVE_ANON = 1, | |
| @@ -18824,10 +21948,12 @@ | |
| LRU_ROTATE = 2, | |
| LRU_SKIP = 3, | |
| LRU_RETRY = 4, | |
| + LRU_STOP = 5, | |
| }; | |
| enum lruvec_flags { | |
| - LRUVEC_CONGESTED = 0, | |
| + LRUVEC_CGROUP_CONGESTED = 0, | |
| + LRUVEC_NODE_CONGESTED = 1, | |
| }; | |
| enum lsm_event { | |
| @@ -18921,6 +22047,201 @@ | |
| STATE_NONLIT_REP = 11, | |
| }; | |
| +enum mac80211_drop_reason { | |
| + RX_CONTINUE = 1, | |
| + RX_QUEUED = 0, | |
| + RX_DROP_MONITOR = 131072, | |
| + RX_DROP_M_UNEXPECTED_4ADDR_FRAME = 131073, | |
| + RX_DROP_M_BAD_BCN_KEYIDX = 131074, | |
| + RX_DROP_M_BAD_MGMT_KEYIDX = 131075, | |
| + RX_DROP_U_MIC_FAIL = 65537, | |
| + RX_DROP_U_REPLAY = 65538, | |
| + RX_DROP_U_BAD_MMIE = 65539, | |
| + RX_DROP_U_DUP = 65540, | |
| + RX_DROP_U_SPURIOUS = 65541, | |
| + RX_DROP_U_DECRYPT_FAIL = 65542, | |
| + RX_DROP_U_NO_KEY_ID = 65543, | |
| + RX_DROP_U_BAD_CIPHER = 65544, | |
| + RX_DROP_U_OOM = 65545, | |
| + RX_DROP_U_NONSEQ_PN = 65546, | |
| + RX_DROP_U_BAD_KEY_COLOR = 65547, | |
| + RX_DROP_U_BAD_4ADDR = 65548, | |
| + RX_DROP_U_BAD_AMSDU = 65549, | |
| + RX_DROP_U_BAD_AMSDU_CIPHER = 65550, | |
| + RX_DROP_U_INVALID_8023 = 65551, | |
| + RX_DROP_U_RUNT_ACTION = 65552, | |
| + RX_DROP_U_UNPROT_ACTION = 65553, | |
| + RX_DROP_U_UNPROT_DUAL = 65554, | |
| + RX_DROP_U_UNPROT_UCAST_MGMT = 65555, | |
| + RX_DROP_U_UNPROT_MCAST_MGMT = 65556, | |
| + RX_DROP_U_UNPROT_BEACON = 65557, | |
| + RX_DROP_U_UNPROT_UNICAST_PUB_ACTION = 65558, | |
| + RX_DROP_U_UNPROT_ROBUST_ACTION = 65559, | |
| + RX_DROP_U_ACTION_UNKNOWN_SRC = 65560, | |
| + RX_DROP_U_REJECTED_ACTION_RESPONSE = 65561, | |
| + RX_DROP_U_EXPECT_DEFRAG_PROT = 65562, | |
| + RX_DROP_U_WEP_DEC_FAIL = 65563, | |
| + RX_DROP_U_NO_IV = 65564, | |
| + RX_DROP_U_NO_ICV = 65565, | |
| + RX_DROP_U_AP_RX_GROUPCAST = 65566, | |
| + RX_DROP_U_SHORT_MMIC = 65567, | |
| + RX_DROP_U_MMIC_FAIL = 65568, | |
| + RX_DROP_U_SHORT_TKIP = 65569, | |
| + RX_DROP_U_TKIP_FAIL = 65570, | |
| + RX_DROP_U_SHORT_CCMP = 65571, | |
| + RX_DROP_U_SHORT_CCMP_MIC = 65572, | |
| + RX_DROP_U_SHORT_GCMP = 65573, | |
| + RX_DROP_U_SHORT_GCMP_MIC = 65574, | |
| + RX_DROP_U_SHORT_CMAC = 65575, | |
| + RX_DROP_U_SHORT_CMAC256 = 65576, | |
| + RX_DROP_U_SHORT_GMAC = 65577, | |
| + RX_DROP_U_UNEXPECTED_VLAN_4ADDR = 65578, | |
| + RX_DROP_U_UNEXPECTED_STA_4ADDR = 65579, | |
| + RX_DROP_U_UNEXPECTED_VLAN_MCAST = 65580, | |
| + RX_DROP_U_NOT_PORT_CONTROL = 65581, | |
| + RX_DROP_U_UNKNOWN_ACTION_REJECTED = 65582, | |
| +}; | |
| + | |
| +enum mac80211_rate_control_flags { | |
| + IEEE80211_TX_RC_USE_RTS_CTS = 1, | |
| + IEEE80211_TX_RC_USE_CTS_PROTECT = 2, | |
| + IEEE80211_TX_RC_USE_SHORT_PREAMBLE = 4, | |
| + IEEE80211_TX_RC_MCS = 8, | |
| + IEEE80211_TX_RC_GREEN_FIELD = 16, | |
| + IEEE80211_TX_RC_40_MHZ_WIDTH = 32, | |
| + IEEE80211_TX_RC_DUP_DATA = 64, | |
| + IEEE80211_TX_RC_SHORT_GI = 128, | |
| + IEEE80211_TX_RC_VHT_MCS = 256, | |
| + IEEE80211_TX_RC_80_MHZ_WIDTH = 512, | |
| + IEEE80211_TX_RC_160_MHZ_WIDTH = 1024, | |
| +}; | |
| + | |
| +enum mac80211_rx_encoding { | |
| + RX_ENC_LEGACY = 0, | |
| + RX_ENC_HT = 1, | |
| + RX_ENC_VHT = 2, | |
| + RX_ENC_HE = 3, | |
| + RX_ENC_EHT = 4, | |
| +}; | |
| + | |
| +enum mac80211_rx_encoding_flags { | |
| + RX_ENC_FLAG_SHORTPRE = 1, | |
| + RX_ENC_FLAG_SHORT_GI = 4, | |
| + RX_ENC_FLAG_HT_GF = 8, | |
| + RX_ENC_FLAG_STBC_MASK = 48, | |
| + RX_ENC_FLAG_LDPC = 64, | |
| + RX_ENC_FLAG_BF = 128, | |
| +}; | |
| + | |
| +enum mac80211_rx_flags { | |
| + RX_FLAG_MMIC_ERROR = 1, | |
| + RX_FLAG_DECRYPTED = 2, | |
| + RX_FLAG_ONLY_MONITOR = 4, | |
| + RX_FLAG_MMIC_STRIPPED = 8, | |
| + RX_FLAG_IV_STRIPPED = 16, | |
| + RX_FLAG_FAILED_FCS_CRC = 32, | |
| + RX_FLAG_FAILED_PLCP_CRC = 64, | |
| + RX_FLAG_MACTIME_IS_RTAP_TS64 = 128, | |
| + RX_FLAG_NO_SIGNAL_VAL = 256, | |
| + RX_FLAG_AMPDU_DETAILS = 512, | |
| + RX_FLAG_PN_VALIDATED = 1024, | |
| + RX_FLAG_DUP_VALIDATED = 2048, | |
| + RX_FLAG_AMPDU_LAST_KNOWN = 4096, | |
| + RX_FLAG_AMPDU_IS_LAST = 8192, | |
| + RX_FLAG_AMPDU_DELIM_CRC_ERROR = 16384, | |
| + RX_FLAG_AMPDU_DELIM_CRC_KNOWN = 32768, | |
| + RX_FLAG_MACTIME = 196608, | |
| + RX_FLAG_MACTIME_PLCP_START = 65536, | |
| + RX_FLAG_MACTIME_START = 131072, | |
| + RX_FLAG_MACTIME_END = 196608, | |
| + RX_FLAG_SKIP_MONITOR = 262144, | |
| + RX_FLAG_AMSDU_MORE = 524288, | |
| + RX_FLAG_RADIOTAP_TLV_AT_END = 1048576, | |
| + RX_FLAG_MIC_STRIPPED = 2097152, | |
| + RX_FLAG_ALLOW_SAME_PN = 4194304, | |
| + RX_FLAG_ICV_STRIPPED = 8388608, | |
| + RX_FLAG_AMPDU_EOF_BIT = 16777216, | |
| + RX_FLAG_AMPDU_EOF_BIT_KNOWN = 33554432, | |
| + RX_FLAG_RADIOTAP_HE = 67108864, | |
| + RX_FLAG_RADIOTAP_HE_MU = 134217728, | |
| + RX_FLAG_RADIOTAP_LSIG = 268435456, | |
| + RX_FLAG_NO_PSDU = 536870912, | |
| + RX_FLAG_8023 = 1073741824, | |
| +}; | |
| + | |
| +enum mac80211_scan_flags { | |
| + SCAN_SW_SCANNING = 0, | |
| + SCAN_HW_SCANNING = 1, | |
| + SCAN_ONCHANNEL_SCANNING = 2, | |
| + SCAN_COMPLETED = 3, | |
| + SCAN_ABORTED = 4, | |
| + SCAN_HW_CANCELLED = 5, | |
| + SCAN_BEACON_WAIT = 6, | |
| + SCAN_BEACON_DONE = 7, | |
| +}; | |
| + | |
| +enum mac80211_scan_state { | |
| + SCAN_DECISION = 0, | |
| + SCAN_SET_CHANNEL = 1, | |
| + SCAN_SEND_PROBE = 2, | |
| + SCAN_SUSPEND = 3, | |
| + SCAN_RESUME = 4, | |
| + SCAN_ABORT = 5, | |
| +}; | |
| + | |
| +enum mac80211_tx_control_flags { | |
| + IEEE80211_TX_CTRL_PORT_CTRL_PROTO = 1, | |
| + IEEE80211_TX_CTRL_PS_RESPONSE = 2, | |
| + IEEE80211_TX_CTRL_RATE_INJECT = 4, | |
| + IEEE80211_TX_CTRL_AMSDU = 8, | |
| + IEEE80211_TX_CTRL_FAST_XMIT = 16, | |
| + IEEE80211_TX_CTRL_SKIP_MPATH_LOOKUP = 32, | |
| + IEEE80211_TX_INTCFL_NEED_TXPROCESSING = 64, | |
| + IEEE80211_TX_CTRL_NO_SEQNO = 128, | |
| + IEEE80211_TX_CTRL_DONT_REORDER = 256, | |
| + IEEE80211_TX_CTRL_MCAST_MLO_FIRST_TX = 512, | |
| + IEEE80211_TX_CTRL_SCAN_TX = 1024, | |
| + IEEE80211_TX_CTRL_MLO_LINK = 4026531840, | |
| +}; | |
| + | |
| +enum mac80211_tx_info_flags { | |
| + IEEE80211_TX_CTL_REQ_TX_STATUS = 1, | |
| + IEEE80211_TX_CTL_ASSIGN_SEQ = 2, | |
| + IEEE80211_TX_CTL_NO_ACK = 4, | |
| + IEEE80211_TX_CTL_CLEAR_PS_FILT = 8, | |
| + IEEE80211_TX_CTL_FIRST_FRAGMENT = 16, | |
| + IEEE80211_TX_CTL_SEND_AFTER_DTIM = 32, | |
| + IEEE80211_TX_CTL_AMPDU = 64, | |
| + IEEE80211_TX_CTL_INJECTED = 128, | |
| + IEEE80211_TX_STAT_TX_FILTERED = 256, | |
| + IEEE80211_TX_STAT_ACK = 512, | |
| + IEEE80211_TX_STAT_AMPDU = 1024, | |
| + IEEE80211_TX_STAT_AMPDU_NO_BACK = 2048, | |
| + IEEE80211_TX_CTL_RATE_CTRL_PROBE = 4096, | |
| + IEEE80211_TX_INTFL_OFFCHAN_TX_OK = 8192, | |
| + IEEE80211_TX_CTL_HW_80211_ENCAP = 16384, | |
| + IEEE80211_TX_INTFL_RETRIED = 32768, | |
| + IEEE80211_TX_INTFL_DONT_ENCRYPT = 65536, | |
| + IEEE80211_TX_CTL_NO_PS_BUFFER = 131072, | |
| + IEEE80211_TX_CTL_MORE_FRAMES = 262144, | |
| + IEEE80211_TX_INTFL_RETRANSMISSION = 524288, | |
| + IEEE80211_TX_INTFL_MLME_CONN_TX = 1048576, | |
| + IEEE80211_TX_INTFL_NL80211_FRAME_TX = 2097152, | |
| + IEEE80211_TX_CTL_LDPC = 4194304, | |
| + IEEE80211_TX_CTL_STBC = 25165824, | |
| + IEEE80211_TX_CTL_TX_OFFCHAN = 33554432, | |
| + IEEE80211_TX_INTFL_TKIP_MIC_FAILURE = 67108864, | |
| + IEEE80211_TX_CTL_NO_CCK_RATE = 134217728, | |
| + IEEE80211_TX_STATUS_EOSP = 268435456, | |
| + IEEE80211_TX_CTL_USE_MINRATE = 536870912, | |
| + IEEE80211_TX_CTL_DONTFRAG = 1073741824, | |
| + IEEE80211_TX_STAT_NOACK_TRANSMITTED = 2147483648, | |
| +}; | |
| + | |
| +enum mac80211_tx_status_flags { | |
| + IEEE80211_TX_STATUS_ACK_SIGNAL_VALID = 1, | |
| +}; | |
| + | |
| enum macvlan_mode { | |
| MACVLAN_MODE_PRIVATE = 1, | |
| MACVLAN_MODE_VEPA = 2, | |
| @@ -18929,6 +22250,17 @@ | |
| MACVLAN_MODE_SOURCE = 16, | |
| }; | |
| +enum maple_status { | |
| + ma_active = 0, | |
| + ma_start = 1, | |
| + ma_root = 2, | |
| + ma_none = 3, | |
| + ma_pause = 4, | |
| + ma_overflow = 5, | |
| + ma_underflow = 6, | |
| + ma_error = 7, | |
| +}; | |
| + | |
| enum maple_type { | |
| maple_dense = 0, | |
| maple_leaf_64 = 1, | |
| @@ -18944,6 +22276,18 @@ | |
| AS_EXITING = 4, | |
| AS_NO_WRITEBACK_TAGS = 5, | |
| AS_LARGE_FOLIO_SUPPORT = 6, | |
| + AS_RELEASE_ALWAYS = 7, | |
| + AS_STABLE_WRITES = 8, | |
| + AS_UNMOVABLE = 9, | |
| +}; | |
| + | |
| +enum mapping_status { | |
| + MAPPING_OK = 0, | |
| + MAPPING_INVALID = 1, | |
| + MAPPING_EMPTY = 2, | |
| + MAPPING_DATA_FIN = 3, | |
| + MAPPING_DUMMY = 4, | |
| + MAPPING_BAD_CSUM = 5, | |
| }; | |
| enum mc_target_type { | |
| @@ -19006,11 +22350,9 @@ | |
| MD_FAILFAST_SUPPORTED = 5, | |
| MD_HAS_PPL = 6, | |
| MD_HAS_MULTIPLE_PPLS = 7, | |
| - MD_ALLOW_SB_UPDATE = 8, | |
| - MD_UPDATING_SB = 9, | |
| - MD_NOT_READY = 10, | |
| - MD_BROKEN = 11, | |
| - MD_DELETED = 12, | |
| + MD_NOT_READY = 8, | |
| + MD_BROKEN = 9, | |
| + MD_DELETED = 10, | |
| }; | |
| enum mddev_sb_flags { | |
| @@ -19020,6 +22362,12 @@ | |
| MD_SB_NEED_REWRITE = 3, | |
| }; | |
| +enum mdio_mutex_lock_class { | |
| + MDIO_MUTEX_NORMAL = 0, | |
| + MDIO_MUTEX_MUX = 1, | |
| + MDIO_MUTEX_NESTED = 2, | |
| +}; | |
| + | |
| enum mds_mitigations { | |
| MDS_MITIGATION_OFF = 0, | |
| MDS_MITIGATION_FULL = 1, | |
| @@ -19032,38 +22380,6 @@ | |
| MEM_CGROUP_NTARGETS = 2, | |
| }; | |
| -enum mem_type { | |
| - MEM_EMPTY = 0, | |
| - MEM_RESERVED = 1, | |
| - MEM_UNKNOWN = 2, | |
| - MEM_FPM = 3, | |
| - MEM_EDO = 4, | |
| - MEM_BEDO = 5, | |
| - MEM_SDR = 6, | |
| - MEM_RDR = 7, | |
| - MEM_DDR = 8, | |
| - MEM_RDDR = 9, | |
| - MEM_RMBS = 10, | |
| - MEM_DDR2 = 11, | |
| - MEM_FB_DDR2 = 12, | |
| - MEM_RDDR2 = 13, | |
| - MEM_XDR = 14, | |
| - MEM_DDR3 = 15, | |
| - MEM_RDDR3 = 16, | |
| - MEM_LRDDR3 = 17, | |
| - MEM_LPDDR3 = 18, | |
| - MEM_DDR4 = 19, | |
| - MEM_RDDR4 = 20, | |
| - MEM_LRDDR4 = 21, | |
| - MEM_LPDDR4 = 22, | |
| - MEM_DDR5 = 23, | |
| - MEM_RDDR5 = 24, | |
| - MEM_LRDDR5 = 25, | |
| - MEM_NVDIMM = 26, | |
| - MEM_WIO2 = 27, | |
| - MEM_HBM2 = 28, | |
| -}; | |
| - | |
| enum membarrier_cmd { | |
| MEMBARRIER_CMD_QUERY = 0, | |
| MEMBARRIER_CMD_GLOBAL = 1, | |
| @@ -19089,12 +22405,7 @@ | |
| MEMBLOCK_MIRROR = 2, | |
| MEMBLOCK_NOMAP = 4, | |
| MEMBLOCK_DRIVER_MANAGED = 8, | |
| -}; | |
| - | |
| -enum membw_throttle_mode { | |
| - THREAD_THROTTLE_UNDEFINED = 0, | |
| - THREAD_THROTTLE_MAX = 1, | |
| - THREAD_THROTTLE_PER_THREAD = 2, | |
| + MEMBLOCK_RSRV_NOINIT = 16, | |
| }; | |
| enum memcg_memory_event { | |
| @@ -19111,14 +22422,14 @@ | |
| }; | |
| enum memcg_stat_item { | |
| - MEMCG_SWAP = 43, | |
| - MEMCG_SOCK = 44, | |
| - MEMCG_PERCPU_B = 45, | |
| - MEMCG_VMALLOC = 46, | |
| - MEMCG_KMEM = 47, | |
| - MEMCG_ZSWAP_B = 48, | |
| - MEMCG_ZSWAPPED = 49, | |
| - MEMCG_NR_STAT = 50, | |
| + MEMCG_SWAP = 47, | |
| + MEMCG_SOCK = 48, | |
| + MEMCG_PERCPU_B = 49, | |
| + MEMCG_VMALLOC = 50, | |
| + MEMCG_KMEM = 51, | |
| + MEMCG_ZSWAP_B = 52, | |
| + MEMCG_ZSWAPPED = 53, | |
| + MEMCG_NR_STAT = 54, | |
| }; | |
| enum meminit_context { | |
| @@ -19134,17 +22445,14 @@ | |
| MEMORY_DEVICE_PCI_P2PDMA = 5, | |
| }; | |
| -enum message_alignments { | |
| - MESSAGE_PADDING_MULTIPLE = 16, | |
| - MESSAGE_MINIMUM_LENGTH = 32, | |
| -}; | |
| - | |
| -enum message_type { | |
| - MESSAGE_INVALID = 0, | |
| - MESSAGE_HANDSHAKE_INITIATION = 1, | |
| - MESSAGE_HANDSHAKE_RESPONSE = 2, | |
| - MESSAGE_HANDSHAKE_COOKIE = 3, | |
| - MESSAGE_DATA = 4, | |
| +enum mesh_path_flags { | |
| + MESH_PATH_ACTIVE = 1, | |
| + MESH_PATH_RESOLVING = 2, | |
| + MESH_PATH_SN_VALID = 4, | |
| + MESH_PATH_FIXED = 8, | |
| + MESH_PATH_RESOLVED = 16, | |
| + MESH_PATH_REQ_QUEUED = 32, | |
| + MESH_PATH_DELETED = 64, | |
| }; | |
| enum metadata_type { | |
| @@ -19185,6 +22493,7 @@ | |
| MF_UNPOISON = 16, | |
| MF_SW_SIMULATED = 32, | |
| MF_NO_RETRY = 64, | |
| + MF_MEM_PRE_REMOVE = 128, | |
| }; | |
| enum mf_result { | |
| @@ -19198,7 +22507,8 @@ | |
| MFILL_ATOMIC_COPY = 0, | |
| MFILL_ATOMIC_ZEROPAGE = 1, | |
| MFILL_ATOMIC_CONTINUE = 2, | |
| - NR_MFILL_ATOMIC_MODES = 3, | |
| + MFILL_ATOMIC_POISON = 3, | |
| + NR_MFILL_ATOMIC_MODES = 4, | |
| }; | |
| enum migrate_mode { | |
| @@ -19221,12 +22531,6 @@ | |
| MR_TYPES = 9, | |
| }; | |
| -enum migrate_vma_direction { | |
| - MIGRATE_VMA_SELECT_SYSTEM = 1, | |
| - MIGRATE_VMA_SELECT_DEVICE_PRIVATE = 2, | |
| - MIGRATE_VMA_SELECT_DEVICE_COHERENT = 4, | |
| -}; | |
| - | |
| enum migratetype { | |
| MIGRATE_UNMOVABLE = 0, | |
| MIGRATE_MOVABLE = 1, | |
| @@ -19245,6 +22549,23 @@ | |
| migrate_misfit = 3, | |
| }; | |
| +enum mipi_dsi_compression_algo { | |
| + MIPI_DSI_COMPRESSION_DSC = 0, | |
| + MIPI_DSI_COMPRESSION_VENDOR = 3, | |
| +}; | |
| + | |
| +enum mipi_dsi_dcs_tear_mode { | |
| + MIPI_DSI_DCS_TEAR_MODE_VBLANK = 0, | |
| + MIPI_DSI_DCS_TEAR_MODE_VHBLANK = 1, | |
| +}; | |
| + | |
| +enum mipi_dsi_pixel_format { | |
| + MIPI_DSI_FMT_RGB888 = 0, | |
| + MIPI_DSI_FMT_RGB666 = 1, | |
| + MIPI_DSI_FMT_RGB666_PACKED = 2, | |
| + MIPI_DSI_FMT_RGB565 = 3, | |
| +}; | |
| + | |
| enum mlx4_access_reg_masks { | |
| MLX4_ACCESS_REG_STATUS_MASK = 127, | |
| MLX4_ACCESS_REG_METHOD_MASK = 127, | |
| @@ -19547,681 +22868,6 @@ | |
| MLX4_ZONE_USE_RR = 8, | |
| }; | |
| -enum mlx5_an_status { | |
| - MLX5_AN_UNAVAILABLE = 0, | |
| - MLX5_AN_COMPLETE = 1, | |
| - MLX5_AN_FAILED = 2, | |
| - MLX5_AN_LINK_UP = 3, | |
| - MLX5_AN_LINK_DOWN = 4, | |
| -}; | |
| - | |
| -enum mlx5_beacon_duration { | |
| - MLX5_BEACON_DURATION_OFF = 0, | |
| - MLX5_BEACON_DURATION_INF = 65535, | |
| -}; | |
| - | |
| -enum mlx5_cap_mode { | |
| - HCA_CAP_OPMOD_GET_MAX = 0, | |
| - HCA_CAP_OPMOD_GET_CUR = 1, | |
| -}; | |
| - | |
| -enum mlx5_cap_type { | |
| - MLX5_CAP_GENERAL = 0, | |
| - MLX5_CAP_ETHERNET_OFFLOADS = 1, | |
| - MLX5_CAP_ODP = 2, | |
| - MLX5_CAP_ATOMIC = 3, | |
| - MLX5_CAP_ROCE = 4, | |
| - MLX5_CAP_IPOIB_OFFLOADS = 5, | |
| - MLX5_CAP_IPOIB_ENHANCED_OFFLOADS = 6, | |
| - MLX5_CAP_FLOW_TABLE = 7, | |
| - MLX5_CAP_ESWITCH_FLOW_TABLE = 8, | |
| - MLX5_CAP_ESWITCH = 9, | |
| - MLX5_CAP_RESERVED = 10, | |
| - MLX5_CAP_VECTOR_CALC = 11, | |
| - MLX5_CAP_QOS = 12, | |
| - MLX5_CAP_DEBUG = 13, | |
| - MLX5_CAP_RESERVED_14 = 14, | |
| - MLX5_CAP_DEV_MEM = 15, | |
| - MLX5_CAP_RESERVED_16 = 16, | |
| - MLX5_CAP_TLS = 17, | |
| - MLX5_CAP_VDPA_EMULATION = 19, | |
| - MLX5_CAP_DEV_EVENT = 20, | |
| - MLX5_CAP_IPSEC = 21, | |
| - MLX5_CAP_CRYPTO = 26, | |
| - MLX5_CAP_DEV_SHAMPO = 29, | |
| - MLX5_CAP_MACSEC = 31, | |
| - MLX5_CAP_GENERAL_2 = 32, | |
| - MLX5_CAP_PORT_SELECTION = 37, | |
| - MLX5_CAP_ADV_VIRTUALIZATION = 38, | |
| - MLX5_CAP_NUM = 39, | |
| -}; | |
| - | |
| -enum mlx5_cmd_addr_l_sz_offset { | |
| - MLX5_NIC_IFC_OFFSET = 8, | |
| -}; | |
| - | |
| -enum mlx5_cmdif_state { | |
| - MLX5_CMDIF_STATE_UNINITIALIZED = 0, | |
| - MLX5_CMDIF_STATE_UP = 1, | |
| - MLX5_CMDIF_STATE_DOWN = 2, | |
| -}; | |
| - | |
| -enum mlx5_coredev_type { | |
| - MLX5_COREDEV_PF = 0, | |
| - MLX5_COREDEV_VF = 1, | |
| - MLX5_COREDEV_SF = 2, | |
| -}; | |
| - | |
| -enum mlx5_dcbx_oper_mode { | |
| - MLX5E_DCBX_PARAM_VER_OPER_HOST = 0, | |
| - MLX5E_DCBX_PARAM_VER_OPER_AUTO = 3, | |
| -}; | |
| - | |
| -enum mlx5_dev_event { | |
| - MLX5_DEV_EVENT_SYS_ERROR = 128, | |
| - MLX5_DEV_EVENT_PORT_AFFINITY = 129, | |
| - MLX5_DEV_EVENT_MULTIPORT_ESW = 130, | |
| -}; | |
| - | |
| -enum mlx5_devcom_components { | |
| - MLX5_DEVCOM_ESW_OFFLOADS = 0, | |
| - MLX5_DEVCOM_NUM_COMPONENTS = 1, | |
| -}; | |
| - | |
| -enum mlx5_device_state { | |
| - MLX5_DEVICE_STATE_UP = 1, | |
| - MLX5_DEVICE_STATE_INTERNAL_ERROR = 2, | |
| -}; | |
| - | |
| -enum mlx5_devlink_param_id { | |
| - MLX5_DEVLINK_PARAM_ID_BASE = 16, | |
| - MLX5_DEVLINK_PARAM_ID_FLOW_STEERING_MODE = 17, | |
| - MLX5_DEVLINK_PARAM_ID_ESW_LARGE_GROUP_NUM = 18, | |
| - MLX5_DEVLINK_PARAM_ID_ESW_PORT_METADATA = 19, | |
| - MLX5_DEVLINK_PARAM_ID_ESW_MULTIPORT = 20, | |
| - MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES = 21, | |
| - MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE = 22, | |
| -}; | |
| - | |
| -enum mlx5_driver_event { | |
| - MLX5_DRIVER_EVENT_TYPE_TRAP = 0, | |
| - MLX5_DRIVER_EVENT_UPLINK_NETDEV = 1, | |
| -}; | |
| - | |
| -enum mlx5_event { | |
| - MLX5_EVENT_TYPE_NOTIFY_ANY = 0, | |
| - MLX5_EVENT_TYPE_COMP = 0, | |
| - MLX5_EVENT_TYPE_PATH_MIG = 1, | |
| - MLX5_EVENT_TYPE_COMM_EST = 2, | |
| - MLX5_EVENT_TYPE_SQ_DRAINED = 3, | |
| - MLX5_EVENT_TYPE_SRQ_LAST_WQE = 19, | |
| - MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 20, | |
| - MLX5_EVENT_TYPE_CQ_ERROR = 4, | |
| - MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 5, | |
| - MLX5_EVENT_TYPE_PATH_MIG_FAILED = 7, | |
| - MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 16, | |
| - MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 17, | |
| - MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 18, | |
| - MLX5_EVENT_TYPE_OBJECT_CHANGE = 39, | |
| - MLX5_EVENT_TYPE_INTERNAL_ERROR = 8, | |
| - MLX5_EVENT_TYPE_PORT_CHANGE = 9, | |
| - MLX5_EVENT_TYPE_GPIO_EVENT = 21, | |
| - MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 22, | |
| - MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 23, | |
| - MLX5_EVENT_TYPE_XRQ_ERROR = 24, | |
| - MLX5_EVENT_TYPE_REMOTE_CONFIG = 25, | |
| - MLX5_EVENT_TYPE_GENERAL_EVENT = 34, | |
| - MLX5_EVENT_TYPE_MONITOR_COUNTER = 36, | |
| - MLX5_EVENT_TYPE_PPS_EVENT = 37, | |
| - MLX5_EVENT_TYPE_DB_BF_CONGESTION = 26, | |
| - MLX5_EVENT_TYPE_STALL_EVENT = 27, | |
| - MLX5_EVENT_TYPE_CMD = 10, | |
| - MLX5_EVENT_TYPE_PAGE_REQUEST = 11, | |
| - MLX5_EVENT_TYPE_PAGE_FAULT = 12, | |
| - MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 13, | |
| - MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 14, | |
| - MLX5_EVENT_TYPE_VHCA_STATE_CHANGE = 15, | |
| - MLX5_EVENT_TYPE_DCT_DRAINED = 28, | |
| - MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 29, | |
| - MLX5_EVENT_TYPE_FPGA_ERROR = 32, | |
| - MLX5_EVENT_TYPE_FPGA_QP_ERROR = 33, | |
| - MLX5_EVENT_TYPE_DEVICE_TRACER = 38, | |
| - MLX5_EVENT_TYPE_MAX = 256, | |
| -}; | |
| - | |
| -enum mlx5_fc_bulk_alloc_bitmask { | |
| - MLX5_FC_BULK_128 = 1, | |
| - MLX5_FC_BULK_256 = 2, | |
| - MLX5_FC_BULK_512 = 4, | |
| - MLX5_FC_BULK_1024 = 8, | |
| - MLX5_FC_BULK_2048 = 16, | |
| - MLX5_FC_BULK_4096 = 32, | |
| - MLX5_FC_BULK_8192 = 64, | |
| - MLX5_FC_BULK_16384 = 128, | |
| -}; | |
| - | |
| -enum mlx5_flow_dest_range_field { | |
| - MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN = 0, | |
| -}; | |
| - | |
| -enum mlx5_flow_destination_type { | |
| - MLX5_FLOW_DESTINATION_TYPE_NONE = 0, | |
| - MLX5_FLOW_DESTINATION_TYPE_VPORT = 1, | |
| - MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 2, | |
| - MLX5_FLOW_DESTINATION_TYPE_TIR = 3, | |
| - MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 4, | |
| - MLX5_FLOW_DESTINATION_TYPE_UPLINK = 5, | |
| - MLX5_FLOW_DESTINATION_TYPE_PORT = 6, | |
| - MLX5_FLOW_DESTINATION_TYPE_COUNTER = 7, | |
| - MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 8, | |
| - MLX5_FLOW_DESTINATION_TYPE_RANGE = 9, | |
| - MLX5_FLOW_DESTINATION_TYPE_TABLE_TYPE = 10, | |
| -}; | |
| - | |
| -enum mlx5_flow_namespace_type { | |
| - MLX5_FLOW_NAMESPACE_BYPASS = 0, | |
| - MLX5_FLOW_NAMESPACE_KERNEL_RX_MACSEC = 1, | |
| - MLX5_FLOW_NAMESPACE_LAG = 2, | |
| - MLX5_FLOW_NAMESPACE_OFFLOADS = 3, | |
| - MLX5_FLOW_NAMESPACE_ETHTOOL = 4, | |
| - MLX5_FLOW_NAMESPACE_KERNEL = 5, | |
| - MLX5_FLOW_NAMESPACE_LEFTOVERS = 6, | |
| - MLX5_FLOW_NAMESPACE_ANCHOR = 7, | |
| - MLX5_FLOW_NAMESPACE_FDB_BYPASS = 8, | |
| - MLX5_FLOW_NAMESPACE_FDB = 9, | |
| - MLX5_FLOW_NAMESPACE_ESW_EGRESS = 10, | |
| - MLX5_FLOW_NAMESPACE_ESW_INGRESS = 11, | |
| - MLX5_FLOW_NAMESPACE_SNIFFER_RX = 12, | |
| - MLX5_FLOW_NAMESPACE_SNIFFER_TX = 13, | |
| - MLX5_FLOW_NAMESPACE_EGRESS = 14, | |
| - MLX5_FLOW_NAMESPACE_EGRESS_IPSEC = 15, | |
| - MLX5_FLOW_NAMESPACE_EGRESS_MACSEC = 16, | |
| - MLX5_FLOW_NAMESPACE_RDMA_RX = 17, | |
| - MLX5_FLOW_NAMESPACE_RDMA_RX_KERNEL = 18, | |
| - MLX5_FLOW_NAMESPACE_RDMA_TX = 19, | |
| - MLX5_FLOW_NAMESPACE_PORT_SEL = 20, | |
| - MLX5_FLOW_NAMESPACE_RDMA_RX_COUNTERS = 21, | |
| - MLX5_FLOW_NAMESPACE_RDMA_TX_COUNTERS = 22, | |
| - MLX5_FLOW_NAMESPACE_RDMA_RX_IPSEC = 23, | |
| - MLX5_FLOW_NAMESPACE_RDMA_TX_IPSEC = 24, | |
| -}; | |
| - | |
| -enum mlx5_flow_resource_owner { | |
| - MLX5_FLOW_RESOURCE_OWNER_FW = 0, | |
| - MLX5_FLOW_RESOURCE_OWNER_SW = 1, | |
| -}; | |
| - | |
| -enum mlx5_flow_steering_mode { | |
| - MLX5_FLOW_STEERING_MODE_DMFS = 0, | |
| - MLX5_FLOW_STEERING_MODE_SMFS = 1, | |
| -}; | |
| - | |
| -enum mlx5_flow_table_miss_action { | |
| - MLX5_FLOW_TABLE_MISS_ACTION_DEF = 0, | |
| - MLX5_FLOW_TABLE_MISS_ACTION_FWD = 1, | |
| - MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN = 2, | |
| -}; | |
| - | |
| -enum mlx5_func_type { | |
| - MLX5_PF = 0, | |
| - MLX5_VF = 1, | |
| - MLX5_SF = 2, | |
| - MLX5_HOST_PF = 3, | |
| - MLX5_FUNC_TYPE_NUM = 4, | |
| -}; | |
| - | |
| -enum mlx5_fw_tracer_ownership_state { | |
| - MLX5_FW_TRACER_RELEASE_OWNERSHIP = 0, | |
| - MLX5_FW_TRACER_ACQUIRE_OWNERSHIP = 1, | |
| -}; | |
| - | |
| -enum mlx5_fw_tracer_state { | |
| - MLX5_TRACER_STATE_UP = 1, | |
| - MLX5_TRACER_RECREATE_DB = 2, | |
| -}; | |
| - | |
| -enum mlx5_ifc_flow_destination_type { | |
| - MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0, | |
| - MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 1, | |
| - MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 2, | |
| - MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 6, | |
| - MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 8, | |
| - MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 10, | |
| -}; | |
| - | |
| -enum mlx5_initializing_bit_offsets { | |
| - MLX5_FW_RESET_SUPPORTED_OFFSET = 30, | |
| -}; | |
| - | |
| -enum mlx5_inline_modes { | |
| - MLX5_INLINE_MODE_NONE = 0, | |
| - MLX5_INLINE_MODE_L2 = 1, | |
| - MLX5_INLINE_MODE_IP = 2, | |
| - MLX5_INLINE_MODE_TCP_UDP = 3, | |
| -}; | |
| - | |
| -enum mlx5_interface_state { | |
| - MLX5_INTERFACE_STATE_UP = 1, | |
| - MLX5_BREAK_FW_WAIT = 2, | |
| -}; | |
| - | |
| -enum mlx5_ipsec_cap { | |
| - MLX5_IPSEC_CAP_CRYPTO = 1, | |
| - MLX5_IPSEC_CAP_ESN = 2, | |
| - MLX5_IPSEC_CAP_PACKET_OFFLOAD = 4, | |
| - MLX5_IPSEC_CAP_ROCE = 8, | |
| - MLX5_IPSEC_CAP_PRIO = 16, | |
| - MLX5_IPSEC_CAP_TUNNEL = 32, | |
| -}; | |
| - | |
| -enum mlx5_lag_mode { | |
| - MLX5_LAG_MODE_NONE = 0, | |
| - MLX5_LAG_MODE_ROCE = 1, | |
| - MLX5_LAG_MODE_SRIOV = 2, | |
| - MLX5_LAG_MODE_MULTIPATH = 3, | |
| - MLX5_LAG_MODE_MPESW = 4, | |
| -}; | |
| - | |
| -enum mlx5_list_type { | |
| - MLX5_NVPRT_LIST_TYPE_UC = 0, | |
| - MLX5_NVPRT_LIST_TYPE_MC = 1, | |
| - MLX5_NVPRT_LIST_TYPE_VLAN = 2, | |
| -}; | |
| - | |
| -enum mlx5_mcam_feature_groups { | |
| - MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0, | |
| -}; | |
| - | |
| -enum mlx5_mcam_reg_groups { | |
| - MLX5_MCAM_REGS_FIRST_128 = 0, | |
| - MLX5_MCAM_REGS_0x9080_0x90FF = 1, | |
| - MLX5_MCAM_REGS_0x9100_0x917F = 2, | |
| - MLX5_MCAM_REGS_NUM = 3, | |
| -}; | |
| - | |
| -enum mlx5_module_id { | |
| - MLX5_MODULE_ID_SFP = 3, | |
| - MLX5_MODULE_ID_QSFP = 12, | |
| - MLX5_MODULE_ID_QSFP_PLUS = 13, | |
| - MLX5_MODULE_ID_QSFP28 = 17, | |
| - MLX5_MODULE_ID_DSFP = 27, | |
| -}; | |
| - | |
| -enum mlx5_monitor_counter_ppcnt { | |
| - MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0, | |
| - MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 1, | |
| - MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 2, | |
| - MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 3, | |
| - MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 4, | |
| - MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 5, | |
| -}; | |
| - | |
| -enum mlx5_pcam_feature_groups { | |
| - MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0, | |
| -}; | |
| - | |
| -enum mlx5_pcam_reg_groups { | |
| - MLX5_PCAM_REGS_5000_TO_507F = 0, | |
| -}; | |
| - | |
| -enum mlx5_pci_status { | |
| - MLX5_PCI_STATUS_DISABLED = 0, | |
| - MLX5_PCI_STATUS_ENABLED = 1, | |
| -}; | |
| - | |
| -enum mlx5_port_status { | |
| - MLX5_PORT_UP = 1, | |
| - MLX5_PORT_DOWN = 2, | |
| -}; | |
| - | |
| -enum mlx5_qcam_feature_groups { | |
| - MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0, | |
| -}; | |
| - | |
| -enum mlx5_qcam_reg_groups { | |
| - MLX5_QCAM_REGS_FIRST_128 = 0, | |
| -}; | |
| - | |
| -enum mlx5_qp_state { | |
| - MLX5_QP_STATE_RST = 0, | |
| - MLX5_QP_STATE_INIT = 1, | |
| - MLX5_QP_STATE_RTR = 2, | |
| - MLX5_QP_STATE_RTS = 3, | |
| - MLX5_QP_STATE_SQER = 4, | |
| - MLX5_QP_STATE_SQD = 5, | |
| - MLX5_QP_STATE_ERR = 6, | |
| - MLX5_QP_STATE_SQ_DRAINING = 7, | |
| - MLX5_QP_STATE_SUSPENDED = 9, | |
| - MLX5_QP_NUM_STATE = 10, | |
| - MLX5_QP_STATE = 11, | |
| - MLX5_QP_STATE_BAD = 12, | |
| -}; | |
| - | |
| -enum mlx5_qpts_trust_state { | |
| - MLX5_QPTS_TRUST_PCP = 1, | |
| - MLX5_QPTS_TRUST_DSCP = 2, | |
| -}; | |
| - | |
| -enum mlx5_res_type { | |
| - MLX5_RES_QP = 0, | |
| - MLX5_RES_RQ = 1, | |
| - MLX5_RES_SQ = 2, | |
| - MLX5_RES_SRQ = 3, | |
| - MLX5_RES_XSRQ = 4, | |
| - MLX5_RES_XRQ = 5, | |
| - MLX5_RES_DCT = 6, | |
| -}; | |
| - | |
| -enum mlx5_rfr_severity_bit_offsets { | |
| - MLX5_RFR_BIT_OFFSET = 7, | |
| -}; | |
| - | |
| -enum mlx5_semaphore_space_address { | |
| - MLX5_SEMAPHORE_SPACE_DOMAIN = 10, | |
| - MLX5_SEMAPHORE_SW_RESET = 32, | |
| -}; | |
| - | |
| -enum mlx5_sgmt_type { | |
| - MLX5_SGMT_TYPE_HW_CQPC = 0, | |
| - MLX5_SGMT_TYPE_HW_SQPC = 1, | |
| - MLX5_SGMT_TYPE_HW_RQPC = 2, | |
| - MLX5_SGMT_TYPE_FULL_SRQC = 3, | |
| - MLX5_SGMT_TYPE_FULL_CQC = 4, | |
| - MLX5_SGMT_TYPE_FULL_EQC = 5, | |
| - MLX5_SGMT_TYPE_FULL_QPC = 6, | |
| - MLX5_SGMT_TYPE_SND_BUFF = 7, | |
| - MLX5_SGMT_TYPE_RCV_BUFF = 8, | |
| - MLX5_SGMT_TYPE_SRQ_BUFF = 9, | |
| - MLX5_SGMT_TYPE_CQ_BUFF = 10, | |
| - MLX5_SGMT_TYPE_EQ_BUFF = 11, | |
| - MLX5_SGMT_TYPE_SX_SLICE = 12, | |
| - MLX5_SGMT_TYPE_SX_SLICE_ALL = 13, | |
| - MLX5_SGMT_TYPE_RDB = 14, | |
| - MLX5_SGMT_TYPE_RX_SLICE_ALL = 15, | |
| - MLX5_SGMT_TYPE_PRM_QUERY_QP = 16, | |
| - MLX5_SGMT_TYPE_PRM_QUERY_CQ = 17, | |
| - MLX5_SGMT_TYPE_PRM_QUERY_MKEY = 18, | |
| - MLX5_SGMT_TYPE_MENU = 19, | |
| - MLX5_SGMT_TYPE_TERMINATE = 20, | |
| - MLX5_SGMT_TYPE_NUM = 21, | |
| -}; | |
| - | |
| -enum mlx5_sw_icm_type { | |
| - MLX5_SW_ICM_TYPE_STEERING = 0, | |
| - MLX5_SW_ICM_TYPE_HEADER_MODIFY = 1, | |
| - MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN = 2, | |
| -}; | |
| - | |
| -enum mlx5_timeouts_types { | |
| - MLX5_TO_FW_PRE_INIT_TIMEOUT_MS = 0, | |
| - MLX5_TO_FW_PRE_INIT_ON_RECOVERY_TIMEOUT_MS = 1, | |
| - MLX5_TO_FW_PRE_INIT_WARN_MESSAGE_INTERVAL_MS = 2, | |
| - MLX5_TO_FW_PRE_INIT_WAIT_MS = 3, | |
| - MLX5_TO_FW_INIT_MS = 4, | |
| - MLX5_TO_CMD_MS = 5, | |
| - MLX5_TO_PCI_TOGGLE_MS = 6, | |
| - MLX5_TO_HEALTH_POLL_INTERVAL_MS = 7, | |
| - MLX5_TO_FULL_CRDUMP_MS = 8, | |
| - MLX5_TO_FW_RESET_MS = 9, | |
| - MLX5_TO_FLUSH_ON_ERROR_MS = 10, | |
| - MLX5_TO_PCI_SYNC_UPDATE_MS = 11, | |
| - MLX5_TO_TEARDOWN_MS = 12, | |
| - MLX5_TO_FSM_REACTIVATE_MS = 13, | |
| - MLX5_TO_RECLAIM_PAGES_MS = 14, | |
| - MLX5_TO_RECLAIM_VFS_PAGES_MS = 15, | |
| - MAX_TIMEOUT_TYPES = 16, | |
| -}; | |
| - | |
| -enum mlx5_traffic_types { | |
| - MLX5_TT_IPV4_TCP = 0, | |
| - MLX5_TT_IPV6_TCP = 1, | |
| - MLX5_TT_IPV4_UDP = 2, | |
| - MLX5_TT_IPV6_UDP = 3, | |
| - MLX5_TT_IPV4_IPSEC_AH = 4, | |
| - MLX5_TT_IPV6_IPSEC_AH = 5, | |
| - MLX5_TT_IPV4_IPSEC_ESP = 6, | |
| - MLX5_TT_IPV6_IPSEC_ESP = 7, | |
| - MLX5_TT_IPV4 = 8, | |
| - MLX5_TT_IPV6 = 9, | |
| - MLX5_TT_ANY = 10, | |
| - MLX5_NUM_TT = 11, | |
| - MLX5_NUM_INDIR_TIRS = 10, | |
| -}; | |
| - | |
| -enum mlx5_tunnel_types { | |
| - MLX5_TT_IPV4_GRE = 0, | |
| - MLX5_TT_IPV6_GRE = 1, | |
| - MLX5_TT_IPV4_IPIP = 2, | |
| - MLX5_TT_IPV6_IPIP = 3, | |
| - MLX5_TT_IPV4_IPV6 = 4, | |
| - MLX5_TT_IPV6_IPV6 = 5, | |
| - MLX5_NUM_TUNNEL_TT = 6, | |
| -}; | |
| - | |
| -enum mlx5_vport_roce_state { | |
| - MLX5_VPORT_ROCE_DISABLED = 0, | |
| - MLX5_VPORT_ROCE_ENABLED = 1, | |
| -}; | |
| - | |
| -enum mlx5_vsc_state { | |
| - MLX5_VSC_UNLOCK = 0, | |
| - MLX5_VSC_LOCK = 1, | |
| -}; | |
| - | |
| -enum mlx5_wol_mode { | |
| - MLX5_WOL_DISABLE = 0, | |
| - MLX5_WOL_SECURED_MAGIC = 2, | |
| - MLX5_WOL_MAGIC = 4, | |
| - MLX5_WOL_ARP = 8, | |
| - MLX5_WOL_BROADCAST = 16, | |
| - MLX5_WOL_MULTICAST = 32, | |
| - MLX5_WOL_UNICAST = 64, | |
| - MLX5_WOL_PHY_ACTIVITY = 128, | |
| -}; | |
| - | |
| -enum mlx5e_channel_state { | |
| - MLX5E_CHANNEL_STATE_XSK = 0, | |
| - MLX5E_CHANNEL_NUM_STATES = 1, | |
| -}; | |
| - | |
| -enum mlx5e_connector_type { | |
| - MLX5E_PORT_UNKNOWN = 0, | |
| - MLX5E_PORT_NONE = 1, | |
| - MLX5E_PORT_TP = 2, | |
| - MLX5E_PORT_AUI = 3, | |
| - MLX5E_PORT_BNC = 4, | |
| - MLX5E_PORT_MII = 5, | |
| - MLX5E_PORT_FIBRE = 6, | |
| - MLX5E_PORT_DA = 7, | |
| - MLX5E_PORT_OTHER = 8, | |
| - MLX5E_CONNECTOR_TYPE_NUMBER = 9, | |
| -}; | |
| - | |
| -enum mlx5e_dma_map_type { | |
| - MLX5E_DMA_MAP_SINGLE = 0, | |
| - MLX5E_DMA_MAP_PAGE = 1, | |
| -}; | |
| - | |
| -enum mlx5e_ext_link_mode { | |
| - MLX5E_SGMII_100M = 0, | |
| - MLX5E_1000BASE_X_SGMII = 1, | |
| - MLX5E_5GBASE_R = 3, | |
| - MLX5E_10GBASE_XFI_XAUI_1 = 4, | |
| - MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5, | |
| - MLX5E_25GAUI_1_25GBASE_CR_KR = 6, | |
| - MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7, | |
| - MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8, | |
| - MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9, | |
| - MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10, | |
| - MLX5E_100GAUI_1_100GBASE_CR_KR = 11, | |
| - MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12, | |
| - MLX5E_200GAUI_2_200GBASE_CR2_KR2 = 13, | |
| - MLX5E_400GAUI_8 = 15, | |
| - MLX5E_400GAUI_4_400GBASE_CR4_KR4 = 16, | |
| - MLX5E_EXT_LINK_MODES_NUMBER = 17, | |
| -}; | |
| - | |
| -enum mlx5e_fec_supported_link_mode { | |
| - MLX5E_FEC_SUPPORTED_LINK_MODES_10G_40G = 0, | |
| - MLX5E_FEC_SUPPORTED_LINK_MODES_25G = 1, | |
| - MLX5E_FEC_SUPPORTED_LINK_MODES_50G = 2, | |
| - MLX5E_FEC_SUPPORTED_LINK_MODES_56G = 3, | |
| - MLX5E_FEC_SUPPORTED_LINK_MODES_100G = 4, | |
| - MLX5E_FEC_SUPPORTED_LINK_MODE_50G_1X = 5, | |
| - MLX5E_FEC_SUPPORTED_LINK_MODE_100G_2X = 6, | |
| - MLX5E_FEC_SUPPORTED_LINK_MODE_200G_4X = 7, | |
| - MLX5E_FEC_SUPPORTED_LINK_MODE_400G_8X = 8, | |
| - MLX5E_MAX_FEC_SUPPORTED_LINK_MODE = 9, | |
| -}; | |
| - | |
| -enum mlx5e_icosq_wqe_type { | |
| - MLX5E_ICOSQ_WQE_NOP = 0, | |
| - MLX5E_ICOSQ_WQE_UMR_RX = 1, | |
| - MLX5E_ICOSQ_WQE_SHAMPO_HD_UMR = 2, | |
| -}; | |
| - | |
| -enum mlx5e_link_mode { | |
| - MLX5E_1000BASE_CX_SGMII = 0, | |
| - MLX5E_1000BASE_KX = 1, | |
| - MLX5E_10GBASE_CX4 = 2, | |
| - MLX5E_10GBASE_KX4 = 3, | |
| - MLX5E_10GBASE_KR = 4, | |
| - MLX5E_20GBASE_KR2 = 5, | |
| - MLX5E_40GBASE_CR4 = 6, | |
| - MLX5E_40GBASE_KR4 = 7, | |
| - MLX5E_56GBASE_R4 = 8, | |
| - MLX5E_10GBASE_CR = 12, | |
| - MLX5E_10GBASE_SR = 13, | |
| - MLX5E_10GBASE_ER = 14, | |
| - MLX5E_40GBASE_SR4 = 15, | |
| - MLX5E_40GBASE_LR4 = 16, | |
| - MLX5E_50GBASE_SR2 = 18, | |
| - MLX5E_100GBASE_CR4 = 20, | |
| - MLX5E_100GBASE_SR4 = 21, | |
| - MLX5E_100GBASE_KR4 = 22, | |
| - MLX5E_100GBASE_LR4 = 23, | |
| - MLX5E_100BASE_TX = 24, | |
| - MLX5E_1000BASE_T = 25, | |
| - MLX5E_10GBASE_T = 26, | |
| - MLX5E_25GBASE_CR = 27, | |
| - MLX5E_25GBASE_KR = 28, | |
| - MLX5E_25GBASE_SR = 29, | |
| - MLX5E_50GBASE_CR2 = 30, | |
| - MLX5E_50GBASE_KR2 = 31, | |
| - MLX5E_LINK_MODES_NUMBER = 32, | |
| -}; | |
| - | |
| -enum mlx5e_mpwrq_umr_mode { | |
| - MLX5E_MPWRQ_UMR_MODE_ALIGNED = 0, | |
| - MLX5E_MPWRQ_UMR_MODE_UNALIGNED = 1, | |
| - MLX5E_MPWRQ_UMR_MODE_OVERSIZED = 2, | |
| - MLX5E_MPWRQ_UMR_MODE_TRIPLE = 3, | |
| -}; | |
| - | |
| -enum mlx5e_priv_flag { | |
| - MLX5E_PFLAG_RX_CQE_BASED_MODER = 0, | |
| - MLX5E_PFLAG_TX_CQE_BASED_MODER = 1, | |
| - MLX5E_PFLAG_RX_CQE_COMPRESS = 2, | |
| - MLX5E_PFLAG_RX_STRIDING_RQ = 3, | |
| - MLX5E_PFLAG_RX_NO_CSUM_COMPLETE = 4, | |
| - MLX5E_PFLAG_XDP_TX_MPWQE = 5, | |
| - MLX5E_PFLAG_SKB_TX_MPWQE = 6, | |
| - MLX5E_PFLAG_TX_PORT_TS = 7, | |
| - MLX5E_NUM_PFLAGS = 8, | |
| -}; | |
| - | |
| -enum mlx5e_profile_feature { | |
| - MLX5E_PROFILE_FEATURE_PTP_RX = 0, | |
| - MLX5E_PROFILE_FEATURE_PTP_TX = 1, | |
| - MLX5E_PROFILE_FEATURE_QOS_HTB = 2, | |
| - MLX5E_PROFILE_FEATURE_FS_VLAN = 3, | |
| - MLX5E_PROFILE_FEATURE_FS_TC = 4, | |
| -}; | |
| - | |
| -enum mlx5e_rq_flag { | |
| - MLX5E_RQ_FLAG_XDP_XMIT = 0, | |
| - MLX5E_RQ_FLAG_XDP_REDIRECT = 1, | |
| -}; | |
| - | |
| -enum mlx5e_rx_res_features { | |
| - MLX5E_RX_RES_FEATURE_INNER_FT = 1, | |
| - MLX5E_RX_RES_FEATURE_PTP = 2, | |
| -}; | |
| - | |
| -enum mlx5e_vlan_rule_type { | |
| - MLX5E_VLAN_RULE_TYPE_UNTAGGED = 0, | |
| - MLX5E_VLAN_RULE_TYPE_ANY_CTAG_VID = 1, | |
| - MLX5E_VLAN_RULE_TYPE_ANY_STAG_VID = 2, | |
| - MLX5E_VLAN_RULE_TYPE_MATCH_CTAG_VID = 3, | |
| - MLX5E_VLAN_RULE_TYPE_MATCH_STAG_VID = 4, | |
| -}; | |
| - | |
| -enum mlx5e_wqe_frag_flag { | |
| - MLX5E_WQE_FRAG_LAST_IN_PAGE = 0, | |
| - MLX5E_WQE_FRAG_SKIP_RELEASE = 1, | |
| -}; | |
| - | |
| -enum mlx5e_xdp_xmit_mode { | |
| - MLX5E_XDP_XMIT_MODE_FRAME = 0, | |
| - MLX5E_XDP_XMIT_MODE_PAGE = 1, | |
| - MLX5E_XDP_XMIT_MODE_XSK = 2, | |
| -}; | |
| - | |
| -enum mlxfw_fsm_reactivate_status { | |
| - MLXFW_FSM_REACTIVATE_STATUS_OK = 0, | |
| - MLXFW_FSM_REACTIVATE_STATUS_BUSY = 1, | |
| - MLXFW_FSM_REACTIVATE_STATUS_PROHIBITED_FW_VER_ERR = 2, | |
| - MLXFW_FSM_REACTIVATE_STATUS_FIRST_PAGE_COPY_FAILED = 3, | |
| - MLXFW_FSM_REACTIVATE_STATUS_FIRST_PAGE_ERASE_FAILED = 4, | |
| - MLXFW_FSM_REACTIVATE_STATUS_FIRST_PAGE_RESTORE_FAILED = 5, | |
| - MLXFW_FSM_REACTIVATE_STATUS_CANDIDATE_FW_DEACTIVATION_FAILED = 6, | |
| - MLXFW_FSM_REACTIVATE_STATUS_FW_ALREADY_ACTIVATED = 7, | |
| - MLXFW_FSM_REACTIVATE_STATUS_ERR_DEVICE_RESET_REQUIRED = 8, | |
| - MLXFW_FSM_REACTIVATE_STATUS_ERR_FW_PROGRAMMING_NEEDED = 9, | |
| - MLXFW_FSM_REACTIVATE_STATUS_MAX = 10, | |
| -}; | |
| - | |
| -enum mlxfw_fsm_state { | |
| - MLXFW_FSM_STATE_IDLE = 0, | |
| - MLXFW_FSM_STATE_LOCKED = 1, | |
| - MLXFW_FSM_STATE_INITIALIZE = 2, | |
| - MLXFW_FSM_STATE_DOWNLOAD = 3, | |
| - MLXFW_FSM_STATE_VERIFY = 4, | |
| - MLXFW_FSM_STATE_APPLY = 5, | |
| - MLXFW_FSM_STATE_ACTIVATE = 6, | |
| -}; | |
| - | |
| -enum mlxfw_fsm_state_err { | |
| - MLXFW_FSM_STATE_ERR_OK = 0, | |
| - MLXFW_FSM_STATE_ERR_ERROR = 1, | |
| - MLXFW_FSM_STATE_ERR_REJECTED_DIGEST_ERR = 2, | |
| - MLXFW_FSM_STATE_ERR_REJECTED_NOT_APPLICABLE = 3, | |
| - MLXFW_FSM_STATE_ERR_REJECTED_UNKNOWN_KEY = 4, | |
| - MLXFW_FSM_STATE_ERR_REJECTED_AUTH_FAILED = 5, | |
| - MLXFW_FSM_STATE_ERR_REJECTED_UNSIGNED = 6, | |
| - MLXFW_FSM_STATE_ERR_REJECTED_KEY_NOT_APPLICABLE = 7, | |
| - MLXFW_FSM_STATE_ERR_REJECTED_BAD_FORMAT = 8, | |
| - MLXFW_FSM_STATE_ERR_BLOCKED_PENDING_RESET = 9, | |
| - MLXFW_FSM_STATE_ERR_MAX = 10, | |
| -}; | |
| - | |
| -enum mlxfw_mfa2_tlv_type { | |
| - MLXFW_MFA2_TLV_MULTI_PART = 1, | |
| - MLXFW_MFA2_TLV_PACKAGE_DESCRIPTOR = 2, | |
| - MLXFW_MFA2_TLV_COMPONENT_DESCRIPTOR = 4, | |
| - MLXFW_MFA2_TLV_COMPONENT_PTR = 34, | |
| - MLXFW_MFA2_TLV_PSID = 42, | |
| -}; | |
| - | |
| -enum mlxsw_reg_mcc_instruction { | |
| - MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 1, | |
| - MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 2, | |
| - MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 3, | |
| - MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 4, | |
| - MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 6, | |
| - MLX5_REG_MCC_INSTRUCTION_CANCEL = 8, | |
| -}; | |
| - | |
| enum mm_cid_state { | |
| MM_CID_UNSET = 4294967295, | |
| MM_CID_LAZY_PUT = 2147483648, | |
| @@ -20250,6 +22896,11 @@ | |
| MMU_NOTIFY_EXCLUSIVE = 7, | |
| }; | |
| +enum mnt_tree_flags_t { | |
| + MNT_TREE_MOVE = 1, | |
| + MNT_TREE_BENEATH = 2, | |
| +}; | |
| + | |
| enum mod_license { | |
| NOT_GPL_ONLY = 0, | |
| GPL_ONLY = 1, | |
| @@ -20274,6 +22925,43 @@ | |
| MODULE_STATE_UNFORMED = 3, | |
| }; | |
| +enum monitor_flags { | |
| + MONITOR_FLAG_CHANGED = 1, | |
| + MONITOR_FLAG_FCSFAIL = 2, | |
| + MONITOR_FLAG_PLCPFAIL = 4, | |
| + MONITOR_FLAG_CONTROL = 8, | |
| + MONITOR_FLAG_OTHER_BSS = 16, | |
| + MONITOR_FLAG_COOK_FRAMES = 32, | |
| + MONITOR_FLAG_ACTIVE = 64, | |
| +}; | |
| + | |
| +enum mountstat { | |
| + MNT_OK = 0, | |
| + MNT_EPERM = 1, | |
| + MNT_ENOENT = 2, | |
| + MNT_EACCES = 13, | |
| + MNT_EINVAL = 22, | |
| +}; | |
| + | |
| +enum mountstat3 { | |
| + MNT3_OK = 0, | |
| + MNT3ERR_PERM = 1, | |
| + MNT3ERR_NOENT = 2, | |
| + MNT3ERR_IO = 5, | |
| + MNT3ERR_ACCES = 13, | |
| + MNT3ERR_NOTDIR = 20, | |
| + MNT3ERR_INVAL = 22, | |
| + MNT3ERR_NAMETOOLONG = 63, | |
| + MNT3ERR_NOTSUPP = 10004, | |
| + MNT3ERR_SERVERFAULT = 10006, | |
| +}; | |
| + | |
| +enum mousedev_emul { | |
| + MOUSEDEV_EMUL_PS2 = 0, | |
| + MOUSEDEV_EMUL_IMPS = 1, | |
| + MOUSEDEV_EMUL_EXPS = 2, | |
| +}; | |
| + | |
| enum mp_irq_source_types { | |
| mp_INT = 0, | |
| mp_NMI = 1, | |
| @@ -20281,6 +22969,103 @@ | |
| mp_ExtINT = 3, | |
| }; | |
| +enum mpath_info_flags { | |
| + MPATH_INFO_FRAME_QLEN = 1, | |
| + MPATH_INFO_SN = 2, | |
| + MPATH_INFO_METRIC = 4, | |
| + MPATH_INFO_EXPTIME = 8, | |
| + MPATH_INFO_DISCOVERY_TIMEOUT = 16, | |
| + MPATH_INFO_DISCOVERY_RETRIES = 32, | |
| + MPATH_INFO_FLAGS = 64, | |
| + MPATH_INFO_HOP_COUNT = 128, | |
| + MPATH_INFO_PATH_CHANGE = 256, | |
| +}; | |
| + | |
| +enum mpls_payload_type { | |
| + MPT_UNSPEC = 0, | |
| + MPT_IPV4 = 4, | |
| + MPT_IPV6 = 6, | |
| +}; | |
| + | |
| +enum mpls_ttl_propagation { | |
| + MPLS_TTL_PROP_DEFAULT = 0, | |
| + MPLS_TTL_PROP_ENABLED = 1, | |
| + MPLS_TTL_PROP_DISABLED = 2, | |
| +}; | |
| + | |
| +enum mptcp_addr_signal_status { | |
| + MPTCP_ADD_ADDR_SIGNAL = 0, | |
| + MPTCP_ADD_ADDR_ECHO = 1, | |
| + MPTCP_RM_ADDR_SIGNAL = 2, | |
| +}; | |
| + | |
| +enum mptcp_event_attr { | |
| + MPTCP_ATTR_UNSPEC = 0, | |
| + MPTCP_ATTR_TOKEN = 1, | |
| + MPTCP_ATTR_FAMILY = 2, | |
| + MPTCP_ATTR_LOC_ID = 3, | |
| + MPTCP_ATTR_REM_ID = 4, | |
| + MPTCP_ATTR_SADDR4 = 5, | |
| + MPTCP_ATTR_SADDR6 = 6, | |
| + MPTCP_ATTR_DADDR4 = 7, | |
| + MPTCP_ATTR_DADDR6 = 8, | |
| + MPTCP_ATTR_SPORT = 9, | |
| + MPTCP_ATTR_DPORT = 10, | |
| + MPTCP_ATTR_BACKUP = 11, | |
| + MPTCP_ATTR_ERROR = 12, | |
| + MPTCP_ATTR_FLAGS = 13, | |
| + MPTCP_ATTR_TIMEOUT = 14, | |
| + MPTCP_ATTR_IF_IDX = 15, | |
| + MPTCP_ATTR_RESET_REASON = 16, | |
| + MPTCP_ATTR_RESET_FLAGS = 17, | |
| + MPTCP_ATTR_SERVER_SIDE = 18, | |
| + __MPTCP_ATTR_MAX = 19, | |
| +}; | |
| + | |
| +enum mptcp_event_type { | |
| + MPTCP_EVENT_UNSPEC = 0, | |
| + MPTCP_EVENT_CREATED = 1, | |
| + MPTCP_EVENT_ESTABLISHED = 2, | |
| + MPTCP_EVENT_CLOSED = 3, | |
| + MPTCP_EVENT_ANNOUNCED = 6, | |
| + MPTCP_EVENT_REMOVED = 7, | |
| + MPTCP_EVENT_SUB_ESTABLISHED = 10, | |
| + MPTCP_EVENT_SUB_CLOSED = 11, | |
| + MPTCP_EVENT_SUB_PRIORITY = 13, | |
| + MPTCP_EVENT_LISTENER_CREATED = 15, | |
| + MPTCP_EVENT_LISTENER_CLOSED = 16, | |
| +}; | |
| + | |
| +enum mptcp_pm_status { | |
| + MPTCP_PM_ADD_ADDR_RECEIVED = 0, | |
| + MPTCP_PM_ADD_ADDR_SEND_ACK = 1, | |
| + MPTCP_PM_RM_ADDR_RECEIVED = 2, | |
| + MPTCP_PM_ESTABLISHED = 3, | |
| + MPTCP_PM_SUBFLOW_ESTABLISHED = 4, | |
| + MPTCP_PM_ALREADY_ESTABLISHED = 5, | |
| + MPTCP_PM_MPC_ENDPOINT_ACCOUNTED = 6, | |
| +}; | |
| + | |
| +enum mptcp_pm_type { | |
| + MPTCP_PM_TYPE_KERNEL = 0, | |
| + MPTCP_PM_TYPE_USERSPACE = 1, | |
| + __MPTCP_PM_TYPE_NR = 2, | |
| + __MPTCP_PM_TYPE_MAX = 1, | |
| +}; | |
| + | |
| +enum mptsas_hotplug_action { | |
| + MPTSAS_ADD_DEVICE = 0, | |
| + MPTSAS_DEL_DEVICE = 1, | |
| + MPTSAS_ADD_RAID = 2, | |
| + MPTSAS_DEL_RAID = 3, | |
| + MPTSAS_ADD_PHYSDISK = 4, | |
| + MPTSAS_ADD_PHYSDISK_REPROBE = 5, | |
| + MPTSAS_DEL_PHYSDISK = 6, | |
| + MPTSAS_DEL_PHYSDISK_REPROBE = 7, | |
| + MPTSAS_ADD_INACTIVE_VOLUME = 8, | |
| + MPTSAS_IGNORE_EVENT = 9, | |
| +}; | |
| + | |
| enum mq_rq_state { | |
| MQ_RQ_IDLE = 0, | |
| MQ_RQ_IN_FLIGHT = 1, | |
| @@ -20293,7 +23078,7 @@ | |
| WIN98_EXTENDED_PARTITION = 15, | |
| LINUX_DATA_PARTITION = 131, | |
| LINUX_LVM_PARTITION = 142, | |
| - LINUX_RAID_PARTITION = 253, | |
| + LINUX_RAID_PARTITION___3 = 253, | |
| SOLARIS_X86_PARTITION = 130, | |
| NEW_SOLARIS_X86_PARTITION = 191, | |
| DM6_AUX1PARTITION = 81, | |
| @@ -20316,15 +23101,33 @@ | |
| enum msi_domain_ids { | |
| MSI_DEFAULT_DOMAIN = 0, | |
| - MSI_SECONDARY_DOMAIN = 1, | |
| - MSI_MAX_DEVICE_IRQDOMAINS = 2, | |
| + MSI_MAX_DEVICE_IRQDOMAINS = 1, | |
| }; | |
| -enum mtd_file_modes { | |
| - MTD_FILE_MODE_NORMAL = 0, | |
| - MTD_FILE_MODE_OTP_FACTORY = 1, | |
| - MTD_FILE_MODE_OTP_USER = 2, | |
| - MTD_FILE_MODE_RAW = 3, | |
| +enum mthp_stat_item { | |
| + MTHP_STAT_ANON_FAULT_ALLOC = 0, | |
| + MTHP_STAT_ANON_FAULT_FALLBACK = 1, | |
| + MTHP_STAT_ANON_FAULT_FALLBACK_CHARGE = 2, | |
| + MTHP_STAT_ANON_SWPOUT = 3, | |
| + MTHP_STAT_ANON_SWPOUT_FALLBACK = 4, | |
| + __MTHP_STAT_COUNT = 5, | |
| +}; | |
| + | |
| +enum mul_step { | |
| + MUL_STEP_1 = 0, | |
| + MUL_STEP_NONE = 0, | |
| + MUL_STEP_2 = 1, | |
| + MUL_STEP_3 = 2, | |
| + MUL_STEP_4 = 3, | |
| + MUL_LAST = 4, | |
| + MUL_LAST_2 = 5, | |
| +}; | |
| + | |
| +enum mul_type { | |
| + MUL_TYPE_START = 0, | |
| + MUL_TYPE_STEP_24x8 = 1, | |
| + MUL_TYPE_STEP_16x16 = 2, | |
| + MUL_TYPE_STEP_32x32 = 3, | |
| }; | |
| enum multi_stop_state { | |
| @@ -20335,17 +23138,46 @@ | |
| MULTI_STOP_EXIT = 4, | |
| }; | |
| -typedef enum { | |
| - AD_MUX_DUMMY = 0, | |
| - AD_MUX_DETACHED = 1, | |
| - AD_MUX_WAITING = 2, | |
| - AD_MUX_ATTACHED = 3, | |
| - AD_MUX_COLLECTING_DISTRIBUTING = 4, | |
| -} mux_states_t; | |
| +enum nbcon_prio { | |
| + NBCON_PRIO_NONE = 0, | |
| + NBCON_PRIO_NORMAL = 1, | |
| + NBCON_PRIO_EMERGENCY = 2, | |
| + NBCON_PRIO_PANIC = 3, | |
| + NBCON_PRIO_MAX = 4, | |
| +}; | |
| -enum muxtype { | |
| - pca954x_ismux = 0, | |
| - pca954x_isswi = 1, | |
| +enum ncq_saw_flag_list { | |
| + ncq_saw_d2h = 1, | |
| + ncq_saw_dmas = 2, | |
| + ncq_saw_sdb = 4, | |
| + ncq_saw_backout = 8, | |
| +}; | |
| + | |
| +enum nested_evmptrld_status { | |
| + EVMPTRLD_DISABLED = 0, | |
| + EVMPTRLD_SUCCEEDED = 1, | |
| + EVMPTRLD_VMFAIL = 2, | |
| + EVMPTRLD_ERROR = 3, | |
| +}; | |
| + | |
| +enum net_bridge_opts { | |
| + BROPT_VLAN_ENABLED = 0, | |
| + BROPT_VLAN_STATS_ENABLED = 1, | |
| + BROPT_NF_CALL_IPTABLES = 2, | |
| + BROPT_NF_CALL_IP6TABLES = 3, | |
| + BROPT_NF_CALL_ARPTABLES = 4, | |
| + BROPT_GROUP_ADDR_SET = 5, | |
| + BROPT_MULTICAST_ENABLED = 6, | |
| + BROPT_MULTICAST_QUERY_USE_IFADDR = 7, | |
| + BROPT_MULTICAST_STATS_ENABLED = 8, | |
| + BROPT_HAS_IPV6_ADDR = 9, | |
| + BROPT_NEIGH_SUPPRESS_ENABLED = 10, | |
| + BROPT_MTU_SET_BY_USER = 11, | |
| + BROPT_VLAN_STATS_PER_PORT = 12, | |
| + BROPT_NO_LL_LEARN = 13, | |
| + BROPT_VLAN_BRIDGE_BINDING = 14, | |
| + BROPT_MCAST_VLAN_SNOOPING_ENABLED = 15, | |
| + BROPT_MST_ENABLED = 16, | |
| }; | |
| enum net_device_flags { | |
| @@ -20456,6 +23288,10 @@ | |
| NETDEV_OFFLOAD_XSTATS_TYPE_L3 = 1, | |
| }; | |
| +enum netdev_qstats_scope { | |
| + NETDEV_QSTATS_SCOPE_QUEUE = 1, | |
| +}; | |
| + | |
| enum netdev_queue_state_t { | |
| __QUEUE_STATE_DRV_XOFF = 0, | |
| __QUEUE_STATE_STACK_XOFF = 1, | |
| @@ -20467,6 +23303,15 @@ | |
| NETDEV_QUEUE_TYPE_TX = 1, | |
| }; | |
| +enum netdev_reg_state { | |
| + NETREG_UNINITIALIZED = 0, | |
| + NETREG_REGISTERED = 1, | |
| + NETREG_UNREGISTERING = 2, | |
| + NETREG_UNREGISTERED = 3, | |
| + NETREG_RELEASED = 4, | |
| + NETREG_DUMMY = 5, | |
| +}; | |
| + | |
| enum netdev_stat_type { | |
| NETDEV_PCPU_STAT_NONE = 0, | |
| NETDEV_PCPU_STAT_LSTATS = 1, | |
| @@ -20502,6 +23347,17 @@ | |
| NETDEV_XDP_ACT_MASK = 127, | |
| }; | |
| +enum netdev_xdp_rx_metadata { | |
| + NETDEV_XDP_RX_METADATA_TIMESTAMP = 1, | |
| + NETDEV_XDP_RX_METADATA_HASH = 2, | |
| + NETDEV_XDP_RX_METADATA_VLAN_TAG = 4, | |
| +}; | |
| + | |
| +enum netdev_xsk_flags { | |
| + NETDEV_XSK_FLAGS_TX_TIMESTAMP = 1, | |
| + NETDEV_XSK_FLAGS_TX_CHECKSUM = 2, | |
| +}; | |
| + | |
| enum netevent_notif_type { | |
| NETEVENT_NEIGH_UPDATE = 1, | |
| NETEVENT_REDIRECT = 2, | |
| @@ -20511,6 +23367,158 @@ | |
| NETEVENT_IPV4_FWD_UPDATE_PRIORITY_UPDATE = 6, | |
| }; | |
| +enum netfs_failure { | |
| + netfs_fail_check_write_begin = 0, | |
| + netfs_fail_copy_to_cache = 1, | |
| + netfs_fail_dio_read_short = 2, | |
| + netfs_fail_dio_read_zero = 3, | |
| + netfs_fail_read = 4, | |
| + netfs_fail_short_read = 5, | |
| + netfs_fail_prepare_write = 6, | |
| + netfs_fail_write = 7, | |
| +} __attribute__((mode(byte))); | |
| + | |
| +enum netfs_folio_trace { | |
| + netfs_folio_is_uptodate = 0, | |
| + netfs_just_prefetch = 1, | |
| + netfs_whole_folio_modify = 2, | |
| + netfs_modify_and_clear = 3, | |
| + netfs_streaming_write = 4, | |
| + netfs_streaming_write_cont = 5, | |
| + netfs_flush_content = 6, | |
| + netfs_streaming_filled_page = 7, | |
| + netfs_streaming_cont_filled_page = 8, | |
| + netfs_folio_trace_clear = 9, | |
| + netfs_folio_trace_clear_s = 10, | |
| + netfs_folio_trace_clear_g = 11, | |
| + netfs_folio_trace_copy_to_cache = 12, | |
| + netfs_folio_trace_end_copy = 13, | |
| + netfs_folio_trace_filled_gaps = 14, | |
| + netfs_folio_trace_kill = 15, | |
| + netfs_folio_trace_launder = 16, | |
| + netfs_folio_trace_mkwrite = 17, | |
| + netfs_folio_trace_mkwrite_plus = 18, | |
| + netfs_folio_trace_read_gaps = 19, | |
| + netfs_folio_trace_redirty = 20, | |
| + netfs_folio_trace_redirtied = 21, | |
| + netfs_folio_trace_store = 22, | |
| + netfs_folio_trace_store_plus = 23, | |
| + netfs_folio_trace_wthru = 24, | |
| + netfs_folio_trace_wthru_plus = 25, | |
| +} __attribute__((mode(byte))); | |
| + | |
| +enum netfs_how_to_modify { | |
| + NETFS_FOLIO_IS_UPTODATE = 0, | |
| + NETFS_JUST_PREFETCH = 1, | |
| + NETFS_WHOLE_FOLIO_MODIFY = 2, | |
| + NETFS_MODIFY_AND_CLEAR = 3, | |
| + NETFS_STREAMING_WRITE = 4, | |
| + NETFS_STREAMING_WRITE_CONT = 5, | |
| + NETFS_FLUSH_CONTENT = 6, | |
| +}; | |
| + | |
| +enum netfs_io_origin { | |
| + NETFS_READAHEAD = 0, | |
| + NETFS_READPAGE = 1, | |
| + NETFS_READ_FOR_WRITE = 2, | |
| + NETFS_WRITEBACK = 3, | |
| + NETFS_WRITETHROUGH = 4, | |
| + NETFS_LAUNDER_WRITE = 5, | |
| + NETFS_UNBUFFERED_WRITE = 6, | |
| + NETFS_DIO_READ = 7, | |
| + NETFS_DIO_WRITE = 8, | |
| + nr__netfs_io_origin = 9, | |
| +} __attribute__((mode(byte))); | |
| + | |
| +enum netfs_io_source { | |
| + NETFS_FILL_WITH_ZEROES = 0, | |
| + NETFS_DOWNLOAD_FROM_SERVER = 1, | |
| + NETFS_READ_FROM_CACHE = 2, | |
| + NETFS_INVALID_READ = 3, | |
| + NETFS_UPLOAD_TO_SERVER = 4, | |
| + NETFS_WRITE_TO_CACHE = 5, | |
| + NETFS_INVALID_WRITE = 6, | |
| +} __attribute__((mode(byte))); | |
| + | |
| +enum netfs_read_from_hole { | |
| + NETFS_READ_HOLE_IGNORE = 0, | |
| + NETFS_READ_HOLE_CLEAR = 1, | |
| + NETFS_READ_HOLE_FAIL = 2, | |
| +}; | |
| + | |
| +enum netfs_read_trace { | |
| + netfs_read_trace_dio_read = 0, | |
| + netfs_read_trace_expanded = 1, | |
| + netfs_read_trace_readahead = 2, | |
| + netfs_read_trace_readpage = 3, | |
| + netfs_read_trace_prefetch_for_write = 4, | |
| + netfs_read_trace_write_begin = 5, | |
| +} __attribute__((mode(byte))); | |
| + | |
| +enum netfs_rreq_ref_trace { | |
| + netfs_rreq_trace_get_for_outstanding = 0, | |
| + netfs_rreq_trace_get_subreq = 1, | |
| + netfs_rreq_trace_put_complete = 2, | |
| + netfs_rreq_trace_put_discard = 3, | |
| + netfs_rreq_trace_put_failed = 4, | |
| + netfs_rreq_trace_put_no_submit = 5, | |
| + netfs_rreq_trace_put_return = 6, | |
| + netfs_rreq_trace_put_subreq = 7, | |
| + netfs_rreq_trace_put_work = 8, | |
| + netfs_rreq_trace_see_work = 9, | |
| + netfs_rreq_trace_new = 10, | |
| +} __attribute__((mode(byte))); | |
| + | |
| +enum netfs_rreq_trace { | |
| + netfs_rreq_trace_assess = 0, | |
| + netfs_rreq_trace_copy = 1, | |
| + netfs_rreq_trace_done = 2, | |
| + netfs_rreq_trace_free = 3, | |
| + netfs_rreq_trace_redirty = 4, | |
| + netfs_rreq_trace_resubmit = 5, | |
| + netfs_rreq_trace_unlock = 6, | |
| + netfs_rreq_trace_unmark = 7, | |
| + netfs_rreq_trace_wait_ip = 8, | |
| + netfs_rreq_trace_wake_ip = 9, | |
| + netfs_rreq_trace_write_done = 10, | |
| +} __attribute__((mode(byte))); | |
| + | |
| +enum netfs_sreq_ref_trace { | |
| + netfs_sreq_trace_get_copy_to_cache = 0, | |
| + netfs_sreq_trace_get_resubmit = 1, | |
| + netfs_sreq_trace_get_short_read = 2, | |
| + netfs_sreq_trace_new = 3, | |
| + netfs_sreq_trace_put_clear = 4, | |
| + netfs_sreq_trace_put_discard = 5, | |
| + netfs_sreq_trace_put_failed = 6, | |
| + netfs_sreq_trace_put_merged = 7, | |
| + netfs_sreq_trace_put_no_copy = 8, | |
| + netfs_sreq_trace_put_wip = 9, | |
| + netfs_sreq_trace_put_work = 10, | |
| + netfs_sreq_trace_put_terminated = 11, | |
| +} __attribute__((mode(byte))); | |
| + | |
| +enum netfs_sreq_trace { | |
| + netfs_sreq_trace_download_instead = 0, | |
| + netfs_sreq_trace_free = 1, | |
| + netfs_sreq_trace_limited = 2, | |
| + netfs_sreq_trace_prepare = 3, | |
| + netfs_sreq_trace_resubmit_short = 4, | |
| + netfs_sreq_trace_submit = 5, | |
| + netfs_sreq_trace_terminated = 6, | |
| + netfs_sreq_trace_write = 7, | |
| + netfs_sreq_trace_write_skip = 8, | |
| + netfs_sreq_trace_write_term = 9, | |
| +} __attribute__((mode(byte))); | |
| + | |
| +enum netfs_write_trace { | |
| + netfs_write_trace_dio_write = 0, | |
| + netfs_write_trace_launder = 1, | |
| + netfs_write_trace_unbuffered_write = 2, | |
| + netfs_write_trace_writeback = 3, | |
| + netfs_write_trace_writethrough = 4, | |
| +} __attribute__((mode(byte))); | |
| + | |
| enum netkit_action { | |
| NETKIT_NEXT = -1, | |
| NETKIT_PASS = 0, | |
| @@ -20582,11 +23590,89 @@ | |
| MAX_NETNS_BPF_ATTACH_TYPE = 2, | |
| }; | |
| +enum new_flow { | |
| + NEW_FLOW = 0, | |
| + OLD_FLOW = 1, | |
| +}; | |
| + | |
| enum nexthop_event_type { | |
| NEXTHOP_EVENT_DEL = 0, | |
| NEXTHOP_EVENT_REPLACE = 1, | |
| NEXTHOP_EVENT_RES_TABLE_PRE_REPLACE = 2, | |
| NEXTHOP_EVENT_BUCKET_REPLACE = 3, | |
| + NEXTHOP_EVENT_HW_STATS_REPORT_DELTA = 4, | |
| +}; | |
| + | |
| +enum nf_ct_ecache_state { | |
| + NFCT_ECACHE_DESTROY_FAIL = 0, | |
| + NFCT_ECACHE_DESTROY_SENT = 1, | |
| +}; | |
| + | |
| +enum nf_ct_ext_id { | |
| + NF_CT_EXT_HELPER = 0, | |
| + NF_CT_EXT_NAT = 1, | |
| + NF_CT_EXT_SEQADJ = 2, | |
| + NF_CT_EXT_ACCT = 3, | |
| + NF_CT_EXT_SYNPROXY = 4, | |
| + NF_CT_EXT_NUM = 5, | |
| +}; | |
| + | |
| +enum nf_ct_helper_flags { | |
| + NF_CT_HELPER_F_USERSPACE = 1, | |
| + NF_CT_HELPER_F_CONFIGURED = 2, | |
| +}; | |
| + | |
| +enum nf_ct_sysctl_index { | |
| + NF_SYSCTL_CT_MAX = 0, | |
| + NF_SYSCTL_CT_COUNT = 1, | |
| + NF_SYSCTL_CT_BUCKETS = 2, | |
| + NF_SYSCTL_CT_CHECKSUM = 3, | |
| + NF_SYSCTL_CT_LOG_INVALID = 4, | |
| + NF_SYSCTL_CT_EXPECT_MAX = 5, | |
| + NF_SYSCTL_CT_ACCT = 6, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_GENERIC = 7, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_SYN_SENT = 8, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_SYN_RECV = 9, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_ESTABLISHED = 10, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_FIN_WAIT = 11, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_CLOSE_WAIT = 12, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_LAST_ACK = 13, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_TIME_WAIT = 14, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_CLOSE = 15, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_RETRANS = 16, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_UNACK = 17, | |
| + NF_SYSCTL_CT_PROTO_TCP_LOOSE = 18, | |
| + NF_SYSCTL_CT_PROTO_TCP_LIBERAL = 19, | |
| + NF_SYSCTL_CT_PROTO_TCP_IGNORE_INVALID_RST = 20, | |
| + NF_SYSCTL_CT_PROTO_TCP_MAX_RETRANS = 21, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_UDP = 22, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_STREAM = 23, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_ICMP = 24, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_ICMPV6 = 25, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_CLOSED = 26, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_COOKIE_WAIT = 27, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_COOKIE_ECHOED = 28, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_ESTABLISHED = 29, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_SHUTDOWN_SENT = 30, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_SHUTDOWN_RECD = 31, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_SHUTDOWN_ACK_SENT = 32, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_HEARTBEAT_SENT = 33, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_DCCP_REQUEST = 34, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_DCCP_RESPOND = 35, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_DCCP_PARTOPEN = 36, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_DCCP_OPEN = 37, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_DCCP_CLOSEREQ = 38, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_DCCP_CLOSING = 39, | |
| + NF_SYSCTL_CT_PROTO_TIMEOUT_DCCP_TIMEWAIT = 40, | |
| + NF_SYSCTL_CT_PROTO_DCCP_LOOSE = 41, | |
| + NF_SYSCTL_CT_LWTUNNEL = 42, | |
| + __NF_SYSCTL_CT_LAST_SYSCTL = 43, | |
| +}; | |
| + | |
| +enum nf_ct_tcp_action { | |
| + NFCT_TCP_IGNORE = 0, | |
| + NFCT_TCP_INVALID = 1, | |
| + NFCT_TCP_ACCEPT = 2, | |
| }; | |
| enum nf_dev_hooks { | |
| @@ -20611,6 +23697,23 @@ | |
| NF_INET_INGRESS = 5, | |
| }; | |
| +enum nf_ip6_hook_priorities { | |
| + NF_IP6_PRI_FIRST = -2147483648, | |
| + NF_IP6_PRI_RAW_BEFORE_DEFRAG = -450, | |
| + NF_IP6_PRI_CONNTRACK_DEFRAG = -400, | |
| + NF_IP6_PRI_RAW = -300, | |
| + NF_IP6_PRI_SELINUX_FIRST = -225, | |
| + NF_IP6_PRI_CONNTRACK = -200, | |
| + NF_IP6_PRI_MANGLE = -150, | |
| + NF_IP6_PRI_NAT_DST = -100, | |
| + NF_IP6_PRI_FILTER = 0, | |
| + NF_IP6_PRI_SECURITY = 50, | |
| + NF_IP6_PRI_NAT_SRC = 100, | |
| + NF_IP6_PRI_SELINUX_LAST = 225, | |
| + NF_IP6_PRI_CONNTRACK_HELPER = 300, | |
| + NF_IP6_PRI_LAST = 2147483647, | |
| +}; | |
| + | |
| enum nf_ip_hook_priorities { | |
| NF_IP_PRI_FIRST = -2147483648, | |
| NF_IP_PRI_RAW_BEFORE_DEFRAG = -450, | |
| @@ -20629,25 +23732,16 @@ | |
| NF_IP_PRI_LAST = 2147483647, | |
| }; | |
| -enum nf_ip_trace_comments { | |
| - NF_IP_TRACE_COMMENT_RULE = 0, | |
| - NF_IP_TRACE_COMMENT_RETURN = 1, | |
| - NF_IP_TRACE_COMMENT_POLICY = 2, | |
| -}; | |
| - | |
| -enum nf_ip_trace_comments___2 { | |
| - NF_IP6_TRACE_COMMENT_RULE = 0, | |
| - NF_IP6_TRACE_COMMENT_RETURN = 1, | |
| - NF_IP6_TRACE_COMMENT_POLICY = 2, | |
| -}; | |
| - | |
| enum nf_log_type { | |
| NF_LOG_TYPE_LOG = 0, | |
| NF_LOG_TYPE_ULOG = 1, | |
| NF_LOG_TYPE_MAX = 2, | |
| }; | |
| -enum nf_nat_manip_type; | |
| +enum nf_nat_manip_type { | |
| + NF_NAT_MANIP_SRC = 0, | |
| + NF_NAT_MANIP_DST = 1, | |
| +}; | |
| enum nfnetlink_groups { | |
| NFNLGRP_NONE = 0, | |
| @@ -20682,6 +23776,384 @@ | |
| NFNL_CB_BATCH = 3, | |
| }; | |
| +enum nfp_app_id { | |
| + NFP_APP_CORE_NIC = 1, | |
| + NFP_APP_BPF_NIC = 2, | |
| + NFP_APP_FLOWER_NIC = 3, | |
| + NFP_APP_ACTIVE_BUFFER_MGMT_NIC = 4, | |
| +}; | |
| + | |
| +enum nfp_bpf_cmsg_status { | |
| + CMSG_RC_SUCCESS = 0, | |
| + CMSG_RC_ERR_MAP_FD = 1, | |
| + CMSG_RC_ERR_MAP_NOENT = 2, | |
| + CMSG_RC_ERR_MAP_ERR = 3, | |
| + CMSG_RC_ERR_MAP_PARSE = 4, | |
| + CMSG_RC_ERR_MAP_EXIST = 5, | |
| + CMSG_RC_ERR_MAP_NOMEM = 6, | |
| + CMSG_RC_ERR_MAP_E2BIG = 7, | |
| +}; | |
| + | |
| +enum nfp_bpf_lm_mode { | |
| + NN_LM_MOD_NONE = 0, | |
| + NN_LM_MOD_INC = 1, | |
| + NN_LM_MOD_DEC = 2, | |
| +}; | |
| + | |
| +enum nfp_bpf_map_use { | |
| + NFP_MAP_UNUSED = 0, | |
| + NFP_MAP_USE_READ = 1, | |
| + NFP_MAP_USE_WRITE = 2, | |
| + NFP_MAP_USE_ATOMIC_CNT = 3, | |
| +}; | |
| + | |
| +enum nfp_bpf_reg_type { | |
| + NN_REG_GPR_A = 1, | |
| + NN_REG_GPR_B = 2, | |
| + NN_REG_GPR_BOTH = 3, | |
| + NN_REG_NNR = 4, | |
| + NN_REG_XFER = 8, | |
| + NN_REG_IMM = 16, | |
| + NN_REG_NONE = 32, | |
| + NN_REG_LMEM = 64, | |
| +}; | |
| + | |
| +enum nfp_ccm_mbox_tlv_type { | |
| + NFP_NET_MBOX_TLV_TYPE_UNKNOWN = 0, | |
| + NFP_NET_MBOX_TLV_TYPE_END = 1, | |
| + NFP_NET_MBOX_TLV_TYPE_MSG = 2, | |
| + NFP_NET_MBOX_TLV_TYPE_MSG_NOSUP = 3, | |
| + NFP_NET_MBOX_TLV_TYPE_RESV = 4, | |
| +}; | |
| + | |
| +enum nfp_ccm_type { | |
| + NFP_CCM_TYPE_BPF_MAP_ALLOC = 1, | |
| + NFP_CCM_TYPE_BPF_MAP_FREE = 2, | |
| + NFP_CCM_TYPE_BPF_MAP_LOOKUP = 3, | |
| + NFP_CCM_TYPE_BPF_MAP_UPDATE = 4, | |
| + NFP_CCM_TYPE_BPF_MAP_DELETE = 5, | |
| + NFP_CCM_TYPE_BPF_MAP_GETNEXT = 6, | |
| + NFP_CCM_TYPE_BPF_MAP_GETFIRST = 7, | |
| + NFP_CCM_TYPE_BPF_BPF_EVENT = 8, | |
| + NFP_CCM_TYPE_CRYPTO_RESET = 9, | |
| + NFP_CCM_TYPE_CRYPTO_ADD = 10, | |
| + NFP_CCM_TYPE_CRYPTO_DEL = 11, | |
| + NFP_CCM_TYPE_CRYPTO_UPDATE = 12, | |
| + NFP_CCM_TYPE_CRYPTO_RESYNC = 13, | |
| + __NFP_CCM_TYPE_MAX = 14, | |
| +}; | |
| + | |
| +enum nfp_cpp_explicit_signal_mode { | |
| + NFP_SIGNAL_NONE = 0, | |
| + NFP_SIGNAL_PUSH = 1, | |
| + NFP_SIGNAL_PUSH_OPTIONAL = -1, | |
| + NFP_SIGNAL_PULL = 2, | |
| + NFP_SIGNAL_PULL_OPTIONAL = -2, | |
| +}; | |
| + | |
| +enum nfp_dev_id { | |
| + NFP_DEV_NFP3800 = 0, | |
| + NFP_DEV_NFP3800_VF = 1, | |
| + NFP_DEV_NFP6000 = 2, | |
| + NFP_DEV_NFP6000_VF = 3, | |
| + NFP_DEV_CNT = 4, | |
| +}; | |
| + | |
| +enum nfp_dump_diag { | |
| + NFP_DUMP_NSP_DIAG = 0, | |
| +}; | |
| + | |
| +enum nfp_dumpspec_type { | |
| + NFP_DUMPSPEC_TYPE_CPP_CSR = 0, | |
| + NFP_DUMPSPEC_TYPE_XPB_CSR = 1, | |
| + NFP_DUMPSPEC_TYPE_ME_CSR = 2, | |
| + NFP_DUMPSPEC_TYPE_INDIRECT_ME_CSR = 3, | |
| + NFP_DUMPSPEC_TYPE_RTSYM = 4, | |
| + NFP_DUMPSPEC_TYPE_HWINFO = 5, | |
| + NFP_DUMPSPEC_TYPE_FWNAME = 6, | |
| + NFP_DUMPSPEC_TYPE_HWINFO_FIELD = 7, | |
| + NFP_DUMPSPEC_TYPE_PROLOG = 10000, | |
| + NFP_DUMPSPEC_TYPE_ERROR = 10001, | |
| +}; | |
| + | |
| +enum nfp_eth_aneg { | |
| + NFP_ANEG_AUTO = 0, | |
| + NFP_ANEG_SEARCH = 1, | |
| + NFP_ANEG_25G_CONSORTIUM = 2, | |
| + NFP_ANEG_25G_IEEE = 3, | |
| + NFP_ANEG_DISABLED = 4, | |
| +}; | |
| + | |
| +enum nfp_eth_fec { | |
| + NFP_FEC_AUTO_BIT = 0, | |
| + NFP_FEC_BASER_BIT = 1, | |
| + NFP_FEC_REED_SOLOMON_BIT = 2, | |
| + NFP_FEC_DISABLED_BIT = 3, | |
| +}; | |
| + | |
| +enum nfp_eth_interface { | |
| + NFP_INTERFACE_NONE = 0, | |
| + NFP_INTERFACE_SFP = 1, | |
| + NFP_INTERFACE_SFPP = 10, | |
| + NFP_INTERFACE_SFP28 = 28, | |
| + NFP_INTERFACE_QSFP = 40, | |
| + NFP_INTERFACE_RJ45 = 45, | |
| + NFP_INTERFACE_CXP = 100, | |
| + NFP_INTERFACE_QSFP28 = 112, | |
| +}; | |
| + | |
| +enum nfp_eth_media { | |
| + NFP_MEDIA_DAC_PASSIVE = 0, | |
| + NFP_MEDIA_DAC_ACTIVE = 1, | |
| + NFP_MEDIA_FIBRE = 2, | |
| +}; | |
| + | |
| +enum nfp_eth_rate { | |
| + RATE_INVALID = 0, | |
| + RATE_10M = 1, | |
| + RATE_100M = 2, | |
| + RATE_1G = 3, | |
| + RATE_10G = 4, | |
| + RATE_25G = 5, | |
| +}; | |
| + | |
| +enum nfp_eth_raw { | |
| + NSP_ETH_RAW_PORT = 0, | |
| + NSP_ETH_RAW_STATE = 1, | |
| + NSP_ETH_RAW_MAC = 2, | |
| + NSP_ETH_RAW_CONTROL = 3, | |
| + NSP_ETH_NUM_RAW = 4, | |
| +}; | |
| + | |
| +enum nfp_ethtool_link_mode_list { | |
| + NFP_MEDIA_W0_RJ45_10M = 0, | |
| + NFP_MEDIA_W0_RJ45_10M_HD = 1, | |
| + NFP_MEDIA_W0_RJ45_100M = 2, | |
| + NFP_MEDIA_W0_RJ45_100M_HD = 3, | |
| + NFP_MEDIA_W0_RJ45_1G = 4, | |
| + NFP_MEDIA_W0_RJ45_2P5G = 5, | |
| + NFP_MEDIA_W0_RJ45_5G = 6, | |
| + NFP_MEDIA_W0_RJ45_10G = 7, | |
| + NFP_MEDIA_1000BASE_CX = 8, | |
| + NFP_MEDIA_1000BASE_KX = 9, | |
| + NFP_MEDIA_10GBASE_KX4 = 10, | |
| + NFP_MEDIA_10GBASE_KR = 11, | |
| + NFP_MEDIA_10GBASE_CX4 = 12, | |
| + NFP_MEDIA_10GBASE_CR = 13, | |
| + NFP_MEDIA_10GBASE_SR = 14, | |
| + NFP_MEDIA_10GBASE_ER = 15, | |
| + NFP_MEDIA_25GBASE_KR = 16, | |
| + NFP_MEDIA_25GBASE_KR_S = 17, | |
| + NFP_MEDIA_25GBASE_CR = 18, | |
| + NFP_MEDIA_25GBASE_CR_S = 19, | |
| + NFP_MEDIA_25GBASE_SR = 20, | |
| + NFP_MEDIA_40GBASE_CR4 = 21, | |
| + NFP_MEDIA_40GBASE_KR4 = 22, | |
| + NFP_MEDIA_40GBASE_SR4 = 23, | |
| + NFP_MEDIA_40GBASE_LR4 = 24, | |
| + NFP_MEDIA_50GBASE_KR = 25, | |
| + NFP_MEDIA_50GBASE_SR = 26, | |
| + NFP_MEDIA_50GBASE_CR = 27, | |
| + NFP_MEDIA_50GBASE_LR = 28, | |
| + NFP_MEDIA_50GBASE_ER = 29, | |
| + NFP_MEDIA_50GBASE_FR = 30, | |
| + NFP_MEDIA_100GBASE_KR4 = 31, | |
| + NFP_MEDIA_100GBASE_SR4 = 32, | |
| + NFP_MEDIA_100GBASE_CR4 = 33, | |
| + NFP_MEDIA_100GBASE_KP4 = 34, | |
| + NFP_MEDIA_100GBASE_CR10 = 35, | |
| + NFP_MEDIA_10GBASE_LR = 36, | |
| + NFP_MEDIA_25GBASE_LR = 37, | |
| + NFP_MEDIA_25GBASE_ER = 38, | |
| + NFP_MEDIA_LINK_MODES_NUMBER = 39, | |
| +}; | |
| + | |
| +enum nfp_mbox_cmd { | |
| + NFP_MBOX_NO_CMD = 0, | |
| + NFP_MBOX_POOL_GET = 1, | |
| + NFP_MBOX_POOL_SET = 2, | |
| + NFP_MBOX_PCIE_ABM_ENABLE = 3, | |
| + NFP_MBOX_PCIE_ABM_DISABLE = 4, | |
| +}; | |
| + | |
| +enum nfp_net_mbox_cmsg_state { | |
| + NFP_NET_MBOX_CMSG_STATE_QUEUED = 0, | |
| + NFP_NET_MBOX_CMSG_STATE_NEXT = 1, | |
| + NFP_NET_MBOX_CMSG_STATE_BUSY = 2, | |
| + NFP_NET_MBOX_CMSG_STATE_REPLY_FOUND = 3, | |
| + NFP_NET_MBOX_CMSG_STATE_DONE = 4, | |
| +}; | |
| + | |
| +enum nfp_nfd_version { | |
| + NFP_NFD_VER_NFD3 = 0, | |
| + NFP_NFD_VER_NFDK = 1, | |
| +}; | |
| + | |
| +enum nfp_nsp_cmd { | |
| + SPCODE_NOOP = 0, | |
| + SPCODE_SOFT_RESET = 1, | |
| + SPCODE_FW_DEFAULT = 2, | |
| + SPCODE_PHY_INIT = 3, | |
| + SPCODE_MAC_INIT = 4, | |
| + SPCODE_PHY_RXADAPT = 5, | |
| + SPCODE_FW_LOAD = 6, | |
| + SPCODE_ETH_RESCAN = 7, | |
| + SPCODE_ETH_CONTROL = 8, | |
| + SPCODE_NSP_WRITE_FLASH = 11, | |
| + SPCODE_NSP_SENSORS = 12, | |
| + SPCODE_NSP_IDENTIFY = 13, | |
| + SPCODE_FW_STORED = 16, | |
| + SPCODE_HWINFO_LOOKUP = 17, | |
| + SPCODE_HWINFO_SET = 18, | |
| + SPCODE_FW_LOADED = 19, | |
| + SPCODE_VERSIONS = 21, | |
| + SPCODE_READ_SFF_EEPROM = 22, | |
| + SPCODE_READ_MEDIA = 23, | |
| +}; | |
| + | |
| +enum nfp_nsp_sensor_id { | |
| + NFP_SENSOR_CHIP_TEMPERATURE = 0, | |
| + NFP_SENSOR_ASSEMBLY_POWER = 1, | |
| + NFP_SENSOR_ASSEMBLY_12V_POWER = 2, | |
| + NFP_SENSOR_ASSEMBLY_3V3_POWER = 3, | |
| +}; | |
| + | |
| +enum nfp_nsp_versions { | |
| + NFP_VERSIONS_BSP = 0, | |
| + NFP_VERSIONS_CPLD = 1, | |
| + NFP_VERSIONS_APP = 2, | |
| + NFP_VERSIONS_BUNDLE = 3, | |
| + NFP_VERSIONS_UNDI = 4, | |
| + NFP_VERSIONS_NCSI = 5, | |
| + NFP_VERSIONS_CFGR = 6, | |
| +}; | |
| + | |
| +enum nfp_port_flags { | |
| + NFP_PORT_CHANGED = 0, | |
| +}; | |
| + | |
| +enum nfp_port_type { | |
| + NFP_PORT_INVALID = 0, | |
| + NFP_PORT_PHYS_PORT = 1, | |
| + NFP_PORT_PF_PORT = 2, | |
| + NFP_PORT_VF_PORT = 3, | |
| +}; | |
| + | |
| +enum nfp_qcp_ptr { | |
| + NFP_QCP_READ_PTR = 0, | |
| + NFP_QCP_WRITE_PTR = 1, | |
| +}; | |
| + | |
| +enum nfp_relo_type { | |
| + RELO_NONE = 0, | |
| + RELO_BR_REL = 1, | |
| + RELO_BR_GO_OUT = 2, | |
| + RELO_BR_GO_ABORT = 3, | |
| + RELO_BR_GO_CALL_PUSH_REGS = 4, | |
| + RELO_BR_GO_CALL_POP_REGS = 5, | |
| + RELO_BR_NEXT_PKT = 6, | |
| + RELO_BR_HELPER = 7, | |
| + RELO_IMMED_REL = 8, | |
| +}; | |
| + | |
| +enum nfp_repr_type { | |
| + NFP_REPR_TYPE_PHYS_PORT = 0, | |
| + NFP_REPR_TYPE_PF = 1, | |
| + NFP_REPR_TYPE_VF = 2, | |
| + __NFP_REPR_TYPE_MAX = 3, | |
| +}; | |
| + | |
| +enum nfp_rtsym_type { | |
| + NFP_RTSYM_TYPE_NONE = 0, | |
| + NFP_RTSYM_TYPE_OBJECT = 1, | |
| + NFP_RTSYM_TYPE_FUNCTION = 2, | |
| + NFP_RTSYM_TYPE_ABS = 3, | |
| +}; | |
| + | |
| +enum nfqnl_attr_config { | |
| + NFQA_CFG_UNSPEC = 0, | |
| + NFQA_CFG_CMD = 1, | |
| + NFQA_CFG_PARAMS = 2, | |
| + NFQA_CFG_QUEUE_MAXLEN = 3, | |
| + NFQA_CFG_MASK = 4, | |
| + NFQA_CFG_FLAGS = 5, | |
| + __NFQA_CFG_MAX = 6, | |
| +}; | |
| + | |
| +enum nfqnl_attr_type { | |
| + NFQA_UNSPEC = 0, | |
| + NFQA_PACKET_HDR = 1, | |
| + NFQA_VERDICT_HDR = 2, | |
| + NFQA_MARK = 3, | |
| + NFQA_TIMESTAMP = 4, | |
| + NFQA_IFINDEX_INDEV = 5, | |
| + NFQA_IFINDEX_OUTDEV = 6, | |
| + NFQA_IFINDEX_PHYSINDEV = 7, | |
| + NFQA_IFINDEX_PHYSOUTDEV = 8, | |
| + NFQA_HWADDR = 9, | |
| + NFQA_PAYLOAD = 10, | |
| + NFQA_CT = 11, | |
| + NFQA_CT_INFO = 12, | |
| + NFQA_CAP_LEN = 13, | |
| + NFQA_SKB_INFO = 14, | |
| + NFQA_EXP = 15, | |
| + NFQA_UID = 16, | |
| + NFQA_GID = 17, | |
| + NFQA_SECCTX = 18, | |
| + NFQA_VLAN = 19, | |
| + NFQA_L2HDR = 20, | |
| + NFQA_PRIORITY = 21, | |
| + NFQA_CGROUP_CLASSID = 22, | |
| + __NFQA_MAX = 23, | |
| +}; | |
| + | |
| +enum nfqnl_config_mode { | |
| + NFQNL_COPY_NONE = 0, | |
| + NFQNL_COPY_META = 1, | |
| + NFQNL_COPY_PACKET = 2, | |
| +}; | |
| + | |
| +enum nfqnl_msg_config_cmds { | |
| + NFQNL_CFG_CMD_NONE = 0, | |
| + NFQNL_CFG_CMD_BIND = 1, | |
| + NFQNL_CFG_CMD_UNBIND = 2, | |
| + NFQNL_CFG_CMD_PF_BIND = 3, | |
| + NFQNL_CFG_CMD_PF_UNBIND = 4, | |
| +}; | |
| + | |
| +enum nfqnl_msg_types { | |
| + NFQNL_MSG_PACKET = 0, | |
| + NFQNL_MSG_VERDICT = 1, | |
| + NFQNL_MSG_CONFIG = 2, | |
| + NFQNL_MSG_VERDICT_BATCH = 3, | |
| + NFQNL_MSG_MAX = 4, | |
| +}; | |
| + | |
| +enum nfqnl_vlan_attr { | |
| + NFQA_VLAN_UNSPEC = 0, | |
| + NFQA_VLAN_PROTO = 1, | |
| + NFQA_VLAN_TCI = 2, | |
| + __NFQA_VLAN_MAX = 3, | |
| +}; | |
| + | |
| +enum nfs3_createmode { | |
| + NFS3_CREATE_UNCHECKED = 0, | |
| + NFS3_CREATE_GUARDED = 1, | |
| + NFS3_CREATE_EXCLUSIVE = 2, | |
| +}; | |
| + | |
| +enum nfs3_ftype { | |
| + NF3NON = 0, | |
| + NF3REG = 1, | |
| + NF3DIR = 2, | |
| + NF3BLK = 3, | |
| + NF3CHR = 4, | |
| + NF3LNK = 5, | |
| + NF3SOCK = 6, | |
| + NF3FIFO = 7, | |
| + NF3BAD = 8, | |
| +}; | |
| + | |
| enum nfs3_stable_how { | |
| NFS_UNSTABLE = 0, | |
| NFS_DATA_SYNC = 1, | |
| @@ -20697,11 +24169,2379 @@ | |
| NFS4_CHANGE_TYPE_IS_UNDEFINED = 4, | |
| }; | |
| +enum nfs_cb_opnum4 { | |
| + OP_CB_GETATTR = 3, | |
| + OP_CB_RECALL = 4, | |
| + OP_CB_LAYOUTRECALL = 5, | |
| + OP_CB_NOTIFY = 6, | |
| + OP_CB_PUSH_DELEG = 7, | |
| + OP_CB_RECALL_ANY = 8, | |
| + OP_CB_RECALLABLE_OBJ_AVAIL = 9, | |
| + OP_CB_RECALL_SLOT = 10, | |
| + OP_CB_SEQUENCE = 11, | |
| + OP_CB_WANTS_CANCELLED = 12, | |
| + OP_CB_NOTIFY_LOCK = 13, | |
| + OP_CB_NOTIFY_DEVICEID = 14, | |
| + OP_CB_OFFLOAD = 15, | |
| + OP_CB_ILLEGAL = 10044, | |
| +}; | |
| + | |
| +enum nfs_opnum4 { | |
| + OP_ACCESS = 3, | |
| + OP_CLOSE = 4, | |
| + OP_COMMIT = 5, | |
| + OP_CREATE = 6, | |
| + OP_DELEGPURGE = 7, | |
| + OP_DELEGRETURN = 8, | |
| + OP_GETATTR = 9, | |
| + OP_GETFH = 10, | |
| + OP_LINK = 11, | |
| + OP_LOCK = 12, | |
| + OP_LOCKT = 13, | |
| + OP_LOCKU = 14, | |
| + OP_LOOKUP = 15, | |
| + OP_LOOKUPP = 16, | |
| + OP_NVERIFY = 17, | |
| + OP_OPEN = 18, | |
| + OP_OPENATTR = 19, | |
| + OP_OPEN_CONFIRM = 20, | |
| + OP_OPEN_DOWNGRADE = 21, | |
| + OP_PUTFH = 22, | |
| + OP_PUTPUBFH = 23, | |
| + OP_PUTROOTFH = 24, | |
| + OP_READ = 25, | |
| + OP_READDIR = 26, | |
| + OP_READLINK = 27, | |
| + OP_REMOVE = 28, | |
| + OP_RENAME = 29, | |
| + OP_RENEW = 30, | |
| + OP_RESTOREFH = 31, | |
| + OP_SAVEFH = 32, | |
| + OP_SECINFO = 33, | |
| + OP_SETATTR = 34, | |
| + OP_SETCLIENTID = 35, | |
| + OP_SETCLIENTID_CONFIRM = 36, | |
| + OP_VERIFY = 37, | |
| + OP_WRITE = 38, | |
| + OP_RELEASE_LOCKOWNER = 39, | |
| + OP_BACKCHANNEL_CTL = 40, | |
| + OP_BIND_CONN_TO_SESSION = 41, | |
| + OP_EXCHANGE_ID = 42, | |
| + OP_CREATE_SESSION = 43, | |
| + OP_DESTROY_SESSION = 44, | |
| + OP_FREE_STATEID = 45, | |
| + OP_GET_DIR_DELEGATION = 46, | |
| + OP_GETDEVICEINFO = 47, | |
| + OP_GETDEVICELIST = 48, | |
| + OP_LAYOUTCOMMIT = 49, | |
| + OP_LAYOUTGET = 50, | |
| + OP_LAYOUTRETURN = 51, | |
| + OP_SECINFO_NO_NAME = 52, | |
| + OP_SEQUENCE = 53, | |
| + OP_SET_SSV = 54, | |
| + OP_TEST_STATEID = 55, | |
| + OP_WANT_DELEGATION = 56, | |
| + OP_DESTROY_CLIENTID = 57, | |
| + OP_RECLAIM_COMPLETE = 58, | |
| + OP_ALLOCATE = 59, | |
| + OP_COPY = 60, | |
| + OP_COPY_NOTIFY = 61, | |
| + OP_DEALLOCATE = 62, | |
| + OP_IO_ADVISE = 63, | |
| + OP_LAYOUTERROR = 64, | |
| + OP_LAYOUTSTATS = 65, | |
| + OP_OFFLOAD_CANCEL = 66, | |
| + OP_OFFLOAD_STATUS = 67, | |
| + OP_READ_PLUS = 68, | |
| + OP_SEEK = 69, | |
| + OP_WRITE_SAME = 70, | |
| + OP_CLONE = 71, | |
| + OP_GETXATTR = 72, | |
| + OP_SETXATTR = 73, | |
| + OP_LISTXATTRS = 74, | |
| + OP_REMOVEXATTR = 75, | |
| + OP_ILLEGAL = 10044, | |
| +}; | |
| + | |
| +enum nfs_param { | |
| + Opt_ac = 0, | |
| + Opt_acdirmax = 1, | |
| + Opt_acdirmin = 2, | |
| + Opt_acl___3 = 3, | |
| + Opt_acregmax = 4, | |
| + Opt_acregmin = 5, | |
| + Opt_actimeo = 6, | |
| + Opt_addr = 7, | |
| + Opt_bg = 8, | |
| + Opt_bsize = 9, | |
| + Opt_clientaddr = 10, | |
| + Opt_cto = 11, | |
| + Opt_fg = 12, | |
| + Opt_fscache = 13, | |
| + Opt_fscache_flag = 14, | |
| + Opt_hard = 15, | |
| + Opt_intr = 16, | |
| + Opt_local_lock = 17, | |
| + Opt_lock = 18, | |
| + Opt_lookupcache = 19, | |
| + Opt_migration = 20, | |
| + Opt_minorversion = 21, | |
| + Opt_mountaddr = 22, | |
| + Opt_mounthost = 23, | |
| + Opt_mountport = 24, | |
| + Opt_mountproto = 25, | |
| + Opt_mountvers = 26, | |
| + Opt_namelen = 27, | |
| + Opt_nconnect = 28, | |
| + Opt_max_connect = 29, | |
| + Opt_port___2 = 30, | |
| + Opt_posix = 31, | |
| + Opt_proto = 32, | |
| + Opt_rdirplus = 33, | |
| + Opt_rdma = 34, | |
| + Opt_resvport = 35, | |
| + Opt_retrans = 36, | |
| + Opt_retry = 37, | |
| + Opt_rsize = 38, | |
| + Opt_sec = 39, | |
| + Opt_sharecache = 40, | |
| + Opt_sloppy = 41, | |
| + Opt_soft = 42, | |
| + Opt_softerr = 43, | |
| + Opt_softreval = 44, | |
| + Opt_source = 45, | |
| + Opt_tcp = 46, | |
| + Opt_timeo = 47, | |
| + Opt_trunkdiscovery = 48, | |
| + Opt_udp = 49, | |
| + Opt_v = 50, | |
| + Opt_vers = 51, | |
| + Opt_wsize = 52, | |
| + Opt_write = 53, | |
| + Opt_xprtsec = 54, | |
| +}; | |
| + | |
| +enum nfs_stat { | |
| + NFS_OK = 0, | |
| + NFSERR_PERM = 1, | |
| + NFSERR_NOENT = 2, | |
| + NFSERR_IO = 5, | |
| + NFSERR_NXIO = 6, | |
| + NFSERR_EAGAIN = 11, | |
| + NFSERR_ACCES = 13, | |
| + NFSERR_EXIST = 17, | |
| + NFSERR_XDEV = 18, | |
| + NFSERR_NODEV = 19, | |
| + NFSERR_NOTDIR = 20, | |
| + NFSERR_ISDIR = 21, | |
| + NFSERR_INVAL = 22, | |
| + NFSERR_FBIG = 27, | |
| + NFSERR_NOSPC = 28, | |
| + NFSERR_ROFS = 30, | |
| + NFSERR_MLINK = 31, | |
| + NFSERR_OPNOTSUPP = 45, | |
| + NFSERR_NAMETOOLONG = 63, | |
| + NFSERR_NOTEMPTY = 66, | |
| + NFSERR_DQUOT = 69, | |
| + NFSERR_STALE = 70, | |
| + NFSERR_REMOTE = 71, | |
| + NFSERR_WFLUSH = 99, | |
| + NFSERR_BADHANDLE = 10001, | |
| + NFSERR_NOT_SYNC = 10002, | |
| + NFSERR_BAD_COOKIE = 10003, | |
| + NFSERR_NOTSUPP = 10004, | |
| + NFSERR_TOOSMALL = 10005, | |
| + NFSERR_SERVERFAULT = 10006, | |
| + NFSERR_BADTYPE = 10007, | |
| + NFSERR_JUKEBOX = 10008, | |
| + NFSERR_SAME = 10009, | |
| + NFSERR_DENIED = 10010, | |
| + NFSERR_EXPIRED = 10011, | |
| + NFSERR_LOCKED = 10012, | |
| + NFSERR_GRACE = 10013, | |
| + NFSERR_FHEXPIRED = 10014, | |
| + NFSERR_SHARE_DENIED = 10015, | |
| + NFSERR_WRONGSEC = 10016, | |
| + NFSERR_CLID_INUSE = 10017, | |
| + NFSERR_RESOURCE = 10018, | |
| + NFSERR_MOVED = 10019, | |
| + NFSERR_NOFILEHANDLE = 10020, | |
| + NFSERR_MINOR_VERS_MISMATCH = 10021, | |
| + NFSERR_STALE_CLIENTID = 10022, | |
| + NFSERR_STALE_STATEID = 10023, | |
| + NFSERR_OLD_STATEID = 10024, | |
| + NFSERR_BAD_STATEID = 10025, | |
| + NFSERR_BAD_SEQID = 10026, | |
| + NFSERR_NOT_SAME = 10027, | |
| + NFSERR_LOCK_RANGE = 10028, | |
| + NFSERR_SYMLINK = 10029, | |
| + NFSERR_RESTOREFH = 10030, | |
| + NFSERR_LEASE_MOVED = 10031, | |
| + NFSERR_ATTRNOTSUPP = 10032, | |
| + NFSERR_NO_GRACE = 10033, | |
| + NFSERR_RECLAIM_BAD = 10034, | |
| + NFSERR_RECLAIM_CONFLICT = 10035, | |
| + NFSERR_BAD_XDR = 10036, | |
| + NFSERR_LOCKS_HELD = 10037, | |
| + NFSERR_OPENMODE = 10038, | |
| + NFSERR_BADOWNER = 10039, | |
| + NFSERR_BADCHAR = 10040, | |
| + NFSERR_BADNAME = 10041, | |
| + NFSERR_BAD_RANGE = 10042, | |
| + NFSERR_LOCK_NOTSUPP = 10043, | |
| + NFSERR_OP_ILLEGAL = 10044, | |
| + NFSERR_DEADLOCK = 10045, | |
| + NFSERR_FILE_OPEN = 10046, | |
| + NFSERR_ADMIN_REVOKED = 10047, | |
| + NFSERR_CB_PATH_DOWN = 10048, | |
| +}; | |
| + | |
| +enum nfs_stat_bytecounters { | |
| + NFSIOS_NORMALREADBYTES = 0, | |
| + NFSIOS_NORMALWRITTENBYTES = 1, | |
| + NFSIOS_DIRECTREADBYTES = 2, | |
| + NFSIOS_DIRECTWRITTENBYTES = 3, | |
| + NFSIOS_SERVERREADBYTES = 4, | |
| + NFSIOS_SERVERWRITTENBYTES = 5, | |
| + NFSIOS_READPAGES = 6, | |
| + NFSIOS_WRITEPAGES = 7, | |
| + __NFSIOS_BYTESMAX = 8, | |
| +}; | |
| + | |
| +enum nfs_stat_eventcounters { | |
| + NFSIOS_INODEREVALIDATE = 0, | |
| + NFSIOS_DENTRYREVALIDATE = 1, | |
| + NFSIOS_DATAINVALIDATE = 2, | |
| + NFSIOS_ATTRINVALIDATE = 3, | |
| + NFSIOS_VFSOPEN = 4, | |
| + NFSIOS_VFSLOOKUP = 5, | |
| + NFSIOS_VFSACCESS = 6, | |
| + NFSIOS_VFSUPDATEPAGE = 7, | |
| + NFSIOS_VFSREADPAGE = 8, | |
| + NFSIOS_VFSREADPAGES = 9, | |
| + NFSIOS_VFSWRITEPAGE = 10, | |
| + NFSIOS_VFSWRITEPAGES = 11, | |
| + NFSIOS_VFSGETDENTS = 12, | |
| + NFSIOS_VFSSETATTR = 13, | |
| + NFSIOS_VFSFLUSH = 14, | |
| + NFSIOS_VFSFSYNC = 15, | |
| + NFSIOS_VFSLOCK = 16, | |
| + NFSIOS_VFSRELEASE = 17, | |
| + NFSIOS_CONGESTIONWAIT = 18, | |
| + NFSIOS_SETATTRTRUNC = 19, | |
| + NFSIOS_EXTENDWRITE = 20, | |
| + NFSIOS_SILLYRENAME = 21, | |
| + NFSIOS_SHORTREAD = 22, | |
| + NFSIOS_SHORTWRITE = 23, | |
| + NFSIOS_DELAY = 24, | |
| + NFSIOS_PNFS_READ = 25, | |
| + NFSIOS_PNFS_WRITE = 26, | |
| + __NFSIOS_COUNTSMAX = 27, | |
| +}; | |
| + | |
| +enum nfsstat4 { | |
| + NFS4_OK = 0, | |
| + NFS4ERR_PERM = 1, | |
| + NFS4ERR_NOENT = 2, | |
| + NFS4ERR_IO = 5, | |
| + NFS4ERR_NXIO = 6, | |
| + NFS4ERR_ACCESS = 13, | |
| + NFS4ERR_EXIST = 17, | |
| + NFS4ERR_XDEV = 18, | |
| + NFS4ERR_NOTDIR = 20, | |
| + NFS4ERR_ISDIR = 21, | |
| + NFS4ERR_INVAL = 22, | |
| + NFS4ERR_FBIG = 27, | |
| + NFS4ERR_NOSPC = 28, | |
| + NFS4ERR_ROFS = 30, | |
| + NFS4ERR_MLINK = 31, | |
| + NFS4ERR_NAMETOOLONG = 63, | |
| + NFS4ERR_NOTEMPTY = 66, | |
| + NFS4ERR_DQUOT = 69, | |
| + NFS4ERR_STALE = 70, | |
| + NFS4ERR_BADHANDLE = 10001, | |
| + NFS4ERR_BAD_COOKIE = 10003, | |
| + NFS4ERR_NOTSUPP = 10004, | |
| + NFS4ERR_TOOSMALL = 10005, | |
| + NFS4ERR_SERVERFAULT = 10006, | |
| + NFS4ERR_BADTYPE = 10007, | |
| + NFS4ERR_DELAY = 10008, | |
| + NFS4ERR_SAME = 10009, | |
| + NFS4ERR_DENIED = 10010, | |
| + NFS4ERR_EXPIRED = 10011, | |
| + NFS4ERR_LOCKED = 10012, | |
| + NFS4ERR_GRACE = 10013, | |
| + NFS4ERR_FHEXPIRED = 10014, | |
| + NFS4ERR_SHARE_DENIED = 10015, | |
| + NFS4ERR_WRONGSEC = 10016, | |
| + NFS4ERR_CLID_INUSE = 10017, | |
| + NFS4ERR_RESOURCE = 10018, | |
| + NFS4ERR_MOVED = 10019, | |
| + NFS4ERR_NOFILEHANDLE = 10020, | |
| + NFS4ERR_MINOR_VERS_MISMATCH = 10021, | |
| + NFS4ERR_STALE_CLIENTID = 10022, | |
| + NFS4ERR_STALE_STATEID = 10023, | |
| + NFS4ERR_OLD_STATEID = 10024, | |
| + NFS4ERR_BAD_STATEID = 10025, | |
| + NFS4ERR_BAD_SEQID = 10026, | |
| + NFS4ERR_NOT_SAME = 10027, | |
| + NFS4ERR_LOCK_RANGE = 10028, | |
| + NFS4ERR_SYMLINK = 10029, | |
| + NFS4ERR_RESTOREFH = 10030, | |
| + NFS4ERR_LEASE_MOVED = 10031, | |
| + NFS4ERR_ATTRNOTSUPP = 10032, | |
| + NFS4ERR_NO_GRACE = 10033, | |
| + NFS4ERR_RECLAIM_BAD = 10034, | |
| + NFS4ERR_RECLAIM_CONFLICT = 10035, | |
| + NFS4ERR_BADXDR = 10036, | |
| + NFS4ERR_LOCKS_HELD = 10037, | |
| + NFS4ERR_OPENMODE = 10038, | |
| + NFS4ERR_BADOWNER = 10039, | |
| + NFS4ERR_BADCHAR = 10040, | |
| + NFS4ERR_BADNAME = 10041, | |
| + NFS4ERR_BAD_RANGE = 10042, | |
| + NFS4ERR_LOCK_NOTSUPP = 10043, | |
| + NFS4ERR_OP_ILLEGAL = 10044, | |
| + NFS4ERR_DEADLOCK = 10045, | |
| + NFS4ERR_FILE_OPEN = 10046, | |
| + NFS4ERR_ADMIN_REVOKED = 10047, | |
| + NFS4ERR_CB_PATH_DOWN = 10048, | |
| + NFS4ERR_BADIOMODE = 10049, | |
| + NFS4ERR_BADLAYOUT = 10050, | |
| + NFS4ERR_BAD_SESSION_DIGEST = 10051, | |
| + NFS4ERR_BADSESSION = 10052, | |
| + NFS4ERR_BADSLOT = 10053, | |
| + NFS4ERR_COMPLETE_ALREADY = 10054, | |
| + NFS4ERR_CONN_NOT_BOUND_TO_SESSION = 10055, | |
| + NFS4ERR_DELEG_ALREADY_WANTED = 10056, | |
| + NFS4ERR_BACK_CHAN_BUSY = 10057, | |
| + NFS4ERR_LAYOUTTRYLATER = 10058, | |
| + NFS4ERR_LAYOUTUNAVAILABLE = 10059, | |
| + NFS4ERR_NOMATCHING_LAYOUT = 10060, | |
| + NFS4ERR_RECALLCONFLICT = 10061, | |
| + NFS4ERR_UNKNOWN_LAYOUTTYPE = 10062, | |
| + NFS4ERR_SEQ_MISORDERED = 10063, | |
| + NFS4ERR_SEQUENCE_POS = 10064, | |
| + NFS4ERR_REQ_TOO_BIG = 10065, | |
| + NFS4ERR_REP_TOO_BIG = 10066, | |
| + NFS4ERR_REP_TOO_BIG_TO_CACHE = 10067, | |
| + NFS4ERR_RETRY_UNCACHED_REP = 10068, | |
| + NFS4ERR_UNSAFE_COMPOUND = 10069, | |
| + NFS4ERR_TOO_MANY_OPS = 10070, | |
| + NFS4ERR_OP_NOT_IN_SESSION = 10071, | |
| + NFS4ERR_HASH_ALG_UNSUPP = 10072, | |
| + NFS4ERR_CLIENTID_BUSY = 10074, | |
| + NFS4ERR_PNFS_IO_HOLE = 10075, | |
| + NFS4ERR_SEQ_FALSE_RETRY = 10076, | |
| + NFS4ERR_BAD_HIGH_SLOT = 10077, | |
| + NFS4ERR_DEADSESSION = 10078, | |
| + NFS4ERR_ENCR_ALG_UNSUPP = 10079, | |
| + NFS4ERR_PNFS_NO_LAYOUT = 10080, | |
| + NFS4ERR_NOT_ONLY_OP = 10081, | |
| + NFS4ERR_WRONG_CRED = 10082, | |
| + NFS4ERR_WRONG_TYPE = 10083, | |
| + NFS4ERR_DIRDELEG_UNAVAIL = 10084, | |
| + NFS4ERR_REJECT_DELEG = 10085, | |
| + NFS4ERR_RETURNCONFLICT = 10086, | |
| + NFS4ERR_DELEG_REVOKED = 10087, | |
| + NFS4ERR_PARTNER_NOTSUPP = 10088, | |
| + NFS4ERR_PARTNER_NO_AUTH = 10089, | |
| + NFS4ERR_UNION_NOTSUPP = 10090, | |
| + NFS4ERR_OFFLOAD_DENIED = 10091, | |
| + NFS4ERR_WRONG_LFS = 10092, | |
| + NFS4ERR_BADLABEL = 10093, | |
| + NFS4ERR_OFFLOAD_NO_REQS = 10094, | |
| + NFS4ERR_NOXATTR = 10095, | |
| + NFS4ERR_XATTR2BIG = 10096, | |
| +}; | |
| + | |
| +enum nfulnl_attr_config { | |
| + NFULA_CFG_UNSPEC = 0, | |
| + NFULA_CFG_CMD = 1, | |
| + NFULA_CFG_MODE = 2, | |
| + NFULA_CFG_NLBUFSIZ = 3, | |
| + NFULA_CFG_TIMEOUT = 4, | |
| + NFULA_CFG_QTHRESH = 5, | |
| + NFULA_CFG_FLAGS = 6, | |
| + __NFULA_CFG_MAX = 7, | |
| +}; | |
| + | |
| +enum nfulnl_attr_type { | |
| + NFULA_UNSPEC = 0, | |
| + NFULA_PACKET_HDR = 1, | |
| + NFULA_MARK = 2, | |
| + NFULA_TIMESTAMP = 3, | |
| + NFULA_IFINDEX_INDEV = 4, | |
| + NFULA_IFINDEX_OUTDEV = 5, | |
| + NFULA_IFINDEX_PHYSINDEV = 6, | |
| + NFULA_IFINDEX_PHYSOUTDEV = 7, | |
| + NFULA_HWADDR = 8, | |
| + NFULA_PAYLOAD = 9, | |
| + NFULA_PREFIX = 10, | |
| + NFULA_UID = 11, | |
| + NFULA_SEQ = 12, | |
| + NFULA_SEQ_GLOBAL = 13, | |
| + NFULA_GID = 14, | |
| + NFULA_HWTYPE = 15, | |
| + NFULA_HWHEADER = 16, | |
| + NFULA_HWLEN = 17, | |
| + NFULA_CT = 18, | |
| + NFULA_CT_INFO = 19, | |
| + NFULA_VLAN = 20, | |
| + NFULA_L2HDR = 21, | |
| + __NFULA_MAX = 22, | |
| +}; | |
| + | |
| +enum nfulnl_msg_config_cmds { | |
| + NFULNL_CFG_CMD_NONE = 0, | |
| + NFULNL_CFG_CMD_BIND = 1, | |
| + NFULNL_CFG_CMD_UNBIND = 2, | |
| + NFULNL_CFG_CMD_PF_BIND = 3, | |
| + NFULNL_CFG_CMD_PF_UNBIND = 4, | |
| +}; | |
| + | |
| +enum nfulnl_msg_types { | |
| + NFULNL_MSG_PACKET = 0, | |
| + NFULNL_MSG_CONFIG = 1, | |
| + NFULNL_MSG_MAX = 2, | |
| +}; | |
| + | |
| +enum nfulnl_vlan_attr { | |
| + NFULA_VLAN_UNSPEC = 0, | |
| + NFULA_VLAN_PROTO = 1, | |
| + NFULA_VLAN_TCI = 2, | |
| + __NFULA_VLAN_MAX = 3, | |
| +}; | |
| + | |
| enum nh_notifier_info_type { | |
| NH_NOTIFIER_INFO_TYPE_SINGLE = 0, | |
| NH_NOTIFIER_INFO_TYPE_GRP = 1, | |
| NH_NOTIFIER_INFO_TYPE_RES_TABLE = 2, | |
| NH_NOTIFIER_INFO_TYPE_RES_BUCKET = 3, | |
| + NH_NOTIFIER_INFO_TYPE_GRP_HW_STATS = 4, | |
| +}; | |
| + | |
| +enum nl80211_ac { | |
| + NL80211_AC_VO = 0, | |
| + NL80211_AC_VI = 1, | |
| + NL80211_AC_BE = 2, | |
| + NL80211_AC_BK = 3, | |
| + NL80211_NUM_ACS = 4, | |
| +}; | |
| + | |
| +enum nl80211_acl_policy { | |
| + NL80211_ACL_POLICY_ACCEPT_UNLESS_LISTED = 0, | |
| + NL80211_ACL_POLICY_DENY_UNLESS_LISTED = 1, | |
| +}; | |
| + | |
| +enum nl80211_ap_settings_flags { | |
| + NL80211_AP_SETTINGS_EXTERNAL_AUTH_SUPPORT = 1, | |
| + NL80211_AP_SETTINGS_SA_QUERY_OFFLOAD_SUPPORT = 2, | |
| +}; | |
| + | |
| +enum nl80211_attr_coalesce_rule { | |
| + __NL80211_COALESCE_RULE_INVALID = 0, | |
| + NL80211_ATTR_COALESCE_RULE_DELAY = 1, | |
| + NL80211_ATTR_COALESCE_RULE_CONDITION = 2, | |
| + NL80211_ATTR_COALESCE_RULE_PKT_PATTERN = 3, | |
| + NUM_NL80211_ATTR_COALESCE_RULE = 4, | |
| + NL80211_ATTR_COALESCE_RULE_MAX = 3, | |
| +}; | |
| + | |
| +enum nl80211_attr_cqm { | |
| + __NL80211_ATTR_CQM_INVALID = 0, | |
| + NL80211_ATTR_CQM_RSSI_THOLD = 1, | |
| + NL80211_ATTR_CQM_RSSI_HYST = 2, | |
| + NL80211_ATTR_CQM_RSSI_THRESHOLD_EVENT = 3, | |
| + NL80211_ATTR_CQM_PKT_LOSS_EVENT = 4, | |
| + NL80211_ATTR_CQM_TXE_RATE = 5, | |
| + NL80211_ATTR_CQM_TXE_PKTS = 6, | |
| + NL80211_ATTR_CQM_TXE_INTVL = 7, | |
| + NL80211_ATTR_CQM_BEACON_LOSS_EVENT = 8, | |
| + NL80211_ATTR_CQM_RSSI_LEVEL = 9, | |
| + __NL80211_ATTR_CQM_AFTER_LAST = 10, | |
| + NL80211_ATTR_CQM_MAX = 9, | |
| +}; | |
| + | |
| +enum nl80211_attrs { | |
| + NL80211_ATTR_UNSPEC = 0, | |
| + NL80211_ATTR_WIPHY = 1, | |
| + NL80211_ATTR_WIPHY_NAME = 2, | |
| + NL80211_ATTR_IFINDEX = 3, | |
| + NL80211_ATTR_IFNAME = 4, | |
| + NL80211_ATTR_IFTYPE = 5, | |
| + NL80211_ATTR_MAC = 6, | |
| + NL80211_ATTR_KEY_DATA = 7, | |
| + NL80211_ATTR_KEY_IDX = 8, | |
| + NL80211_ATTR_KEY_CIPHER = 9, | |
| + NL80211_ATTR_KEY_SEQ = 10, | |
| + NL80211_ATTR_KEY_DEFAULT = 11, | |
| + NL80211_ATTR_BEACON_INTERVAL = 12, | |
| + NL80211_ATTR_DTIM_PERIOD = 13, | |
| + NL80211_ATTR_BEACON_HEAD = 14, | |
| + NL80211_ATTR_BEACON_TAIL = 15, | |
| + NL80211_ATTR_STA_AID = 16, | |
| + NL80211_ATTR_STA_FLAGS = 17, | |
| + NL80211_ATTR_STA_LISTEN_INTERVAL = 18, | |
| + NL80211_ATTR_STA_SUPPORTED_RATES = 19, | |
| + NL80211_ATTR_STA_VLAN = 20, | |
| + NL80211_ATTR_STA_INFO = 21, | |
| + NL80211_ATTR_WIPHY_BANDS = 22, | |
| + NL80211_ATTR_MNTR_FLAGS = 23, | |
| + NL80211_ATTR_MESH_ID = 24, | |
| + NL80211_ATTR_STA_PLINK_ACTION = 25, | |
| + NL80211_ATTR_MPATH_NEXT_HOP = 26, | |
| + NL80211_ATTR_MPATH_INFO = 27, | |
| + NL80211_ATTR_BSS_CTS_PROT = 28, | |
| + NL80211_ATTR_BSS_SHORT_PREAMBLE = 29, | |
| + NL80211_ATTR_BSS_SHORT_SLOT_TIME = 30, | |
| + NL80211_ATTR_HT_CAPABILITY = 31, | |
| + NL80211_ATTR_SUPPORTED_IFTYPES = 32, | |
| + NL80211_ATTR_REG_ALPHA2 = 33, | |
| + NL80211_ATTR_REG_RULES = 34, | |
| + NL80211_ATTR_MESH_CONFIG = 35, | |
| + NL80211_ATTR_BSS_BASIC_RATES = 36, | |
| + NL80211_ATTR_WIPHY_TXQ_PARAMS = 37, | |
| + NL80211_ATTR_WIPHY_FREQ = 38, | |
| + NL80211_ATTR_WIPHY_CHANNEL_TYPE = 39, | |
| + NL80211_ATTR_KEY_DEFAULT_MGMT = 40, | |
| + NL80211_ATTR_MGMT_SUBTYPE = 41, | |
| + NL80211_ATTR_IE = 42, | |
| + NL80211_ATTR_MAX_NUM_SCAN_SSIDS = 43, | |
| + NL80211_ATTR_SCAN_FREQUENCIES = 44, | |
| + NL80211_ATTR_SCAN_SSIDS = 45, | |
| + NL80211_ATTR_GENERATION = 46, | |
| + NL80211_ATTR_BSS = 47, | |
| + NL80211_ATTR_REG_INITIATOR = 48, | |
| + NL80211_ATTR_REG_TYPE = 49, | |
| + NL80211_ATTR_SUPPORTED_COMMANDS = 50, | |
| + NL80211_ATTR_FRAME = 51, | |
| + NL80211_ATTR_SSID = 52, | |
| + NL80211_ATTR_AUTH_TYPE = 53, | |
| + NL80211_ATTR_REASON_CODE = 54, | |
| + NL80211_ATTR_KEY_TYPE = 55, | |
| + NL80211_ATTR_MAX_SCAN_IE_LEN = 56, | |
| + NL80211_ATTR_CIPHER_SUITES = 57, | |
| + NL80211_ATTR_FREQ_BEFORE = 58, | |
| + NL80211_ATTR_FREQ_AFTER = 59, | |
| + NL80211_ATTR_FREQ_FIXED = 60, | |
| + NL80211_ATTR_WIPHY_RETRY_SHORT = 61, | |
| + NL80211_ATTR_WIPHY_RETRY_LONG = 62, | |
| + NL80211_ATTR_WIPHY_FRAG_THRESHOLD = 63, | |
| + NL80211_ATTR_WIPHY_RTS_THRESHOLD = 64, | |
| + NL80211_ATTR_TIMED_OUT = 65, | |
| + NL80211_ATTR_USE_MFP = 66, | |
| + NL80211_ATTR_STA_FLAGS2 = 67, | |
| + NL80211_ATTR_CONTROL_PORT = 68, | |
| + NL80211_ATTR_TESTDATA = 69, | |
| + NL80211_ATTR_PRIVACY = 70, | |
| + NL80211_ATTR_DISCONNECTED_BY_AP = 71, | |
| + NL80211_ATTR_STATUS_CODE = 72, | |
| + NL80211_ATTR_CIPHER_SUITES_PAIRWISE = 73, | |
| + NL80211_ATTR_CIPHER_SUITE_GROUP = 74, | |
| + NL80211_ATTR_WPA_VERSIONS = 75, | |
| + NL80211_ATTR_AKM_SUITES = 76, | |
| + NL80211_ATTR_REQ_IE = 77, | |
| + NL80211_ATTR_RESP_IE = 78, | |
| + NL80211_ATTR_PREV_BSSID = 79, | |
| + NL80211_ATTR_KEY = 80, | |
| + NL80211_ATTR_KEYS = 81, | |
| + NL80211_ATTR_PID = 82, | |
| + NL80211_ATTR_4ADDR = 83, | |
| + NL80211_ATTR_SURVEY_INFO = 84, | |
| + NL80211_ATTR_PMKID = 85, | |
| + NL80211_ATTR_MAX_NUM_PMKIDS = 86, | |
| + NL80211_ATTR_DURATION = 87, | |
| + NL80211_ATTR_COOKIE = 88, | |
| + NL80211_ATTR_WIPHY_COVERAGE_CLASS = 89, | |
| + NL80211_ATTR_TX_RATES = 90, | |
| + NL80211_ATTR_FRAME_MATCH = 91, | |
| + NL80211_ATTR_ACK = 92, | |
| + NL80211_ATTR_PS_STATE = 93, | |
| + NL80211_ATTR_CQM = 94, | |
| + NL80211_ATTR_LOCAL_STATE_CHANGE = 95, | |
| + NL80211_ATTR_AP_ISOLATE = 96, | |
| + NL80211_ATTR_WIPHY_TX_POWER_SETTING = 97, | |
| + NL80211_ATTR_WIPHY_TX_POWER_LEVEL = 98, | |
| + NL80211_ATTR_TX_FRAME_TYPES = 99, | |
| + NL80211_ATTR_RX_FRAME_TYPES = 100, | |
| + NL80211_ATTR_FRAME_TYPE = 101, | |
| + NL80211_ATTR_CONTROL_PORT_ETHERTYPE = 102, | |
| + NL80211_ATTR_CONTROL_PORT_NO_ENCRYPT = 103, | |
| + NL80211_ATTR_SUPPORT_IBSS_RSN = 104, | |
| + NL80211_ATTR_WIPHY_ANTENNA_TX = 105, | |
| + NL80211_ATTR_WIPHY_ANTENNA_RX = 106, | |
| + NL80211_ATTR_MCAST_RATE = 107, | |
| + NL80211_ATTR_OFFCHANNEL_TX_OK = 108, | |
| + NL80211_ATTR_BSS_HT_OPMODE = 109, | |
| + NL80211_ATTR_KEY_DEFAULT_TYPES = 110, | |
| + NL80211_ATTR_MAX_REMAIN_ON_CHANNEL_DURATION = 111, | |
| + NL80211_ATTR_MESH_SETUP = 112, | |
| + NL80211_ATTR_WIPHY_ANTENNA_AVAIL_TX = 113, | |
| + NL80211_ATTR_WIPHY_ANTENNA_AVAIL_RX = 114, | |
| + NL80211_ATTR_SUPPORT_MESH_AUTH = 115, | |
| + NL80211_ATTR_STA_PLINK_STATE = 116, | |
| + NL80211_ATTR_WOWLAN_TRIGGERS = 117, | |
| + NL80211_ATTR_WOWLAN_TRIGGERS_SUPPORTED = 118, | |
| + NL80211_ATTR_SCHED_SCAN_INTERVAL = 119, | |
| + NL80211_ATTR_INTERFACE_COMBINATIONS = 120, | |
| + NL80211_ATTR_SOFTWARE_IFTYPES = 121, | |
| + NL80211_ATTR_REKEY_DATA = 122, | |
| + NL80211_ATTR_MAX_NUM_SCHED_SCAN_SSIDS = 123, | |
| + NL80211_ATTR_MAX_SCHED_SCAN_IE_LEN = 124, | |
| + NL80211_ATTR_SCAN_SUPP_RATES = 125, | |
| + NL80211_ATTR_HIDDEN_SSID = 126, | |
| + NL80211_ATTR_IE_PROBE_RESP = 127, | |
| + NL80211_ATTR_IE_ASSOC_RESP = 128, | |
| + NL80211_ATTR_STA_WME = 129, | |
| + NL80211_ATTR_SUPPORT_AP_UAPSD = 130, | |
| + NL80211_ATTR_ROAM_SUPPORT = 131, | |
| + NL80211_ATTR_SCHED_SCAN_MATCH = 132, | |
| + NL80211_ATTR_MAX_MATCH_SETS = 133, | |
| + NL80211_ATTR_PMKSA_CANDIDATE = 134, | |
| + NL80211_ATTR_TX_NO_CCK_RATE = 135, | |
| + NL80211_ATTR_TDLS_ACTION = 136, | |
| + NL80211_ATTR_TDLS_DIALOG_TOKEN = 137, | |
| + NL80211_ATTR_TDLS_OPERATION = 138, | |
| + NL80211_ATTR_TDLS_SUPPORT = 139, | |
| + NL80211_ATTR_TDLS_EXTERNAL_SETUP = 140, | |
| + NL80211_ATTR_DEVICE_AP_SME = 141, | |
| + NL80211_ATTR_DONT_WAIT_FOR_ACK = 142, | |
| + NL80211_ATTR_FEATURE_FLAGS = 143, | |
| + NL80211_ATTR_PROBE_RESP_OFFLOAD = 144, | |
| + NL80211_ATTR_PROBE_RESP = 145, | |
| + NL80211_ATTR_DFS_REGION = 146, | |
| + NL80211_ATTR_DISABLE_HT = 147, | |
| + NL80211_ATTR_HT_CAPABILITY_MASK = 148, | |
| + NL80211_ATTR_NOACK_MAP = 149, | |
| + NL80211_ATTR_INACTIVITY_TIMEOUT = 150, | |
| + NL80211_ATTR_RX_SIGNAL_DBM = 151, | |
| + NL80211_ATTR_BG_SCAN_PERIOD = 152, | |
| + NL80211_ATTR_WDEV = 153, | |
| + NL80211_ATTR_USER_REG_HINT_TYPE = 154, | |
| + NL80211_ATTR_CONN_FAILED_REASON = 155, | |
| + NL80211_ATTR_AUTH_DATA = 156, | |
| + NL80211_ATTR_VHT_CAPABILITY = 157, | |
| + NL80211_ATTR_SCAN_FLAGS = 158, | |
| + NL80211_ATTR_CHANNEL_WIDTH = 159, | |
| + NL80211_ATTR_CENTER_FREQ1 = 160, | |
| + NL80211_ATTR_CENTER_FREQ2 = 161, | |
| + NL80211_ATTR_P2P_CTWINDOW = 162, | |
| + NL80211_ATTR_P2P_OPPPS = 163, | |
| + NL80211_ATTR_LOCAL_MESH_POWER_MODE = 164, | |
| + NL80211_ATTR_ACL_POLICY = 165, | |
| + NL80211_ATTR_MAC_ADDRS = 166, | |
| + NL80211_ATTR_MAC_ACL_MAX = 167, | |
| + NL80211_ATTR_RADAR_EVENT = 168, | |
| + NL80211_ATTR_EXT_CAPA = 169, | |
| + NL80211_ATTR_EXT_CAPA_MASK = 170, | |
| + NL80211_ATTR_STA_CAPABILITY = 171, | |
| + NL80211_ATTR_STA_EXT_CAPABILITY = 172, | |
| + NL80211_ATTR_PROTOCOL_FEATURES = 173, | |
| + NL80211_ATTR_SPLIT_WIPHY_DUMP = 174, | |
| + NL80211_ATTR_DISABLE_VHT = 175, | |
| + NL80211_ATTR_VHT_CAPABILITY_MASK = 176, | |
| + NL80211_ATTR_MDID = 177, | |
| + NL80211_ATTR_IE_RIC = 178, | |
| + NL80211_ATTR_CRIT_PROT_ID = 179, | |
| + NL80211_ATTR_MAX_CRIT_PROT_DURATION = 180, | |
| + NL80211_ATTR_PEER_AID = 181, | |
| + NL80211_ATTR_COALESCE_RULE = 182, | |
| + NL80211_ATTR_CH_SWITCH_COUNT = 183, | |
| + NL80211_ATTR_CH_SWITCH_BLOCK_TX = 184, | |
| + NL80211_ATTR_CSA_IES = 185, | |
| + NL80211_ATTR_CNTDWN_OFFS_BEACON = 186, | |
| + NL80211_ATTR_CNTDWN_OFFS_PRESP = 187, | |
| + NL80211_ATTR_RXMGMT_FLAGS = 188, | |
| + NL80211_ATTR_STA_SUPPORTED_CHANNELS = 189, | |
| + NL80211_ATTR_STA_SUPPORTED_OPER_CLASSES = 190, | |
| + NL80211_ATTR_HANDLE_DFS = 191, | |
| + NL80211_ATTR_SUPPORT_5_MHZ = 192, | |
| + NL80211_ATTR_SUPPORT_10_MHZ = 193, | |
| + NL80211_ATTR_OPMODE_NOTIF = 194, | |
| + NL80211_ATTR_VENDOR_ID = 195, | |
| + NL80211_ATTR_VENDOR_SUBCMD = 196, | |
| + NL80211_ATTR_VENDOR_DATA = 197, | |
| + NL80211_ATTR_VENDOR_EVENTS = 198, | |
| + NL80211_ATTR_QOS_MAP = 199, | |
| + NL80211_ATTR_MAC_HINT = 200, | |
| + NL80211_ATTR_WIPHY_FREQ_HINT = 201, | |
| + NL80211_ATTR_MAX_AP_ASSOC_STA = 202, | |
| + NL80211_ATTR_TDLS_PEER_CAPABILITY = 203, | |
| + NL80211_ATTR_SOCKET_OWNER = 204, | |
| + NL80211_ATTR_CSA_C_OFFSETS_TX = 205, | |
| + NL80211_ATTR_MAX_CSA_COUNTERS = 206, | |
| + NL80211_ATTR_TDLS_INITIATOR = 207, | |
| + NL80211_ATTR_USE_RRM = 208, | |
| + NL80211_ATTR_WIPHY_DYN_ACK = 209, | |
| + NL80211_ATTR_TSID = 210, | |
| + NL80211_ATTR_USER_PRIO = 211, | |
| + NL80211_ATTR_ADMITTED_TIME = 212, | |
| + NL80211_ATTR_SMPS_MODE = 213, | |
| + NL80211_ATTR_OPER_CLASS = 214, | |
| + NL80211_ATTR_MAC_MASK = 215, | |
| + NL80211_ATTR_WIPHY_SELF_MANAGED_REG = 216, | |
| + NL80211_ATTR_EXT_FEATURES = 217, | |
| + NL80211_ATTR_SURVEY_RADIO_STATS = 218, | |
| + NL80211_ATTR_NETNS_FD = 219, | |
| + NL80211_ATTR_SCHED_SCAN_DELAY = 220, | |
| + NL80211_ATTR_REG_INDOOR = 221, | |
| + NL80211_ATTR_MAX_NUM_SCHED_SCAN_PLANS = 222, | |
| + NL80211_ATTR_MAX_SCAN_PLAN_INTERVAL = 223, | |
| + NL80211_ATTR_MAX_SCAN_PLAN_ITERATIONS = 224, | |
| + NL80211_ATTR_SCHED_SCAN_PLANS = 225, | |
| + NL80211_ATTR_PBSS = 226, | |
| + NL80211_ATTR_BSS_SELECT = 227, | |
| + NL80211_ATTR_STA_SUPPORT_P2P_PS = 228, | |
| + NL80211_ATTR_PAD = 229, | |
| + NL80211_ATTR_IFTYPE_EXT_CAPA = 230, | |
| + NL80211_ATTR_MU_MIMO_GROUP_DATA = 231, | |
| + NL80211_ATTR_MU_MIMO_FOLLOW_MAC_ADDR = 232, | |
| + NL80211_ATTR_SCAN_START_TIME_TSF = 233, | |
| + NL80211_ATTR_SCAN_START_TIME_TSF_BSSID = 234, | |
| + NL80211_ATTR_MEASUREMENT_DURATION = 235, | |
| + NL80211_ATTR_MEASUREMENT_DURATION_MANDATORY = 236, | |
| + NL80211_ATTR_MESH_PEER_AID = 237, | |
| + NL80211_ATTR_NAN_MASTER_PREF = 238, | |
| + NL80211_ATTR_BANDS = 239, | |
| + NL80211_ATTR_NAN_FUNC = 240, | |
| + NL80211_ATTR_NAN_MATCH = 241, | |
| + NL80211_ATTR_FILS_KEK = 242, | |
| + NL80211_ATTR_FILS_NONCES = 243, | |
| + NL80211_ATTR_MULTICAST_TO_UNICAST_ENABLED = 244, | |
| + NL80211_ATTR_BSSID = 245, | |
| + NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI = 246, | |
| + NL80211_ATTR_SCHED_SCAN_RSSI_ADJUST = 247, | |
| + NL80211_ATTR_TIMEOUT_REASON = 248, | |
| + NL80211_ATTR_FILS_ERP_USERNAME = 249, | |
| + NL80211_ATTR_FILS_ERP_REALM = 250, | |
| + NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM = 251, | |
| + NL80211_ATTR_FILS_ERP_RRK = 252, | |
| + NL80211_ATTR_FILS_CACHE_ID = 253, | |
| + NL80211_ATTR_PMK = 254, | |
| + NL80211_ATTR_SCHED_SCAN_MULTI = 255, | |
| + NL80211_ATTR_SCHED_SCAN_MAX_REQS = 256, | |
| + NL80211_ATTR_WANT_1X_4WAY_HS = 257, | |
| + NL80211_ATTR_PMKR0_NAME = 258, | |
| + NL80211_ATTR_PORT_AUTHORIZED = 259, | |
| + NL80211_ATTR_EXTERNAL_AUTH_ACTION = 260, | |
| + NL80211_ATTR_EXTERNAL_AUTH_SUPPORT = 261, | |
| + NL80211_ATTR_NSS = 262, | |
| + NL80211_ATTR_ACK_SIGNAL = 263, | |
| + NL80211_ATTR_CONTROL_PORT_OVER_NL80211 = 264, | |
| + NL80211_ATTR_TXQ_STATS = 265, | |
| + NL80211_ATTR_TXQ_LIMIT = 266, | |
| + NL80211_ATTR_TXQ_MEMORY_LIMIT = 267, | |
| + NL80211_ATTR_TXQ_QUANTUM = 268, | |
| + NL80211_ATTR_HE_CAPABILITY = 269, | |
| + NL80211_ATTR_FTM_RESPONDER = 270, | |
| + NL80211_ATTR_FTM_RESPONDER_STATS = 271, | |
| + NL80211_ATTR_TIMEOUT = 272, | |
| + NL80211_ATTR_PEER_MEASUREMENTS = 273, | |
| + NL80211_ATTR_AIRTIME_WEIGHT = 274, | |
| + NL80211_ATTR_STA_TX_POWER_SETTING = 275, | |
| + NL80211_ATTR_STA_TX_POWER = 276, | |
| + NL80211_ATTR_SAE_PASSWORD = 277, | |
| + NL80211_ATTR_TWT_RESPONDER = 278, | |
| + NL80211_ATTR_HE_OBSS_PD = 279, | |
| + NL80211_ATTR_WIPHY_EDMG_CHANNELS = 280, | |
| + NL80211_ATTR_WIPHY_EDMG_BW_CONFIG = 281, | |
| + NL80211_ATTR_VLAN_ID = 282, | |
| + NL80211_ATTR_HE_BSS_COLOR = 283, | |
| + NL80211_ATTR_IFTYPE_AKM_SUITES = 284, | |
| + NL80211_ATTR_TID_CONFIG = 285, | |
| + NL80211_ATTR_CONTROL_PORT_NO_PREAUTH = 286, | |
| + NL80211_ATTR_PMK_LIFETIME = 287, | |
| + NL80211_ATTR_PMK_REAUTH_THRESHOLD = 288, | |
| + NL80211_ATTR_RECEIVE_MULTICAST = 289, | |
| + NL80211_ATTR_WIPHY_FREQ_OFFSET = 290, | |
| + NL80211_ATTR_CENTER_FREQ1_OFFSET = 291, | |
| + NL80211_ATTR_SCAN_FREQ_KHZ = 292, | |
| + NL80211_ATTR_HE_6GHZ_CAPABILITY = 293, | |
| + NL80211_ATTR_FILS_DISCOVERY = 294, | |
| + NL80211_ATTR_UNSOL_BCAST_PROBE_RESP = 295, | |
| + NL80211_ATTR_S1G_CAPABILITY = 296, | |
| + NL80211_ATTR_S1G_CAPABILITY_MASK = 297, | |
| + NL80211_ATTR_SAE_PWE = 298, | |
| + NL80211_ATTR_RECONNECT_REQUESTED = 299, | |
| + NL80211_ATTR_SAR_SPEC = 300, | |
| + NL80211_ATTR_DISABLE_HE = 301, | |
| + NL80211_ATTR_OBSS_COLOR_BITMAP = 302, | |
| + NL80211_ATTR_COLOR_CHANGE_COUNT = 303, | |
| + NL80211_ATTR_COLOR_CHANGE_COLOR = 304, | |
| + NL80211_ATTR_COLOR_CHANGE_ELEMS = 305, | |
| + NL80211_ATTR_MBSSID_CONFIG = 306, | |
| + NL80211_ATTR_MBSSID_ELEMS = 307, | |
| + NL80211_ATTR_RADAR_BACKGROUND = 308, | |
| + NL80211_ATTR_AP_SETTINGS_FLAGS = 309, | |
| + NL80211_ATTR_EHT_CAPABILITY = 310, | |
| + NL80211_ATTR_DISABLE_EHT = 311, | |
| + NL80211_ATTR_MLO_LINKS = 312, | |
| + NL80211_ATTR_MLO_LINK_ID = 313, | |
| + NL80211_ATTR_MLD_ADDR = 314, | |
| + NL80211_ATTR_MLO_SUPPORT = 315, | |
| + NL80211_ATTR_MAX_NUM_AKM_SUITES = 316, | |
| + NL80211_ATTR_EML_CAPABILITY = 317, | |
| + NL80211_ATTR_MLD_CAPA_AND_OPS = 318, | |
| + NL80211_ATTR_TX_HW_TIMESTAMP = 319, | |
| + NL80211_ATTR_RX_HW_TIMESTAMP = 320, | |
| + NL80211_ATTR_TD_BITMAP = 321, | |
| + NL80211_ATTR_PUNCT_BITMAP = 322, | |
| + NL80211_ATTR_MAX_HW_TIMESTAMP_PEERS = 323, | |
| + NL80211_ATTR_HW_TIMESTAMP_ENABLED = 324, | |
| + NL80211_ATTR_EMA_RNR_ELEMS = 325, | |
| + NL80211_ATTR_MLO_LINK_DISABLED = 326, | |
| + NL80211_ATTR_BSS_DUMP_INCLUDE_USE_DATA = 327, | |
| + NL80211_ATTR_MLO_TTLM_DLINK = 328, | |
| + NL80211_ATTR_MLO_TTLM_ULINK = 329, | |
| + NL80211_ATTR_ASSOC_SPP_AMSDU = 330, | |
| + __NL80211_ATTR_AFTER_LAST = 331, | |
| + NUM_NL80211_ATTR = 331, | |
| + NL80211_ATTR_MAX = 330, | |
| +}; | |
| + | |
| +enum nl80211_auth_type { | |
| + NL80211_AUTHTYPE_OPEN_SYSTEM = 0, | |
| + NL80211_AUTHTYPE_SHARED_KEY = 1, | |
| + NL80211_AUTHTYPE_FT = 2, | |
| + NL80211_AUTHTYPE_NETWORK_EAP = 3, | |
| + NL80211_AUTHTYPE_SAE = 4, | |
| + NL80211_AUTHTYPE_FILS_SK = 5, | |
| + NL80211_AUTHTYPE_FILS_SK_PFS = 6, | |
| + NL80211_AUTHTYPE_FILS_PK = 7, | |
| + __NL80211_AUTHTYPE_NUM = 8, | |
| + NL80211_AUTHTYPE_MAX = 7, | |
| + NL80211_AUTHTYPE_AUTOMATIC = 8, | |
| +}; | |
| + | |
| +enum nl80211_band { | |
| + NL80211_BAND_2GHZ = 0, | |
| + NL80211_BAND_5GHZ = 1, | |
| + NL80211_BAND_60GHZ = 2, | |
| + NL80211_BAND_6GHZ = 3, | |
| + NL80211_BAND_S1GHZ = 4, | |
| + NL80211_BAND_LC = 5, | |
| + NUM_NL80211_BANDS = 6, | |
| +}; | |
| + | |
| +enum nl80211_band_attr { | |
| + __NL80211_BAND_ATTR_INVALID = 0, | |
| + NL80211_BAND_ATTR_FREQS = 1, | |
| + NL80211_BAND_ATTR_RATES = 2, | |
| + NL80211_BAND_ATTR_HT_MCS_SET = 3, | |
| + NL80211_BAND_ATTR_HT_CAPA = 4, | |
| + NL80211_BAND_ATTR_HT_AMPDU_FACTOR = 5, | |
| + NL80211_BAND_ATTR_HT_AMPDU_DENSITY = 6, | |
| + NL80211_BAND_ATTR_VHT_MCS_SET = 7, | |
| + NL80211_BAND_ATTR_VHT_CAPA = 8, | |
| + NL80211_BAND_ATTR_IFTYPE_DATA = 9, | |
| + NL80211_BAND_ATTR_EDMG_CHANNELS = 10, | |
| + NL80211_BAND_ATTR_EDMG_BW_CONFIG = 11, | |
| + NL80211_BAND_ATTR_S1G_MCS_NSS_SET = 12, | |
| + NL80211_BAND_ATTR_S1G_CAPA = 13, | |
| + __NL80211_BAND_ATTR_AFTER_LAST = 14, | |
| + NL80211_BAND_ATTR_MAX = 13, | |
| +}; | |
| + | |
| +enum nl80211_band_iftype_attr { | |
| + __NL80211_BAND_IFTYPE_ATTR_INVALID = 0, | |
| + NL80211_BAND_IFTYPE_ATTR_IFTYPES = 1, | |
| + NL80211_BAND_IFTYPE_ATTR_HE_CAP_MAC = 2, | |
| + NL80211_BAND_IFTYPE_ATTR_HE_CAP_PHY = 3, | |
| + NL80211_BAND_IFTYPE_ATTR_HE_CAP_MCS_SET = 4, | |
| + NL80211_BAND_IFTYPE_ATTR_HE_CAP_PPE = 5, | |
| + NL80211_BAND_IFTYPE_ATTR_HE_6GHZ_CAPA = 6, | |
| + NL80211_BAND_IFTYPE_ATTR_VENDOR_ELEMS = 7, | |
| + NL80211_BAND_IFTYPE_ATTR_EHT_CAP_MAC = 8, | |
| + NL80211_BAND_IFTYPE_ATTR_EHT_CAP_PHY = 9, | |
| + NL80211_BAND_IFTYPE_ATTR_EHT_CAP_MCS_SET = 10, | |
| + NL80211_BAND_IFTYPE_ATTR_EHT_CAP_PPE = 11, | |
| + __NL80211_BAND_IFTYPE_ATTR_AFTER_LAST = 12, | |
| + NL80211_BAND_IFTYPE_ATTR_MAX = 11, | |
| +}; | |
| + | |
| +enum nl80211_bitrate_attr { | |
| + __NL80211_BITRATE_ATTR_INVALID = 0, | |
| + NL80211_BITRATE_ATTR_RATE = 1, | |
| + NL80211_BITRATE_ATTR_2GHZ_SHORTPREAMBLE = 2, | |
| + __NL80211_BITRATE_ATTR_AFTER_LAST = 3, | |
| + NL80211_BITRATE_ATTR_MAX = 2, | |
| +}; | |
| + | |
| +enum nl80211_bss { | |
| + __NL80211_BSS_INVALID = 0, | |
| + NL80211_BSS_BSSID = 1, | |
| + NL80211_BSS_FREQUENCY = 2, | |
| + NL80211_BSS_TSF = 3, | |
| + NL80211_BSS_BEACON_INTERVAL = 4, | |
| + NL80211_BSS_CAPABILITY = 5, | |
| + NL80211_BSS_INFORMATION_ELEMENTS = 6, | |
| + NL80211_BSS_SIGNAL_MBM = 7, | |
| + NL80211_BSS_SIGNAL_UNSPEC = 8, | |
| + NL80211_BSS_STATUS = 9, | |
| + NL80211_BSS_SEEN_MS_AGO = 10, | |
| + NL80211_BSS_BEACON_IES = 11, | |
| + NL80211_BSS_CHAN_WIDTH = 12, | |
| + NL80211_BSS_BEACON_TSF = 13, | |
| + NL80211_BSS_PRESP_DATA = 14, | |
| + NL80211_BSS_LAST_SEEN_BOOTTIME = 15, | |
| + NL80211_BSS_PAD = 16, | |
| + NL80211_BSS_PARENT_TSF = 17, | |
| + NL80211_BSS_PARENT_BSSID = 18, | |
| + NL80211_BSS_CHAIN_SIGNAL = 19, | |
| + NL80211_BSS_FREQUENCY_OFFSET = 20, | |
| + NL80211_BSS_MLO_LINK_ID = 21, | |
| + NL80211_BSS_MLD_ADDR = 22, | |
| + NL80211_BSS_USE_FOR = 23, | |
| + NL80211_BSS_CANNOT_USE_REASONS = 24, | |
| + __NL80211_BSS_AFTER_LAST = 25, | |
| + NL80211_BSS_MAX = 24, | |
| +}; | |
| + | |
| +enum nl80211_bss_cannot_use_reasons { | |
| + NL80211_BSS_CANNOT_USE_NSTR_NONPRIMARY = 1, | |
| + NL80211_BSS_CANNOT_USE_6GHZ_PWR_MISMATCH = 2, | |
| +}; | |
| + | |
| +enum nl80211_bss_color_attributes { | |
| + __NL80211_HE_BSS_COLOR_ATTR_INVALID = 0, | |
| + NL80211_HE_BSS_COLOR_ATTR_COLOR = 1, | |
| + NL80211_HE_BSS_COLOR_ATTR_DISABLED = 2, | |
| + NL80211_HE_BSS_COLOR_ATTR_PARTIAL = 3, | |
| + __NL80211_HE_BSS_COLOR_ATTR_LAST = 4, | |
| + NL80211_HE_BSS_COLOR_ATTR_MAX = 3, | |
| +}; | |
| + | |
| +enum nl80211_bss_select_attr { | |
| + __NL80211_BSS_SELECT_ATTR_INVALID = 0, | |
| + NL80211_BSS_SELECT_ATTR_RSSI = 1, | |
| + NL80211_BSS_SELECT_ATTR_BAND_PREF = 2, | |
| + NL80211_BSS_SELECT_ATTR_RSSI_ADJUST = 3, | |
| + __NL80211_BSS_SELECT_ATTR_AFTER_LAST = 4, | |
| + NL80211_BSS_SELECT_ATTR_MAX = 3, | |
| +}; | |
| + | |
| +enum nl80211_bss_status { | |
| + NL80211_BSS_STATUS_AUTHENTICATED = 0, | |
| + NL80211_BSS_STATUS_ASSOCIATED = 1, | |
| + NL80211_BSS_STATUS_IBSS_JOINED = 2, | |
| +}; | |
| + | |
| +enum nl80211_bss_use_for { | |
| + NL80211_BSS_USE_FOR_NORMAL = 1, | |
| + NL80211_BSS_USE_FOR_MLD_LINK = 2, | |
| +}; | |
| + | |
| +enum nl80211_chan_width { | |
| + NL80211_CHAN_WIDTH_20_NOHT = 0, | |
| + NL80211_CHAN_WIDTH_20 = 1, | |
| + NL80211_CHAN_WIDTH_40 = 2, | |
| + NL80211_CHAN_WIDTH_80 = 3, | |
| + NL80211_CHAN_WIDTH_80P80 = 4, | |
| + NL80211_CHAN_WIDTH_160 = 5, | |
| + NL80211_CHAN_WIDTH_5 = 6, | |
| + NL80211_CHAN_WIDTH_10 = 7, | |
| + NL80211_CHAN_WIDTH_1 = 8, | |
| + NL80211_CHAN_WIDTH_2 = 9, | |
| + NL80211_CHAN_WIDTH_4 = 10, | |
| + NL80211_CHAN_WIDTH_8 = 11, | |
| + NL80211_CHAN_WIDTH_16 = 12, | |
| + NL80211_CHAN_WIDTH_320 = 13, | |
| +}; | |
| + | |
| +enum nl80211_channel_type { | |
| + NL80211_CHAN_NO_HT = 0, | |
| + NL80211_CHAN_HT20 = 1, | |
| + NL80211_CHAN_HT40MINUS = 2, | |
| + NL80211_CHAN_HT40PLUS = 3, | |
| +}; | |
| + | |
| +enum nl80211_coalesce_condition { | |
| + NL80211_COALESCE_CONDITION_MATCH = 0, | |
| + NL80211_COALESCE_CONDITION_NO_MATCH = 1, | |
| +}; | |
| + | |
| +enum nl80211_commands { | |
| + NL80211_CMD_UNSPEC = 0, | |
| + NL80211_CMD_GET_WIPHY = 1, | |
| + NL80211_CMD_SET_WIPHY = 2, | |
| + NL80211_CMD_NEW_WIPHY = 3, | |
| + NL80211_CMD_DEL_WIPHY = 4, | |
| + NL80211_CMD_GET_INTERFACE = 5, | |
| + NL80211_CMD_SET_INTERFACE = 6, | |
| + NL80211_CMD_NEW_INTERFACE = 7, | |
| + NL80211_CMD_DEL_INTERFACE = 8, | |
| + NL80211_CMD_GET_KEY = 9, | |
| + NL80211_CMD_SET_KEY = 10, | |
| + NL80211_CMD_NEW_KEY = 11, | |
| + NL80211_CMD_DEL_KEY = 12, | |
| + NL80211_CMD_GET_BEACON = 13, | |
| + NL80211_CMD_SET_BEACON = 14, | |
| + NL80211_CMD_START_AP = 15, | |
| + NL80211_CMD_NEW_BEACON = 15, | |
| + NL80211_CMD_STOP_AP = 16, | |
| + NL80211_CMD_DEL_BEACON = 16, | |
| + NL80211_CMD_GET_STATION = 17, | |
| + NL80211_CMD_SET_STATION = 18, | |
| + NL80211_CMD_NEW_STATION = 19, | |
| + NL80211_CMD_DEL_STATION = 20, | |
| + NL80211_CMD_GET_MPATH = 21, | |
| + NL80211_CMD_SET_MPATH = 22, | |
| + NL80211_CMD_NEW_MPATH = 23, | |
| + NL80211_CMD_DEL_MPATH = 24, | |
| + NL80211_CMD_SET_BSS = 25, | |
| + NL80211_CMD_SET_REG = 26, | |
| + NL80211_CMD_REQ_SET_REG = 27, | |
| + NL80211_CMD_GET_MESH_CONFIG = 28, | |
| + NL80211_CMD_SET_MESH_CONFIG = 29, | |
| + NL80211_CMD_SET_MGMT_EXTRA_IE = 30, | |
| + NL80211_CMD_GET_REG = 31, | |
| + NL80211_CMD_GET_SCAN = 32, | |
| + NL80211_CMD_TRIGGER_SCAN = 33, | |
| + NL80211_CMD_NEW_SCAN_RESULTS = 34, | |
| + NL80211_CMD_SCAN_ABORTED = 35, | |
| + NL80211_CMD_REG_CHANGE = 36, | |
| + NL80211_CMD_AUTHENTICATE = 37, | |
| + NL80211_CMD_ASSOCIATE = 38, | |
| + NL80211_CMD_DEAUTHENTICATE = 39, | |
| + NL80211_CMD_DISASSOCIATE = 40, | |
| + NL80211_CMD_MICHAEL_MIC_FAILURE = 41, | |
| + NL80211_CMD_REG_BEACON_HINT = 42, | |
| + NL80211_CMD_JOIN_IBSS = 43, | |
| + NL80211_CMD_LEAVE_IBSS = 44, | |
| + NL80211_CMD_TESTMODE = 45, | |
| + NL80211_CMD_CONNECT = 46, | |
| + NL80211_CMD_ROAM = 47, | |
| + NL80211_CMD_DISCONNECT = 48, | |
| + NL80211_CMD_SET_WIPHY_NETNS = 49, | |
| + NL80211_CMD_GET_SURVEY = 50, | |
| + NL80211_CMD_NEW_SURVEY_RESULTS = 51, | |
| + NL80211_CMD_SET_PMKSA = 52, | |
| + NL80211_CMD_DEL_PMKSA = 53, | |
| + NL80211_CMD_FLUSH_PMKSA = 54, | |
| + NL80211_CMD_REMAIN_ON_CHANNEL = 55, | |
| + NL80211_CMD_CANCEL_REMAIN_ON_CHANNEL = 56, | |
| + NL80211_CMD_SET_TX_BITRATE_MASK = 57, | |
| + NL80211_CMD_REGISTER_FRAME = 58, | |
| + NL80211_CMD_REGISTER_ACTION = 58, | |
| + NL80211_CMD_FRAME = 59, | |
| + NL80211_CMD_ACTION = 59, | |
| + NL80211_CMD_FRAME_TX_STATUS = 60, | |
| + NL80211_CMD_ACTION_TX_STATUS = 60, | |
| + NL80211_CMD_SET_POWER_SAVE = 61, | |
| + NL80211_CMD_GET_POWER_SAVE = 62, | |
| + NL80211_CMD_SET_CQM = 63, | |
| + NL80211_CMD_NOTIFY_CQM = 64, | |
| + NL80211_CMD_SET_CHANNEL = 65, | |
| + NL80211_CMD_SET_WDS_PEER = 66, | |
| + NL80211_CMD_FRAME_WAIT_CANCEL = 67, | |
| + NL80211_CMD_JOIN_MESH = 68, | |
| + NL80211_CMD_LEAVE_MESH = 69, | |
| + NL80211_CMD_UNPROT_DEAUTHENTICATE = 70, | |
| + NL80211_CMD_UNPROT_DISASSOCIATE = 71, | |
| + NL80211_CMD_NEW_PEER_CANDIDATE = 72, | |
| + NL80211_CMD_GET_WOWLAN = 73, | |
| + NL80211_CMD_SET_WOWLAN = 74, | |
| + NL80211_CMD_START_SCHED_SCAN = 75, | |
| + NL80211_CMD_STOP_SCHED_SCAN = 76, | |
| + NL80211_CMD_SCHED_SCAN_RESULTS = 77, | |
| + NL80211_CMD_SCHED_SCAN_STOPPED = 78, | |
| + NL80211_CMD_SET_REKEY_OFFLOAD = 79, | |
| + NL80211_CMD_PMKSA_CANDIDATE = 80, | |
| + NL80211_CMD_TDLS_OPER = 81, | |
| + NL80211_CMD_TDLS_MGMT = 82, | |
| + NL80211_CMD_UNEXPECTED_FRAME = 83, | |
| + NL80211_CMD_PROBE_CLIENT = 84, | |
| + NL80211_CMD_REGISTER_BEACONS = 85, | |
| + NL80211_CMD_UNEXPECTED_4ADDR_FRAME = 86, | |
| + NL80211_CMD_SET_NOACK_MAP = 87, | |
| + NL80211_CMD_CH_SWITCH_NOTIFY = 88, | |
| + NL80211_CMD_START_P2P_DEVICE = 89, | |
| + NL80211_CMD_STOP_P2P_DEVICE = 90, | |
| + NL80211_CMD_CONN_FAILED = 91, | |
| + NL80211_CMD_SET_MCAST_RATE = 92, | |
| + NL80211_CMD_SET_MAC_ACL = 93, | |
| + NL80211_CMD_RADAR_DETECT = 94, | |
| + NL80211_CMD_GET_PROTOCOL_FEATURES = 95, | |
| + NL80211_CMD_UPDATE_FT_IES = 96, | |
| + NL80211_CMD_FT_EVENT = 97, | |
| + NL80211_CMD_CRIT_PROTOCOL_START = 98, | |
| + NL80211_CMD_CRIT_PROTOCOL_STOP = 99, | |
| + NL80211_CMD_GET_COALESCE = 100, | |
| + NL80211_CMD_SET_COALESCE = 101, | |
| + NL80211_CMD_CHANNEL_SWITCH = 102, | |
| + NL80211_CMD_VENDOR = 103, | |
| + NL80211_CMD_SET_QOS_MAP = 104, | |
| + NL80211_CMD_ADD_TX_TS = 105, | |
| + NL80211_CMD_DEL_TX_TS = 106, | |
| + NL80211_CMD_GET_MPP = 107, | |
| + NL80211_CMD_JOIN_OCB = 108, | |
| + NL80211_CMD_LEAVE_OCB = 109, | |
| + NL80211_CMD_CH_SWITCH_STARTED_NOTIFY = 110, | |
| + NL80211_CMD_TDLS_CHANNEL_SWITCH = 111, | |
| + NL80211_CMD_TDLS_CANCEL_CHANNEL_SWITCH = 112, | |
| + NL80211_CMD_WIPHY_REG_CHANGE = 113, | |
| + NL80211_CMD_ABORT_SCAN = 114, | |
| + NL80211_CMD_START_NAN = 115, | |
| + NL80211_CMD_STOP_NAN = 116, | |
| + NL80211_CMD_ADD_NAN_FUNCTION = 117, | |
| + NL80211_CMD_DEL_NAN_FUNCTION = 118, | |
| + NL80211_CMD_CHANGE_NAN_CONFIG = 119, | |
| + NL80211_CMD_NAN_MATCH = 120, | |
| + NL80211_CMD_SET_MULTICAST_TO_UNICAST = 121, | |
| + NL80211_CMD_UPDATE_CONNECT_PARAMS = 122, | |
| + NL80211_CMD_SET_PMK = 123, | |
| + NL80211_CMD_DEL_PMK = 124, | |
| + NL80211_CMD_PORT_AUTHORIZED = 125, | |
| + NL80211_CMD_RELOAD_REGDB = 126, | |
| + NL80211_CMD_EXTERNAL_AUTH = 127, | |
| + NL80211_CMD_STA_OPMODE_CHANGED = 128, | |
| + NL80211_CMD_CONTROL_PORT_FRAME = 129, | |
| + NL80211_CMD_GET_FTM_RESPONDER_STATS = 130, | |
| + NL80211_CMD_PEER_MEASUREMENT_START = 131, | |
| + NL80211_CMD_PEER_MEASUREMENT_RESULT = 132, | |
| + NL80211_CMD_PEER_MEASUREMENT_COMPLETE = 133, | |
| + NL80211_CMD_NOTIFY_RADAR = 134, | |
| + NL80211_CMD_UPDATE_OWE_INFO = 135, | |
| + NL80211_CMD_PROBE_MESH_LINK = 136, | |
| + NL80211_CMD_SET_TID_CONFIG = 137, | |
| + NL80211_CMD_UNPROT_BEACON = 138, | |
| + NL80211_CMD_CONTROL_PORT_FRAME_TX_STATUS = 139, | |
| + NL80211_CMD_SET_SAR_SPECS = 140, | |
| + NL80211_CMD_OBSS_COLOR_COLLISION = 141, | |
| + NL80211_CMD_COLOR_CHANGE_REQUEST = 142, | |
| + NL80211_CMD_COLOR_CHANGE_STARTED = 143, | |
| + NL80211_CMD_COLOR_CHANGE_ABORTED = 144, | |
| + NL80211_CMD_COLOR_CHANGE_COMPLETED = 145, | |
| + NL80211_CMD_SET_FILS_AAD = 146, | |
| + NL80211_CMD_ASSOC_COMEBACK = 147, | |
| + NL80211_CMD_ADD_LINK = 148, | |
| + NL80211_CMD_REMOVE_LINK = 149, | |
| + NL80211_CMD_ADD_LINK_STA = 150, | |
| + NL80211_CMD_MODIFY_LINK_STA = 151, | |
| + NL80211_CMD_REMOVE_LINK_STA = 152, | |
| + NL80211_CMD_SET_HW_TIMESTAMP = 153, | |
| + NL80211_CMD_LINKS_REMOVED = 154, | |
| + NL80211_CMD_SET_TID_TO_LINK_MAPPING = 155, | |
| + __NL80211_CMD_AFTER_LAST = 156, | |
| + NL80211_CMD_MAX = 155, | |
| +}; | |
| + | |
| +enum nl80211_connect_failed_reason { | |
| + NL80211_CONN_FAIL_MAX_CLIENTS = 0, | |
| + NL80211_CONN_FAIL_BLOCKED_CLIENT = 1, | |
| +}; | |
| + | |
| +enum nl80211_cqm_rssi_threshold_event { | |
| + NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW = 0, | |
| + NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH = 1, | |
| + NL80211_CQM_RSSI_BEACON_LOSS_EVENT = 2, | |
| +}; | |
| + | |
| +enum nl80211_crit_proto_id { | |
| + NL80211_CRIT_PROTO_UNSPEC = 0, | |
| + NL80211_CRIT_PROTO_DHCP = 1, | |
| + NL80211_CRIT_PROTO_EAPOL = 2, | |
| + NL80211_CRIT_PROTO_APIPA = 3, | |
| + NUM_NL80211_CRIT_PROTO = 4, | |
| +}; | |
| + | |
| +enum nl80211_dfs_regions { | |
| + NL80211_DFS_UNSET = 0, | |
| + NL80211_DFS_FCC = 1, | |
| + NL80211_DFS_ETSI = 2, | |
| + NL80211_DFS_JP = 3, | |
| +}; | |
| + | |
| +enum nl80211_dfs_state { | |
| + NL80211_DFS_USABLE = 0, | |
| + NL80211_DFS_UNAVAILABLE = 1, | |
| + NL80211_DFS_AVAILABLE = 2, | |
| +}; | |
| + | |
| +enum nl80211_eht_gi { | |
| + NL80211_RATE_INFO_EHT_GI_0_8 = 0, | |
| + NL80211_RATE_INFO_EHT_GI_1_6 = 1, | |
| + NL80211_RATE_INFO_EHT_GI_3_2 = 2, | |
| +}; | |
| + | |
| +enum nl80211_eht_ru_alloc { | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_26 = 0, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_52 = 1, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_52P26 = 2, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_106 = 3, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_106P26 = 4, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_242 = 5, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_484 = 6, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_484P242 = 7, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_996 = 8, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_996P484 = 9, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_996P484P242 = 10, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_2x996 = 11, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_2x996P484 = 12, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_3x996 = 13, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_3x996P484 = 14, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC_4x996 = 15, | |
| +}; | |
| + | |
| +enum nl80211_ext_feature_index { | |
| + NL80211_EXT_FEATURE_VHT_IBSS = 0, | |
| + NL80211_EXT_FEATURE_RRM = 1, | |
| + NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER = 2, | |
| + NL80211_EXT_FEATURE_SCAN_START_TIME = 3, | |
| + NL80211_EXT_FEATURE_BSS_PARENT_TSF = 4, | |
| + NL80211_EXT_FEATURE_SET_SCAN_DWELL = 5, | |
| + NL80211_EXT_FEATURE_BEACON_RATE_LEGACY = 6, | |
| + NL80211_EXT_FEATURE_BEACON_RATE_HT = 7, | |
| + NL80211_EXT_FEATURE_BEACON_RATE_VHT = 8, | |
| + NL80211_EXT_FEATURE_FILS_STA = 9, | |
| + NL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA = 10, | |
| + NL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA_CONNECTED = 11, | |
| + NL80211_EXT_FEATURE_SCHED_SCAN_RELATIVE_RSSI = 12, | |
| + NL80211_EXT_FEATURE_CQM_RSSI_LIST = 13, | |
| + NL80211_EXT_FEATURE_FILS_SK_OFFLOAD = 14, | |
| + NL80211_EXT_FEATURE_4WAY_HANDSHAKE_STA_PSK = 15, | |
| + NL80211_EXT_FEATURE_4WAY_HANDSHAKE_STA_1X = 16, | |
| + NL80211_EXT_FEATURE_FILS_MAX_CHANNEL_TIME = 17, | |
| + NL80211_EXT_FEATURE_ACCEPT_BCAST_PROBE_RESP = 18, | |
| + NL80211_EXT_FEATURE_OCE_PROBE_REQ_HIGH_TX_RATE = 19, | |
| + NL80211_EXT_FEATURE_OCE_PROBE_REQ_DEFERRAL_SUPPRESSION = 20, | |
| + NL80211_EXT_FEATURE_MFP_OPTIONAL = 21, | |
| + NL80211_EXT_FEATURE_LOW_SPAN_SCAN = 22, | |
| + NL80211_EXT_FEATURE_LOW_POWER_SCAN = 23, | |
| + NL80211_EXT_FEATURE_HIGH_ACCURACY_SCAN = 24, | |
| + NL80211_EXT_FEATURE_DFS_OFFLOAD = 25, | |
| + NL80211_EXT_FEATURE_CONTROL_PORT_OVER_NL80211 = 26, | |
| + NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT = 27, | |
| + NL80211_EXT_FEATURE_DATA_ACK_SIGNAL_SUPPORT = 27, | |
| + NL80211_EXT_FEATURE_TXQS = 28, | |
| + NL80211_EXT_FEATURE_SCAN_RANDOM_SN = 29, | |
| + NL80211_EXT_FEATURE_SCAN_MIN_PREQ_CONTENT = 30, | |
| + NL80211_EXT_FEATURE_CAN_REPLACE_PTK0 = 31, | |
| + NL80211_EXT_FEATURE_ENABLE_FTM_RESPONDER = 32, | |
| + NL80211_EXT_FEATURE_AIRTIME_FAIRNESS = 33, | |
| + NL80211_EXT_FEATURE_AP_PMKSA_CACHING = 34, | |
| + NL80211_EXT_FEATURE_SCHED_SCAN_BAND_SPECIFIC_RSSI_THOLD = 35, | |
| + NL80211_EXT_FEATURE_EXT_KEY_ID = 36, | |
| + NL80211_EXT_FEATURE_STA_TX_PWR = 37, | |
| + NL80211_EXT_FEATURE_SAE_OFFLOAD = 38, | |
| + NL80211_EXT_FEATURE_VLAN_OFFLOAD = 39, | |
| + NL80211_EXT_FEATURE_AQL = 40, | |
| + NL80211_EXT_FEATURE_BEACON_PROTECTION = 41, | |
| + NL80211_EXT_FEATURE_CONTROL_PORT_NO_PREAUTH = 42, | |
| + NL80211_EXT_FEATURE_PROTECTED_TWT = 43, | |
| + NL80211_EXT_FEATURE_DEL_IBSS_STA = 44, | |
| + NL80211_EXT_FEATURE_MULTICAST_REGISTRATIONS = 45, | |
| + NL80211_EXT_FEATURE_BEACON_PROTECTION_CLIENT = 46, | |
| + NL80211_EXT_FEATURE_SCAN_FREQ_KHZ = 47, | |
| + NL80211_EXT_FEATURE_CONTROL_PORT_OVER_NL80211_TX_STATUS = 48, | |
| + NL80211_EXT_FEATURE_OPERATING_CHANNEL_VALIDATION = 49, | |
| + NL80211_EXT_FEATURE_4WAY_HANDSHAKE_AP_PSK = 50, | |
| + NL80211_EXT_FEATURE_SAE_OFFLOAD_AP = 51, | |
| + NL80211_EXT_FEATURE_FILS_DISCOVERY = 52, | |
| + NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP = 53, | |
| + NL80211_EXT_FEATURE_BEACON_RATE_HE = 54, | |
| + NL80211_EXT_FEATURE_SECURE_LTF = 55, | |
| + NL80211_EXT_FEATURE_SECURE_RTT = 56, | |
| + NL80211_EXT_FEATURE_PROT_RANGE_NEGO_AND_MEASURE = 57, | |
| + NL80211_EXT_FEATURE_BSS_COLOR = 58, | |
| + NL80211_EXT_FEATURE_FILS_CRYPTO_OFFLOAD = 59, | |
| + NL80211_EXT_FEATURE_RADAR_BACKGROUND = 60, | |
| + NL80211_EXT_FEATURE_POWERED_ADDR_CHANGE = 61, | |
| + NL80211_EXT_FEATURE_PUNCT = 62, | |
| + NL80211_EXT_FEATURE_SECURE_NAN = 63, | |
| + NL80211_EXT_FEATURE_AUTH_AND_DEAUTH_RANDOM_TA = 64, | |
| + NL80211_EXT_FEATURE_OWE_OFFLOAD = 65, | |
| + NL80211_EXT_FEATURE_OWE_OFFLOAD_AP = 66, | |
| + NL80211_EXT_FEATURE_DFS_CONCURRENT = 67, | |
| + NL80211_EXT_FEATURE_SPP_AMSDU_SUPPORT = 68, | |
| + NUM_NL80211_EXT_FEATURES = 69, | |
| + MAX_NL80211_EXT_FEATURES = 68, | |
| +}; | |
| + | |
| +enum nl80211_external_auth_action { | |
| + NL80211_EXTERNAL_AUTH_START = 0, | |
| + NL80211_EXTERNAL_AUTH_ABORT = 1, | |
| +}; | |
| + | |
| +enum nl80211_feature_flags { | |
| + NL80211_FEATURE_SK_TX_STATUS = 1, | |
| + NL80211_FEATURE_HT_IBSS = 2, | |
| + NL80211_FEATURE_INACTIVITY_TIMER = 4, | |
| + NL80211_FEATURE_CELL_BASE_REG_HINTS = 8, | |
| + NL80211_FEATURE_P2P_DEVICE_NEEDS_CHANNEL = 16, | |
| + NL80211_FEATURE_SAE = 32, | |
| + NL80211_FEATURE_LOW_PRIORITY_SCAN = 64, | |
| + NL80211_FEATURE_SCAN_FLUSH = 128, | |
| + NL80211_FEATURE_AP_SCAN = 256, | |
| + NL80211_FEATURE_VIF_TXPOWER = 512, | |
| + NL80211_FEATURE_NEED_OBSS_SCAN = 1024, | |
| + NL80211_FEATURE_P2P_GO_CTWIN = 2048, | |
| + NL80211_FEATURE_P2P_GO_OPPPS = 4096, | |
| + NL80211_FEATURE_ADVERTISE_CHAN_LIMITS = 16384, | |
| + NL80211_FEATURE_FULL_AP_CLIENT_STATE = 32768, | |
| + NL80211_FEATURE_USERSPACE_MPM = 65536, | |
| + NL80211_FEATURE_ACTIVE_MONITOR = 131072, | |
| + NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE = 262144, | |
| + NL80211_FEATURE_DS_PARAM_SET_IE_IN_PROBES = 524288, | |
| + NL80211_FEATURE_WFA_TPC_IE_IN_PROBES = 1048576, | |
| + NL80211_FEATURE_QUIET = 2097152, | |
| + NL80211_FEATURE_TX_POWER_INSERTION = 4194304, | |
| + NL80211_FEATURE_ACKTO_ESTIMATION = 8388608, | |
| + NL80211_FEATURE_STATIC_SMPS = 16777216, | |
| + NL80211_FEATURE_DYNAMIC_SMPS = 33554432, | |
| + NL80211_FEATURE_SUPPORTS_WMM_ADMISSION = 67108864, | |
| + NL80211_FEATURE_MAC_ON_CREATE = 134217728, | |
| + NL80211_FEATURE_TDLS_CHANNEL_SWITCH = 268435456, | |
| + NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR = 536870912, | |
| + NL80211_FEATURE_SCHED_SCAN_RANDOM_MAC_ADDR = 1073741824, | |
| + NL80211_FEATURE_ND_RANDOM_MAC_ADDR = 2147483648, | |
| +}; | |
| + | |
| +enum nl80211_fils_discovery_attributes { | |
| + __NL80211_FILS_DISCOVERY_ATTR_INVALID = 0, | |
| + NL80211_FILS_DISCOVERY_ATTR_INT_MIN = 1, | |
| + NL80211_FILS_DISCOVERY_ATTR_INT_MAX = 2, | |
| + NL80211_FILS_DISCOVERY_ATTR_TMPL = 3, | |
| + __NL80211_FILS_DISCOVERY_ATTR_LAST = 4, | |
| + NL80211_FILS_DISCOVERY_ATTR_MAX = 3, | |
| +}; | |
| + | |
| +enum nl80211_frequency_attr { | |
| + __NL80211_FREQUENCY_ATTR_INVALID = 0, | |
| + NL80211_FREQUENCY_ATTR_FREQ = 1, | |
| + NL80211_FREQUENCY_ATTR_DISABLED = 2, | |
| + NL80211_FREQUENCY_ATTR_NO_IR = 3, | |
| + __NL80211_FREQUENCY_ATTR_NO_IBSS = 4, | |
| + NL80211_FREQUENCY_ATTR_RADAR = 5, | |
| + NL80211_FREQUENCY_ATTR_MAX_TX_POWER = 6, | |
| + NL80211_FREQUENCY_ATTR_DFS_STATE = 7, | |
| + NL80211_FREQUENCY_ATTR_DFS_TIME = 8, | |
| + NL80211_FREQUENCY_ATTR_NO_HT40_MINUS = 9, | |
| + NL80211_FREQUENCY_ATTR_NO_HT40_PLUS = 10, | |
| + NL80211_FREQUENCY_ATTR_NO_80MHZ = 11, | |
| + NL80211_FREQUENCY_ATTR_NO_160MHZ = 12, | |
| + NL80211_FREQUENCY_ATTR_DFS_CAC_TIME = 13, | |
| + NL80211_FREQUENCY_ATTR_INDOOR_ONLY = 14, | |
| + NL80211_FREQUENCY_ATTR_IR_CONCURRENT = 15, | |
| + NL80211_FREQUENCY_ATTR_NO_20MHZ = 16, | |
| + NL80211_FREQUENCY_ATTR_NO_10MHZ = 17, | |
| + NL80211_FREQUENCY_ATTR_WMM = 18, | |
| + NL80211_FREQUENCY_ATTR_NO_HE = 19, | |
| + NL80211_FREQUENCY_ATTR_OFFSET = 20, | |
| + NL80211_FREQUENCY_ATTR_1MHZ = 21, | |
| + NL80211_FREQUENCY_ATTR_2MHZ = 22, | |
| + NL80211_FREQUENCY_ATTR_4MHZ = 23, | |
| + NL80211_FREQUENCY_ATTR_8MHZ = 24, | |
| + NL80211_FREQUENCY_ATTR_16MHZ = 25, | |
| + NL80211_FREQUENCY_ATTR_NO_320MHZ = 26, | |
| + NL80211_FREQUENCY_ATTR_NO_EHT = 27, | |
| + NL80211_FREQUENCY_ATTR_PSD = 28, | |
| + NL80211_FREQUENCY_ATTR_DFS_CONCURRENT = 29, | |
| + NL80211_FREQUENCY_ATTR_NO_6GHZ_VLP_CLIENT = 30, | |
| + NL80211_FREQUENCY_ATTR_NO_6GHZ_AFC_CLIENT = 31, | |
| + NL80211_FREQUENCY_ATTR_CAN_MONITOR = 32, | |
| + __NL80211_FREQUENCY_ATTR_AFTER_LAST = 33, | |
| + NL80211_FREQUENCY_ATTR_MAX = 32, | |
| +}; | |
| + | |
| +enum nl80211_ftm_responder_attributes { | |
| + __NL80211_FTM_RESP_ATTR_INVALID = 0, | |
| + NL80211_FTM_RESP_ATTR_ENABLED = 1, | |
| + NL80211_FTM_RESP_ATTR_LCI = 2, | |
| + NL80211_FTM_RESP_ATTR_CIVICLOC = 3, | |
| + __NL80211_FTM_RESP_ATTR_LAST = 4, | |
| + NL80211_FTM_RESP_ATTR_MAX = 3, | |
| +}; | |
| + | |
| +enum nl80211_ftm_responder_stats { | |
| + __NL80211_FTM_STATS_INVALID = 0, | |
| + NL80211_FTM_STATS_SUCCESS_NUM = 1, | |
| + NL80211_FTM_STATS_PARTIAL_NUM = 2, | |
| + NL80211_FTM_STATS_FAILED_NUM = 3, | |
| + NL80211_FTM_STATS_ASAP_NUM = 4, | |
| + NL80211_FTM_STATS_NON_ASAP_NUM = 5, | |
| + NL80211_FTM_STATS_TOTAL_DURATION_MSEC = 6, | |
| + NL80211_FTM_STATS_UNKNOWN_TRIGGERS_NUM = 7, | |
| + NL80211_FTM_STATS_RESCHEDULE_REQUESTS_NUM = 8, | |
| + NL80211_FTM_STATS_OUT_OF_WINDOW_TRIGGERS_NUM = 9, | |
| + NL80211_FTM_STATS_PAD = 10, | |
| + __NL80211_FTM_STATS_AFTER_LAST = 11, | |
| + NL80211_FTM_STATS_MAX = 10, | |
| +}; | |
| + | |
| +enum nl80211_he_gi { | |
| + NL80211_RATE_INFO_HE_GI_0_8 = 0, | |
| + NL80211_RATE_INFO_HE_GI_1_6 = 1, | |
| + NL80211_RATE_INFO_HE_GI_3_2 = 2, | |
| +}; | |
| + | |
| +enum nl80211_he_ltf { | |
| + NL80211_RATE_INFO_HE_1XLTF = 0, | |
| + NL80211_RATE_INFO_HE_2XLTF = 1, | |
| + NL80211_RATE_INFO_HE_4XLTF = 2, | |
| +}; | |
| + | |
| +enum nl80211_he_ru_alloc { | |
| + NL80211_RATE_INFO_HE_RU_ALLOC_26 = 0, | |
| + NL80211_RATE_INFO_HE_RU_ALLOC_52 = 1, | |
| + NL80211_RATE_INFO_HE_RU_ALLOC_106 = 2, | |
| + NL80211_RATE_INFO_HE_RU_ALLOC_242 = 3, | |
| + NL80211_RATE_INFO_HE_RU_ALLOC_484 = 4, | |
| + NL80211_RATE_INFO_HE_RU_ALLOC_996 = 5, | |
| + NL80211_RATE_INFO_HE_RU_ALLOC_2x996 = 6, | |
| +}; | |
| + | |
| +enum nl80211_hidden_ssid { | |
| + NL80211_HIDDEN_SSID_NOT_IN_USE = 0, | |
| + NL80211_HIDDEN_SSID_ZERO_LEN = 1, | |
| + NL80211_HIDDEN_SSID_ZERO_CONTENTS = 2, | |
| +}; | |
| + | |
| +enum nl80211_if_combination_attrs { | |
| + NL80211_IFACE_COMB_UNSPEC = 0, | |
| + NL80211_IFACE_COMB_LIMITS = 1, | |
| + NL80211_IFACE_COMB_MAXNUM = 2, | |
| + NL80211_IFACE_COMB_STA_AP_BI_MATCH = 3, | |
| + NL80211_IFACE_COMB_NUM_CHANNELS = 4, | |
| + NL80211_IFACE_COMB_RADAR_DETECT_WIDTHS = 5, | |
| + NL80211_IFACE_COMB_RADAR_DETECT_REGIONS = 6, | |
| + NL80211_IFACE_COMB_BI_MIN_GCD = 7, | |
| + NUM_NL80211_IFACE_COMB = 8, | |
| + MAX_NL80211_IFACE_COMB = 7, | |
| +}; | |
| + | |
| +enum nl80211_iface_limit_attrs { | |
| + NL80211_IFACE_LIMIT_UNSPEC = 0, | |
| + NL80211_IFACE_LIMIT_MAX = 1, | |
| + NL80211_IFACE_LIMIT_TYPES = 2, | |
| + NUM_NL80211_IFACE_LIMIT = 3, | |
| + MAX_NL80211_IFACE_LIMIT = 2, | |
| +}; | |
| + | |
| +enum nl80211_iftype { | |
| + NL80211_IFTYPE_UNSPECIFIED = 0, | |
| + NL80211_IFTYPE_ADHOC = 1, | |
| + NL80211_IFTYPE_STATION = 2, | |
| + NL80211_IFTYPE_AP = 3, | |
| + NL80211_IFTYPE_AP_VLAN = 4, | |
| + NL80211_IFTYPE_WDS = 5, | |
| + NL80211_IFTYPE_MONITOR = 6, | |
| + NL80211_IFTYPE_MESH_POINT = 7, | |
| + NL80211_IFTYPE_P2P_CLIENT = 8, | |
| + NL80211_IFTYPE_P2P_GO = 9, | |
| + NL80211_IFTYPE_P2P_DEVICE = 10, | |
| + NL80211_IFTYPE_OCB = 11, | |
| + NL80211_IFTYPE_NAN = 12, | |
| + NUM_NL80211_IFTYPES = 13, | |
| + NL80211_IFTYPE_MAX = 12, | |
| +}; | |
| + | |
| +enum nl80211_iftype_akm_attributes { | |
| + __NL80211_IFTYPE_AKM_ATTR_INVALID = 0, | |
| + NL80211_IFTYPE_AKM_ATTR_IFTYPES = 1, | |
| + NL80211_IFTYPE_AKM_ATTR_SUITES = 2, | |
| + __NL80211_IFTYPE_AKM_ATTR_LAST = 3, | |
| + NL80211_IFTYPE_AKM_ATTR_MAX = 2, | |
| +}; | |
| + | |
| +enum nl80211_internal_flags_selector { | |
| + NL80211_IFL_SEL_NONE = 0, | |
| + NL80211_IFL_SEL_WIPHY = 1, | |
| + NL80211_IFL_SEL_WDEV = 2, | |
| + NL80211_IFL_SEL_NETDEV = 3, | |
| + NL80211_IFL_SEL_NETDEV_LINK = 4, | |
| + NL80211_IFL_SEL_NETDEV_NO_MLO = 5, | |
| + NL80211_IFL_SEL_WIPHY_RTNL = 6, | |
| + NL80211_IFL_SEL_WIPHY_RTNL_NOMTX = 7, | |
| + NL80211_IFL_SEL_WDEV_RTNL = 8, | |
| + NL80211_IFL_SEL_NETDEV_RTNL = 9, | |
| + NL80211_IFL_SEL_NETDEV_UP = 10, | |
| + NL80211_IFL_SEL_NETDEV_UP_LINK = 11, | |
| + NL80211_IFL_SEL_NETDEV_UP_NO_MLO = 12, | |
| + NL80211_IFL_SEL_NETDEV_UP_NO_MLO_CLEAR = 13, | |
| + NL80211_IFL_SEL_NETDEV_UP_NOTMX = 14, | |
| + NL80211_IFL_SEL_NETDEV_UP_NOTMX_NOMLO = 15, | |
| + NL80211_IFL_SEL_NETDEV_UP_CLEAR = 16, | |
| + NL80211_IFL_SEL_WDEV_UP = 17, | |
| + NL80211_IFL_SEL_WDEV_UP_LINK = 18, | |
| + NL80211_IFL_SEL_WDEV_UP_RTNL = 19, | |
| + NL80211_IFL_SEL_WIPHY_CLEAR = 20, | |
| +}; | |
| + | |
| +enum nl80211_key_attributes { | |
| + __NL80211_KEY_INVALID = 0, | |
| + NL80211_KEY_DATA = 1, | |
| + NL80211_KEY_IDX = 2, | |
| + NL80211_KEY_CIPHER = 3, | |
| + NL80211_KEY_SEQ = 4, | |
| + NL80211_KEY_DEFAULT = 5, | |
| + NL80211_KEY_DEFAULT_MGMT = 6, | |
| + NL80211_KEY_TYPE = 7, | |
| + NL80211_KEY_DEFAULT_TYPES = 8, | |
| + NL80211_KEY_MODE = 9, | |
| + NL80211_KEY_DEFAULT_BEACON = 10, | |
| + __NL80211_KEY_AFTER_LAST = 11, | |
| + NL80211_KEY_MAX = 10, | |
| +}; | |
| + | |
| +enum nl80211_key_default_types { | |
| + __NL80211_KEY_DEFAULT_TYPE_INVALID = 0, | |
| + NL80211_KEY_DEFAULT_TYPE_UNICAST = 1, | |
| + NL80211_KEY_DEFAULT_TYPE_MULTICAST = 2, | |
| + NUM_NL80211_KEY_DEFAULT_TYPES = 3, | |
| +}; | |
| + | |
| +enum nl80211_key_mode { | |
| + NL80211_KEY_RX_TX = 0, | |
| + NL80211_KEY_NO_TX = 1, | |
| + NL80211_KEY_SET_TX = 2, | |
| +}; | |
| + | |
| +enum nl80211_key_type { | |
| + NL80211_KEYTYPE_GROUP = 0, | |
| + NL80211_KEYTYPE_PAIRWISE = 1, | |
| + NL80211_KEYTYPE_PEERKEY = 2, | |
| + NUM_NL80211_KEYTYPES = 3, | |
| +}; | |
| + | |
| +enum nl80211_mbssid_config_attributes { | |
| + __NL80211_MBSSID_CONFIG_ATTR_INVALID = 0, | |
| + NL80211_MBSSID_CONFIG_ATTR_MAX_INTERFACES = 1, | |
| + NL80211_MBSSID_CONFIG_ATTR_MAX_EMA_PROFILE_PERIODICITY = 2, | |
| + NL80211_MBSSID_CONFIG_ATTR_INDEX = 3, | |
| + NL80211_MBSSID_CONFIG_ATTR_TX_IFINDEX = 4, | |
| + NL80211_MBSSID_CONFIG_ATTR_EMA = 5, | |
| + __NL80211_MBSSID_CONFIG_ATTR_LAST = 6, | |
| + NL80211_MBSSID_CONFIG_ATTR_MAX = 5, | |
| +}; | |
| + | |
| +enum nl80211_mesh_power_mode { | |
| + NL80211_MESH_POWER_UNKNOWN = 0, | |
| + NL80211_MESH_POWER_ACTIVE = 1, | |
| + NL80211_MESH_POWER_LIGHT_SLEEP = 2, | |
| + NL80211_MESH_POWER_DEEP_SLEEP = 3, | |
| + __NL80211_MESH_POWER_AFTER_LAST = 4, | |
| + NL80211_MESH_POWER_MAX = 3, | |
| +}; | |
| + | |
| +enum nl80211_mesh_setup_params { | |
| + __NL80211_MESH_SETUP_INVALID = 0, | |
| + NL80211_MESH_SETUP_ENABLE_VENDOR_PATH_SEL = 1, | |
| + NL80211_MESH_SETUP_ENABLE_VENDOR_METRIC = 2, | |
| + NL80211_MESH_SETUP_IE = 3, | |
| + NL80211_MESH_SETUP_USERSPACE_AUTH = 4, | |
| + NL80211_MESH_SETUP_USERSPACE_AMPE = 5, | |
| + NL80211_MESH_SETUP_ENABLE_VENDOR_SYNC = 6, | |
| + NL80211_MESH_SETUP_USERSPACE_MPM = 7, | |
| + NL80211_MESH_SETUP_AUTH_PROTOCOL = 8, | |
| + __NL80211_MESH_SETUP_ATTR_AFTER_LAST = 9, | |
| + NL80211_MESH_SETUP_ATTR_MAX = 8, | |
| +}; | |
| + | |
| +enum nl80211_meshconf_params { | |
| + __NL80211_MESHCONF_INVALID = 0, | |
| + NL80211_MESHCONF_RETRY_TIMEOUT = 1, | |
| + NL80211_MESHCONF_CONFIRM_TIMEOUT = 2, | |
| + NL80211_MESHCONF_HOLDING_TIMEOUT = 3, | |
| + NL80211_MESHCONF_MAX_PEER_LINKS = 4, | |
| + NL80211_MESHCONF_MAX_RETRIES = 5, | |
| + NL80211_MESHCONF_TTL = 6, | |
| + NL80211_MESHCONF_AUTO_OPEN_PLINKS = 7, | |
| + NL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES = 8, | |
| + NL80211_MESHCONF_PATH_REFRESH_TIME = 9, | |
| + NL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT = 10, | |
| + NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT = 11, | |
| + NL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL = 12, | |
| + NL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME = 13, | |
| + NL80211_MESHCONF_HWMP_ROOTMODE = 14, | |
| + NL80211_MESHCONF_ELEMENT_TTL = 15, | |
| + NL80211_MESHCONF_HWMP_RANN_INTERVAL = 16, | |
| + NL80211_MESHCONF_GATE_ANNOUNCEMENTS = 17, | |
| + NL80211_MESHCONF_HWMP_PERR_MIN_INTERVAL = 18, | |
| + NL80211_MESHCONF_FORWARDING = 19, | |
| + NL80211_MESHCONF_RSSI_THRESHOLD = 20, | |
| + NL80211_MESHCONF_SYNC_OFFSET_MAX_NEIGHBOR = 21, | |
| + NL80211_MESHCONF_HT_OPMODE = 22, | |
| + NL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT = 23, | |
| + NL80211_MESHCONF_HWMP_ROOT_INTERVAL = 24, | |
| + NL80211_MESHCONF_HWMP_CONFIRMATION_INTERVAL = 25, | |
| + NL80211_MESHCONF_POWER_MODE = 26, | |
| + NL80211_MESHCONF_AWAKE_WINDOW = 27, | |
| + NL80211_MESHCONF_PLINK_TIMEOUT = 28, | |
| + NL80211_MESHCONF_CONNECTED_TO_GATE = 29, | |
| + NL80211_MESHCONF_NOLEARN = 30, | |
| + NL80211_MESHCONF_CONNECTED_TO_AS = 31, | |
| + __NL80211_MESHCONF_ATTR_AFTER_LAST = 32, | |
| + NL80211_MESHCONF_ATTR_MAX = 31, | |
| +}; | |
| + | |
| +enum nl80211_mfp { | |
| + NL80211_MFP_NO = 0, | |
| + NL80211_MFP_REQUIRED = 1, | |
| + NL80211_MFP_OPTIONAL = 2, | |
| +}; | |
| + | |
| +enum nl80211_mntr_flags { | |
| + __NL80211_MNTR_FLAG_INVALID = 0, | |
| + NL80211_MNTR_FLAG_FCSFAIL = 1, | |
| + NL80211_MNTR_FLAG_PLCPFAIL = 2, | |
| + NL80211_MNTR_FLAG_CONTROL = 3, | |
| + NL80211_MNTR_FLAG_OTHER_BSS = 4, | |
| + NL80211_MNTR_FLAG_COOK_FRAMES = 5, | |
| + NL80211_MNTR_FLAG_ACTIVE = 6, | |
| + __NL80211_MNTR_FLAG_AFTER_LAST = 7, | |
| + NL80211_MNTR_FLAG_MAX = 6, | |
| +}; | |
| + | |
| +enum nl80211_mpath_info { | |
| + __NL80211_MPATH_INFO_INVALID = 0, | |
| + NL80211_MPATH_INFO_FRAME_QLEN = 1, | |
| + NL80211_MPATH_INFO_SN = 2, | |
| + NL80211_MPATH_INFO_METRIC = 3, | |
| + NL80211_MPATH_INFO_EXPTIME = 4, | |
| + NL80211_MPATH_INFO_FLAGS = 5, | |
| + NL80211_MPATH_INFO_DISCOVERY_TIMEOUT = 6, | |
| + NL80211_MPATH_INFO_DISCOVERY_RETRIES = 7, | |
| + NL80211_MPATH_INFO_HOP_COUNT = 8, | |
| + NL80211_MPATH_INFO_PATH_CHANGE = 9, | |
| + __NL80211_MPATH_INFO_AFTER_LAST = 10, | |
| + NL80211_MPATH_INFO_MAX = 9, | |
| +}; | |
| + | |
| +enum nl80211_multicast_groups { | |
| + NL80211_MCGRP_CONFIG = 0, | |
| + NL80211_MCGRP_SCAN = 1, | |
| + NL80211_MCGRP_REGULATORY = 2, | |
| + NL80211_MCGRP_MLME = 3, | |
| + NL80211_MCGRP_VENDOR = 4, | |
| + NL80211_MCGRP_NAN = 5, | |
| + NL80211_MCGRP_TESTMODE = 6, | |
| +}; | |
| + | |
| +enum nl80211_nan_func_attributes { | |
| + __NL80211_NAN_FUNC_INVALID = 0, | |
| + NL80211_NAN_FUNC_TYPE = 1, | |
| + NL80211_NAN_FUNC_SERVICE_ID = 2, | |
| + NL80211_NAN_FUNC_PUBLISH_TYPE = 3, | |
| + NL80211_NAN_FUNC_PUBLISH_BCAST = 4, | |
| + NL80211_NAN_FUNC_SUBSCRIBE_ACTIVE = 5, | |
| + NL80211_NAN_FUNC_FOLLOW_UP_ID = 6, | |
| + NL80211_NAN_FUNC_FOLLOW_UP_REQ_ID = 7, | |
| + NL80211_NAN_FUNC_FOLLOW_UP_DEST = 8, | |
| + NL80211_NAN_FUNC_CLOSE_RANGE = 9, | |
| + NL80211_NAN_FUNC_TTL = 10, | |
| + NL80211_NAN_FUNC_SERVICE_INFO = 11, | |
| + NL80211_NAN_FUNC_SRF = 12, | |
| + NL80211_NAN_FUNC_RX_MATCH_FILTER = 13, | |
| + NL80211_NAN_FUNC_TX_MATCH_FILTER = 14, | |
| + NL80211_NAN_FUNC_INSTANCE_ID = 15, | |
| + NL80211_NAN_FUNC_TERM_REASON = 16, | |
| + NUM_NL80211_NAN_FUNC_ATTR = 17, | |
| + NL80211_NAN_FUNC_ATTR_MAX = 16, | |
| +}; | |
| + | |
| +enum nl80211_nan_func_term_reason { | |
| + NL80211_NAN_FUNC_TERM_REASON_USER_REQUEST = 0, | |
| + NL80211_NAN_FUNC_TERM_REASON_TTL_EXPIRED = 1, | |
| + NL80211_NAN_FUNC_TERM_REASON_ERROR = 2, | |
| +}; | |
| + | |
| +enum nl80211_nan_function_type { | |
| + NL80211_NAN_FUNC_PUBLISH = 0, | |
| + NL80211_NAN_FUNC_SUBSCRIBE = 1, | |
| + NL80211_NAN_FUNC_FOLLOW_UP = 2, | |
| + __NL80211_NAN_FUNC_TYPE_AFTER_LAST = 3, | |
| + NL80211_NAN_FUNC_MAX_TYPE = 2, | |
| +}; | |
| + | |
| +enum nl80211_nan_match_attributes { | |
| + __NL80211_NAN_MATCH_INVALID = 0, | |
| + NL80211_NAN_MATCH_FUNC_LOCAL = 1, | |
| + NL80211_NAN_MATCH_FUNC_PEER = 2, | |
| + NUM_NL80211_NAN_MATCH_ATTR = 3, | |
| + NL80211_NAN_MATCH_ATTR_MAX = 2, | |
| +}; | |
| + | |
| +enum nl80211_nan_publish_type { | |
| + NL80211_NAN_SOLICITED_PUBLISH = 1, | |
| + NL80211_NAN_UNSOLICITED_PUBLISH = 2, | |
| +}; | |
| + | |
| +enum nl80211_nan_srf_attributes { | |
| + __NL80211_NAN_SRF_INVALID = 0, | |
| + NL80211_NAN_SRF_INCLUDE = 1, | |
| + NL80211_NAN_SRF_BF = 2, | |
| + NL80211_NAN_SRF_BF_IDX = 3, | |
| + NL80211_NAN_SRF_MAC_ADDRS = 4, | |
| + NUM_NL80211_NAN_SRF_ATTR = 5, | |
| + NL80211_NAN_SRF_ATTR_MAX = 4, | |
| +}; | |
| + | |
| +enum nl80211_obss_pd_attributes { | |
| + __NL80211_HE_OBSS_PD_ATTR_INVALID = 0, | |
| + NL80211_HE_OBSS_PD_ATTR_MIN_OFFSET = 1, | |
| + NL80211_HE_OBSS_PD_ATTR_MAX_OFFSET = 2, | |
| + NL80211_HE_OBSS_PD_ATTR_NON_SRG_MAX_OFFSET = 3, | |
| + NL80211_HE_OBSS_PD_ATTR_BSS_COLOR_BITMAP = 4, | |
| + NL80211_HE_OBSS_PD_ATTR_PARTIAL_BSSID_BITMAP = 5, | |
| + NL80211_HE_OBSS_PD_ATTR_SR_CTRL = 6, | |
| + __NL80211_HE_OBSS_PD_ATTR_LAST = 7, | |
| + NL80211_HE_OBSS_PD_ATTR_MAX = 6, | |
| +}; | |
| + | |
| +enum nl80211_packet_pattern_attr { | |
| + __NL80211_PKTPAT_INVALID = 0, | |
| + NL80211_PKTPAT_MASK = 1, | |
| + NL80211_PKTPAT_PATTERN = 2, | |
| + NL80211_PKTPAT_OFFSET = 3, | |
| + NUM_NL80211_PKTPAT = 4, | |
| + MAX_NL80211_PKTPAT = 3, | |
| +}; | |
| + | |
| +enum nl80211_peer_measurement_attrs { | |
| + __NL80211_PMSR_ATTR_INVALID = 0, | |
| + NL80211_PMSR_ATTR_MAX_PEERS = 1, | |
| + NL80211_PMSR_ATTR_REPORT_AP_TSF = 2, | |
| + NL80211_PMSR_ATTR_RANDOMIZE_MAC_ADDR = 3, | |
| + NL80211_PMSR_ATTR_TYPE_CAPA = 4, | |
| + NL80211_PMSR_ATTR_PEERS = 5, | |
| + NUM_NL80211_PMSR_ATTR = 6, | |
| + NL80211_PMSR_ATTR_MAX = 5, | |
| +}; | |
| + | |
| +enum nl80211_peer_measurement_ftm_capa { | |
| + __NL80211_PMSR_FTM_CAPA_ATTR_INVALID = 0, | |
| + NL80211_PMSR_FTM_CAPA_ATTR_ASAP = 1, | |
| + NL80211_PMSR_FTM_CAPA_ATTR_NON_ASAP = 2, | |
| + NL80211_PMSR_FTM_CAPA_ATTR_REQ_LCI = 3, | |
| + NL80211_PMSR_FTM_CAPA_ATTR_REQ_CIVICLOC = 4, | |
| + NL80211_PMSR_FTM_CAPA_ATTR_PREAMBLES = 5, | |
| + NL80211_PMSR_FTM_CAPA_ATTR_BANDWIDTHS = 6, | |
| + NL80211_PMSR_FTM_CAPA_ATTR_MAX_BURSTS_EXPONENT = 7, | |
| + NL80211_PMSR_FTM_CAPA_ATTR_MAX_FTMS_PER_BURST = 8, | |
| + NL80211_PMSR_FTM_CAPA_ATTR_TRIGGER_BASED = 9, | |
| + NL80211_PMSR_FTM_CAPA_ATTR_NON_TRIGGER_BASED = 10, | |
| + NUM_NL80211_PMSR_FTM_CAPA_ATTR = 11, | |
| + NL80211_PMSR_FTM_CAPA_ATTR_MAX = 10, | |
| +}; | |
| + | |
| +enum nl80211_peer_measurement_ftm_failure_reasons { | |
| + NL80211_PMSR_FTM_FAILURE_UNSPECIFIED = 0, | |
| + NL80211_PMSR_FTM_FAILURE_NO_RESPONSE = 1, | |
| + NL80211_PMSR_FTM_FAILURE_REJECTED = 2, | |
| + NL80211_PMSR_FTM_FAILURE_WRONG_CHANNEL = 3, | |
| + NL80211_PMSR_FTM_FAILURE_PEER_NOT_CAPABLE = 4, | |
| + NL80211_PMSR_FTM_FAILURE_INVALID_TIMESTAMP = 5, | |
| + NL80211_PMSR_FTM_FAILURE_PEER_BUSY = 6, | |
| + NL80211_PMSR_FTM_FAILURE_BAD_CHANGED_PARAMS = 7, | |
| +}; | |
| + | |
| +enum nl80211_peer_measurement_ftm_req { | |
| + __NL80211_PMSR_FTM_REQ_ATTR_INVALID = 0, | |
| + NL80211_PMSR_FTM_REQ_ATTR_ASAP = 1, | |
| + NL80211_PMSR_FTM_REQ_ATTR_PREAMBLE = 2, | |
| + NL80211_PMSR_FTM_REQ_ATTR_NUM_BURSTS_EXP = 3, | |
| + NL80211_PMSR_FTM_REQ_ATTR_BURST_PERIOD = 4, | |
| + NL80211_PMSR_FTM_REQ_ATTR_BURST_DURATION = 5, | |
| + NL80211_PMSR_FTM_REQ_ATTR_FTMS_PER_BURST = 6, | |
| + NL80211_PMSR_FTM_REQ_ATTR_NUM_FTMR_RETRIES = 7, | |
| + NL80211_PMSR_FTM_REQ_ATTR_REQUEST_LCI = 8, | |
| + NL80211_PMSR_FTM_REQ_ATTR_REQUEST_CIVICLOC = 9, | |
| + NL80211_PMSR_FTM_REQ_ATTR_TRIGGER_BASED = 10, | |
| + NL80211_PMSR_FTM_REQ_ATTR_NON_TRIGGER_BASED = 11, | |
| + NL80211_PMSR_FTM_REQ_ATTR_LMR_FEEDBACK = 12, | |
| + NL80211_PMSR_FTM_REQ_ATTR_BSS_COLOR = 13, | |
| + NUM_NL80211_PMSR_FTM_REQ_ATTR = 14, | |
| + NL80211_PMSR_FTM_REQ_ATTR_MAX = 13, | |
| +}; | |
| + | |
| +enum nl80211_peer_measurement_ftm_resp { | |
| + __NL80211_PMSR_FTM_RESP_ATTR_INVALID = 0, | |
| + NL80211_PMSR_FTM_RESP_ATTR_FAIL_REASON = 1, | |
| + NL80211_PMSR_FTM_RESP_ATTR_BURST_INDEX = 2, | |
| + NL80211_PMSR_FTM_RESP_ATTR_NUM_FTMR_ATTEMPTS = 3, | |
| + NL80211_PMSR_FTM_RESP_ATTR_NUM_FTMR_SUCCESSES = 4, | |
| + NL80211_PMSR_FTM_RESP_ATTR_BUSY_RETRY_TIME = 5, | |
| + NL80211_PMSR_FTM_RESP_ATTR_NUM_BURSTS_EXP = 6, | |
| + NL80211_PMSR_FTM_RESP_ATTR_BURST_DURATION = 7, | |
| + NL80211_PMSR_FTM_RESP_ATTR_FTMS_PER_BURST = 8, | |
| + NL80211_PMSR_FTM_RESP_ATTR_RSSI_AVG = 9, | |
| + NL80211_PMSR_FTM_RESP_ATTR_RSSI_SPREAD = 10, | |
| + NL80211_PMSR_FTM_RESP_ATTR_TX_RATE = 11, | |
| + NL80211_PMSR_FTM_RESP_ATTR_RX_RATE = 12, | |
| + NL80211_PMSR_FTM_RESP_ATTR_RTT_AVG = 13, | |
| + NL80211_PMSR_FTM_RESP_ATTR_RTT_VARIANCE = 14, | |
| + NL80211_PMSR_FTM_RESP_ATTR_RTT_SPREAD = 15, | |
| + NL80211_PMSR_FTM_RESP_ATTR_DIST_AVG = 16, | |
| + NL80211_PMSR_FTM_RESP_ATTR_DIST_VARIANCE = 17, | |
| + NL80211_PMSR_FTM_RESP_ATTR_DIST_SPREAD = 18, | |
| + NL80211_PMSR_FTM_RESP_ATTR_LCI = 19, | |
| + NL80211_PMSR_FTM_RESP_ATTR_CIVICLOC = 20, | |
| + NL80211_PMSR_FTM_RESP_ATTR_PAD = 21, | |
| + NUM_NL80211_PMSR_FTM_RESP_ATTR = 22, | |
| + NL80211_PMSR_FTM_RESP_ATTR_MAX = 21, | |
| +}; | |
| + | |
| +enum nl80211_peer_measurement_peer_attrs { | |
| + __NL80211_PMSR_PEER_ATTR_INVALID = 0, | |
| + NL80211_PMSR_PEER_ATTR_ADDR = 1, | |
| + NL80211_PMSR_PEER_ATTR_CHAN = 2, | |
| + NL80211_PMSR_PEER_ATTR_REQ = 3, | |
| + NL80211_PMSR_PEER_ATTR_RESP = 4, | |
| + NUM_NL80211_PMSR_PEER_ATTRS = 5, | |
| + NL80211_PMSR_PEER_ATTR_MAX = 4, | |
| +}; | |
| + | |
| +enum nl80211_peer_measurement_req { | |
| + __NL80211_PMSR_REQ_ATTR_INVALID = 0, | |
| + NL80211_PMSR_REQ_ATTR_DATA = 1, | |
| + NL80211_PMSR_REQ_ATTR_GET_AP_TSF = 2, | |
| + NUM_NL80211_PMSR_REQ_ATTRS = 3, | |
| + NL80211_PMSR_REQ_ATTR_MAX = 2, | |
| +}; | |
| + | |
| +enum nl80211_peer_measurement_resp { | |
| + __NL80211_PMSR_RESP_ATTR_INVALID = 0, | |
| + NL80211_PMSR_RESP_ATTR_DATA = 1, | |
| + NL80211_PMSR_RESP_ATTR_STATUS = 2, | |
| + NL80211_PMSR_RESP_ATTR_HOST_TIME = 3, | |
| + NL80211_PMSR_RESP_ATTR_AP_TSF = 4, | |
| + NL80211_PMSR_RESP_ATTR_FINAL = 5, | |
| + NL80211_PMSR_RESP_ATTR_PAD = 6, | |
| + NUM_NL80211_PMSR_RESP_ATTRS = 7, | |
| + NL80211_PMSR_RESP_ATTR_MAX = 6, | |
| +}; | |
| + | |
| +enum nl80211_peer_measurement_status { | |
| + NL80211_PMSR_STATUS_SUCCESS = 0, | |
| + NL80211_PMSR_STATUS_REFUSED = 1, | |
| + NL80211_PMSR_STATUS_TIMEOUT = 2, | |
| + NL80211_PMSR_STATUS_FAILURE = 3, | |
| +}; | |
| + | |
| +enum nl80211_peer_measurement_type { | |
| + NL80211_PMSR_TYPE_INVALID = 0, | |
| + NL80211_PMSR_TYPE_FTM = 1, | |
| + NUM_NL80211_PMSR_TYPES = 2, | |
| + NL80211_PMSR_TYPE_MAX = 1, | |
| +}; | |
| + | |
| +enum nl80211_plink_action { | |
| + NL80211_PLINK_ACTION_NO_ACTION = 0, | |
| + NL80211_PLINK_ACTION_OPEN = 1, | |
| + NL80211_PLINK_ACTION_BLOCK = 2, | |
| + NUM_NL80211_PLINK_ACTIONS = 3, | |
| +}; | |
| + | |
| +enum nl80211_plink_state { | |
| + NL80211_PLINK_LISTEN = 0, | |
| + NL80211_PLINK_OPN_SNT = 1, | |
| + NL80211_PLINK_OPN_RCVD = 2, | |
| + NL80211_PLINK_CNF_RCVD = 3, | |
| + NL80211_PLINK_ESTAB = 4, | |
| + NL80211_PLINK_HOLDING = 5, | |
| + NL80211_PLINK_BLOCKED = 6, | |
| + NUM_NL80211_PLINK_STATES = 7, | |
| + MAX_NL80211_PLINK_STATES = 6, | |
| +}; | |
| + | |
| +enum nl80211_pmksa_candidate_attr { | |
| + __NL80211_PMKSA_CANDIDATE_INVALID = 0, | |
| + NL80211_PMKSA_CANDIDATE_INDEX = 1, | |
| + NL80211_PMKSA_CANDIDATE_BSSID = 2, | |
| + NL80211_PMKSA_CANDIDATE_PREAUTH = 3, | |
| + NUM_NL80211_PMKSA_CANDIDATE = 4, | |
| + MAX_NL80211_PMKSA_CANDIDATE = 3, | |
| +}; | |
| + | |
| +enum nl80211_preamble { | |
| + NL80211_PREAMBLE_LEGACY = 0, | |
| + NL80211_PREAMBLE_HT = 1, | |
| + NL80211_PREAMBLE_VHT = 2, | |
| + NL80211_PREAMBLE_DMG = 3, | |
| + NL80211_PREAMBLE_HE = 4, | |
| +}; | |
| + | |
| +enum nl80211_protocol_features { | |
| + NL80211_PROTOCOL_FEATURE_SPLIT_WIPHY_DUMP = 1, | |
| +}; | |
| + | |
| +enum nl80211_ps_state { | |
| + NL80211_PS_DISABLED = 0, | |
| + NL80211_PS_ENABLED = 1, | |
| +}; | |
| + | |
| +enum nl80211_radar_event { | |
| + NL80211_RADAR_DETECTED = 0, | |
| + NL80211_RADAR_CAC_FINISHED = 1, | |
| + NL80211_RADAR_CAC_ABORTED = 2, | |
| + NL80211_RADAR_NOP_FINISHED = 3, | |
| + NL80211_RADAR_PRE_CAC_EXPIRED = 4, | |
| + NL80211_RADAR_CAC_STARTED = 5, | |
| +}; | |
| + | |
| +enum nl80211_rate_info { | |
| + __NL80211_RATE_INFO_INVALID = 0, | |
| + NL80211_RATE_INFO_BITRATE = 1, | |
| + NL80211_RATE_INFO_MCS = 2, | |
| + NL80211_RATE_INFO_40_MHZ_WIDTH = 3, | |
| + NL80211_RATE_INFO_SHORT_GI = 4, | |
| + NL80211_RATE_INFO_BITRATE32 = 5, | |
| + NL80211_RATE_INFO_VHT_MCS = 6, | |
| + NL80211_RATE_INFO_VHT_NSS = 7, | |
| + NL80211_RATE_INFO_80_MHZ_WIDTH = 8, | |
| + NL80211_RATE_INFO_80P80_MHZ_WIDTH = 9, | |
| + NL80211_RATE_INFO_160_MHZ_WIDTH = 10, | |
| + NL80211_RATE_INFO_10_MHZ_WIDTH = 11, | |
| + NL80211_RATE_INFO_5_MHZ_WIDTH = 12, | |
| + NL80211_RATE_INFO_HE_MCS = 13, | |
| + NL80211_RATE_INFO_HE_NSS = 14, | |
| + NL80211_RATE_INFO_HE_GI = 15, | |
| + NL80211_RATE_INFO_HE_DCM = 16, | |
| + NL80211_RATE_INFO_HE_RU_ALLOC = 17, | |
| + NL80211_RATE_INFO_320_MHZ_WIDTH = 18, | |
| + NL80211_RATE_INFO_EHT_MCS = 19, | |
| + NL80211_RATE_INFO_EHT_NSS = 20, | |
| + NL80211_RATE_INFO_EHT_GI = 21, | |
| + NL80211_RATE_INFO_EHT_RU_ALLOC = 22, | |
| + NL80211_RATE_INFO_S1G_MCS = 23, | |
| + NL80211_RATE_INFO_S1G_NSS = 24, | |
| + NL80211_RATE_INFO_1_MHZ_WIDTH = 25, | |
| + NL80211_RATE_INFO_2_MHZ_WIDTH = 26, | |
| + NL80211_RATE_INFO_4_MHZ_WIDTH = 27, | |
| + NL80211_RATE_INFO_8_MHZ_WIDTH = 28, | |
| + NL80211_RATE_INFO_16_MHZ_WIDTH = 29, | |
| + __NL80211_RATE_INFO_AFTER_LAST = 30, | |
| + NL80211_RATE_INFO_MAX = 29, | |
| +}; | |
| + | |
| +enum nl80211_reg_initiator { | |
| + NL80211_REGDOM_SET_BY_CORE = 0, | |
| + NL80211_REGDOM_SET_BY_USER = 1, | |
| + NL80211_REGDOM_SET_BY_DRIVER = 2, | |
| + NL80211_REGDOM_SET_BY_COUNTRY_IE = 3, | |
| +}; | |
| + | |
| +enum nl80211_reg_rule_attr { | |
| + __NL80211_REG_RULE_ATTR_INVALID = 0, | |
| + NL80211_ATTR_REG_RULE_FLAGS = 1, | |
| + NL80211_ATTR_FREQ_RANGE_START = 2, | |
| + NL80211_ATTR_FREQ_RANGE_END = 3, | |
| + NL80211_ATTR_FREQ_RANGE_MAX_BW = 4, | |
| + NL80211_ATTR_POWER_RULE_MAX_ANT_GAIN = 5, | |
| + NL80211_ATTR_POWER_RULE_MAX_EIRP = 6, | |
| + NL80211_ATTR_DFS_CAC_TIME = 7, | |
| + NL80211_ATTR_POWER_RULE_PSD = 8, | |
| + __NL80211_REG_RULE_ATTR_AFTER_LAST = 9, | |
| + NL80211_REG_RULE_ATTR_MAX = 8, | |
| +}; | |
| + | |
| +enum nl80211_reg_rule_flags { | |
| + NL80211_RRF_NO_OFDM = 1, | |
| + NL80211_RRF_NO_CCK = 2, | |
| + NL80211_RRF_NO_INDOOR = 4, | |
| + NL80211_RRF_NO_OUTDOOR = 8, | |
| + NL80211_RRF_DFS = 16, | |
| + NL80211_RRF_PTP_ONLY = 32, | |
| + NL80211_RRF_PTMP_ONLY = 64, | |
| + NL80211_RRF_NO_IR = 128, | |
| + __NL80211_RRF_NO_IBSS = 256, | |
| + NL80211_RRF_AUTO_BW = 2048, | |
| + NL80211_RRF_IR_CONCURRENT = 4096, | |
| + NL80211_RRF_NO_HT40MINUS = 8192, | |
| + NL80211_RRF_NO_HT40PLUS = 16384, | |
| + NL80211_RRF_NO_80MHZ = 32768, | |
| + NL80211_RRF_NO_160MHZ = 65536, | |
| + NL80211_RRF_NO_HE = 131072, | |
| + NL80211_RRF_NO_320MHZ = 262144, | |
| + NL80211_RRF_NO_EHT = 524288, | |
| + NL80211_RRF_PSD = 1048576, | |
| + NL80211_RRF_DFS_CONCURRENT = 2097152, | |
| + NL80211_RRF_NO_6GHZ_VLP_CLIENT = 4194304, | |
| + NL80211_RRF_NO_6GHZ_AFC_CLIENT = 8388608, | |
| +}; | |
| + | |
| +enum nl80211_reg_type { | |
| + NL80211_REGDOM_TYPE_COUNTRY = 0, | |
| + NL80211_REGDOM_TYPE_WORLD = 1, | |
| + NL80211_REGDOM_TYPE_CUSTOM_WORLD = 2, | |
| + NL80211_REGDOM_TYPE_INTERSECTION = 3, | |
| +}; | |
| + | |
| +enum nl80211_rekey_data { | |
| + __NL80211_REKEY_DATA_INVALID = 0, | |
| + NL80211_REKEY_DATA_KEK = 1, | |
| + NL80211_REKEY_DATA_KCK = 2, | |
| + NL80211_REKEY_DATA_REPLAY_CTR = 3, | |
| + NL80211_REKEY_DATA_AKM = 4, | |
| + NUM_NL80211_REKEY_DATA = 5, | |
| + MAX_NL80211_REKEY_DATA = 4, | |
| +}; | |
| + | |
| +enum nl80211_sae_pwe_mechanism { | |
| + NL80211_SAE_PWE_UNSPECIFIED = 0, | |
| + NL80211_SAE_PWE_HUNT_AND_PECK = 1, | |
| + NL80211_SAE_PWE_HASH_TO_ELEMENT = 2, | |
| + NL80211_SAE_PWE_BOTH = 3, | |
| +}; | |
| + | |
| +enum nl80211_sar_attrs { | |
| + __NL80211_SAR_ATTR_INVALID = 0, | |
| + NL80211_SAR_ATTR_TYPE = 1, | |
| + NL80211_SAR_ATTR_SPECS = 2, | |
| + __NL80211_SAR_ATTR_LAST = 3, | |
| + NL80211_SAR_ATTR_MAX = 2, | |
| +}; | |
| + | |
| +enum nl80211_sar_specs_attrs { | |
| + __NL80211_SAR_ATTR_SPECS_INVALID = 0, | |
| + NL80211_SAR_ATTR_SPECS_POWER = 1, | |
| + NL80211_SAR_ATTR_SPECS_RANGE_INDEX = 2, | |
| + NL80211_SAR_ATTR_SPECS_START_FREQ = 3, | |
| + NL80211_SAR_ATTR_SPECS_END_FREQ = 4, | |
| + __NL80211_SAR_ATTR_SPECS_LAST = 5, | |
| + NL80211_SAR_ATTR_SPECS_MAX = 4, | |
| +}; | |
| + | |
| +enum nl80211_sar_type { | |
| + NL80211_SAR_TYPE_POWER = 0, | |
| + NUM_NL80211_SAR_TYPE = 1, | |
| +}; | |
| + | |
| +enum nl80211_scan_flags { | |
| + NL80211_SCAN_FLAG_LOW_PRIORITY = 1, | |
| + NL80211_SCAN_FLAG_FLUSH = 2, | |
| + NL80211_SCAN_FLAG_AP = 4, | |
| + NL80211_SCAN_FLAG_RANDOM_ADDR = 8, | |
| + NL80211_SCAN_FLAG_FILS_MAX_CHANNEL_TIME = 16, | |
| + NL80211_SCAN_FLAG_ACCEPT_BCAST_PROBE_RESP = 32, | |
| + NL80211_SCAN_FLAG_OCE_PROBE_REQ_HIGH_TX_RATE = 64, | |
| + NL80211_SCAN_FLAG_OCE_PROBE_REQ_DEFERRAL_SUPPRESSION = 128, | |
| + NL80211_SCAN_FLAG_LOW_SPAN = 256, | |
| + NL80211_SCAN_FLAG_LOW_POWER = 512, | |
| + NL80211_SCAN_FLAG_HIGH_ACCURACY = 1024, | |
| + NL80211_SCAN_FLAG_RANDOM_SN = 2048, | |
| + NL80211_SCAN_FLAG_MIN_PREQ_CONTENT = 4096, | |
| + NL80211_SCAN_FLAG_FREQ_KHZ = 8192, | |
| + NL80211_SCAN_FLAG_COLOCATED_6GHZ = 16384, | |
| +}; | |
| + | |
| +enum nl80211_sched_scan_match_attr { | |
| + __NL80211_SCHED_SCAN_MATCH_ATTR_INVALID = 0, | |
| + NL80211_SCHED_SCAN_MATCH_ATTR_SSID = 1, | |
| + NL80211_SCHED_SCAN_MATCH_ATTR_RSSI = 2, | |
| + NL80211_SCHED_SCAN_MATCH_ATTR_RELATIVE_RSSI = 3, | |
| + NL80211_SCHED_SCAN_MATCH_ATTR_RSSI_ADJUST = 4, | |
| + NL80211_SCHED_SCAN_MATCH_ATTR_BSSID = 5, | |
| + NL80211_SCHED_SCAN_MATCH_PER_BAND_RSSI = 6, | |
| + __NL80211_SCHED_SCAN_MATCH_ATTR_AFTER_LAST = 7, | |
| + NL80211_SCHED_SCAN_MATCH_ATTR_MAX = 6, | |
| +}; | |
| + | |
| +enum nl80211_sched_scan_plan { | |
| + __NL80211_SCHED_SCAN_PLAN_INVALID = 0, | |
| + NL80211_SCHED_SCAN_PLAN_INTERVAL = 1, | |
| + NL80211_SCHED_SCAN_PLAN_ITERATIONS = 2, | |
| + __NL80211_SCHED_SCAN_PLAN_AFTER_LAST = 3, | |
| + NL80211_SCHED_SCAN_PLAN_MAX = 2, | |
| +}; | |
| + | |
| +enum nl80211_smps_mode { | |
| + NL80211_SMPS_OFF = 0, | |
| + NL80211_SMPS_STATIC = 1, | |
| + NL80211_SMPS_DYNAMIC = 2, | |
| + __NL80211_SMPS_AFTER_LAST = 3, | |
| + NL80211_SMPS_MAX = 2, | |
| +}; | |
| + | |
| +enum nl80211_sta_bss_param { | |
| + __NL80211_STA_BSS_PARAM_INVALID = 0, | |
| + NL80211_STA_BSS_PARAM_CTS_PROT = 1, | |
| + NL80211_STA_BSS_PARAM_SHORT_PREAMBLE = 2, | |
| + NL80211_STA_BSS_PARAM_SHORT_SLOT_TIME = 3, | |
| + NL80211_STA_BSS_PARAM_DTIM_PERIOD = 4, | |
| + NL80211_STA_BSS_PARAM_BEACON_INTERVAL = 5, | |
| + __NL80211_STA_BSS_PARAM_AFTER_LAST = 6, | |
| + NL80211_STA_BSS_PARAM_MAX = 5, | |
| +}; | |
| + | |
| +enum nl80211_sta_flags { | |
| + __NL80211_STA_FLAG_INVALID = 0, | |
| + NL80211_STA_FLAG_AUTHORIZED = 1, | |
| + NL80211_STA_FLAG_SHORT_PREAMBLE = 2, | |
| + NL80211_STA_FLAG_WME = 3, | |
| + NL80211_STA_FLAG_MFP = 4, | |
| + NL80211_STA_FLAG_AUTHENTICATED = 5, | |
| + NL80211_STA_FLAG_TDLS_PEER = 6, | |
| + NL80211_STA_FLAG_ASSOCIATED = 7, | |
| + NL80211_STA_FLAG_SPP_AMSDU = 8, | |
| + __NL80211_STA_FLAG_AFTER_LAST = 9, | |
| + NL80211_STA_FLAG_MAX = 8, | |
| +}; | |
| + | |
| +enum nl80211_sta_info { | |
| + __NL80211_STA_INFO_INVALID = 0, | |
| + NL80211_STA_INFO_INACTIVE_TIME = 1, | |
| + NL80211_STA_INFO_RX_BYTES = 2, | |
| + NL80211_STA_INFO_TX_BYTES = 3, | |
| + NL80211_STA_INFO_LLID = 4, | |
| + NL80211_STA_INFO_PLID = 5, | |
| + NL80211_STA_INFO_PLINK_STATE = 6, | |
| + NL80211_STA_INFO_SIGNAL = 7, | |
| + NL80211_STA_INFO_TX_BITRATE = 8, | |
| + NL80211_STA_INFO_RX_PACKETS = 9, | |
| + NL80211_STA_INFO_TX_PACKETS = 10, | |
| + NL80211_STA_INFO_TX_RETRIES = 11, | |
| + NL80211_STA_INFO_TX_FAILED = 12, | |
| + NL80211_STA_INFO_SIGNAL_AVG = 13, | |
| + NL80211_STA_INFO_RX_BITRATE = 14, | |
| + NL80211_STA_INFO_BSS_PARAM = 15, | |
| + NL80211_STA_INFO_CONNECTED_TIME = 16, | |
| + NL80211_STA_INFO_STA_FLAGS = 17, | |
| + NL80211_STA_INFO_BEACON_LOSS = 18, | |
| + NL80211_STA_INFO_T_OFFSET = 19, | |
| + NL80211_STA_INFO_LOCAL_PM = 20, | |
| + NL80211_STA_INFO_PEER_PM = 21, | |
| + NL80211_STA_INFO_NONPEER_PM = 22, | |
| + NL80211_STA_INFO_RX_BYTES64 = 23, | |
| + NL80211_STA_INFO_TX_BYTES64 = 24, | |
| + NL80211_STA_INFO_CHAIN_SIGNAL = 25, | |
| + NL80211_STA_INFO_CHAIN_SIGNAL_AVG = 26, | |
| + NL80211_STA_INFO_EXPECTED_THROUGHPUT = 27, | |
| + NL80211_STA_INFO_RX_DROP_MISC = 28, | |
| + NL80211_STA_INFO_BEACON_RX = 29, | |
| + NL80211_STA_INFO_BEACON_SIGNAL_AVG = 30, | |
| + NL80211_STA_INFO_TID_STATS = 31, | |
| + NL80211_STA_INFO_RX_DURATION = 32, | |
| + NL80211_STA_INFO_PAD = 33, | |
| + NL80211_STA_INFO_ACK_SIGNAL = 34, | |
| + NL80211_STA_INFO_ACK_SIGNAL_AVG = 35, | |
| + NL80211_STA_INFO_RX_MPDUS = 36, | |
| + NL80211_STA_INFO_FCS_ERROR_COUNT = 37, | |
| + NL80211_STA_INFO_CONNECTED_TO_GATE = 38, | |
| + NL80211_STA_INFO_TX_DURATION = 39, | |
| + NL80211_STA_INFO_AIRTIME_WEIGHT = 40, | |
| + NL80211_STA_INFO_AIRTIME_LINK_METRIC = 41, | |
| + NL80211_STA_INFO_ASSOC_AT_BOOTTIME = 42, | |
| + NL80211_STA_INFO_CONNECTED_TO_AS = 43, | |
| + __NL80211_STA_INFO_AFTER_LAST = 44, | |
| + NL80211_STA_INFO_MAX = 43, | |
| +}; | |
| + | |
| +enum nl80211_sta_p2p_ps_status { | |
| + NL80211_P2P_PS_UNSUPPORTED = 0, | |
| + NL80211_P2P_PS_SUPPORTED = 1, | |
| + NUM_NL80211_P2P_PS_STATUS = 2, | |
| +}; | |
| + | |
| +enum nl80211_sta_wme_attr { | |
| + __NL80211_STA_WME_INVALID = 0, | |
| + NL80211_STA_WME_UAPSD_QUEUES = 1, | |
| + NL80211_STA_WME_MAX_SP = 2, | |
| + __NL80211_STA_WME_AFTER_LAST = 3, | |
| + NL80211_STA_WME_MAX = 2, | |
| +}; | |
| + | |
| +enum nl80211_survey_info { | |
| + __NL80211_SURVEY_INFO_INVALID = 0, | |
| + NL80211_SURVEY_INFO_FREQUENCY = 1, | |
| + NL80211_SURVEY_INFO_NOISE = 2, | |
| + NL80211_SURVEY_INFO_IN_USE = 3, | |
| + NL80211_SURVEY_INFO_TIME = 4, | |
| + NL80211_SURVEY_INFO_TIME_BUSY = 5, | |
| + NL80211_SURVEY_INFO_TIME_EXT_BUSY = 6, | |
| + NL80211_SURVEY_INFO_TIME_RX = 7, | |
| + NL80211_SURVEY_INFO_TIME_TX = 8, | |
| + NL80211_SURVEY_INFO_TIME_SCAN = 9, | |
| + NL80211_SURVEY_INFO_PAD = 10, | |
| + NL80211_SURVEY_INFO_TIME_BSS_RX = 11, | |
| + NL80211_SURVEY_INFO_FREQUENCY_OFFSET = 12, | |
| + __NL80211_SURVEY_INFO_AFTER_LAST = 13, | |
| + NL80211_SURVEY_INFO_MAX = 12, | |
| +}; | |
| + | |
| +enum nl80211_tdls_operation { | |
| + NL80211_TDLS_DISCOVERY_REQ = 0, | |
| + NL80211_TDLS_SETUP = 1, | |
| + NL80211_TDLS_TEARDOWN = 2, | |
| + NL80211_TDLS_ENABLE_LINK = 3, | |
| + NL80211_TDLS_DISABLE_LINK = 4, | |
| +}; | |
| + | |
| +enum nl80211_tid_config { | |
| + NL80211_TID_CONFIG_ENABLE = 0, | |
| + NL80211_TID_CONFIG_DISABLE = 1, | |
| +}; | |
| + | |
| +enum nl80211_tid_config_attr { | |
| + __NL80211_TID_CONFIG_ATTR_INVALID = 0, | |
| + NL80211_TID_CONFIG_ATTR_PAD = 1, | |
| + NL80211_TID_CONFIG_ATTR_VIF_SUPP = 2, | |
| + NL80211_TID_CONFIG_ATTR_PEER_SUPP = 3, | |
| + NL80211_TID_CONFIG_ATTR_OVERRIDE = 4, | |
| + NL80211_TID_CONFIG_ATTR_TIDS = 5, | |
| + NL80211_TID_CONFIG_ATTR_NOACK = 6, | |
| + NL80211_TID_CONFIG_ATTR_RETRY_SHORT = 7, | |
| + NL80211_TID_CONFIG_ATTR_RETRY_LONG = 8, | |
| + NL80211_TID_CONFIG_ATTR_AMPDU_CTRL = 9, | |
| + NL80211_TID_CONFIG_ATTR_RTSCTS_CTRL = 10, | |
| + NL80211_TID_CONFIG_ATTR_AMSDU_CTRL = 11, | |
| + NL80211_TID_CONFIG_ATTR_TX_RATE_TYPE = 12, | |
| + NL80211_TID_CONFIG_ATTR_TX_RATE = 13, | |
| + __NL80211_TID_CONFIG_ATTR_AFTER_LAST = 14, | |
| + NL80211_TID_CONFIG_ATTR_MAX = 13, | |
| +}; | |
| + | |
| +enum nl80211_tid_stats { | |
| + __NL80211_TID_STATS_INVALID = 0, | |
| + NL80211_TID_STATS_RX_MSDU = 1, | |
| + NL80211_TID_STATS_TX_MSDU = 2, | |
| + NL80211_TID_STATS_TX_MSDU_RETRIES = 3, | |
| + NL80211_TID_STATS_TX_MSDU_FAILED = 4, | |
| + NL80211_TID_STATS_PAD = 5, | |
| + NL80211_TID_STATS_TXQ_STATS = 6, | |
| + NUM_NL80211_TID_STATS = 7, | |
| + NL80211_TID_STATS_MAX = 6, | |
| +}; | |
| + | |
| +enum nl80211_timeout_reason { | |
| + NL80211_TIMEOUT_UNSPECIFIED = 0, | |
| + NL80211_TIMEOUT_SCAN = 1, | |
| + NL80211_TIMEOUT_AUTH = 2, | |
| + NL80211_TIMEOUT_ASSOC = 3, | |
| +}; | |
| + | |
| +enum nl80211_tx_power_setting { | |
| + NL80211_TX_POWER_AUTOMATIC = 0, | |
| + NL80211_TX_POWER_LIMITED = 1, | |
| + NL80211_TX_POWER_FIXED = 2, | |
| +}; | |
| + | |
| +enum nl80211_tx_rate_attributes { | |
| + __NL80211_TXRATE_INVALID = 0, | |
| + NL80211_TXRATE_LEGACY = 1, | |
| + NL80211_TXRATE_HT = 2, | |
| + NL80211_TXRATE_VHT = 3, | |
| + NL80211_TXRATE_GI = 4, | |
| + NL80211_TXRATE_HE = 5, | |
| + NL80211_TXRATE_HE_GI = 6, | |
| + NL80211_TXRATE_HE_LTF = 7, | |
| + __NL80211_TXRATE_AFTER_LAST = 8, | |
| + NL80211_TXRATE_MAX = 7, | |
| +}; | |
| + | |
| +enum nl80211_tx_rate_setting { | |
| + NL80211_TX_RATE_AUTOMATIC = 0, | |
| + NL80211_TX_RATE_LIMITED = 1, | |
| + NL80211_TX_RATE_FIXED = 2, | |
| +}; | |
| + | |
| +enum nl80211_txq_attr { | |
| + __NL80211_TXQ_ATTR_INVALID = 0, | |
| + NL80211_TXQ_ATTR_AC = 1, | |
| + NL80211_TXQ_ATTR_TXOP = 2, | |
| + NL80211_TXQ_ATTR_CWMIN = 3, | |
| + NL80211_TXQ_ATTR_CWMAX = 4, | |
| + NL80211_TXQ_ATTR_AIFS = 5, | |
| + __NL80211_TXQ_ATTR_AFTER_LAST = 6, | |
| + NL80211_TXQ_ATTR_MAX = 5, | |
| +}; | |
| + | |
| +enum nl80211_txq_stats { | |
| + __NL80211_TXQ_STATS_INVALID = 0, | |
| + NL80211_TXQ_STATS_BACKLOG_BYTES = 1, | |
| + NL80211_TXQ_STATS_BACKLOG_PACKETS = 2, | |
| + NL80211_TXQ_STATS_FLOWS = 3, | |
| + NL80211_TXQ_STATS_DROPS = 4, | |
| + NL80211_TXQ_STATS_ECN_MARKS = 5, | |
| + NL80211_TXQ_STATS_OVERLIMIT = 6, | |
| + NL80211_TXQ_STATS_OVERMEMORY = 7, | |
| + NL80211_TXQ_STATS_COLLISIONS = 8, | |
| + NL80211_TXQ_STATS_TX_BYTES = 9, | |
| + NL80211_TXQ_STATS_TX_PACKETS = 10, | |
| + NL80211_TXQ_STATS_MAX_FLOWS = 11, | |
| + NUM_NL80211_TXQ_STATS = 12, | |
| + NL80211_TXQ_STATS_MAX = 11, | |
| +}; | |
| + | |
| +enum nl80211_txrate_gi { | |
| + NL80211_TXRATE_DEFAULT_GI = 0, | |
| + NL80211_TXRATE_FORCE_SGI = 1, | |
| + NL80211_TXRATE_FORCE_LGI = 2, | |
| +}; | |
| + | |
| +enum nl80211_unsol_bcast_probe_resp_attributes { | |
| + __NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_INVALID = 0, | |
| + NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_INT = 1, | |
| + NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_TMPL = 2, | |
| + __NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_LAST = 3, | |
| + NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_MAX = 2, | |
| +}; | |
| + | |
| +enum nl80211_user_reg_hint_type { | |
| + NL80211_USER_REG_HINT_USER = 0, | |
| + NL80211_USER_REG_HINT_CELL_BASE = 1, | |
| + NL80211_USER_REG_HINT_INDOOR = 2, | |
| +}; | |
| + | |
| +enum nl80211_wmm_rule { | |
| + __NL80211_WMMR_INVALID = 0, | |
| + NL80211_WMMR_CW_MIN = 1, | |
| + NL80211_WMMR_CW_MAX = 2, | |
| + NL80211_WMMR_AIFSN = 3, | |
| + NL80211_WMMR_TXOP = 4, | |
| + __NL80211_WMMR_LAST = 5, | |
| + NL80211_WMMR_MAX = 4, | |
| +}; | |
| + | |
| +enum nl80211_wowlan_tcp_attrs { | |
| + __NL80211_WOWLAN_TCP_INVALID = 0, | |
| + NL80211_WOWLAN_TCP_SRC_IPV4 = 1, | |
| + NL80211_WOWLAN_TCP_DST_IPV4 = 2, | |
| + NL80211_WOWLAN_TCP_DST_MAC = 3, | |
| + NL80211_WOWLAN_TCP_SRC_PORT = 4, | |
| + NL80211_WOWLAN_TCP_DST_PORT = 5, | |
| + NL80211_WOWLAN_TCP_DATA_PAYLOAD = 6, | |
| + NL80211_WOWLAN_TCP_DATA_PAYLOAD_SEQ = 7, | |
| + NL80211_WOWLAN_TCP_DATA_PAYLOAD_TOKEN = 8, | |
| + NL80211_WOWLAN_TCP_DATA_INTERVAL = 9, | |
| + NL80211_WOWLAN_TCP_WAKE_PAYLOAD = 10, | |
| + NL80211_WOWLAN_TCP_WAKE_MASK = 11, | |
| + NUM_NL80211_WOWLAN_TCP = 12, | |
| + MAX_NL80211_WOWLAN_TCP = 11, | |
| +}; | |
| + | |
| +enum nl80211_wowlan_triggers { | |
| + __NL80211_WOWLAN_TRIG_INVALID = 0, | |
| + NL80211_WOWLAN_TRIG_ANY = 1, | |
| + NL80211_WOWLAN_TRIG_DISCONNECT = 2, | |
| + NL80211_WOWLAN_TRIG_MAGIC_PKT = 3, | |
| + NL80211_WOWLAN_TRIG_PKT_PATTERN = 4, | |
| + NL80211_WOWLAN_TRIG_GTK_REKEY_SUPPORTED = 5, | |
| + NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE = 6, | |
| + NL80211_WOWLAN_TRIG_EAP_IDENT_REQUEST = 7, | |
| + NL80211_WOWLAN_TRIG_4WAY_HANDSHAKE = 8, | |
| + NL80211_WOWLAN_TRIG_RFKILL_RELEASE = 9, | |
| + NL80211_WOWLAN_TRIG_WAKEUP_PKT_80211 = 10, | |
| + NL80211_WOWLAN_TRIG_WAKEUP_PKT_80211_LEN = 11, | |
| + NL80211_WOWLAN_TRIG_WAKEUP_PKT_8023 = 12, | |
| + NL80211_WOWLAN_TRIG_WAKEUP_PKT_8023_LEN = 13, | |
| + NL80211_WOWLAN_TRIG_TCP_CONNECTION = 14, | |
| + NL80211_WOWLAN_TRIG_WAKEUP_TCP_MATCH = 15, | |
| + NL80211_WOWLAN_TRIG_WAKEUP_TCP_CONNLOST = 16, | |
| + NL80211_WOWLAN_TRIG_WAKEUP_TCP_NOMORETOKENS = 17, | |
| + NL80211_WOWLAN_TRIG_NET_DETECT = 18, | |
| + NL80211_WOWLAN_TRIG_NET_DETECT_RESULTS = 19, | |
| + NL80211_WOWLAN_TRIG_UNPROTECTED_DEAUTH_DISASSOC = 20, | |
| + NUM_NL80211_WOWLAN_TRIG = 21, | |
| + MAX_NL80211_WOWLAN_TRIG = 20, | |
| +}; | |
| + | |
| +enum nl80211_wpa_versions { | |
| + NL80211_WPA_VERSION_1 = 1, | |
| + NL80211_WPA_VERSION_2 = 2, | |
| + NL80211_WPA_VERSION_3 = 4, | |
| }; | |
| enum nla_policy_validation { | |
| @@ -20778,10 +26618,14 @@ | |
| NR_KERNEL_STACK_KB = 37, | |
| NR_PAGETABLE = 38, | |
| NR_SECONDARY_PAGETABLE = 39, | |
| - NR_SWAPCACHE = 40, | |
| - PGPROMOTE_SUCCESS = 41, | |
| - PGPROMOTE_CANDIDATE = 42, | |
| - NR_VM_NODE_STAT_ITEMS = 43, | |
| + NR_IOMMU_PAGES = 40, | |
| + NR_SWAPCACHE = 41, | |
| + PGPROMOTE_SUCCESS = 42, | |
| + PGPROMOTE_CANDIDATE = 43, | |
| + PGDEMOTE_KSWAPD = 44, | |
| + PGDEMOTE_DIRECT = 45, | |
| + PGDEMOTE_KHUGEPAGED = 46, | |
| + NR_VM_NODE_STAT_ITEMS = 47, | |
| }; | |
| enum node_states { | |
| @@ -20795,28 +26639,39 @@ | |
| NR_NODE_STATES = 6, | |
| }; | |
| -enum noise_handshake_state { | |
| - HANDSHAKE_ZEROED = 0, | |
| - HANDSHAKE_CREATED_INITIATION = 1, | |
| - HANDSHAKE_CONSUMED_INITIATION = 2, | |
| - HANDSHAKE_CREATED_RESPONSE = 3, | |
| - HANDSHAKE_CONSUMED_RESPONSE = 4, | |
| -}; | |
| - | |
| -enum noise_lengths { | |
| - NOISE_PUBLIC_KEY_LEN = 32, | |
| - NOISE_SYMMETRIC_KEY_LEN = 32, | |
| - NOISE_TIMESTAMP_LEN = 12, | |
| - NOISE_AUTHTAG_LEN = 16, | |
| - NOISE_HASH_LEN = 32, | |
| -}; | |
| - | |
| enum notify_state { | |
| SECCOMP_NOTIFY_INIT = 0, | |
| SECCOMP_NOTIFY_SENT = 1, | |
| SECCOMP_NOTIFY_REPLIED = 2, | |
| }; | |
| +enum nsim_dev_hwstats_do { | |
| + NSIM_DEV_HWSTATS_DO_DISABLE = 0, | |
| + NSIM_DEV_HWSTATS_DO_ENABLE = 1, | |
| + NSIM_DEV_HWSTATS_DO_FAIL = 2, | |
| +}; | |
| + | |
| +enum nsim_dev_port_type { | |
| + NSIM_DEV_PORT_TYPE_PF = 0, | |
| + NSIM_DEV_PORT_TYPE_VF = 1, | |
| +}; | |
| + | |
| +enum nsim_devlink_param_id { | |
| + NSIM_DEVLINK_PARAM_ID_BASE = 16, | |
| + NSIM_DEVLINK_PARAM_ID_TEST1 = 17, | |
| +}; | |
| + | |
| +enum nsim_resource_id { | |
| + NSIM_RESOURCE_NONE = 0, | |
| + NSIM_RESOURCE_IPV4 = 1, | |
| + NSIM_RESOURCE_IPV4_FIB = 2, | |
| + NSIM_RESOURCE_IPV4_FIB_RULES = 3, | |
| + NSIM_RESOURCE_IPV6 = 4, | |
| + NSIM_RESOURCE_IPV6_FIB = 5, | |
| + NSIM_RESOURCE_IPV6_FIB_RULES = 6, | |
| + NSIM_RESOURCE_NEXTHOPS = 7, | |
| +}; | |
| + | |
| enum numa_faults_stats { | |
| NUMA_MEM = 0, | |
| NUMA_CPU = 1, | |
| @@ -20846,154 +26701,34 @@ | |
| node_overloaded = 2, | |
| }; | |
| -enum nvdimm_fwa_capability { | |
| - NVDIMM_FWA_CAP_INVALID = 0, | |
| - NVDIMM_FWA_CAP_NONE = 1, | |
| - NVDIMM_FWA_CAP_QUIESCE = 2, | |
| - NVDIMM_FWA_CAP_LIVE = 3, | |
| -}; | |
| - | |
| -enum nvdimm_fwa_state { | |
| - NVDIMM_FWA_INVALID = 0, | |
| - NVDIMM_FWA_IDLE = 1, | |
| - NVDIMM_FWA_ARMED = 2, | |
| - NVDIMM_FWA_BUSY = 3, | |
| - NVDIMM_FWA_ARM_OVERFLOW = 4, | |
| -}; | |
| - | |
| -enum nvme_admin_opcode { | |
| - nvme_admin_delete_sq = 0, | |
| - nvme_admin_create_sq = 1, | |
| - nvme_admin_get_log_page = 2, | |
| - nvme_admin_delete_cq = 4, | |
| - nvme_admin_create_cq = 5, | |
| - nvme_admin_identify = 6, | |
| - nvme_admin_abort_cmd = 8, | |
| - nvme_admin_set_features = 9, | |
| - nvme_admin_get_features = 10, | |
| - nvme_admin_async_event = 12, | |
| - nvme_admin_ns_mgmt = 13, | |
| - nvme_admin_activate_fw = 16, | |
| - nvme_admin_download_fw = 17, | |
| - nvme_admin_dev_self_test = 20, | |
| - nvme_admin_ns_attach = 21, | |
| - nvme_admin_keep_alive = 24, | |
| - nvme_admin_directive_send = 25, | |
| - nvme_admin_directive_recv = 26, | |
| - nvme_admin_virtual_mgmt = 28, | |
| - nvme_admin_nvme_mi_send = 29, | |
| - nvme_admin_nvme_mi_recv = 30, | |
| - nvme_admin_dbbuf = 124, | |
| - nvme_admin_format_nvm = 128, | |
| - nvme_admin_security_send = 129, | |
| - nvme_admin_security_recv = 130, | |
| - nvme_admin_sanitize_nvm = 132, | |
| - nvme_admin_get_lba_status = 134, | |
| - nvme_admin_vendor_start = 192, | |
| -}; | |
| - | |
| -enum nvme_ctrl_attr { | |
| - NVME_CTRL_ATTR_HID_128_BIT = 1, | |
| - NVME_CTRL_ATTR_TBKAS = 64, | |
| - NVME_CTRL_ATTR_ELBAS = 32768, | |
| -}; | |
| - | |
| -enum nvme_ctrl_flags { | |
| - NVME_CTRL_FAILFAST_EXPIRED = 0, | |
| - NVME_CTRL_ADMIN_Q_STOPPED = 1, | |
| - NVME_CTRL_STARTED_ONCE = 2, | |
| - NVME_CTRL_STOPPED = 3, | |
| -}; | |
| - | |
| -enum nvme_ctrl_state { | |
| - NVME_CTRL_NEW = 0, | |
| - NVME_CTRL_LIVE = 1, | |
| - NVME_CTRL_RESETTING = 2, | |
| - NVME_CTRL_CONNECTING = 3, | |
| - NVME_CTRL_DELETING = 4, | |
| - NVME_CTRL_DELETING_NOIO = 5, | |
| - NVME_CTRL_DEAD = 6, | |
| -}; | |
| - | |
| -enum nvme_ctrl_type { | |
| - NVME_CTRL_IO = 1, | |
| - NVME_CTRL_DISC = 2, | |
| - NVME_CTRL_ADMIN = 3, | |
| -}; | |
| - | |
| -enum nvme_dctype { | |
| - NVME_DCTYPE_NOT_REPORTED = 0, | |
| - NVME_DCTYPE_DDC = 1, | |
| - NVME_DCTYPE_CDC = 2, | |
| -}; | |
| - | |
| -enum nvme_disposition { | |
| - COMPLETE = 0, | |
| - RETRY = 1, | |
| - FAILOVER = 2, | |
| - AUTHENTICATE = 3, | |
| -}; | |
| - | |
| -enum nvme_ns_features { | |
| - NVME_NS_EXT_LBAS = 1, | |
| - NVME_NS_METADATA_SUPPORTED = 2, | |
| - NVME_NS_DEAC = 3, | |
| -}; | |
| - | |
| -enum nvme_opcode { | |
| - nvme_cmd_flush = 0, | |
| - nvme_cmd_write = 1, | |
| - nvme_cmd_read = 2, | |
| - nvme_cmd_write_uncor = 4, | |
| - nvme_cmd_compare = 5, | |
| - nvme_cmd_write_zeroes = 8, | |
| - nvme_cmd_dsm = 9, | |
| - nvme_cmd_verify = 12, | |
| - nvme_cmd_resv_register = 13, | |
| - nvme_cmd_resv_report = 14, | |
| - nvme_cmd_resv_acquire = 17, | |
| - nvme_cmd_resv_release = 21, | |
| - nvme_cmd_zone_mgmt_send = 121, | |
| - nvme_cmd_zone_mgmt_recv = 122, | |
| - nvme_cmd_zone_append = 125, | |
| - nvme_cmd_vendor_start = 128, | |
| -}; | |
| - | |
| -enum nvme_quirks { | |
| - NVME_QUIRK_STRIPE_SIZE = 1, | |
| - NVME_QUIRK_IDENTIFY_CNS = 2, | |
| - NVME_QUIRK_DEALLOCATE_ZEROES = 4, | |
| - NVME_QUIRK_DELAY_BEFORE_CHK_RDY = 8, | |
| - NVME_QUIRK_NO_APST = 16, | |
| - NVME_QUIRK_NO_DEEPEST_PS = 32, | |
| - NVME_QUIRK_MEDIUM_PRIO_SQ = 128, | |
| - NVME_QUIRK_IGNORE_DEV_SUBNQN = 256, | |
| - NVME_QUIRK_DISABLE_WRITE_ZEROES = 512, | |
| - NVME_QUIRK_SIMPLE_SUSPEND = 1024, | |
| - NVME_QUIRK_SINGLE_VECTOR = 2048, | |
| - NVME_QUIRK_128_BYTES_SQES = 4096, | |
| - NVME_QUIRK_SHARED_TAGS = 8192, | |
| - NVME_QUIRK_NO_TEMP_THRESH_CHANGE = 16384, | |
| - NVME_QUIRK_NO_NS_DESC_LIST = 32768, | |
| - NVME_QUIRK_DMA_ADDRESS_BITS_48 = 65536, | |
| - NVME_QUIRK_SKIP_CID_GEN = 131072, | |
| - NVME_QUIRK_BOGUS_NID = 262144, | |
| - NVME_QUIRK_NO_SECONDARY_TEMP_THRESH = 524288, | |
| +enum numa_vmaskip_reason { | |
| + NUMAB_SKIP_UNSUITABLE = 0, | |
| + NUMAB_SKIP_SHARED_RO = 1, | |
| + NUMAB_SKIP_INACCESSIBLE = 2, | |
| + NUMAB_SKIP_SCAN_DELAY = 3, | |
| + NUMAB_SKIP_PID_INACTIVE = 4, | |
| + NUMAB_SKIP_IGNORE_PID = 5, | |
| + NUMAB_SKIP_SEQ_COMPLETED = 6, | |
| }; | |
| -enum nvme_subsys_type { | |
| - NVME_NQN_DISC = 1, | |
| - NVME_NQN_NVME = 2, | |
| - NVME_NQN_CURR = 3, | |
| +enum nv_adma_regbits { | |
| + CMDEND = 32768, | |
| + WNB = 16384, | |
| + IGN = 8192, | |
| + CS1n = 4096, | |
| + DA2 = 1024, | |
| + DA1 = 512, | |
| + DA0 = 256, | |
| }; | |
| -enum nvme_zone_mgmt_action { | |
| - NVME_ZONE_CLOSE = 1, | |
| - NVME_ZONE_FINISH = 2, | |
| - NVME_ZONE_OPEN = 3, | |
| - NVME_ZONE_RESET = 4, | |
| - NVME_ZONE_OFFLINE = 5, | |
| - NVME_ZONE_SET_DESC_EXT = 16, | |
| +enum nv_host_type { | |
| + GENERIC = 0, | |
| + NFORCE2 = 1, | |
| + NFORCE3 = 1, | |
| + CK804 = 2, | |
| + ADMA = 3, | |
| + MCP5x = 4, | |
| + SWNCQ = 5, | |
| }; | |
| enum nvmem_type { | |
| @@ -21004,16 +26739,20 @@ | |
| NVMEM_TYPE_FRAM = 4, | |
| }; | |
| -enum nvmf_capsule_command { | |
| - nvme_fabrics_type_property_set = 0, | |
| - nvme_fabrics_type_connect = 1, | |
| - nvme_fabrics_type_property_get = 4, | |
| - nvme_fabrics_type_auth_send = 5, | |
| - nvme_fabrics_type_auth_receive = 6, | |
| +enum nvmx_vmentry_status { | |
| + NVMX_VMENTRY_SUCCESS = 0, | |
| + NVMX_VMENTRY_VMFAIL = 1, | |
| + NVMX_VMENTRY_VMEXIT = 2, | |
| + NVMX_VMENTRY_KVM_INTERNAL_ERROR = 3, | |
| }; | |
| -enum nvmf_fabrics_opcode { | |
| - nvme_fabrics_command = 127, | |
| +enum objext_flags { | |
| + OBJEXTS_ALLOC_FAIL = 4, | |
| + __NR_OBJEXTS_FLAGS = 8, | |
| +}; | |
| + | |
| +enum ocb_deferred_task_flags { | |
| + OCB_WORK_HOUSEKEEPING = 0, | |
| }; | |
| enum offload_act_command { | |
| @@ -21029,54 +26768,174 @@ | |
| CONSTRAINT_MEMCG = 3, | |
| }; | |
| -enum ovl_copyop { | |
| - OVL_COPY = 0, | |
| - OVL_CLONE = 1, | |
| - OVL_DEDUPE = 2, | |
| +enum owner_state { | |
| + OWNER_NULL = 1, | |
| + OWNER_WRITER = 2, | |
| + OWNER_READER = 4, | |
| + OWNER_NONSPINNABLE = 8, | |
| }; | |
| -enum ovl_entry_flag { | |
| - OVL_E_UPPER_ALIAS = 0, | |
| - OVL_E_OPAQUE = 1, | |
| - OVL_E_CONNECTED = 2, | |
| +enum p9_cache_bits { | |
| + CACHE_NONE = 0, | |
| + CACHE_FILE = 1, | |
| + CACHE_META = 2, | |
| + CACHE_WRITEBACK = 4, | |
| + CACHE_LOOSE = 8, | |
| + CACHE_FSCACHE = 128, | |
| }; | |
| -enum ovl_inode_flag { | |
| - OVL_IMPURE = 0, | |
| - OVL_WHITEOUTS = 1, | |
| - OVL_INDEX = 2, | |
| - OVL_UPPERDATA = 3, | |
| - OVL_CONST_INO = 4, | |
| +enum p9_cache_shortcuts { | |
| + CACHE_SC_NONE = 0, | |
| + CACHE_SC_READAHEAD = 1, | |
| + CACHE_SC_MMAP = 5, | |
| + CACHE_SC_LOOSE = 15, | |
| + CACHE_SC_FSCACHE = 143, | |
| }; | |
| -enum ovl_path_type { | |
| - __OVL_PATH_UPPER = 1, | |
| - __OVL_PATH_MERGE = 2, | |
| - __OVL_PATH_ORIGIN = 4, | |
| +enum p9_fid_reftype { | |
| + P9_FID_REF_CREATE = 0, | |
| + P9_FID_REF_GET = 1, | |
| + P9_FID_REF_PUT = 2, | |
| + P9_FID_REF_DESTROY = 3, | |
| +} __attribute__((mode(byte))); | |
| + | |
| +enum p9_msg_t { | |
| + P9_TLERROR = 6, | |
| + P9_RLERROR = 7, | |
| + P9_TSTATFS = 8, | |
| + P9_RSTATFS = 9, | |
| + P9_TLOPEN = 12, | |
| + P9_RLOPEN = 13, | |
| + P9_TLCREATE = 14, | |
| + P9_RLCREATE = 15, | |
| + P9_TSYMLINK = 16, | |
| + P9_RSYMLINK = 17, | |
| + P9_TMKNOD = 18, | |
| + P9_RMKNOD = 19, | |
| + P9_TRENAME = 20, | |
| + P9_RRENAME = 21, | |
| + P9_TREADLINK = 22, | |
| + P9_RREADLINK = 23, | |
| + P9_TGETATTR = 24, | |
| + P9_RGETATTR = 25, | |
| + P9_TSETATTR = 26, | |
| + P9_RSETATTR = 27, | |
| + P9_TXATTRWALK = 30, | |
| + P9_RXATTRWALK = 31, | |
| + P9_TXATTRCREATE = 32, | |
| + P9_RXATTRCREATE = 33, | |
| + P9_TREADDIR = 40, | |
| + P9_RREADDIR = 41, | |
| + P9_TFSYNC = 50, | |
| + P9_RFSYNC = 51, | |
| + P9_TLOCK = 52, | |
| + P9_RLOCK = 53, | |
| + P9_TGETLOCK = 54, | |
| + P9_RGETLOCK = 55, | |
| + P9_TLINK = 70, | |
| + P9_RLINK = 71, | |
| + P9_TMKDIR = 72, | |
| + P9_RMKDIR = 73, | |
| + P9_TRENAMEAT = 74, | |
| + P9_RRENAMEAT = 75, | |
| + P9_TUNLINKAT = 76, | |
| + P9_RUNLINKAT = 77, | |
| + P9_TVERSION = 100, | |
| + P9_RVERSION = 101, | |
| + P9_TAUTH = 102, | |
| + P9_RAUTH = 103, | |
| + P9_TATTACH = 104, | |
| + P9_RATTACH = 105, | |
| + P9_TERROR = 106, | |
| + P9_RERROR = 107, | |
| + P9_TFLUSH = 108, | |
| + P9_RFLUSH = 109, | |
| + P9_TWALK = 110, | |
| + P9_RWALK = 111, | |
| + P9_TOPEN = 112, | |
| + P9_ROPEN = 113, | |
| + P9_TCREATE = 114, | |
| + P9_RCREATE = 115, | |
| + P9_TREAD = 116, | |
| + P9_RREAD = 117, | |
| + P9_TWRITE = 118, | |
| + P9_RWRITE = 119, | |
| + P9_TCLUNK = 120, | |
| + P9_RCLUNK = 121, | |
| + P9_TREMOVE = 122, | |
| + P9_RREMOVE = 123, | |
| + P9_TSTAT = 124, | |
| + P9_RSTAT = 125, | |
| + P9_TWSTAT = 126, | |
| + P9_RWSTAT = 127, | |
| }; | |
| -enum ovl_xattr { | |
| - OVL_XATTR_OPAQUE = 0, | |
| - OVL_XATTR_REDIRECT = 1, | |
| - OVL_XATTR_ORIGIN = 2, | |
| - OVL_XATTR_IMPURE = 3, | |
| - OVL_XATTR_NLINK = 4, | |
| - OVL_XATTR_UPPER = 5, | |
| - OVL_XATTR_METACOPY = 6, | |
| - OVL_XATTR_PROTATTR = 7, | |
| +enum p9_open_mode_t { | |
| + P9_OREAD = 0, | |
| + P9_OWRITE = 1, | |
| + P9_ORDWR = 2, | |
| + P9_OEXEC = 3, | |
| + P9_OTRUNC = 16, | |
| + P9_OREXEC = 32, | |
| + P9_ORCLOSE = 64, | |
| + P9_OAPPEND = 128, | |
| + P9_OEXCL = 4096, | |
| + P9L_MODE_MASK = 8191, | |
| + P9L_DIRECT = 8192, | |
| + P9L_NOWRITECACHE = 16384, | |
| + P9L_LOOSE = 32768, | |
| }; | |
| -enum owner_state { | |
| - OWNER_NULL = 1, | |
| - OWNER_WRITER = 2, | |
| - OWNER_READER = 4, | |
| - OWNER_NONSPINNABLE = 8, | |
| +enum p9_perm_t { | |
| + P9_DMDIR = 2147483648, | |
| + P9_DMAPPEND = 1073741824, | |
| + P9_DMEXCL = 536870912, | |
| + P9_DMMOUNT = 268435456, | |
| + P9_DMAUTH = 134217728, | |
| + P9_DMTMP = 67108864, | |
| + P9_DMSYMLINK = 33554432, | |
| + P9_DMLINK = 16777216, | |
| + P9_DMDEVICE = 8388608, | |
| + P9_DMNAMEDPIPE = 2097152, | |
| + P9_DMSOCKET = 1048576, | |
| + P9_DMSETUID = 524288, | |
| + P9_DMSETGID = 262144, | |
| + P9_DMSETVTX = 65536, | |
| }; | |
| -enum packet_merge { | |
| - MLX5E_PACKET_MERGE_NONE = 0, | |
| - MLX5E_PACKET_MERGE_LRO = 1, | |
| - MLX5E_PACKET_MERGE_SHAMPO = 2, | |
| +enum p9_proto_versions { | |
| + p9_proto_legacy = 0, | |
| + p9_proto_2000u = 1, | |
| + p9_proto_2000L = 2, | |
| +}; | |
| + | |
| +enum p9_req_status_t { | |
| + REQ_STATUS_ALLOC = 0, | |
| + REQ_STATUS_UNSENT = 1, | |
| + REQ_STATUS_SENT = 2, | |
| + REQ_STATUS_RCVD = 3, | |
| + REQ_STATUS_FLSHD = 4, | |
| + REQ_STATUS_ERROR = 5, | |
| +}; | |
| + | |
| +enum p9_session_flags { | |
| + V9FS_PROTO_2000U = 1, | |
| + V9FS_PROTO_2000L = 2, | |
| + V9FS_ACCESS_SINGLE = 4, | |
| + V9FS_ACCESS_USER = 8, | |
| + V9FS_ACCESS_CLIENT = 16, | |
| + V9FS_POSIX_ACL = 32, | |
| + V9FS_NO_XATTR = 64, | |
| + V9FS_IGNORE_QV = 128, | |
| + V9FS_DIRECT_IO = 256, | |
| + V9FS_SYNC = 512, | |
| +}; | |
| + | |
| +enum p9_trans_status { | |
| + Connected = 0, | |
| + BeginDisconnect = 1, | |
| + Disconnected = 2, | |
| + Hung = 3, | |
| }; | |
| enum packet_sock_flags { | |
| @@ -21089,12 +26948,6 @@ | |
| PACKET_SOCK_QDISC_BYPASS = 6, | |
| }; | |
| -enum packet_state { | |
| - PACKET_STATE_UNCRYPTED = 0, | |
| - PACKET_STATE_CRYPTED = 1, | |
| - PACKET_STATE_DEAD = 2, | |
| -}; | |
| - | |
| enum page_cache_mode { | |
| _PAGE_CACHE_MODE_WB = 0, | |
| _PAGE_CACHE_MODE_WC = 1, | |
| @@ -21105,24 +26958,28 @@ | |
| _PAGE_CACHE_MODE_NUM = 8, | |
| }; | |
| -enum page_entry_size { | |
| - PE_SIZE_PTE = 0, | |
| - PE_SIZE_PMD = 1, | |
| - PE_SIZE_PUD = 2, | |
| -}; | |
| - | |
| enum page_memcg_data_flags { | |
| - MEMCG_DATA_OBJCGS = 1, | |
| + MEMCG_DATA_OBJEXTS = 1, | |
| MEMCG_DATA_KMEM = 2, | |
| __NR_MEMCG_DATA_FLAGS = 4, | |
| }; | |
| +enum page_size_enum { | |
| + __PAGE_SIZE = 4096, | |
| +}; | |
| + | |
| enum page_walk_action { | |
| ACTION_SUBTREE = 0, | |
| ACTION_CONTINUE = 1, | |
| ACTION_AGAIN = 2, | |
| }; | |
| +enum page_walk_lock { | |
| + PGWALK_RDLOCK = 0, | |
| + PGWALK_WRLOCK = 1, | |
| + PGWALK_WRLOCK_VERIFY = 2, | |
| +}; | |
| + | |
| enum pageblock_bits { | |
| PB_migrate = 0, | |
| PB_migrate_end = 2, | |
| @@ -21142,34 +26999,31 @@ | |
| PG_active = 8, | |
| PG_workingset = 9, | |
| PG_error = 10, | |
| - PG_slab = 11, | |
| - PG_owner_priv_1 = 12, | |
| - PG_arch_1 = 13, | |
| - PG_reserved = 14, | |
| - PG_private = 15, | |
| - PG_private_2 = 16, | |
| - PG_mappedtodisk = 17, | |
| - PG_reclaim = 18, | |
| - PG_swapbacked = 19, | |
| - PG_unevictable = 20, | |
| - PG_mlocked = 21, | |
| - PG_uncached = 22, | |
| - PG_hwpoison = 23, | |
| - __NR_PAGEFLAGS = 24, | |
| - PG_readahead = 18, | |
| - PG_anon_exclusive = 17, | |
| - PG_checked = 12, | |
| - PG_swapcache = 12, | |
| - PG_fscache = 16, | |
| - PG_pinned = 12, | |
| + PG_owner_priv_1 = 11, | |
| + PG_arch_1 = 12, | |
| + PG_reserved = 13, | |
| + PG_private = 14, | |
| + PG_private_2 = 15, | |
| + PG_mappedtodisk = 16, | |
| + PG_reclaim = 17, | |
| + PG_swapbacked = 18, | |
| + PG_unevictable = 19, | |
| + PG_mlocked = 20, | |
| + PG_uncached = 21, | |
| + PG_hwpoison = 22, | |
| + __NR_PAGEFLAGS = 23, | |
| + PG_readahead = 17, | |
| + PG_anon_exclusive = 16, | |
| + PG_checked = 11, | |
| + PG_swapcache = 11, | |
| + PG_fscache = 15, | |
| + PG_pinned = 11, | |
| PG_savepinned = 4, | |
| - PG_foreign = 12, | |
| - PG_xen_remapped = 12, | |
| - PG_isolated = 18, | |
| + PG_foreign = 11, | |
| + PG_xen_remapped = 11, | |
| + PG_isolated = 17, | |
| PG_reported = 3, | |
| - PG_vmemmap_self_hosted = 12, | |
| PG_has_hwpoisoned = 10, | |
| - PG_hugetlb = 8, | |
| PG_large_rmappable = 9, | |
| }; | |
| @@ -21180,20 +27034,26 @@ | |
| PAGE_CLEAN = 3, | |
| } pageout_t; | |
| +enum partition_cmd { | |
| + partcmd_enable = 0, | |
| + partcmd_enablei = 1, | |
| + partcmd_disable = 2, | |
| + partcmd_update = 3, | |
| + partcmd_invalidate = 4, | |
| +}; | |
| + | |
| enum passtype { | |
| PASS_SCAN = 0, | |
| PASS_REVOKE = 1, | |
| PASS_REPLAY = 2, | |
| }; | |
| -enum pch_board_ids { | |
| - PCH_BOARD_HSW = 0, | |
| - PCH_BOARD_WPT = 1, | |
| - PCH_BOARD_SKL = 2, | |
| - PCH_BOARD_CNL = 3, | |
| - PCH_BOARD_CML = 4, | |
| - PCH_BOARD_LWB = 5, | |
| - PCH_BOARD_WBG = 6, | |
| +enum pce_status { | |
| + PCE_STATUS_NONE = 0, | |
| + PCE_STATUS_ACQUIRED = 1, | |
| + PCE_STATUS_PREPARED = 2, | |
| + PCE_STATUS_ENABLED = 3, | |
| + PCE_STATUS_ERROR = 4, | |
| }; | |
| enum pci_bar_type { | |
| @@ -21324,9 +27184,9 @@ | |
| pbn_titan_2_4000000 = 110, | |
| pbn_titan_4_4000000 = 111, | |
| pbn_titan_8_4000000 = 112, | |
| - pbn_moxa8250_2p = 113, | |
| - pbn_moxa8250_4p = 114, | |
| - pbn_moxa8250_8p = 115, | |
| + pbn_moxa_2 = 113, | |
| + pbn_moxa_4 = 114, | |
| + pbn_moxa_8 = 115, | |
| }; | |
| enum pci_bus_flags { | |
| @@ -21490,6 +27350,13 @@ | |
| PERF_ADDR_FILTER_ACTION_FILTER = 2, | |
| }; | |
| +enum perf_adl_uncore_imc_freerunning_types { | |
| + ADL_MMIO_UNCORE_IMC_DATA_TOTAL = 0, | |
| + ADL_MMIO_UNCORE_IMC_DATA_READ = 1, | |
| + ADL_MMIO_UNCORE_IMC_DATA_WRITE = 2, | |
| + ADL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX = 3, | |
| +}; | |
| + | |
| enum perf_bpf_event_type { | |
| PERF_BPF_EVENT_UNKNOWN = 0, | |
| PERF_BPF_EVENT_PROG_LOAD = 1, | |
| @@ -21517,7 +27384,8 @@ | |
| PERF_SAMPLE_BRANCH_TYPE_SAVE = 65536, | |
| PERF_SAMPLE_BRANCH_HW_INDEX = 131072, | |
| PERF_SAMPLE_BRANCH_PRIV_SAVE = 262144, | |
| - PERF_SAMPLE_BRANCH_MAX = 524288, | |
| + PERF_SAMPLE_BRANCH_COUNTERS = 524288, | |
| + PERF_SAMPLE_BRANCH_MAX = 1048576, | |
| }; | |
| enum perf_branch_sample_type_shift { | |
| @@ -21540,26 +27408,8 @@ | |
| PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, | |
| PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, | |
| PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18, | |
| - PERF_SAMPLE_BRANCH_MAX_SHIFT = 19, | |
| -}; | |
| - | |
| -enum perf_cstate_core_events { | |
| - PERF_CSTATE_CORE_C1_RES = 0, | |
| - PERF_CSTATE_CORE_C3_RES = 1, | |
| - PERF_CSTATE_CORE_C6_RES = 2, | |
| - PERF_CSTATE_CORE_C7_RES = 3, | |
| - PERF_CSTATE_CORE_EVENT_MAX = 4, | |
| -}; | |
| - | |
| -enum perf_cstate_pkg_events { | |
| - PERF_CSTATE_PKG_C2_RES = 0, | |
| - PERF_CSTATE_PKG_C3_RES = 1, | |
| - PERF_CSTATE_PKG_C6_RES = 2, | |
| - PERF_CSTATE_PKG_C7_RES = 3, | |
| - PERF_CSTATE_PKG_C8_RES = 4, | |
| - PERF_CSTATE_PKG_C9_RES = 5, | |
| - PERF_CSTATE_PKG_C10_RES = 6, | |
| - PERF_CSTATE_PKG_EVENT_MAX = 7, | |
| + PERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19, | |
| + PERF_SAMPLE_BRANCH_MAX_SHIFT = 20, | |
| }; | |
| enum perf_event_ioc_flags { | |
| @@ -21747,16 +27597,6 @@ | |
| PERF_UPROBE_REF_CTR_OFFSET_SHIFT = 32, | |
| }; | |
| -enum perf_rapl_events { | |
| - PERF_RAPL_PP0 = 0, | |
| - PERF_RAPL_PKG = 1, | |
| - PERF_RAPL_RAM = 2, | |
| - PERF_RAPL_PP1 = 3, | |
| - PERF_RAPL_PSYS = 4, | |
| - PERF_RAPL_MAX = 5, | |
| - NR_RAPL_DOMAINS = 5, | |
| -}; | |
| - | |
| enum perf_record_ksymbol_type { | |
| PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, | |
| PERF_RECORD_KSYMBOL_TYPE_BPF = 1, | |
| @@ -21770,6 +27610,15 @@ | |
| PERF_SAMPLE_REGS_ABI_64 = 2, | |
| }; | |
| +enum perf_snb_uncore_imc_freerunning_types { | |
| + SNB_PCI_UNCORE_IMC_DATA_READS = 0, | |
| + SNB_PCI_UNCORE_IMC_DATA_WRITES = 1, | |
| + SNB_PCI_UNCORE_IMC_GT_REQUESTS = 2, | |
| + SNB_PCI_UNCORE_IMC_IA_REQUESTS = 3, | |
| + SNB_PCI_UNCORE_IMC_IO_REQUESTS = 4, | |
| + SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX = 5, | |
| +}; | |
| + | |
| enum perf_sw_ids { | |
| PERF_COUNT_SW_CPU_CLOCK = 0, | |
| PERF_COUNT_SW_TASK_CLOCK = 1, | |
| @@ -21786,6 +27635,13 @@ | |
| PERF_COUNT_SW_MAX = 12, | |
| }; | |
| +enum perf_tgl_uncore_imc_freerunning_types { | |
| + TGL_MMIO_UNCORE_IMC_DATA_TOTAL = 0, | |
| + TGL_MMIO_UNCORE_IMC_DATA_READ = 1, | |
| + TGL_MMIO_UNCORE_IMC_DATA_WRITE = 2, | |
| + TGL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX = 3, | |
| +}; | |
| + | |
| enum perf_type_id { | |
| PERF_TYPE_HARDWARE = 0, | |
| PERF_TYPE_SOFTWARE = 1, | |
| @@ -21796,18 +27652,49 @@ | |
| PERF_TYPE_MAX = 6, | |
| }; | |
| -typedef enum { | |
| - AD_PERIODIC_DUMMY = 0, | |
| - AD_NO_PERIODIC = 1, | |
| - AD_FAST_PERIODIC = 2, | |
| - AD_SLOW_PERIODIC = 3, | |
| - AD_PERIODIC_TX = 4, | |
| -} periodic_states_t; | |
| +enum perf_uncore_icx_iio_freerunning_type_id { | |
| + ICX_IIO_MSR_IOCLK = 0, | |
| + ICX_IIO_MSR_BW_IN = 1, | |
| + ICX_IIO_FREERUNNING_TYPE_MAX = 2, | |
| +}; | |
| -enum pfn_cache_usage { | |
| - KVM_GUEST_USES_PFN = 1, | |
| - KVM_HOST_USES_PFN = 2, | |
| - KVM_GUEST_AND_HOST_USE_PFN = 3, | |
| +enum perf_uncore_icx_imc_freerunning_type_id { | |
| + ICX_IMC_DCLK = 0, | |
| + ICX_IMC_DDR = 1, | |
| + ICX_IMC_DDRT = 2, | |
| + ICX_IMC_FREERUNNING_TYPE_MAX = 3, | |
| +}; | |
| + | |
| +enum perf_uncore_iio_freerunning_type_id { | |
| + SKX_IIO_MSR_IOCLK = 0, | |
| + SKX_IIO_MSR_BW = 1, | |
| + SKX_IIO_MSR_UTIL = 2, | |
| + SKX_IIO_FREERUNNING_TYPE_MAX = 3, | |
| +}; | |
| + | |
| +enum perf_uncore_snr_iio_freerunning_type_id { | |
| + SNR_IIO_MSR_IOCLK = 0, | |
| + SNR_IIO_MSR_BW_IN = 1, | |
| + SNR_IIO_FREERUNNING_TYPE_MAX = 2, | |
| +}; | |
| + | |
| +enum perf_uncore_snr_imc_freerunning_type_id { | |
| + SNR_IMC_DCLK = 0, | |
| + SNR_IMC_DDR = 1, | |
| + SNR_IMC_FREERUNNING_TYPE_MAX = 2, | |
| +}; | |
| + | |
| +enum perf_uncore_spr_iio_freerunning_type_id { | |
| + SPR_IIO_MSR_IOCLK = 0, | |
| + SPR_IIO_MSR_BW_IN = 1, | |
| + SPR_IIO_MSR_BW_OUT = 2, | |
| + SPR_IIO_FREERUNNING_TYPE_MAX = 3, | |
| +}; | |
| + | |
| +enum perf_uncore_spr_imc_freerunning_type_id { | |
| + SPR_IMC_DCLK = 0, | |
| + SPR_IMC_PQ_CYCLES = 1, | |
| + SPR_IMC_FREERUNNING_TYPE_MAX = 2, | |
| }; | |
| enum pg_level { | |
| @@ -21832,6 +27719,29 @@ | |
| HPAGE_PUD = 3, | |
| }; | |
| +enum phy_event { | |
| + PHYE_LOSS_OF_SIGNAL = 0, | |
| + PHYE_OOB_DONE = 1, | |
| + PHYE_OOB_ERROR = 2, | |
| + PHYE_SPINUP_HOLD = 3, | |
| + PHYE_RESUME_TIMEOUT = 4, | |
| + PHYE_SHUTDOWN = 5, | |
| + PHY_NUM_EVENTS = 6, | |
| +}; | |
| + | |
| +enum phy_func { | |
| + PHY_FUNC_NOP = 0, | |
| + PHY_FUNC_LINK_RESET = 1, | |
| + PHY_FUNC_HARD_RESET = 2, | |
| + PHY_FUNC_DISABLE = 3, | |
| + PHY_FUNC_CLEAR_ERROR_LOG = 5, | |
| + PHY_FUNC_CLEAR_AFFIL = 6, | |
| + PHY_FUNC_TX_SATA_PS_SIGNAL = 7, | |
| + PHY_FUNC_RELEASE_SPINUP_HOLD = 16, | |
| + PHY_FUNC_SET_LINK_RATE = 17, | |
| + PHY_FUNC_GET_EVENTS = 18, | |
| +}; | |
| + | |
| typedef enum { | |
| PHY_INTERFACE_MODE_NA = 0, | |
| PHY_INTERFACE_MODE_INTERNAL = 1, | |
| @@ -21851,21 +27761,22 @@ | |
| PHY_INTERFACE_MODE_XGMII = 15, | |
| PHY_INTERFACE_MODE_XLGMII = 16, | |
| PHY_INTERFACE_MODE_MOCA = 17, | |
| - PHY_INTERFACE_MODE_QSGMII = 18, | |
| - PHY_INTERFACE_MODE_TRGMII = 19, | |
| - PHY_INTERFACE_MODE_100BASEX = 20, | |
| - PHY_INTERFACE_MODE_1000BASEX = 21, | |
| - PHY_INTERFACE_MODE_2500BASEX = 22, | |
| - PHY_INTERFACE_MODE_5GBASER = 23, | |
| - PHY_INTERFACE_MODE_RXAUI = 24, | |
| - PHY_INTERFACE_MODE_XAUI = 25, | |
| - PHY_INTERFACE_MODE_10GBASER = 26, | |
| - PHY_INTERFACE_MODE_25GBASER = 27, | |
| - PHY_INTERFACE_MODE_USXGMII = 28, | |
| - PHY_INTERFACE_MODE_10GKR = 29, | |
| - PHY_INTERFACE_MODE_QUSGMII = 30, | |
| - PHY_INTERFACE_MODE_1000BASEKX = 31, | |
| - PHY_INTERFACE_MODE_MAX = 32, | |
| + PHY_INTERFACE_MODE_PSGMII = 18, | |
| + PHY_INTERFACE_MODE_QSGMII = 19, | |
| + PHY_INTERFACE_MODE_TRGMII = 20, | |
| + PHY_INTERFACE_MODE_100BASEX = 21, | |
| + PHY_INTERFACE_MODE_1000BASEX = 22, | |
| + PHY_INTERFACE_MODE_2500BASEX = 23, | |
| + PHY_INTERFACE_MODE_5GBASER = 24, | |
| + PHY_INTERFACE_MODE_RXAUI = 25, | |
| + PHY_INTERFACE_MODE_XAUI = 26, | |
| + PHY_INTERFACE_MODE_10GBASER = 27, | |
| + PHY_INTERFACE_MODE_25GBASER = 28, | |
| + PHY_INTERFACE_MODE_USXGMII = 29, | |
| + PHY_INTERFACE_MODE_10GKR = 30, | |
| + PHY_INTERFACE_MODE_QUSGMII = 31, | |
| + PHY_INTERFACE_MODE_1000BASEKX = 32, | |
| + PHY_INTERFACE_MODE_MAX = 33, | |
| } phy_interface_t; | |
| enum phy_media { | |
| @@ -21897,18 +27808,21 @@ | |
| PHY_MODE_DP = 19, | |
| }; | |
| -enum phy_port_state { | |
| - MLX5_AAA_111 = 0, | |
| -}; | |
| - | |
| enum phy_state { | |
| PHY_DOWN = 0, | |
| PHY_READY = 1, | |
| PHY_HALTED = 2, | |
| - PHY_UP = 3, | |
| - PHY_RUNNING = 4, | |
| - PHY_NOLINK = 5, | |
| - PHY_CABLETEST = 6, | |
| + PHY_ERROR = 3, | |
| + PHY_UP = 4, | |
| + PHY_RUNNING = 5, | |
| + PHY_NOLINK = 6, | |
| + PHY_CABLETEST = 7, | |
| +}; | |
| + | |
| +enum phy_state_work { | |
| + PHY_STATE_WORK_NONE = 0, | |
| + PHY_STATE_WORK_ANEG = 1, | |
| + PHY_STATE_WORK_SUSPEND = 2, | |
| }; | |
| enum phy_tunable_id { | |
| @@ -21919,6 +27833,11 @@ | |
| __ETHTOOL_PHY_TUNABLE_COUNT = 4, | |
| }; | |
| +enum phy_upstream { | |
| + PHY_UPSTREAM_MAC = 0, | |
| + PHY_UPSTREAM_PHY = 1, | |
| +}; | |
| + | |
| enum pid_type { | |
| PIDTYPE_PID = 0, | |
| PIDTYPE_TGID = 1, | |
| @@ -21927,6 +27846,26 @@ | |
| PIDTYPE_MAX = 4, | |
| }; | |
| +enum piix_controller_ids { | |
| + piix_pata_mwdma = 0, | |
| + piix_pata_33 = 1, | |
| + ich_pata_33 = 2, | |
| + ich_pata_66 = 3, | |
| + ich_pata_100 = 4, | |
| + ich_pata_100_nomwdma1 = 5, | |
| + ich5_sata = 6, | |
| + ich6_sata = 7, | |
| + ich6m_sata = 8, | |
| + ich8_sata = 9, | |
| + ich8_2port_sata = 10, | |
| + ich8m_apple_sata = 11, | |
| + tolapai_sata = 12, | |
| + piix_pata_vmw = 13, | |
| + ich8_sata_snb = 14, | |
| + ich8_2port_sata_snb = 15, | |
| + ich8_2port_sata_byt = 16, | |
| +}; | |
| + | |
| enum pin_config_param { | |
| PIN_CONFIG_BIAS_BUS_HOLD = 0, | |
| PIN_CONFIG_BIAS_DISABLE = 1, | |
| @@ -21957,6 +27896,27 @@ | |
| PIN_CONFIG_MAX = 255, | |
| }; | |
| +enum pkcs7_actions { | |
| + ACT_pkcs7_check_content_type = 0, | |
| + ACT_pkcs7_extract_cert = 1, | |
| + ACT_pkcs7_note_OID = 2, | |
| + ACT_pkcs7_note_certificate_list = 3, | |
| + ACT_pkcs7_note_content = 4, | |
| + ACT_pkcs7_note_data = 5, | |
| + ACT_pkcs7_note_signed_info = 6, | |
| + ACT_pkcs7_note_signeddata_version = 7, | |
| + ACT_pkcs7_note_signerinfo_version = 8, | |
| + ACT_pkcs7_sig_note_authenticated_attr = 9, | |
| + ACT_pkcs7_sig_note_digest_algo = 10, | |
| + ACT_pkcs7_sig_note_issuer = 11, | |
| + ACT_pkcs7_sig_note_pkey_algo = 12, | |
| + ACT_pkcs7_sig_note_serial = 13, | |
| + ACT_pkcs7_sig_note_set_of_authattrs = 14, | |
| + ACT_pkcs7_sig_note_signature = 15, | |
| + ACT_pkcs7_sig_note_skid = 16, | |
| + NR__pkcs7_actions = 17, | |
| +}; | |
| + | |
| enum pkey_id_type { | |
| PKEY_ID_PGP = 0, | |
| PKEY_ID_X509 = 1, | |
| @@ -21970,14 +27930,11 @@ | |
| PKT_HASH_TYPE_L4 = 3, | |
| }; | |
| -enum pl2303_type { | |
| - TYPE_H = 0, | |
| - TYPE_HX = 1, | |
| - TYPE_TA = 2, | |
| - TYPE_TB = 3, | |
| - TYPE_HXD = 4, | |
| - TYPE_HXN = 5, | |
| - TYPE_COUNT = 6, | |
| +enum pkt_vec { | |
| + PKT_VEC_PKT_LEN = 0, | |
| + PKT_VEC_PKT_PTR = 2, | |
| + PKT_VEC_QSEL_SET = 4, | |
| + PKT_VEC_QSEL_VAL = 6, | |
| }; | |
| enum pm_qos_flags_status { | |
| @@ -21999,206 +27956,26 @@ | |
| PM_QOS_MIN = 2, | |
| }; | |
| -enum pmbus_data_format { | |
| - linear = 0, | |
| - ieee754 = 1, | |
| - direct = 2, | |
| - vid = 3, | |
| -}; | |
| - | |
| -enum pmbus_fan_mode { | |
| - percent = 0, | |
| - rpm = 1, | |
| -}; | |
| - | |
| -enum pmbus_regs { | |
| - PMBUS_PAGE = 0, | |
| - PMBUS_OPERATION = 1, | |
| - PMBUS_ON_OFF_CONFIG = 2, | |
| - PMBUS_CLEAR_FAULTS = 3, | |
| - PMBUS_PHASE = 4, | |
| - PMBUS_WRITE_PROTECT = 16, | |
| - PMBUS_CAPABILITY = 25, | |
| - PMBUS_QUERY = 26, | |
| - PMBUS_SMBALERT_MASK = 27, | |
| - PMBUS_VOUT_MODE = 32, | |
| - PMBUS_VOUT_COMMAND = 33, | |
| - PMBUS_VOUT_TRIM = 34, | |
| - PMBUS_VOUT_CAL_OFFSET = 35, | |
| - PMBUS_VOUT_MAX = 36, | |
| - PMBUS_VOUT_MARGIN_HIGH = 37, | |
| - PMBUS_VOUT_MARGIN_LOW = 38, | |
| - PMBUS_VOUT_TRANSITION_RATE = 39, | |
| - PMBUS_VOUT_DROOP = 40, | |
| - PMBUS_VOUT_SCALE_LOOP = 41, | |
| - PMBUS_VOUT_SCALE_MONITOR = 42, | |
| - PMBUS_COEFFICIENTS = 48, | |
| - PMBUS_POUT_MAX = 49, | |
| - PMBUS_FAN_CONFIG_12 = 58, | |
| - PMBUS_FAN_COMMAND_1 = 59, | |
| - PMBUS_FAN_COMMAND_2 = 60, | |
| - PMBUS_FAN_CONFIG_34 = 61, | |
| - PMBUS_FAN_COMMAND_3 = 62, | |
| - PMBUS_FAN_COMMAND_4 = 63, | |
| - PMBUS_VOUT_OV_FAULT_LIMIT = 64, | |
| - PMBUS_VOUT_OV_FAULT_RESPONSE = 65, | |
| - PMBUS_VOUT_OV_WARN_LIMIT = 66, | |
| - PMBUS_VOUT_UV_WARN_LIMIT = 67, | |
| - PMBUS_VOUT_UV_FAULT_LIMIT = 68, | |
| - PMBUS_VOUT_UV_FAULT_RESPONSE = 69, | |
| - PMBUS_IOUT_OC_FAULT_LIMIT = 70, | |
| - PMBUS_IOUT_OC_FAULT_RESPONSE = 71, | |
| - PMBUS_IOUT_OC_LV_FAULT_LIMIT = 72, | |
| - PMBUS_IOUT_OC_LV_FAULT_RESPONSE = 73, | |
| - PMBUS_IOUT_OC_WARN_LIMIT = 74, | |
| - PMBUS_IOUT_UC_FAULT_LIMIT = 75, | |
| - PMBUS_IOUT_UC_FAULT_RESPONSE = 76, | |
| - PMBUS_OT_FAULT_LIMIT = 79, | |
| - PMBUS_OT_FAULT_RESPONSE = 80, | |
| - PMBUS_OT_WARN_LIMIT = 81, | |
| - PMBUS_UT_WARN_LIMIT = 82, | |
| - PMBUS_UT_FAULT_LIMIT = 83, | |
| - PMBUS_UT_FAULT_RESPONSE = 84, | |
| - PMBUS_VIN_OV_FAULT_LIMIT = 85, | |
| - PMBUS_VIN_OV_FAULT_RESPONSE = 86, | |
| - PMBUS_VIN_OV_WARN_LIMIT = 87, | |
| - PMBUS_VIN_UV_WARN_LIMIT = 88, | |
| - PMBUS_VIN_UV_FAULT_LIMIT = 89, | |
| - PMBUS_IIN_OC_FAULT_LIMIT = 91, | |
| - PMBUS_IIN_OC_WARN_LIMIT = 93, | |
| - PMBUS_POUT_OP_FAULT_LIMIT = 104, | |
| - PMBUS_POUT_OP_WARN_LIMIT = 106, | |
| - PMBUS_PIN_OP_WARN_LIMIT = 107, | |
| - PMBUS_STATUS_BYTE = 120, | |
| - PMBUS_STATUS_WORD = 121, | |
| - PMBUS_STATUS_VOUT = 122, | |
| - PMBUS_STATUS_IOUT = 123, | |
| - PMBUS_STATUS_INPUT = 124, | |
| - PMBUS_STATUS_TEMPERATURE = 125, | |
| - PMBUS_STATUS_CML = 126, | |
| - PMBUS_STATUS_OTHER = 127, | |
| - PMBUS_STATUS_MFR_SPECIFIC = 128, | |
| - PMBUS_STATUS_FAN_12 = 129, | |
| - PMBUS_STATUS_FAN_34 = 130, | |
| - PMBUS_READ_VIN = 136, | |
| - PMBUS_READ_IIN = 137, | |
| - PMBUS_READ_VCAP = 138, | |
| - PMBUS_READ_VOUT = 139, | |
| - PMBUS_READ_IOUT = 140, | |
| - PMBUS_READ_TEMPERATURE_1 = 141, | |
| - PMBUS_READ_TEMPERATURE_2 = 142, | |
| - PMBUS_READ_TEMPERATURE_3 = 143, | |
| - PMBUS_READ_FAN_SPEED_1 = 144, | |
| - PMBUS_READ_FAN_SPEED_2 = 145, | |
| - PMBUS_READ_FAN_SPEED_3 = 146, | |
| - PMBUS_READ_FAN_SPEED_4 = 147, | |
| - PMBUS_READ_DUTY_CYCLE = 148, | |
| - PMBUS_READ_FREQUENCY = 149, | |
| - PMBUS_READ_POUT = 150, | |
| - PMBUS_READ_PIN = 151, | |
| - PMBUS_REVISION = 152, | |
| - PMBUS_MFR_ID = 153, | |
| - PMBUS_MFR_MODEL = 154, | |
| - PMBUS_MFR_REVISION = 155, | |
| - PMBUS_MFR_LOCATION = 156, | |
| - PMBUS_MFR_DATE = 157, | |
| - PMBUS_MFR_SERIAL = 158, | |
| - PMBUS_MFR_VIN_MIN = 160, | |
| - PMBUS_MFR_VIN_MAX = 161, | |
| - PMBUS_MFR_IIN_MAX = 162, | |
| - PMBUS_MFR_PIN_MAX = 163, | |
| - PMBUS_MFR_VOUT_MIN = 164, | |
| - PMBUS_MFR_VOUT_MAX = 165, | |
| - PMBUS_MFR_IOUT_MAX = 166, | |
| - PMBUS_MFR_POUT_MAX = 167, | |
| - PMBUS_IC_DEVICE_ID = 173, | |
| - PMBUS_IC_DEVICE_REV = 174, | |
| - PMBUS_MFR_MAX_TEMP_1 = 192, | |
| - PMBUS_MFR_MAX_TEMP_2 = 193, | |
| - PMBUS_MFR_MAX_TEMP_3 = 194, | |
| - PMBUS_VIRT_BASE = 256, | |
| - PMBUS_VIRT_READ_TEMP_AVG = 257, | |
| - PMBUS_VIRT_READ_TEMP_MIN = 258, | |
| - PMBUS_VIRT_READ_TEMP_MAX = 259, | |
| - PMBUS_VIRT_RESET_TEMP_HISTORY = 260, | |
| - PMBUS_VIRT_READ_VIN_AVG = 261, | |
| - PMBUS_VIRT_READ_VIN_MIN = 262, | |
| - PMBUS_VIRT_READ_VIN_MAX = 263, | |
| - PMBUS_VIRT_RESET_VIN_HISTORY = 264, | |
| - PMBUS_VIRT_READ_IIN_AVG = 265, | |
| - PMBUS_VIRT_READ_IIN_MIN = 266, | |
| - PMBUS_VIRT_READ_IIN_MAX = 267, | |
| - PMBUS_VIRT_RESET_IIN_HISTORY = 268, | |
| - PMBUS_VIRT_READ_PIN_AVG = 269, | |
| - PMBUS_VIRT_READ_PIN_MIN = 270, | |
| - PMBUS_VIRT_READ_PIN_MAX = 271, | |
| - PMBUS_VIRT_RESET_PIN_HISTORY = 272, | |
| - PMBUS_VIRT_READ_POUT_AVG = 273, | |
| - PMBUS_VIRT_READ_POUT_MIN = 274, | |
| - PMBUS_VIRT_READ_POUT_MAX = 275, | |
| - PMBUS_VIRT_RESET_POUT_HISTORY = 276, | |
| - PMBUS_VIRT_READ_VOUT_AVG = 277, | |
| - PMBUS_VIRT_READ_VOUT_MIN = 278, | |
| - PMBUS_VIRT_READ_VOUT_MAX = 279, | |
| - PMBUS_VIRT_RESET_VOUT_HISTORY = 280, | |
| - PMBUS_VIRT_READ_IOUT_AVG = 281, | |
| - PMBUS_VIRT_READ_IOUT_MIN = 282, | |
| - PMBUS_VIRT_READ_IOUT_MAX = 283, | |
| - PMBUS_VIRT_RESET_IOUT_HISTORY = 284, | |
| - PMBUS_VIRT_READ_TEMP2_AVG = 285, | |
| - PMBUS_VIRT_READ_TEMP2_MIN = 286, | |
| - PMBUS_VIRT_READ_TEMP2_MAX = 287, | |
| - PMBUS_VIRT_RESET_TEMP2_HISTORY = 288, | |
| - PMBUS_VIRT_READ_VMON = 289, | |
| - PMBUS_VIRT_VMON_UV_WARN_LIMIT = 290, | |
| - PMBUS_VIRT_VMON_OV_WARN_LIMIT = 291, | |
| - PMBUS_VIRT_VMON_UV_FAULT_LIMIT = 292, | |
| - PMBUS_VIRT_VMON_OV_FAULT_LIMIT = 293, | |
| - PMBUS_VIRT_STATUS_VMON = 294, | |
| - PMBUS_VIRT_FAN_TARGET_1 = 295, | |
| - PMBUS_VIRT_FAN_TARGET_2 = 296, | |
| - PMBUS_VIRT_FAN_TARGET_3 = 297, | |
| - PMBUS_VIRT_FAN_TARGET_4 = 298, | |
| - PMBUS_VIRT_PWM_1 = 299, | |
| - PMBUS_VIRT_PWM_2 = 300, | |
| - PMBUS_VIRT_PWM_3 = 301, | |
| - PMBUS_VIRT_PWM_4 = 302, | |
| - PMBUS_VIRT_PWM_ENABLE_1 = 303, | |
| - PMBUS_VIRT_PWM_ENABLE_2 = 304, | |
| - PMBUS_VIRT_PWM_ENABLE_3 = 305, | |
| - PMBUS_VIRT_PWM_ENABLE_4 = 306, | |
| - PMBUS_VIRT_SAMPLES = 307, | |
| - PMBUS_VIRT_IN_SAMPLES = 308, | |
| - PMBUS_VIRT_CURR_SAMPLES = 309, | |
| - PMBUS_VIRT_POWER_SAMPLES = 310, | |
| - PMBUS_VIRT_TEMP_SAMPLES = 311, | |
| +enum pmc_type { | |
| + KVM_PMC_GP = 0, | |
| + KVM_PMC_FIXED = 1, | |
| }; | |
| -enum pmbus_sensor_classes { | |
| - PSC_VOLTAGE_IN = 0, | |
| - PSC_VOLTAGE_OUT = 1, | |
| - PSC_CURRENT_IN = 2, | |
| - PSC_CURRENT_OUT = 3, | |
| - PSC_POWER = 4, | |
| - PSC_TEMPERATURE = 5, | |
| - PSC_FAN = 6, | |
| - PSC_PWM = 7, | |
| - PSC_NUM_CLASSES = 8, | |
| +enum pmu_type { | |
| + PMU_TYPE_COUNTER = 0, | |
| + PMU_TYPE_EVNTSEL = 1, | |
| }; | |
| -enum pmc_type { | |
| - KVM_PMC_GP = 0, | |
| - KVM_PMC_FIXED = 1, | |
| +enum pnfs_iomode { | |
| + IOMODE_READ = 1, | |
| + IOMODE_RW = 2, | |
| + IOMODE_ANY = 3, | |
| }; | |
| -enum poison_cmd_enabled_bits { | |
| - CXL_POISON_ENABLED_LIST = 0, | |
| - CXL_POISON_ENABLED_INJECT = 1, | |
| - CXL_POISON_ENABLED_CLEAR = 2, | |
| - CXL_POISON_ENABLED_SCAN_CAPS = 3, | |
| - CXL_POISON_ENABLED_SCAN_MEDIA = 4, | |
| - CXL_POISON_ENABLED_SCAN_RESULTS = 5, | |
| - CXL_POISON_ENABLED_MAX = 6, | |
| +enum pnfs_try_status { | |
| + PNFS_ATTEMPTED = 0, | |
| + PNFS_NOT_ATTEMPTED = 1, | |
| + PNFS_TRY_AGAIN = 2, | |
| }; | |
| enum policy_opt { | |
| @@ -22247,7 +28024,7 @@ | |
| Opt_template = 42, | |
| Opt_keyrings = 43, | |
| Opt_label = 44, | |
| - Opt_err___8 = 45, | |
| + Opt_err___9 = 45, | |
| }; | |
| enum policy_rule_list { | |
| @@ -22267,25 +28044,25 @@ | |
| PT_OLD_TIMESPEC = 3, | |
| }; | |
| -enum port_module_event_error_type { | |
| - MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0, | |
| - MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX = 1, | |
| - MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 2, | |
| - MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 3, | |
| - MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 4, | |
| - MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER = 5, | |
| - MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 6, | |
| - MLX5_MODULE_EVENT_ERROR_BAD_CABLE = 7, | |
| - MLX5_MODULE_EVENT_ERROR_PCIE_POWER_SLOT_EXCEEDED = 12, | |
| - MLX5_MODULE_EVENT_ERROR_NUM = 13, | |
| +enum pool_workqueue_stats { | |
| + PWQ_STAT_STARTED = 0, | |
| + PWQ_STAT_COMPLETED = 1, | |
| + PWQ_STAT_CPU_TIME = 2, | |
| + PWQ_STAT_CPU_INTENSIVE = 3, | |
| + PWQ_STAT_CM_WAKEUP = 4, | |
| + PWQ_STAT_REPATRIATED = 5, | |
| + PWQ_STAT_MAYDAY = 6, | |
| + PWQ_STAT_RESCUED = 7, | |
| + PWQ_NR_STATS = 8, | |
| }; | |
| -enum port_module_event_status_type { | |
| - MLX5_MODULE_STATUS_PLUGGED = 1, | |
| - MLX5_MODULE_STATUS_UNPLUGGED = 2, | |
| - MLX5_MODULE_STATUS_ERROR = 3, | |
| - MLX5_MODULE_STATUS_DISABLED = 4, | |
| - MLX5_MODULE_STATUS_NUM = 5, | |
| +enum port_event { | |
| + PORTE_BYTES_DMAED = 0, | |
| + PORTE_BROADCAST_RCVD = 1, | |
| + PORTE_LINK_RESET_ERR = 2, | |
| + PORTE_TIMER_EVENT = 3, | |
| + PORTE_HARD_RESET = 4, | |
| + PORT_NUM_EVENTS = 5, | |
| }; | |
| enum port_pkey_state { | |
| @@ -22294,13 +28071,6 @@ | |
| IB_PORT_PKEY_LISTED = 2, | |
| }; | |
| -enum port_state_policy { | |
| - MLX5_POLICY_DOWN = 0, | |
| - MLX5_POLICY_UP = 1, | |
| - MLX5_POLICY_FOLLOW = 2, | |
| - MLX5_POLICY_INVALID = 4294967295, | |
| -}; | |
| - | |
| enum positive_aop_returns { | |
| AOP_WRITEPAGE_ACTIVATE = 524288, | |
| AOP_TRUNCATED_PAGE = 524289, | |
| @@ -22472,6 +28242,25 @@ | |
| PROBE_FORCE_SYNCHRONOUS = 2, | |
| }; | |
| +enum proc_cn_event { | |
| + PROC_EVENT_NONE = 0, | |
| + PROC_EVENT_FORK = 1, | |
| + PROC_EVENT_EXEC = 2, | |
| + PROC_EVENT_UID = 4, | |
| + PROC_EVENT_GID = 64, | |
| + PROC_EVENT_SID = 128, | |
| + PROC_EVENT_PTRACE = 256, | |
| + PROC_EVENT_COMM = 512, | |
| + PROC_EVENT_NONZERO_EXIT = 536870912, | |
| + PROC_EVENT_COREDUMP = 1073741824, | |
| + PROC_EVENT_EXIT = 2147483648, | |
| +}; | |
| + | |
| +enum proc_cn_mcast_op { | |
| + PROC_CN_MCAST_LISTEN = 1, | |
| + PROC_CN_MCAST_IGNORE = 2, | |
| +}; | |
| + | |
| enum proc_hidepid { | |
| HIDEPID_OFF = 0, | |
| HIDEPID_NO_ACCESS = 1, | |
| @@ -22480,7 +28269,7 @@ | |
| }; | |
| enum proc_param { | |
| - Opt_gid___5 = 0, | |
| + Opt_gid___6 = 0, | |
| Opt_hidepid = 1, | |
| Opt_subset = 2, | |
| }; | |
| @@ -22490,6 +28279,18 @@ | |
| PROC_PIDONLY_ON = 1, | |
| }; | |
| +enum procmap_query_flags { | |
| + PROCFS_PROCMAP_EXACT_OR_NEXT_VMA = 1, | |
| + PROCFS_PROCMAP_FILE_BACKED_VMA = 2, | |
| +}; | |
| + | |
| +enum procmap_vma_flags { | |
| + PROCFS_PROCMAP_VMA_READABLE = 1, | |
| + PROCFS_PROCMAP_VMA_WRITABLE = 2, | |
| + PROCFS_PROCMAP_VMA_EXECUTABLE = 4, | |
| + PROCFS_PROCMAP_VMA_SHARED = 8, | |
| +}; | |
| + | |
| enum prs_errcode { | |
| PERR_NONE = 0, | |
| PERR_INVCPUS = 1, | |
| @@ -22499,44 +28300,13 @@ | |
| PERR_NOCPUS = 5, | |
| PERR_HOTPLUG = 6, | |
| PERR_CPUSEMPTY = 7, | |
| + PERR_HKEEPING = 8, | |
| }; | |
| -enum psample_command { | |
| - PSAMPLE_CMD_SAMPLE = 0, | |
| - PSAMPLE_CMD_GET_GROUP = 1, | |
| - PSAMPLE_CMD_NEW_GROUP = 2, | |
| - PSAMPLE_CMD_DEL_GROUP = 3, | |
| -}; | |
| - | |
| -enum psample_nl_multicast_groups { | |
| - PSAMPLE_NL_MCGRP_CONFIG = 0, | |
| - PSAMPLE_NL_MCGRP_SAMPLE = 1, | |
| -}; | |
| - | |
| -enum psample_tunnel_key_attr { | |
| - PSAMPLE_TUNNEL_KEY_ATTR_ID = 0, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_IPV4_SRC = 1, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_IPV4_DST = 2, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_TOS = 3, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_TTL = 4, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_DONT_FRAGMENT = 5, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_CSUM = 6, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_OAM = 7, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_GENEVE_OPTS = 8, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_TP_SRC = 9, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_TP_DST = 10, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_VXLAN_OPTS = 11, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_IPV6_SRC = 12, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_IPV6_DST = 13, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_PAD = 14, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_ERSPAN_OPTS = 15, | |
| - PSAMPLE_TUNNEL_KEY_ATTR_IPV4_INFO_BRIDGE = 16, | |
| - __PSAMPLE_TUNNEL_KEY_ATTR_MAX = 17, | |
| -}; | |
| - | |
| -enum psc_op { | |
| - SNP_PAGE_STATE_PRIVATE = 1, | |
| - SNP_PAGE_STATE_SHARED = 2, | |
| +enum ps2_disposition { | |
| + PS2_PROCESS = 0, | |
| + PS2_IGNORE = 1, | |
| + PS2_ERROR = 2, | |
| }; | |
| enum psi_aggregators { | |
| @@ -22549,8 +28319,7 @@ | |
| PSI_IO = 0, | |
| PSI_MEM = 1, | |
| PSI_CPU = 2, | |
| - PSI_IRQ = 3, | |
| - NR_PSI_RESOURCES = 4, | |
| + NR_PSI_RESOURCES = 3, | |
| }; | |
| enum psi_states { | |
| @@ -22560,9 +28329,8 @@ | |
| PSI_MEM_FULL = 3, | |
| PSI_CPU_SOME = 4, | |
| PSI_CPU_FULL = 5, | |
| - PSI_IRQ_FULL = 6, | |
| - PSI_NONIDLE = 7, | |
| - NR_PSI_STATES = 8, | |
| + PSI_NONIDLE = 6, | |
| + NR_PSI_STATES = 7, | |
| }; | |
| enum psi_task_count { | |
| @@ -22573,17 +28341,50 @@ | |
| NR_PSI_TASK_COUNTS = 4, | |
| }; | |
| -enum pstore_type_id { | |
| - PSTORE_TYPE_DMESG = 0, | |
| - PSTORE_TYPE_MCE = 1, | |
| - PSTORE_TYPE_CONSOLE = 2, | |
| - PSTORE_TYPE_FTRACE = 3, | |
| - PSTORE_TYPE_PPC_RTAS = 4, | |
| - PSTORE_TYPE_PPC_OF = 5, | |
| - PSTORE_TYPE_PPC_COMMON = 6, | |
| - PSTORE_TYPE_PMSG = 7, | |
| - PSTORE_TYPE_PPC_OPAL = 8, | |
| - PSTORE_TYPE_MAX = 9, | |
| +typedef enum { | |
| + PSMOUSE_BAD_DATA = 0, | |
| + PSMOUSE_GOOD_DATA = 1, | |
| + PSMOUSE_FULL_PACKET = 2, | |
| +} psmouse_ret_t; | |
| + | |
| +enum psmouse_scale { | |
| + PSMOUSE_SCALE11 = 0, | |
| + PSMOUSE_SCALE21 = 1, | |
| +}; | |
| + | |
| +enum psmouse_state { | |
| + PSMOUSE_IGNORE = 0, | |
| + PSMOUSE_INITIALIZING = 1, | |
| + PSMOUSE_RESYNCING = 2, | |
| + PSMOUSE_CMD_MODE = 3, | |
| + PSMOUSE_ACTIVATED = 4, | |
| +}; | |
| + | |
| +enum psmouse_type { | |
| + PSMOUSE_NONE = 0, | |
| + PSMOUSE_PS2 = 1, | |
| + PSMOUSE_PS2PP = 2, | |
| + PSMOUSE_THINKPS = 3, | |
| + PSMOUSE_GENPS = 4, | |
| + PSMOUSE_IMPS = 5, | |
| + PSMOUSE_IMEX = 6, | |
| + PSMOUSE_SYNAPTICS = 7, | |
| + PSMOUSE_ALPS = 8, | |
| + PSMOUSE_LIFEBOOK = 9, | |
| + PSMOUSE_TRACKPOINT = 10, | |
| + PSMOUSE_TOUCHKIT_PS2 = 11, | |
| + PSMOUSE_CORTRON = 12, | |
| + PSMOUSE_HGPK = 13, | |
| + PSMOUSE_ELANTECH = 14, | |
| + PSMOUSE_FSP = 15, | |
| + PSMOUSE_SYNAPTICS_RELATIVE = 16, | |
| + PSMOUSE_CYPRESS = 17, | |
| + PSMOUSE_FOCALTECH = 18, | |
| + PSMOUSE_VMMOUSE = 19, | |
| + PSMOUSE_BYD = 20, | |
| + PSMOUSE_SYNAPTICS_SMBUS = 21, | |
| + PSMOUSE_ELANTECH_SMBUS = 22, | |
| + PSMOUSE_AUTO = 23, | |
| }; | |
| enum pt_capabilities { | |
| @@ -22610,8 +28411,9 @@ | |
| enum ptp_clock_events { | |
| PTP_CLOCK_ALARM = 0, | |
| PTP_CLOCK_EXTTS = 1, | |
| - PTP_CLOCK_PPS = 2, | |
| - PTP_CLOCK_PPSUSR = 3, | |
| + PTP_CLOCK_EXTOFF = 2, | |
| + PTP_CLOCK_PPS = 3, | |
| + PTP_CLOCK_PPSUSR = 4, | |
| }; | |
| enum ptp_pin_function { | |
| @@ -22645,9 +28447,19 @@ | |
| QP_TRANS_SQD2RTS = 5, | |
| }; | |
| -enum queue_mode { | |
| - QUEUE_MODE_STRICT_PRIORITY = 0, | |
| - QUEUE_MODE_STREAM_RESERVATION = 1, | |
| +enum queue_stop_reason { | |
| + IEEE80211_QUEUE_STOP_REASON_DRIVER = 0, | |
| + IEEE80211_QUEUE_STOP_REASON_PS = 1, | |
| + IEEE80211_QUEUE_STOP_REASON_CSA = 2, | |
| + IEEE80211_QUEUE_STOP_REASON_AGGREGATION = 3, | |
| + IEEE80211_QUEUE_STOP_REASON_SUSPEND = 4, | |
| + IEEE80211_QUEUE_STOP_REASON_SKB_ADD = 5, | |
| + IEEE80211_QUEUE_STOP_REASON_OFFCHANNEL = 6, | |
| + IEEE80211_QUEUE_STOP_REASON_FLUSH = 7, | |
| + IEEE80211_QUEUE_STOP_REASON_TDLS_TEARDOWN = 8, | |
| + IEEE80211_QUEUE_STOP_REASON_RESERVE_TID = 9, | |
| + IEEE80211_QUEUE_STOP_REASON_IFTYPE_CHANGE = 10, | |
| + IEEE80211_QUEUE_STOP_REASONS = 11, | |
| }; | |
| enum quota_type { | |
| @@ -22657,23 +28469,85 @@ | |
| }; | |
| enum ramfs_param { | |
| - Opt_mode___4 = 0, | |
| + Opt_mode___5 = 0, | |
| }; | |
| -enum rapl_unit_quirk { | |
| - RAPL_UNIT_QUIRK_NONE = 0, | |
| - RAPL_UNIT_QUIRK_INTEL_HSW = 1, | |
| - RAPL_UNIT_QUIRK_INTEL_SPR = 2, | |
| +enum rate_control_capabilities { | |
| + RATE_CTRL_CAPA_VHT_EXT_NSS_BW = 1, | |
| + RATE_CTRL_CAPA_AMPDU_TRIGGER = 2, | |
| }; | |
| -enum rcutorture_type { | |
| - RCU_FLAVOR = 0, | |
| - RCU_TASKS_FLAVOR = 1, | |
| - RCU_TASKS_RUDE_FLAVOR = 2, | |
| - RCU_TASKS_TRACING_FLAVOR = 3, | |
| - RCU_TRIVIAL_FLAVOR = 4, | |
| - SRCU_FLAVOR = 5, | |
| - INVALID_RCU_FLAVOR = 6, | |
| +enum rate_info_bw { | |
| + RATE_INFO_BW_20 = 0, | |
| + RATE_INFO_BW_5 = 1, | |
| + RATE_INFO_BW_10 = 2, | |
| + RATE_INFO_BW_40 = 3, | |
| + RATE_INFO_BW_80 = 4, | |
| + RATE_INFO_BW_160 = 5, | |
| + RATE_INFO_BW_HE_RU = 6, | |
| + RATE_INFO_BW_320 = 7, | |
| + RATE_INFO_BW_EHT_RU = 8, | |
| + RATE_INFO_BW_1 = 9, | |
| + RATE_INFO_BW_2 = 10, | |
| + RATE_INFO_BW_4 = 11, | |
| + RATE_INFO_BW_8 = 12, | |
| + RATE_INFO_BW_16 = 13, | |
| +}; | |
| + | |
| +enum rate_info_flags { | |
| + RATE_INFO_FLAGS_MCS = 1, | |
| + RATE_INFO_FLAGS_VHT_MCS = 2, | |
| + RATE_INFO_FLAGS_SHORT_GI = 4, | |
| + RATE_INFO_FLAGS_DMG = 8, | |
| + RATE_INFO_FLAGS_HE_MCS = 16, | |
| + RATE_INFO_FLAGS_EDMG = 32, | |
| + RATE_INFO_FLAGS_EXTENDED_SC_DMG = 64, | |
| + RATE_INFO_FLAGS_EHT_MCS = 128, | |
| + RATE_INFO_FLAGS_S1G_MCS = 256, | |
| +}; | |
| + | |
| +enum rc_driver_type { | |
| + RC_DRIVER_SCANCODE = 0, | |
| + RC_DRIVER_IR_RAW = 1, | |
| + RC_DRIVER_IR_RAW_TX = 2, | |
| +}; | |
| + | |
| +enum rc_filter_type { | |
| + RC_FILTER_NORMAL = 0, | |
| + RC_FILTER_WAKEUP = 1, | |
| + RC_FILTER_MAX = 2, | |
| +}; | |
| + | |
| +enum rc_proto { | |
| + RC_PROTO_UNKNOWN = 0, | |
| + RC_PROTO_OTHER = 1, | |
| + RC_PROTO_RC5 = 2, | |
| + RC_PROTO_RC5X_20 = 3, | |
| + RC_PROTO_RC5_SZ = 4, | |
| + RC_PROTO_JVC = 5, | |
| + RC_PROTO_SONY12 = 6, | |
| + RC_PROTO_SONY15 = 7, | |
| + RC_PROTO_SONY20 = 8, | |
| + RC_PROTO_NEC = 9, | |
| + RC_PROTO_NECX = 10, | |
| + RC_PROTO_NEC32 = 11, | |
| + RC_PROTO_SANYO = 12, | |
| + RC_PROTO_MCIR2_KBD = 13, | |
| + RC_PROTO_MCIR2_MSE = 14, | |
| + RC_PROTO_RC6_0 = 15, | |
| + RC_PROTO_RC6_6A_20 = 16, | |
| + RC_PROTO_RC6_6A_24 = 17, | |
| + RC_PROTO_RC6_6A_32 = 18, | |
| + RC_PROTO_RC6_MCE = 19, | |
| + RC_PROTO_SHARP = 20, | |
| + RC_PROTO_XMP = 21, | |
| + RC_PROTO_CEC = 22, | |
| + RC_PROTO_IMON = 23, | |
| + RC_PROTO_RCMM12 = 24, | |
| + RC_PROTO_RCMM24 = 25, | |
| + RC_PROTO_RCMM32 = 26, | |
| + RC_PROTO_XBOX_DVD = 27, | |
| + RC_PROTO_MAX = 27, | |
| }; | |
| enum rdma_ah_attr_type { | |
| @@ -22743,27 +28617,6 @@ | |
| RDMA_RESTRACK_MAX = 8, | |
| }; | |
| -enum rdt_group_type { | |
| - RDTCTRL_GROUP = 0, | |
| - RDTMON_GROUP = 1, | |
| - RDT_NUM_GROUP = 2, | |
| -}; | |
| - | |
| -enum rdt_param { | |
| - Opt_cdp = 0, | |
| - Opt_cdpl2 = 1, | |
| - Opt_mba_mbps = 2, | |
| - nr__rdt_params = 3, | |
| -}; | |
| - | |
| -enum rdtgrp_mode { | |
| - RDT_MODE_SHAREABLE = 0, | |
| - RDT_MODE_EXCLUSIVE = 1, | |
| - RDT_MODE_PSEUDO_LOCKSETUP = 2, | |
| - RDT_MODE_PSEUDO_LOCKED = 3, | |
| - RDT_NUM_MODES = 4, | |
| -}; | |
| - | |
| enum reboot_mode { | |
| REBOOT_UNDEFINED = -1, | |
| REBOOT_COLD = 0, | |
| @@ -22813,6 +28666,13 @@ | |
| DST_OP_NO_MARK = 2, | |
| }; | |
| +enum reg_request_treatment { | |
| + REG_REQ_OK = 0, | |
| + REG_REQ_IGNORE = 1, | |
| + REG_REQ_INTERSECT = 2, | |
| + REG_REQ_ALREADY_SET = 3, | |
| +}; | |
| + | |
| enum reg_type { | |
| REG_TYPE_RM = 0, | |
| REG_TYPE_REG = 1, | |
| @@ -22843,16 +28703,16 @@ | |
| REGMAP_ENDIAN_NATIVE = 3, | |
| }; | |
| -enum regulator_type { | |
| - REGULATOR_VOLTAGE = 0, | |
| - REGULATOR_CURRENT = 1, | |
| -}; | |
| - | |
| enum release_type { | |
| leaf_only = 0, | |
| whole_subtree = 1, | |
| }; | |
| +enum reloc_stage { | |
| + MOVE_DATA_EXTENTS = 0, | |
| + UPDATE_DATA_PTRS = 1, | |
| +}; | |
| + | |
| enum req_flag_bits { | |
| __REQ_FAILFAST_DEV = 8, | |
| __REQ_FAILFAST_TRANSPORT = 9, | |
| @@ -22883,13 +28743,13 @@ | |
| REQ_OP_FLUSH = 2, | |
| REQ_OP_DISCARD = 3, | |
| REQ_OP_SECURE_ERASE = 5, | |
| + REQ_OP_ZONE_APPEND = 7, | |
| REQ_OP_WRITE_ZEROES = 9, | |
| REQ_OP_ZONE_OPEN = 10, | |
| REQ_OP_ZONE_CLOSE = 11, | |
| REQ_OP_ZONE_FINISH = 12, | |
| - REQ_OP_ZONE_APPEND = 13, | |
| - REQ_OP_ZONE_RESET = 15, | |
| - REQ_OP_ZONE_RESET_ALL = 17, | |
| + REQ_OP_ZONE_RESET = 13, | |
| + REQ_OP_ZONE_RESET_ALL = 15, | |
| REQ_OP_DRV_IN = 34, | |
| REQ_OP_DRV_OUT = 35, | |
| REQ_OP_LAST = 36, | |
| @@ -22960,20 +28820,6 @@ | |
| CDP_DATA = 2, | |
| }; | |
| -enum resctrl_event_id { | |
| - QOS_L3_OCCUP_EVENT_ID = 1, | |
| - QOS_L3_MBM_TOTAL_EVENT_ID = 2, | |
| - QOS_L3_MBM_LOCAL_EVENT_ID = 3, | |
| -}; | |
| - | |
| -enum resctrl_res_level { | |
| - RDT_RESOURCE_L3 = 0, | |
| - RDT_RESOURCE_L2 = 1, | |
| - RDT_RESOURCE_MBA = 2, | |
| - RDT_RESOURCE_SMBA = 3, | |
| - RDT_NUM_RESOURCES = 4, | |
| -}; | |
| - | |
| enum resolve_mode { | |
| RESOLVE_TBD = 0, | |
| RESOLVE_PTR = 1, | |
| @@ -22997,6 +28843,30 @@ | |
| RETBLEED_CMD_STUFF = 4, | |
| }; | |
| +enum rfds_mitigations { | |
| + RFDS_MITIGATION_OFF = 0, | |
| + RFDS_MITIGATION_VERW = 1, | |
| + RFDS_MITIGATION_UCODE_NEEDED = 2, | |
| +}; | |
| + | |
| +enum rfkill_hard_block_reasons { | |
| + RFKILL_HARD_BLOCK_SIGNAL = 1, | |
| + RFKILL_HARD_BLOCK_NOT_OWNER = 2, | |
| +}; | |
| + | |
| +enum rfkill_type { | |
| + RFKILL_TYPE_ALL = 0, | |
| + RFKILL_TYPE_WLAN = 1, | |
| + RFKILL_TYPE_BLUETOOTH = 2, | |
| + RFKILL_TYPE_UWB = 3, | |
| + RFKILL_TYPE_WIMAX = 4, | |
| + RFKILL_TYPE_WWAN = 5, | |
| + RFKILL_TYPE_GPS = 6, | |
| + RFKILL_TYPE_FM = 7, | |
| + RFKILL_TYPE_NFC = 8, | |
| + NUM_RFKILL_TYPES = 9, | |
| +}; | |
| + | |
| enum ring_buffer_flags { | |
| RB_FL_OVERWRITE = 1, | |
| }; | |
| @@ -23016,12 +28886,103 @@ | |
| UCOUNT_RLIMIT_COUNTS = 4, | |
| }; | |
| +enum rmap_level { | |
| + RMAP_LEVEL_PTE = 0, | |
| + RMAP_LEVEL_PMD = 1, | |
| +}; | |
| + | |
| +typedef enum { | |
| + ROLE_UNKNOWN = 0, | |
| + ROLE_INITIATOR = 1, | |
| + ROLE_TARGET = 2, | |
| +} role_t; | |
| + | |
| +enum routing_attribute { | |
| + DIRECT_ROUTING = 0, | |
| + SUBTRACTIVE_ROUTING = 1, | |
| + TABLE_ROUTING = 2, | |
| +}; | |
| + | |
| enum rp_check { | |
| RP_CHECK_CALL = 0, | |
| RP_CHECK_CHAIN_CALL = 1, | |
| RP_CHECK_RET = 2, | |
| }; | |
| +enum rpc_accept_stat { | |
| + RPC_SUCCESS = 0, | |
| + RPC_PROG_UNAVAIL = 1, | |
| + RPC_PROG_MISMATCH = 2, | |
| + RPC_PROC_UNAVAIL = 3, | |
| + RPC_GARBAGE_ARGS = 4, | |
| + RPC_SYSTEM_ERR = 5, | |
| + RPC_DROP_REPLY = 60000, | |
| +}; | |
| + | |
| +enum rpc_auth_flavors { | |
| + RPC_AUTH_NULL = 0, | |
| + RPC_AUTH_UNIX = 1, | |
| + RPC_AUTH_SHORT = 2, | |
| + RPC_AUTH_DES = 3, | |
| + RPC_AUTH_KRB = 4, | |
| + RPC_AUTH_GSS = 6, | |
| + RPC_AUTH_TLS = 7, | |
| + RPC_AUTH_MAXFLAVOR = 8, | |
| + RPC_AUTH_GSS_KRB5 = 390003, | |
| + RPC_AUTH_GSS_KRB5I = 390004, | |
| + RPC_AUTH_GSS_KRB5P = 390005, | |
| + RPC_AUTH_GSS_LKEY = 390006, | |
| + RPC_AUTH_GSS_LKEYI = 390007, | |
| + RPC_AUTH_GSS_LKEYP = 390008, | |
| + RPC_AUTH_GSS_SPKM = 390009, | |
| + RPC_AUTH_GSS_SPKMI = 390010, | |
| + RPC_AUTH_GSS_SPKMP = 390011, | |
| +}; | |
| + | |
| +enum rpc_auth_stat { | |
| + RPC_AUTH_OK = 0, | |
| + RPC_AUTH_BADCRED = 1, | |
| + RPC_AUTH_REJECTEDCRED = 2, | |
| + RPC_AUTH_BADVERF = 3, | |
| + RPC_AUTH_REJECTEDVERF = 4, | |
| + RPC_AUTH_TOOWEAK = 5, | |
| + RPCSEC_GSS_CREDPROBLEM = 13, | |
| + RPCSEC_GSS_CTXPROBLEM = 14, | |
| +}; | |
| + | |
| +enum rpc_display_format_t { | |
| + RPC_DISPLAY_ADDR = 0, | |
| + RPC_DISPLAY_PORT = 1, | |
| + RPC_DISPLAY_PROTO = 2, | |
| + RPC_DISPLAY_HEX_ADDR = 3, | |
| + RPC_DISPLAY_HEX_PORT = 4, | |
| + RPC_DISPLAY_NETID = 5, | |
| + RPC_DISPLAY_MAX = 6, | |
| +}; | |
| + | |
| +enum rpc_msg_type { | |
| + RPC_CALL = 0, | |
| + RPC_REPLY = 1, | |
| +}; | |
| + | |
| +enum rpc_reject_stat { | |
| + RPC_MISMATCH = 0, | |
| + RPC_AUTH_ERROR = 1, | |
| +}; | |
| + | |
| +enum rpc_reply_stat { | |
| + RPC_MSG_ACCEPTED = 0, | |
| + RPC_MSG_DENIED = 1, | |
| +}; | |
| + | |
| +enum rpm_request { | |
| + RPM_REQ_NONE = 0, | |
| + RPM_REQ_IDLE = 1, | |
| + RPM_REQ_SUSPEND = 2, | |
| + RPM_REQ_AUTOSUSPEND = 3, | |
| + RPM_REQ_RESUME = 4, | |
| +}; | |
| + | |
| enum rpm_status { | |
| RPM_INVALID = -1, | |
| RPM_ACTIVE = 0, | |
| @@ -23035,27 +28996,28 @@ | |
| RQ_END_IO_FREE = 1, | |
| }; | |
| -enum rq_onoff_reason { | |
| - RQ_ONOFF_HOTPLUG = 0, | |
| - RQ_ONOFF_TOPOLOGY = 1, | |
| -}; | |
| - | |
| enum rq_qos_id { | |
| RQ_QOS_WBT = 0, | |
| RQ_QOS_LATENCY = 1, | |
| RQ_QOS_COST = 2, | |
| }; | |
| -enum rrrr_ids { | |
| - R4_GEN = 0, | |
| - R4_RD = 1, | |
| - R4_WR = 2, | |
| - R4_DRD = 3, | |
| - R4_DWR = 4, | |
| - R4_IRD = 5, | |
| - R4_PREF = 6, | |
| - R4_EVICT = 7, | |
| - R4_SNOOP = 8, | |
| +enum rsaprivkey_actions { | |
| + ACT_rsa_get_d = 0, | |
| + ACT_rsa_get_dp = 1, | |
| + ACT_rsa_get_dq = 2, | |
| + ACT_rsa_get_e = 3, | |
| + ACT_rsa_get_n = 4, | |
| + ACT_rsa_get_p = 5, | |
| + ACT_rsa_get_q = 6, | |
| + ACT_rsa_get_qinv = 7, | |
| + NR__rsaprivkey_actions = 8, | |
| +}; | |
| + | |
| +enum rsapubkey_actions { | |
| + ACT_rsa_get_e___2 = 0, | |
| + ACT_rsa_get_n___2 = 1, | |
| + NR__rsapubkey_actions = 2, | |
| }; | |
| enum rseq_cpu_id_state { | |
| @@ -23069,6 +29031,12 @@ | |
| RSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE = 4, | |
| }; | |
| +enum rseq_cs_flags_bit { | |
| + RSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT_BIT = 0, | |
| + RSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT = 1, | |
| + RSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT = 2, | |
| +}; | |
| + | |
| enum rseq_event_mask_bits { | |
| RSEQ_EVENT_PREEMPT_BIT = 0, | |
| RSEQ_EVENT_SIGNAL_BIT = 1, | |
| @@ -23194,6 +29162,7 @@ | |
| enum rtnl_link_flags { | |
| RTNL_FLAG_DOIT_UNLOCKED = 1, | |
| RTNL_FLAG_BULK_DEL_SUPPORTED = 2, | |
| + RTNL_FLAG_DUMP_UNLOCKED = 4, | |
| }; | |
| enum rw_hint { | |
| @@ -23203,7 +29172,7 @@ | |
| WRITE_LIFE_MEDIUM = 3, | |
| WRITE_LIFE_LONG = 4, | |
| WRITE_LIFE_EXTREME = 5, | |
| -}; | |
| +} __attribute__((mode(byte))); | |
| enum rwsem_waiter_type { | |
| RWSEM_WAITING_FOR_WRITE = 0, | |
| @@ -23225,15 +29194,11 @@ | |
| typedef enum rx_handler_result rx_handler_result_t; | |
| -typedef enum { | |
| - AD_RX_DUMMY = 0, | |
| - AD_RX_INITIALIZE = 1, | |
| - AD_RX_PORT_DISABLED = 2, | |
| - AD_RX_LACP_DISABLED = 3, | |
| - AD_RX_EXPIRED = 4, | |
| - AD_RX_DEFAULTED = 5, | |
| - AD_RX_CURRENT = 6, | |
| -} rx_states_t; | |
| +enum s2idle_states { | |
| + S2IDLE_STATE_NONE = 0, | |
| + S2IDLE_STATE_ENTER = 1, | |
| + S2IDLE_STATE_WAKE = 2, | |
| +}; | |
| enum s_alloc { | |
| sa_rootdomain = 0, | |
| @@ -23256,6 +29221,94 @@ | |
| SAM_STAT_TASK_ABORTED = 64, | |
| }; | |
| +enum sas_device_type { | |
| + SAS_PHY_UNUSED = 0, | |
| + SAS_END_DEVICE = 1, | |
| + SAS_EDGE_EXPANDER_DEVICE = 2, | |
| + SAS_FANOUT_EXPANDER_DEVICE = 3, | |
| + SAS_HA = 4, | |
| + SAS_SATA_DEV = 5, | |
| + SAS_SATA_PM = 7, | |
| + SAS_SATA_PM_PORT = 8, | |
| + SAS_SATA_PENDING = 9, | |
| +}; | |
| + | |
| +enum sas_ha_state { | |
| + SAS_HA_REGISTERED = 0, | |
| + SAS_HA_DRAINING = 1, | |
| + SAS_HA_ATA_EH_ACTIVE = 2, | |
| + SAS_HA_FROZEN = 3, | |
| + SAS_HA_RESUMING = 4, | |
| +}; | |
| + | |
| +enum sas_internal_abort { | |
| + SAS_INTERNAL_ABORT_SINGLE = 0, | |
| + SAS_INTERNAL_ABORT_DEV = 1, | |
| +}; | |
| + | |
| +enum sas_linkrate { | |
| + SAS_LINK_RATE_UNKNOWN = 0, | |
| + SAS_PHY_DISABLED = 1, | |
| + SAS_PHY_RESET_PROBLEM = 2, | |
| + SAS_SATA_SPINUP_HOLD = 3, | |
| + SAS_SATA_PORT_SELECTOR = 4, | |
| + SAS_PHY_RESET_IN_PROGRESS = 5, | |
| + SAS_LINK_RATE_1_5_GBPS = 8, | |
| + SAS_LINK_RATE_G1 = 8, | |
| + SAS_LINK_RATE_3_0_GBPS = 9, | |
| + SAS_LINK_RATE_G2 = 9, | |
| + SAS_LINK_RATE_6_0_GBPS = 10, | |
| + SAS_LINK_RATE_12_0_GBPS = 11, | |
| + SAS_LINK_RATE_22_5_GBPS = 12, | |
| + SAS_LINK_RATE_FAILED = 16, | |
| + SAS_PHY_VIRTUAL = 17, | |
| +}; | |
| + | |
| +enum sas_oob_mode { | |
| + OOB_NOT_CONNECTED = 0, | |
| + SATA_OOB_MODE = 1, | |
| + SAS_OOB_MODE = 2, | |
| +}; | |
| + | |
| +enum sas_open_rej_reason { | |
| + SAS_OREJ_UNKNOWN = 0, | |
| + SAS_OREJ_BAD_DEST = 1, | |
| + SAS_OREJ_CONN_RATE = 2, | |
| + SAS_OREJ_EPROTO = 3, | |
| + SAS_OREJ_RESV_AB0 = 4, | |
| + SAS_OREJ_RESV_AB1 = 5, | |
| + SAS_OREJ_RESV_AB2 = 6, | |
| + SAS_OREJ_RESV_AB3 = 7, | |
| + SAS_OREJ_WRONG_DEST = 8, | |
| + SAS_OREJ_STP_NORES = 9, | |
| + SAS_OREJ_NO_DEST = 10, | |
| + SAS_OREJ_PATH_BLOCKED = 11, | |
| + SAS_OREJ_RSVD_CONT0 = 12, | |
| + SAS_OREJ_RSVD_CONT1 = 13, | |
| + SAS_OREJ_RSVD_INIT0 = 14, | |
| + SAS_OREJ_RSVD_INIT1 = 15, | |
| + SAS_OREJ_RSVD_STOP0 = 16, | |
| + SAS_OREJ_RSVD_STOP1 = 17, | |
| + SAS_OREJ_RSVD_RETRY = 18, | |
| +}; | |
| + | |
| +enum sas_phy_role { | |
| + PHY_ROLE_NONE = 0, | |
| + PHY_ROLE_TARGET = 64, | |
| + PHY_ROLE_INITIATOR = 128, | |
| +}; | |
| + | |
| +enum sas_protocol { | |
| + SAS_PROTOCOL_NONE = 0, | |
| + SAS_PROTOCOL_SATA = 1, | |
| + SAS_PROTOCOL_SMP = 2, | |
| + SAS_PROTOCOL_STP = 4, | |
| + SAS_PROTOCOL_SSP = 8, | |
| + SAS_PROTOCOL_ALL = 14, | |
| + SAS_PROTOCOL_STP_ALL = 5, | |
| + SAS_PROTOCOL_INTERNAL_ABORT = 16, | |
| +}; | |
| + | |
| enum scan_balance { | |
| SCAN_EQUAL = 0, | |
| SCAN_FRACT = 1, | |
| @@ -23298,6 +29351,45 @@ | |
| SCAN_PAGE_FILLED = 31, | |
| }; | |
| +typedef enum { | |
| + SCB_FLAG_NONE = 0, | |
| + SCB_TRANSMISSION_ERROR = 1, | |
| + SCB_OTHERTCL_TIMEOUT = 2, | |
| + SCB_DEVICE_RESET = 4, | |
| + SCB_SENSE = 8, | |
| + SCB_CDB32_PTR = 16, | |
| + SCB_RECOVERY_SCB = 32, | |
| + SCB_AUTO_NEGOTIATE = 64, | |
| + SCB_NEGOTIATE = 128, | |
| + SCB_ABORT = 256, | |
| + SCB_ACTIVE = 512, | |
| + SCB_TARGET_IMMEDIATE = 1024, | |
| + SCB_PACKETIZED = 2048, | |
| + SCB_EXPECT_PPR_BUSFREE = 4096, | |
| + SCB_PKT_SENSE = 8192, | |
| + SCB_EXTERNAL_RESET = 16384, | |
| + SCB_ON_COL_LIST = 32768, | |
| + SCB_SILENT = 65536, | |
| +} scb_flag; | |
| + | |
| +typedef enum { | |
| + SCB_FREE = 0, | |
| + SCB_OTHERTCL_TIMEOUT___2 = 2, | |
| + SCB_DEVICE_RESET___2 = 4, | |
| + SCB_SENSE___2 = 8, | |
| + SCB_CDB32_PTR___2 = 16, | |
| + SCB_RECOVERY_SCB___2 = 32, | |
| + SCB_AUTO_NEGOTIATE___2 = 64, | |
| + SCB_NEGOTIATE___2 = 128, | |
| + SCB_ABORT___2 = 256, | |
| + SCB_UNTAGGEDQ = 512, | |
| + SCB_ACTIVE___2 = 1024, | |
| + SCB_TARGET_IMMEDIATE___2 = 2048, | |
| + SCB_TRANSMISSION_ERROR___2 = 4096, | |
| + SCB_TARGET_SCB = 8192, | |
| + SCB_SILENT___2 = 16384, | |
| +} scb_flag___2; | |
| + | |
| enum sched_tunable_scaling { | |
| SCHED_TUNABLESCALING_NONE = 0, | |
| SCHED_TUNABLESCALING_LOG = 1, | |
| @@ -23311,19 +29403,6 @@ | |
| SCRUB_STRIPE_FLAG_NO_REPORT = 2, | |
| }; | |
| -enum scrub_type { | |
| - SCRUB_UNKNOWN = 0, | |
| - SCRUB_NONE = 1, | |
| - SCRUB_SW_PROG = 2, | |
| - SCRUB_SW_SRC = 3, | |
| - SCRUB_SW_PROG_SRC = 4, | |
| - SCRUB_SW_TUNABLE = 5, | |
| - SCRUB_HW_PROG = 6, | |
| - SCRUB_HW_SRC = 7, | |
| - SCRUB_HW_PROG_SRC = 8, | |
| - SCRUB_HW_TUNABLE = 9, | |
| -}; | |
| - | |
| enum scsi_cmnd_submitter { | |
| SUBMITTED_BY_BLOCK_LAYER = 0, | |
| SUBMITTED_BY_SCSI_ERROR_HANDLER = 1, | |
| @@ -23373,11 +29452,6 @@ | |
| FAST_IO_FAIL = 8201, | |
| }; | |
| -enum scsi_host_guard_type { | |
| - SHOST_DIX_GUARD_CRC = 1, | |
| - SHOST_DIX_GUARD_IP = 2, | |
| -}; | |
| - | |
| enum scsi_host_prot_capabilities { | |
| SHOST_DIF_TYPE1_PROTECTION = 1, | |
| SHOST_DIF_TYPE2_PROTECTION = 2, | |
| @@ -23424,6 +29498,7 @@ | |
| SCSIML_STAT_NOSPC = 2, | |
| SCSIML_STAT_MED_ERROR = 3, | |
| SCSIML_STAT_TGT_FAILURE = 4, | |
| + SCSIML_STAT_DL_TIMEOUT = 5, | |
| }; | |
| enum scsi_msg_byte { | |
| @@ -23457,6 +29532,15 @@ | |
| ABORT = 6, | |
| }; | |
| +enum scsi_pr_type { | |
| + SCSI_PR_WRITE_EXCLUSIVE = 1, | |
| + SCSI_PR_EXCLUSIVE_ACCESS = 3, | |
| + SCSI_PR_WRITE_EXCLUSIVE_REG_ONLY = 5, | |
| + SCSI_PR_EXCLUSIVE_ACCESS_REG_ONLY = 6, | |
| + SCSI_PR_WRITE_EXCLUSIVE_ALL_REGS = 7, | |
| + SCSI_PR_EXCLUSIVE_ACCESS_ALL_REGS = 8, | |
| +}; | |
| + | |
| enum scsi_prot_flags { | |
| SCSI_PROT_TRANSFER_PI = 1, | |
| SCSI_PROT_GUARD_CHECK = 2, | |
| @@ -23501,6 +29585,33 @@ | |
| enum scsi_vpd_parameters { | |
| SCSI_VPD_HEADER_SIZE = 4, | |
| + SCSI_VPD_LIST_SIZE = 36, | |
| +}; | |
| + | |
| +enum sctp_cid { | |
| + SCTP_CID_DATA = 0, | |
| + SCTP_CID_INIT = 1, | |
| + SCTP_CID_INIT_ACK = 2, | |
| + SCTP_CID_SACK = 3, | |
| + SCTP_CID_HEARTBEAT = 4, | |
| + SCTP_CID_HEARTBEAT_ACK = 5, | |
| + SCTP_CID_ABORT = 6, | |
| + SCTP_CID_SHUTDOWN = 7, | |
| + SCTP_CID_SHUTDOWN_ACK = 8, | |
| + SCTP_CID_ERROR = 9, | |
| + SCTP_CID_COOKIE_ECHO = 10, | |
| + SCTP_CID_COOKIE_ACK = 11, | |
| + SCTP_CID_ECN_ECNE = 12, | |
| + SCTP_CID_ECN_CWR = 13, | |
| + SCTP_CID_SHUTDOWN_COMPLETE = 14, | |
| + SCTP_CID_AUTH = 15, | |
| + SCTP_CID_I_DATA = 64, | |
| + SCTP_CID_FWD_TSN = 192, | |
| + SCTP_CID_ASCONF = 193, | |
| + SCTP_CID_I_FWD_TSN = 194, | |
| + SCTP_CID_ASCONF_ACK = 128, | |
| + SCTP_CID_RECONF = 130, | |
| + SCTP_CID_PAD = 132, | |
| }; | |
| enum sctp_conntrack { | |
| @@ -23522,6 +29633,54 @@ | |
| SCTP_EP_TYPE_ASSOCIATION = 1, | |
| }; | |
| +enum sctp_event_timeout { | |
| + SCTP_EVENT_TIMEOUT_NONE = 0, | |
| + SCTP_EVENT_TIMEOUT_T1_COOKIE = 1, | |
| + SCTP_EVENT_TIMEOUT_T1_INIT = 2, | |
| + SCTP_EVENT_TIMEOUT_T2_SHUTDOWN = 3, | |
| + SCTP_EVENT_TIMEOUT_T3_RTX = 4, | |
| + SCTP_EVENT_TIMEOUT_T4_RTO = 5, | |
| + SCTP_EVENT_TIMEOUT_T5_SHUTDOWN_GUARD = 6, | |
| + SCTP_EVENT_TIMEOUT_HEARTBEAT = 7, | |
| + SCTP_EVENT_TIMEOUT_RECONF = 8, | |
| + SCTP_EVENT_TIMEOUT_PROBE = 9, | |
| + SCTP_EVENT_TIMEOUT_SACK = 10, | |
| + SCTP_EVENT_TIMEOUT_AUTOCLOSE = 11, | |
| +}; | |
| + | |
| +enum sctp_msg_flags { | |
| + MSG_NOTIFICATION = 32768, | |
| +}; | |
| + | |
| +enum sctp_param { | |
| + SCTP_PARAM_HEARTBEAT_INFO = 256, | |
| + SCTP_PARAM_IPV4_ADDRESS = 1280, | |
| + SCTP_PARAM_IPV6_ADDRESS = 1536, | |
| + SCTP_PARAM_STATE_COOKIE = 1792, | |
| + SCTP_PARAM_UNRECOGNIZED_PARAMETERS = 2048, | |
| + SCTP_PARAM_COOKIE_PRESERVATIVE = 2304, | |
| + SCTP_PARAM_HOST_NAME_ADDRESS = 2816, | |
| + SCTP_PARAM_SUPPORTED_ADDRESS_TYPES = 3072, | |
| + SCTP_PARAM_ECN_CAPABLE = 128, | |
| + SCTP_PARAM_RANDOM = 640, | |
| + SCTP_PARAM_CHUNKS = 896, | |
| + SCTP_PARAM_HMAC_ALGO = 1152, | |
| + SCTP_PARAM_SUPPORTED_EXT = 2176, | |
| + SCTP_PARAM_FWD_TSN_SUPPORT = 192, | |
| + SCTP_PARAM_ADD_IP = 448, | |
| + SCTP_PARAM_DEL_IP = 704, | |
| + SCTP_PARAM_ERR_CAUSE = 960, | |
| + SCTP_PARAM_SET_PRIMARY = 1216, | |
| + SCTP_PARAM_SUCCESS_REPORT = 1472, | |
| + SCTP_PARAM_ADAPTATION_LAYER_IND = 1728, | |
| + SCTP_PARAM_RESET_OUT_REQUEST = 3328, | |
| + SCTP_PARAM_RESET_IN_REQUEST = 3584, | |
| + SCTP_PARAM_RESET_TSN_REQUEST = 3840, | |
| + SCTP_PARAM_RESET_RESPONSE = 4096, | |
| + SCTP_PARAM_RESET_ADD_OUT_STREAMS = 4352, | |
| + SCTP_PARAM_RESET_ADD_IN_STREAMS = 4608, | |
| +}; | |
| + | |
| enum sctp_scope { | |
| SCTP_SCOPE_GLOBAL = 0, | |
| SCTP_SCOPE_PRIVATE = 1, | |
| @@ -23547,114 +29706,48 @@ | |
| SCTP_STATE_SHUTDOWN_ACK_SENT = 7, | |
| }; | |
| -enum scx_cpu_preempt_reason { | |
| - SCX_CPU_PREEMPT_RT = 0, | |
| - SCX_CPU_PREEMPT_DL = 1, | |
| - SCX_CPU_PREEMPT_STOP = 2, | |
| - SCX_CPU_PREEMPT_UNKNOWN = 3, | |
| -}; | |
| - | |
| -enum scx_ent_dsq_flags { | |
| - SCX_TASK_DSQ_ON_PRIQ = 1, | |
| -}; | |
| - | |
| -enum scx_ent_flags { | |
| - SCX_TASK_QUEUED = 1, | |
| - SCX_TASK_BAL_KEEP = 2, | |
| - SCX_TASK_ENQ_LOCAL = 4, | |
| - SCX_TASK_OPS_PREPPED = 256, | |
| - SCX_TASK_OPS_ENABLED = 512, | |
| - SCX_TASK_WATCHDOG_RESET = 65536, | |
| - SCX_TASK_DEQD_FOR_SLEEP = 131072, | |
| - SCX_TASK_CURSOR = -2147483648, | |
| -}; | |
| - | |
| -enum scx_exit_type { | |
| - SCX_EXIT_NONE = 0, | |
| - SCX_EXIT_DONE = 1, | |
| - SCX_EXIT_UNREG = 64, | |
| - SCX_EXIT_SYSRQ = 65, | |
| - SCX_EXIT_ERROR = 1024, | |
| - SCX_EXIT_ERROR_BPF = 1025, | |
| - SCX_EXIT_ERROR_STALL = 1026, | |
| -}; | |
| - | |
| -enum scx_internal_consts { | |
| - SCX_NR_ONLINE_OPS = 27, | |
| - SCX_DSP_DFL_MAX_BATCH = 32, | |
| - SCX_DSP_MAX_LOOPS = 32, | |
| - SCX_WATCHDOG_MAX_TIMEOUT = 30000, | |
| -}; | |
| - | |
| -enum scx_kf_mask { | |
| - SCX_KF_UNLOCKED = 0, | |
| - SCX_KF_INIT = 1, | |
| - SCX_KF_SLEEPABLE = 2, | |
| - SCX_KF_CPU_RELEASE = 4, | |
| - SCX_KF_DISPATCH = 8, | |
| - SCX_KF_ENQUEUE = 16, | |
| - SCX_KF_REST = 32, | |
| - __SCX_KF_RQ_LOCKED = 60, | |
| - __SCX_KF_TERMINAL = 48, | |
| -}; | |
| - | |
| -enum scx_kick_flags { | |
| - SCX_KICK_PREEMPT = 1, | |
| - SCX_KICK_WAIT = 2, | |
| -}; | |
| - | |
| -enum scx_ops_enable_state { | |
| - SCX_OPS_PREPPING = 0, | |
| - SCX_OPS_ENABLING = 1, | |
| - SCX_OPS_ENABLED = 2, | |
| - SCX_OPS_DISABLING = 3, | |
| - SCX_OPS_DISABLED = 4, | |
| -}; | |
| - | |
| -enum scx_ops_flags { | |
| - SCX_OPS_KEEP_BUILTIN_IDLE = 1, | |
| - SCX_OPS_ENQ_LAST = 2, | |
| - SCX_OPS_ENQ_EXITING = 4, | |
| - SCX_OPS_CGROUP_KNOB_WEIGHT = 65536, | |
| - SCX_OPS_ALL_FLAGS = 65543, | |
| -}; | |
| +typedef enum { | |
| + search_hashChain = 0, | |
| + search_binaryTree = 1, | |
| + search_rowHash = 2, | |
| +} searchMethod_e; | |
| -enum scx_ops_state { | |
| - SCX_OPSS_NONE = 0, | |
| - SCX_OPSS_QUEUEING = 1, | |
| - SCX_OPSS_QUEUED = 2, | |
| - SCX_OPSS_DISPATCHING = 3, | |
| - SCX_OPSS_QSEQ_SHIFT = 2, | |
| - SCX_OPSS_STATE_MASK = 3, | |
| - SCX_OPSS_QSEQ_MASK = -4, | |
| -}; | |
| +typedef enum { | |
| + C46 = 6, | |
| + C56_66 = 8, | |
| +} seeprom_chip_t; | |
| -enum scx_pick_idle_cpu_flags { | |
| - SCX_PICK_IDLE_CORE = 1, | |
| +enum seg6_end_dt_mode { | |
| + DT_INVALID_MODE = -22, | |
| + DT_LEGACY_MODE = 0, | |
| + DT_VRF_MODE = 1, | |
| }; | |
| -enum scx_rq_flags { | |
| - SCX_RQ_CAN_STOP_TICK = 1, | |
| +enum seg6_local_flv_action { | |
| + SEG6_LOCAL_FLV_ACT_UNSPEC = 0, | |
| + SEG6_LOCAL_FLV_ACT_END = 1, | |
| + SEG6_LOCAL_FLV_ACT_PSP = 2, | |
| + SEG6_LOCAL_FLV_ACT_USP = 3, | |
| + SEG6_LOCAL_FLV_ACT_USD = 4, | |
| + __SEG6_LOCAL_FLV_ACT_MAX = 5, | |
| }; | |
| -enum scx_tg_flags { | |
| - SCX_TG_ONLINE = 1, | |
| - SCX_TG_INITED = 2, | |
| +enum seg6_local_pktinfo { | |
| + SEG6_LOCAL_PKTINFO_NOHDR = 0, | |
| + SEG6_LOCAL_PKTINFO_SL_ZERO = 1, | |
| + SEG6_LOCAL_PKTINFO_SL_ONE = 2, | |
| + SEG6_LOCAL_PKTINFO_SL_MORE = 3, | |
| + __SEG6_LOCAL_PKTINFO_MAX = 4, | |
| }; | |
| -enum scx_wake_flags { | |
| - SCX_WAKE_EXEC = 2, | |
| - SCX_WAKE_FORK = 4, | |
| - SCX_WAKE_TTWU = 8, | |
| - SCX_WAKE_SYNC = 16, | |
| +enum segment_cache_field { | |
| + SEG_FIELD_SEL = 0, | |
| + SEG_FIELD_BASE = 1, | |
| + SEG_FIELD_LIMIT = 2, | |
| + SEG_FIELD_AR = 3, | |
| + SEG_FIELD_NR = 4, | |
| }; | |
| -typedef enum { | |
| - search_hashChain = 0, | |
| - search_binaryTree = 1, | |
| - search_rowHash = 2, | |
| -} searchMethod_e; | |
| - | |
| enum sel_inos { | |
| SEL_ROOT_INO = 2, | |
| SEL_LOAD = 3, | |
| @@ -23698,6 +29791,16 @@ | |
| SERIO_ATTACH_DRIVER = 4, | |
| }; | |
| +enum service_response { | |
| + SAS_TASK_COMPLETE = 0, | |
| + SAS_TASK_UNDELIVERED = -1, | |
| +}; | |
| + | |
| +enum set_key_cmd { | |
| + SET_KEY = 0, | |
| + DISABLE_KEY = 1, | |
| +}; | |
| + | |
| enum severity_level { | |
| MCE_NO_SEVERITY = 0, | |
| MCE_DEFERRED_SEVERITY = 1, | |
| @@ -23728,33 +29831,8 @@ | |
| SGX_ATTR_ASYNC_EXIT_NOTIFY = 1024, | |
| }; | |
| -enum sgx_encl_flags { | |
| - SGX_ENCL_IOCTL = 1, | |
| - SGX_ENCL_DEBUG = 2, | |
| - SGX_ENCL_CREATED = 4, | |
| - SGX_ENCL_INITIALIZED = 8, | |
| -}; | |
| - | |
| -enum sgx_encls_function { | |
| - ECREATE = 0, | |
| - EADD = 1, | |
| - EINIT = 2, | |
| - EREMOVE = 3, | |
| - EDGBRD = 4, | |
| - EDGBWR = 5, | |
| - EEXTEND = 6, | |
| - ELDU = 8, | |
| - EBLOCK = 9, | |
| - EPA = 10, | |
| - EWB = 11, | |
| - ETRACK = 12, | |
| - EAUG = 13, | |
| - EMODPR = 14, | |
| - EMODT = 15, | |
| -}; | |
| - | |
| -enum sgx_page_flags { | |
| - SGX_PAGE_MEASURE = 1, | |
| +enum sgx_miscselect { | |
| + SGX_MISC_EXINFO = 1, | |
| }; | |
| enum sgx_page_type { | |
| @@ -23765,38 +29843,40 @@ | |
| SGX_PAGE_TYPE_TRIM = 4, | |
| }; | |
| -enum sgx_return_code { | |
| - SGX_EPC_PAGE_CONFLICT = 7, | |
| - SGX_NOT_TRACKED = 11, | |
| - SGX_CHILD_PRESENT = 13, | |
| - SGX_INVALID_EINITTOKEN = 16, | |
| - SGX_PAGE_NOT_MODIFIABLE = 20, | |
| - SGX_UNMASKED_EVENT = 128, | |
| +enum shf_op { | |
| + SHF_OP_NONE = 0, | |
| + SHF_OP_AND = 2, | |
| + SHF_OP_OR = 5, | |
| + SHF_OP_ASHR = 6, | |
| }; | |
| -enum sgx_secinfo_flags { | |
| - SGX_SECINFO_R = 1, | |
| - SGX_SECINFO_W = 2, | |
| - SGX_SECINFO_X = 4, | |
| - SGX_SECINFO_SECS = 0, | |
| - SGX_SECINFO_TCS = 256, | |
| - SGX_SECINFO_REG = 512, | |
| - SGX_SECINFO_VA = 768, | |
| - SGX_SECINFO_TRIM = 1024, | |
| +enum shf_sc { | |
| + SHF_SC_R_ROT = 0, | |
| + SHF_SC_NONE = 0, | |
| + SHF_SC_R_SHF = 1, | |
| + SHF_SC_L_SHF = 2, | |
| + SHF_SC_R_DSHF = 3, | |
| }; | |
| enum shmem_param { | |
| - Opt_gid___6 = 0, | |
| + Opt_gid___7 = 0, | |
| Opt_huge = 1, | |
| - Opt_mode___5 = 2, | |
| + Opt_mode___6 = 2, | |
| Opt_mpol = 3, | |
| Opt_nr_blocks = 4, | |
| Opt_nr_inodes___2 = 5, | |
| Opt_size___2 = 6, | |
| - Opt_uid___5 = 7, | |
| - Opt_inode32___2 = 8, | |
| - Opt_inode64___2 = 9, | |
| + Opt_uid___6 = 7, | |
| + Opt_inode32 = 8, | |
| + Opt_inode64 = 9, | |
| Opt_noswap = 10, | |
| + Opt_quota___2 = 11, | |
| + Opt_usrquota___2 = 12, | |
| + Opt_grpquota___2 = 13, | |
| + Opt_usrquota_block_hardlimit = 14, | |
| + Opt_usrquota_inode_hardlimit = 15, | |
| + Opt_grpquota_block_hardlimit = 16, | |
| + Opt_grpquota_inode_hardlimit = 17, | |
| }; | |
| enum show_regs_mode { | |
| @@ -23805,6 +29885,12 @@ | |
| SHOW_REGS_ALL = 2, | |
| }; | |
| +enum shrink_type { | |
| + SHRINK_DESTROY = 0, | |
| + SHRINK_BUSY_STOP = 1, | |
| + SHRINK_BUSY_SKIP = 2, | |
| +}; | |
| + | |
| enum si_type { | |
| SI_TYPE_INVALID = 0, | |
| SI_KCS = 1, | |
| @@ -23850,6 +29936,20 @@ | |
| SK_PSOCK_RX_STRP_ENABLED = 1, | |
| }; | |
| +enum sk_rst_reason { | |
| + SK_RST_REASON_NOT_SPECIFIED = 0, | |
| + SK_RST_REASON_NO_SOCKET = 1, | |
| + SK_RST_REASON_MPTCP_RST_EUNSPEC = 2, | |
| + SK_RST_REASON_MPTCP_RST_EMPTCP = 3, | |
| + SK_RST_REASON_MPTCP_RST_ERESOURCE = 4, | |
| + SK_RST_REASON_MPTCP_RST_EPROHIBIT = 5, | |
| + SK_RST_REASON_MPTCP_RST_EWQ2BIG = 6, | |
| + SK_RST_REASON_MPTCP_RST_EBADPERF = 7, | |
| + SK_RST_REASON_MPTCP_RST_EMIDDLEBOX = 8, | |
| + SK_RST_REASON_ERROR = 9, | |
| + SK_RST_REASON_MAX = 10, | |
| +}; | |
| + | |
| enum skb_drop_reason { | |
| SKB_NOT_DROPPED_YET = 0, | |
| SKB_CONSUMED = 1, | |
| @@ -23869,67 +29969,79 @@ | |
| SKB_DROP_REASON_IP_NOPROTO = 15, | |
| SKB_DROP_REASON_SOCKET_RCVBUFF = 16, | |
| SKB_DROP_REASON_PROTO_MEM = 17, | |
| - SKB_DROP_REASON_TCP_MD5NOTFOUND = 18, | |
| - SKB_DROP_REASON_TCP_MD5UNEXPECTED = 19, | |
| - SKB_DROP_REASON_TCP_MD5FAILURE = 20, | |
| - SKB_DROP_REASON_SOCKET_BACKLOG = 21, | |
| - SKB_DROP_REASON_TCP_FLAGS = 22, | |
| - SKB_DROP_REASON_TCP_ZEROWINDOW = 23, | |
| - SKB_DROP_REASON_TCP_OLD_DATA = 24, | |
| - SKB_DROP_REASON_TCP_OVERWINDOW = 25, | |
| - SKB_DROP_REASON_TCP_OFOMERGE = 26, | |
| - SKB_DROP_REASON_TCP_RFC7323_PAWS = 27, | |
| - SKB_DROP_REASON_TCP_INVALID_SEQUENCE = 28, | |
| - SKB_DROP_REASON_TCP_RESET = 29, | |
| - SKB_DROP_REASON_TCP_INVALID_SYN = 30, | |
| - SKB_DROP_REASON_TCP_CLOSE = 31, | |
| - SKB_DROP_REASON_TCP_FASTOPEN = 32, | |
| - SKB_DROP_REASON_TCP_OLD_ACK = 33, | |
| - SKB_DROP_REASON_TCP_TOO_OLD_ACK = 34, | |
| - SKB_DROP_REASON_TCP_ACK_UNSENT_DATA = 35, | |
| - SKB_DROP_REASON_TCP_OFO_QUEUE_PRUNE = 36, | |
| - SKB_DROP_REASON_TCP_OFO_DROP = 37, | |
| - SKB_DROP_REASON_IP_OUTNOROUTES = 38, | |
| - SKB_DROP_REASON_BPF_CGROUP_EGRESS = 39, | |
| - SKB_DROP_REASON_IPV6DISABLED = 40, | |
| - SKB_DROP_REASON_NEIGH_CREATEFAIL = 41, | |
| - SKB_DROP_REASON_NEIGH_FAILED = 42, | |
| - SKB_DROP_REASON_NEIGH_QUEUEFULL = 43, | |
| - SKB_DROP_REASON_NEIGH_DEAD = 44, | |
| - SKB_DROP_REASON_TC_EGRESS = 45, | |
| - SKB_DROP_REASON_QDISC_DROP = 46, | |
| - SKB_DROP_REASON_CPU_BACKLOG = 47, | |
| - SKB_DROP_REASON_XDP = 48, | |
| - SKB_DROP_REASON_TC_INGRESS = 49, | |
| - SKB_DROP_REASON_UNHANDLED_PROTO = 50, | |
| - SKB_DROP_REASON_SKB_CSUM = 51, | |
| - SKB_DROP_REASON_SKB_GSO_SEG = 52, | |
| - SKB_DROP_REASON_SKB_UCOPY_FAULT = 53, | |
| - SKB_DROP_REASON_DEV_HDR = 54, | |
| - SKB_DROP_REASON_DEV_READY = 55, | |
| - SKB_DROP_REASON_FULL_RING = 56, | |
| - SKB_DROP_REASON_NOMEM = 57, | |
| - SKB_DROP_REASON_HDR_TRUNC = 58, | |
| - SKB_DROP_REASON_TAP_FILTER = 59, | |
| - SKB_DROP_REASON_TAP_TXFILTER = 60, | |
| - SKB_DROP_REASON_ICMP_CSUM = 61, | |
| - SKB_DROP_REASON_INVALID_PROTO = 62, | |
| - SKB_DROP_REASON_IP_INADDRERRORS = 63, | |
| - SKB_DROP_REASON_IP_INNOROUTES = 64, | |
| - SKB_DROP_REASON_PKT_TOO_BIG = 65, | |
| - SKB_DROP_REASON_DUP_FRAG = 66, | |
| - SKB_DROP_REASON_FRAG_REASM_TIMEOUT = 67, | |
| - SKB_DROP_REASON_FRAG_TOO_FAR = 68, | |
| - SKB_DROP_REASON_TCP_MINTTL = 69, | |
| - SKB_DROP_REASON_IPV6_BAD_EXTHDR = 70, | |
| - SKB_DROP_REASON_IPV6_NDISC_FRAG = 71, | |
| - SKB_DROP_REASON_IPV6_NDISC_HOP_LIMIT = 72, | |
| - SKB_DROP_REASON_IPV6_NDISC_BAD_CODE = 73, | |
| - SKB_DROP_REASON_IPV6_NDISC_BAD_OPTIONS = 74, | |
| - SKB_DROP_REASON_IPV6_NDISC_NS_OTHERHOST = 75, | |
| - SKB_DROP_REASON_QUEUE_PURGE = 76, | |
| - SKB_DROP_REASON_TC_ERROR = 77, | |
| - SKB_DROP_REASON_MAX = 78, | |
| + SKB_DROP_REASON_TCP_AUTH_HDR = 18, | |
| + SKB_DROP_REASON_TCP_MD5NOTFOUND = 19, | |
| + SKB_DROP_REASON_TCP_MD5UNEXPECTED = 20, | |
| + SKB_DROP_REASON_TCP_MD5FAILURE = 21, | |
| + SKB_DROP_REASON_TCP_AONOTFOUND = 22, | |
| + SKB_DROP_REASON_TCP_AOUNEXPECTED = 23, | |
| + SKB_DROP_REASON_TCP_AOKEYNOTFOUND = 24, | |
| + SKB_DROP_REASON_TCP_AOFAILURE = 25, | |
| + SKB_DROP_REASON_SOCKET_BACKLOG = 26, | |
| + SKB_DROP_REASON_TCP_FLAGS = 27, | |
| + SKB_DROP_REASON_TCP_ABORT_ON_DATA = 28, | |
| + SKB_DROP_REASON_TCP_ZEROWINDOW = 29, | |
| + SKB_DROP_REASON_TCP_OLD_DATA = 30, | |
| + SKB_DROP_REASON_TCP_OVERWINDOW = 31, | |
| + SKB_DROP_REASON_TCP_OFOMERGE = 32, | |
| + SKB_DROP_REASON_TCP_RFC7323_PAWS = 33, | |
| + SKB_DROP_REASON_TCP_OLD_SEQUENCE = 34, | |
| + SKB_DROP_REASON_TCP_INVALID_SEQUENCE = 35, | |
| + SKB_DROP_REASON_TCP_INVALID_ACK_SEQUENCE = 36, | |
| + SKB_DROP_REASON_TCP_RESET = 37, | |
| + SKB_DROP_REASON_TCP_INVALID_SYN = 38, | |
| + SKB_DROP_REASON_TCP_CLOSE = 39, | |
| + SKB_DROP_REASON_TCP_FASTOPEN = 40, | |
| + SKB_DROP_REASON_TCP_OLD_ACK = 41, | |
| + SKB_DROP_REASON_TCP_TOO_OLD_ACK = 42, | |
| + SKB_DROP_REASON_TCP_ACK_UNSENT_DATA = 43, | |
| + SKB_DROP_REASON_TCP_OFO_QUEUE_PRUNE = 44, | |
| + SKB_DROP_REASON_TCP_OFO_DROP = 45, | |
| + SKB_DROP_REASON_IP_OUTNOROUTES = 46, | |
| + SKB_DROP_REASON_BPF_CGROUP_EGRESS = 47, | |
| + SKB_DROP_REASON_IPV6DISABLED = 48, | |
| + SKB_DROP_REASON_NEIGH_CREATEFAIL = 49, | |
| + SKB_DROP_REASON_NEIGH_FAILED = 50, | |
| + SKB_DROP_REASON_NEIGH_QUEUEFULL = 51, | |
| + SKB_DROP_REASON_NEIGH_DEAD = 52, | |
| + SKB_DROP_REASON_TC_EGRESS = 53, | |
| + SKB_DROP_REASON_SECURITY_HOOK = 54, | |
| + SKB_DROP_REASON_QDISC_DROP = 55, | |
| + SKB_DROP_REASON_CPU_BACKLOG = 56, | |
| + SKB_DROP_REASON_XDP = 57, | |
| + SKB_DROP_REASON_TC_INGRESS = 58, | |
| + SKB_DROP_REASON_UNHANDLED_PROTO = 59, | |
| + SKB_DROP_REASON_SKB_CSUM = 60, | |
| + SKB_DROP_REASON_SKB_GSO_SEG = 61, | |
| + SKB_DROP_REASON_SKB_UCOPY_FAULT = 62, | |
| + SKB_DROP_REASON_DEV_HDR = 63, | |
| + SKB_DROP_REASON_DEV_READY = 64, | |
| + SKB_DROP_REASON_FULL_RING = 65, | |
| + SKB_DROP_REASON_NOMEM = 66, | |
| + SKB_DROP_REASON_HDR_TRUNC = 67, | |
| + SKB_DROP_REASON_TAP_FILTER = 68, | |
| + SKB_DROP_REASON_TAP_TXFILTER = 69, | |
| + SKB_DROP_REASON_ICMP_CSUM = 70, | |
| + SKB_DROP_REASON_INVALID_PROTO = 71, | |
| + SKB_DROP_REASON_IP_INADDRERRORS = 72, | |
| + SKB_DROP_REASON_IP_INNOROUTES = 73, | |
| + SKB_DROP_REASON_PKT_TOO_BIG = 74, | |
| + SKB_DROP_REASON_DUP_FRAG = 75, | |
| + SKB_DROP_REASON_FRAG_REASM_TIMEOUT = 76, | |
| + SKB_DROP_REASON_FRAG_TOO_FAR = 77, | |
| + SKB_DROP_REASON_TCP_MINTTL = 78, | |
| + SKB_DROP_REASON_IPV6_BAD_EXTHDR = 79, | |
| + SKB_DROP_REASON_IPV6_NDISC_FRAG = 80, | |
| + SKB_DROP_REASON_IPV6_NDISC_HOP_LIMIT = 81, | |
| + SKB_DROP_REASON_IPV6_NDISC_BAD_CODE = 82, | |
| + SKB_DROP_REASON_IPV6_NDISC_BAD_OPTIONS = 83, | |
| + SKB_DROP_REASON_IPV6_NDISC_NS_OTHERHOST = 84, | |
| + SKB_DROP_REASON_QUEUE_PURGE = 85, | |
| + SKB_DROP_REASON_TC_COOKIE_ERROR = 86, | |
| + SKB_DROP_REASON_PACKET_SOCK_ERROR = 87, | |
| + SKB_DROP_REASON_TC_CHAIN_NOTFOUND = 88, | |
| + SKB_DROP_REASON_TC_RECLASSIFY_LOOP = 89, | |
| + SKB_DROP_REASON_MAX = 90, | |
| SKB_DROP_REASON_SUBSYS_MASK = 4294901760, | |
| }; | |
| @@ -23937,13 +30049,15 @@ | |
| SKB_DROP_REASON_SUBSYS_CORE = 0, | |
| SKB_DROP_REASON_SUBSYS_MAC80211_UNUSABLE = 1, | |
| SKB_DROP_REASON_SUBSYS_MAC80211_MONITOR = 2, | |
| - SKB_DROP_REASON_SUBSYS_NUM = 3, | |
| + SKB_DROP_REASON_SUBSYS_OPENVSWITCH = 3, | |
| + SKB_DROP_REASON_SUBSYS_NUM = 4, | |
| }; | |
| enum skb_ext_id { | |
| SKB_EXT_BRIDGE_NF = 0, | |
| SKB_EXT_SEC_PATH = 1, | |
| - SKB_EXT_NUM = 2, | |
| + SKB_EXT_MPTCP = 2, | |
| + SKB_EXT_NUM = 3, | |
| }; | |
| enum sknetlink_groups { | |
| @@ -23955,13 +30069,6 @@ | |
| __SKNLGRP_MAX = 5, | |
| }; | |
| -enum slab_modes { | |
| - M_NONE = 0, | |
| - M_PARTIAL = 1, | |
| - M_FREE = 2, | |
| - M_FULL_NOLIST = 3, | |
| -}; | |
| - | |
| enum slab_stat_type { | |
| SL_ALL = 0, | |
| SL_PARTIAL = 1, | |
| @@ -23973,9 +30080,8 @@ | |
| enum slab_state { | |
| DOWN = 0, | |
| PARTIAL = 1, | |
| - PARTIAL_NODE = 2, | |
| - UP = 3, | |
| - FULL = 4, | |
| + UP = 2, | |
| + FULL = 3, | |
| }; | |
| enum slave_port_gen_event { | |
| @@ -24018,31 +30124,34 @@ | |
| SMCA_PIE = 11, | |
| SMCA_UMC = 12, | |
| SMCA_UMC_V2 = 13, | |
| - SMCA_PB = 14, | |
| - SMCA_PSP = 15, | |
| - SMCA_PSP_V2 = 16, | |
| - SMCA_SMU = 17, | |
| - SMCA_SMU_V2 = 18, | |
| - SMCA_MP5 = 19, | |
| - SMCA_MPDMA = 20, | |
| - SMCA_NBIO = 21, | |
| - SMCA_PCIE = 22, | |
| - SMCA_PCIE_V2 = 23, | |
| - SMCA_XGMI_PCS = 24, | |
| - SMCA_NBIF = 25, | |
| - SMCA_SHUB = 26, | |
| - SMCA_SATA = 27, | |
| - SMCA_USB = 28, | |
| - SMCA_GMI_PCS = 29, | |
| - SMCA_XGMI_PHY = 30, | |
| - SMCA_WAFL_PHY = 31, | |
| - SMCA_GMI_PHY = 32, | |
| - N_SMCA_BANK_TYPES = 33, | |
| + SMCA_MA_LLC = 14, | |
| + SMCA_PB = 15, | |
| + SMCA_PSP = 16, | |
| + SMCA_PSP_V2 = 17, | |
| + SMCA_SMU = 18, | |
| + SMCA_SMU_V2 = 19, | |
| + SMCA_MP5 = 20, | |
| + SMCA_MPDMA = 21, | |
| + SMCA_NBIO = 22, | |
| + SMCA_PCIE = 23, | |
| + SMCA_PCIE_V2 = 24, | |
| + SMCA_XGMI_PCS = 25, | |
| + SMCA_NBIF = 26, | |
| + SMCA_SHUB = 27, | |
| + SMCA_SATA = 28, | |
| + SMCA_USB = 29, | |
| + SMCA_USR_DP = 30, | |
| + SMCA_USR_CP = 31, | |
| + SMCA_GMI_PCS = 32, | |
| + SMCA_XGMI_PHY = 33, | |
| + SMCA_WAFL_PHY = 34, | |
| + SMCA_GMI_PHY = 35, | |
| + N_SMCA_BANK_TYPES = 36, | |
| }; | |
| enum snoop_when { | |
| SUBMIT = 0, | |
| - COMPLETE___2 = 1, | |
| + COMPLETE = 1, | |
| }; | |
| enum sock_flags { | |
| @@ -24100,6 +30209,10 @@ | |
| SS_DISCONNECTING = 4, | |
| } socket_state; | |
| +enum sony_worker { | |
| + SONY_WORKER_STATE = 0, | |
| +}; | |
| + | |
| enum special_kfunc_type { | |
| KF_bpf_obj_new_impl = 0, | |
| KF_bpf_obj_drop_impl = 1, | |
| @@ -24123,7 +30236,11 @@ | |
| KF_bpf_percpu_obj_new_impl = 19, | |
| KF_bpf_percpu_obj_drop_impl = 20, | |
| KF_bpf_throw = 21, | |
| - KF_bpf_iter_css_task_new = 22, | |
| + KF_bpf_wq_set_callback_impl = 22, | |
| + KF_bpf_preempt_disable = 23, | |
| + KF_bpf_preempt_enable = 24, | |
| + KF_bpf_iter_css_task_new = 25, | |
| + KF_bpf_session_cookie = 26, | |
| }; | |
| enum spectre_v1_mitigation { | |
| @@ -24172,10 +30289,17 @@ | |
| SPECTRE_V2_USER_SECCOMP = 4, | |
| }; | |
| -enum spi_mem_data_dir { | |
| - SPI_MEM_NO_DATA = 0, | |
| - SPI_MEM_DATA_IN = 1, | |
| - SPI_MEM_DATA_OUT = 2, | |
| +enum spi_compare_returns { | |
| + SPI_COMPARE_SUCCESS = 0, | |
| + SPI_COMPARE_FAILURE = 1, | |
| + SPI_COMPARE_SKIP_TEST = 2, | |
| +}; | |
| + | |
| +enum spi_signal_type { | |
| + SPI_SIGNAL_UNKNOWN = 1, | |
| + SPI_SIGNAL_SE = 2, | |
| + SPI_SIGNAL_LVD = 3, | |
| + SPI_SIGNAL_HVD = 4, | |
| }; | |
| enum split_lock_detect_state { | |
| @@ -24193,6 +30317,24 @@ | |
| SRBDS_MITIGATION_HYPERVISOR = 4, | |
| }; | |
| +enum srso_mitigation { | |
| + SRSO_MITIGATION_NONE = 0, | |
| + SRSO_MITIGATION_UCODE_NEEDED = 1, | |
| + SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED = 2, | |
| + SRSO_MITIGATION_MICROCODE = 3, | |
| + SRSO_MITIGATION_SAFE_RET = 4, | |
| + SRSO_MITIGATION_IBPB = 5, | |
| + SRSO_MITIGATION_IBPB_ON_VMEXIT = 6, | |
| +}; | |
| + | |
| +enum srso_mitigation_cmd { | |
| + SRSO_CMD_OFF = 0, | |
| + SRSO_CMD_MICROCODE = 1, | |
| + SRSO_CMD_SAFE_RET = 2, | |
| + SRSO_CMD_IBPB = 3, | |
| + SRSO_CMD_IBPB_ON_VMEXIT = 4, | |
| +}; | |
| + | |
| enum ssb_mitigation { | |
| SPEC_STORE_BYPASS_NONE = 0, | |
| SPEC_STORE_BYPASS_DISABLE = 1, | |
| @@ -24208,6 +30350,21 @@ | |
| SPEC_STORE_BYPASS_CMD_SECCOMP = 4, | |
| }; | |
| +enum sta_notify_cmd { | |
| + STA_NOTIFY_SLEEP = 0, | |
| + STA_NOTIFY_AWAKE = 1, | |
| +}; | |
| + | |
| +enum sta_stats_type { | |
| + STA_STATS_RATE_TYPE_INVALID = 0, | |
| + STA_STATS_RATE_TYPE_LEGACY = 1, | |
| + STA_STATS_RATE_TYPE_HT = 2, | |
| + STA_STATS_RATE_TYPE_VHT = 3, | |
| + STA_STATS_RATE_TYPE_HE = 4, | |
| + STA_STATS_RATE_TYPE_S1G = 5, | |
| + STA_STATS_RATE_TYPE_EHT = 6, | |
| +}; | |
| + | |
| enum stack_type { | |
| STACK_TYPE_UNKNOWN = 0, | |
| STACK_TYPE_TASK = 1, | |
| @@ -24267,11 +30424,18 @@ | |
| Reset = 7, | |
| }; | |
| -typedef enum { | |
| - STATUSTYPE_INFO = 0, | |
| - STATUSTYPE_TABLE = 1, | |
| - STATUSTYPE_IMA = 2, | |
| -} status_type_t; | |
| +enum static_regs { | |
| + STATIC_REG_IMMA = 20, | |
| + STATIC_REG_IMM = 21, | |
| + STATIC_REG_STACK = 22, | |
| + STATIC_REG_PKT_LEN = 22, | |
| +}; | |
| + | |
| +enum station_parameters_apply_mask { | |
| + STATION_PARAM_APPLY_UAPSD = 1, | |
| + STATION_PARAM_APPLY_CAPABILITY = 2, | |
| + STATION_PARAM_APPLY_PLINK_STATE = 4, | |
| +}; | |
| typedef enum { | |
| not_streaming = 0, | |
| @@ -24287,13 +30451,14 @@ | |
| enum string_size_units { | |
| STRING_UNITS_10 = 0, | |
| STRING_UNITS_2 = 1, | |
| + STRING_UNITS_MASK = 1, | |
| + STRING_UNITS_NO_SPACE = 1073741824, | |
| + STRING_UNITS_NO_BYTES = 2147483648, | |
| }; | |
| -enum subparts_cmd { | |
| - partcmd_enable = 0, | |
| - partcmd_disable = 1, | |
| - partcmd_update = 2, | |
| - partcmd_invalidate = 3, | |
| +enum sum_check_bits { | |
| + SUM_CHECK_P = 0, | |
| + SUM_CHECK_Q = 1, | |
| }; | |
| enum sum_check_flags { | |
| @@ -24306,10 +30471,41 @@ | |
| DENY_LEGACY = 1, | |
| }; | |
| -enum suspend_mode { | |
| - PRESUSPEND = 0, | |
| - PRESUSPEND_UNDO = 1, | |
| - POSTSUSPEND = 2, | |
| +enum survey_info_flags { | |
| + SURVEY_INFO_NOISE_DBM = 1, | |
| + SURVEY_INFO_IN_USE = 2, | |
| + SURVEY_INFO_TIME = 4, | |
| + SURVEY_INFO_TIME_BUSY = 8, | |
| + SURVEY_INFO_TIME_EXT_BUSY = 16, | |
| + SURVEY_INFO_TIME_RX = 32, | |
| + SURVEY_INFO_TIME_TX = 64, | |
| + SURVEY_INFO_TIME_SCAN = 128, | |
| + SURVEY_INFO_TIME_BSS_RX = 256, | |
| +}; | |
| + | |
| +enum suspend_stat_step { | |
| + SUSPEND_WORKING = 0, | |
| + SUSPEND_FREEZE = 1, | |
| + SUSPEND_PREPARE = 2, | |
| + SUSPEND_SUSPEND = 3, | |
| + SUSPEND_SUSPEND_LATE = 4, | |
| + SUSPEND_SUSPEND_NOIRQ = 5, | |
| + SUSPEND_RESUME_NOIRQ = 6, | |
| + SUSPEND_RESUME_EARLY = 7, | |
| + SUSPEND_RESUME = 8, | |
| +}; | |
| + | |
| +enum svc_auth_status { | |
| + SVC_GARBAGE = 1, | |
| + SVC_SYSERR = 2, | |
| + SVC_VALID = 3, | |
| + SVC_NEGATIVE = 4, | |
| + SVC_OK = 5, | |
| + SVC_DROP = 6, | |
| + SVC_CLOSE = 7, | |
| + SVC_DENIED = 8, | |
| + SVC_PENDING = 9, | |
| + SVC_COMPLETE = 10, | |
| }; | |
| enum sw_activity { | |
| @@ -24352,20 +30548,7 @@ | |
| SWITCHDEV_VXLAN_FDB_OFFLOADED = 14, | |
| SWITCHDEV_BRPORT_OFFLOADED = 15, | |
| SWITCHDEV_BRPORT_UNOFFLOADED = 16, | |
| -}; | |
| - | |
| -enum switchdev_obj_id { | |
| - SWITCHDEV_OBJ_ID_UNDEFINED = 0, | |
| - SWITCHDEV_OBJ_ID_PORT_VLAN = 1, | |
| - SWITCHDEV_OBJ_ID_PORT_MDB = 2, | |
| - SWITCHDEV_OBJ_ID_HOST_MDB = 3, | |
| - SWITCHDEV_OBJ_ID_MRP = 4, | |
| - SWITCHDEV_OBJ_ID_RING_TEST_MRP = 5, | |
| - SWITCHDEV_OBJ_ID_RING_ROLE_MRP = 6, | |
| - SWITCHDEV_OBJ_ID_RING_STATE_MRP = 7, | |
| - SWITCHDEV_OBJ_ID_IN_TEST_MRP = 8, | |
| - SWITCHDEV_OBJ_ID_IN_ROLE_MRP = 9, | |
| - SWITCHDEV_OBJ_ID_IN_STATE_MRP = 10, | |
| + SWITCHDEV_BRPORT_REPLAY = 17, | |
| }; | |
| typedef enum { | |
| @@ -24375,10 +30558,11 @@ | |
| set_repeat = 3, | |
| } symbolEncodingType_e; | |
| -enum sync_rst_state_type { | |
| - MLX5_SYNC_RST_STATE_RESET_REQUEST = 0, | |
| - MLX5_SYNC_RST_STATE_RESET_NOW = 1, | |
| - MLX5_SYNC_RST_STATE_RESET_ABORT = 2, | |
| +enum synaptics_pkt_type { | |
| + SYN_NEWABS = 0, | |
| + SYN_NEWABS_STRICT = 1, | |
| + SYN_NEWABS_RELAXED = 2, | |
| + SYN_OLDABS = 3, | |
| }; | |
| enum sys_off_mode { | |
| @@ -24429,6 +30613,21 @@ | |
| TAA_MITIGATION_TSX_DISABLED = 3, | |
| }; | |
| +enum task_attribute { | |
| + TASK_ATTR_SIMPLE = 0, | |
| + TASK_ATTR_HOQ = 1, | |
| + TASK_ATTR_ORDERED = 2, | |
| + TASK_ATTR_ACA = 4, | |
| +}; | |
| + | |
| +enum task_disposition { | |
| + TASK_IS_DONE = 0, | |
| + TASK_IS_ABORTED = 1, | |
| + TASK_IS_AT_LU = 2, | |
| + TASK_IS_NOT_AT_LU = 3, | |
| + TASK_ABORT_FAILED = 4, | |
| +}; | |
| + | |
| enum task_work_notify_mode { | |
| TWA_NONE = 0, | |
| TWA_RESUME = 1, | |
| @@ -24436,6 +30635,11 @@ | |
| TWA_SIGNAL_NO_IPI = 3, | |
| }; | |
| +enum tc_clsbpf_command { | |
| + TC_CLSBPF_OFFLOAD = 0, | |
| + TC_CLSBPF_STATS = 1, | |
| +}; | |
| + | |
| enum tc_clsu32_command { | |
| TC_CLSU32_NEW_KNODE = 0, | |
| TC_CLSU32_REPLACE_KNODE = 1, | |
| @@ -24451,18 +30655,6 @@ | |
| TC_FIFO_STATS = 2, | |
| }; | |
| -enum tc_htb_command { | |
| - TC_HTB_CREATE = 0, | |
| - TC_HTB_DESTROY = 1, | |
| - TC_HTB_LEAF_ALLOC_QUEUE = 2, | |
| - TC_HTB_LEAF_TO_INNER = 3, | |
| - TC_HTB_LEAF_DEL = 4, | |
| - TC_HTB_LEAF_DEL_LAST = 5, | |
| - TC_HTB_LEAF_DEL_LAST_FORCE = 6, | |
| - TC_HTB_NODE_MODIFY = 7, | |
| - TC_HTB_LEAF_QUERY_QUEUE = 8, | |
| -}; | |
| - | |
| enum tc_link_layer { | |
| TC_LINKLAYER_UNAWARE = 0, | |
| TC_LINKLAYER_ETHERNET = 1, | |
| @@ -24504,6 +30696,13 @@ | |
| TC_SETUP_ACT = 20, | |
| }; | |
| +enum tc_taprio_qopt_cmd { | |
| + TAPRIO_CMD_REPLACE = 0, | |
| + TAPRIO_CMD_DESTROY = 1, | |
| + TAPRIO_CMD_STATS = 2, | |
| + TAPRIO_CMD_QUEUE_STATS = 3, | |
| +}; | |
| + | |
| enum tca_id { | |
| TCA_ID_UNSPEC = 0, | |
| TCA_ID_POLICE = 1, | |
| @@ -24534,6 +30733,15 @@ | |
| TCF_PROTO_OPS_DOIT_UNLOCKED = 1, | |
| }; | |
| +enum tcp_bit_set { | |
| + TCP_SYN_SET = 0, | |
| + TCP_SYNACK_SET = 1, | |
| + TCP_FIN_SET = 2, | |
| + TCP_ACK_SET = 3, | |
| + TCP_RST_SET = 4, | |
| + TCP_NONE_SET = 5, | |
| +}; | |
| + | |
| enum tcp_ca_ack_event_flags { | |
| CA_ACK_SLOWPATH = 1, | |
| CA_ACK_WIN_UPDATE = 2, | |
| @@ -24565,6 +30773,24 @@ | |
| __TCP_CHRONO_MAX = 4, | |
| }; | |
| +enum tcp_conntrack { | |
| + TCP_CONNTRACK_NONE = 0, | |
| + TCP_CONNTRACK_SYN_SENT = 1, | |
| + TCP_CONNTRACK_SYN_RECV = 2, | |
| + TCP_CONNTRACK_ESTABLISHED = 3, | |
| + TCP_CONNTRACK_FIN_WAIT = 4, | |
| + TCP_CONNTRACK_CLOSE_WAIT = 5, | |
| + TCP_CONNTRACK_LAST_ACK = 6, | |
| + TCP_CONNTRACK_TIME_WAIT = 7, | |
| + TCP_CONNTRACK_CLOSE = 8, | |
| + TCP_CONNTRACK_LISTEN = 9, | |
| + TCP_CONNTRACK_MAX = 10, | |
| + TCP_CONNTRACK_IGNORE = 11, | |
| + TCP_CONNTRACK_RETRANS = 12, | |
| + TCP_CONNTRACK_UNACK = 13, | |
| + TCP_CONNTRACK_TIMEOUT_MAX = 14, | |
| +}; | |
| + | |
| enum tcp_fastopen_client_fail { | |
| TFO_STATUS_UNSPEC = 0, | |
| TFO_COOKIE_UNAVAILABLE = 1, | |
| @@ -24593,6 +30819,16 @@ | |
| TCP_SEQ_STATE_ESTABLISHED = 1, | |
| }; | |
| +enum tcp_skb_cb_sacked_flags { | |
| + TCPCB_SACKED_ACKED = 1, | |
| + TCPCB_SACKED_RETRANS = 2, | |
| + TCPCB_LOST = 4, | |
| + TCPCB_TAGBITS = 7, | |
| + TCPCB_REPAIRED = 16, | |
| + TCPCB_EVER_RETRANS = 128, | |
| + TCPCB_RETRANS = 146, | |
| +}; | |
| + | |
| enum tcp_synack_type { | |
| TCP_SYNACK_NORMAL = 0, | |
| TCP_SYNACK_FASTOPEN = 1, | |
| @@ -24671,6 +30907,9 @@ | |
| THERMAL_DEVICE_POWER_CAPABILITY_CHANGED = 6, | |
| THERMAL_TABLE_CHANGED = 7, | |
| THERMAL_EVENT_KEEP_ALIVE = 8, | |
| + THERMAL_TZ_BIND_CDEV = 9, | |
| + THERMAL_TZ_UNBIND_CDEV = 10, | |
| + THERMAL_INSTANCE_WEIGHT_CHANGED = 11, | |
| }; | |
| enum thermal_trend { | |
| @@ -24711,12 +30950,6 @@ | |
| TICKDEV_MODE_ONESHOT = 1, | |
| }; | |
| -enum tick_nohz_mode { | |
| - NOHZ_MODE_INACTIVE = 0, | |
| - NOHZ_MODE_LOWRES = 1, | |
| - NOHZ_MODE_HIGHRES = 2, | |
| -}; | |
| - | |
| enum timekeeping_adv_mode { | |
| TK_ADV_TICK = 0, | |
| TK_ADV_FREQ = 1, | |
| @@ -24762,6 +30995,7 @@ | |
| TPM_STS_GO = 32, | |
| TPM_STS_DATA_AVAIL = 16, | |
| TPM_STS_DATA_EXPECT = 8, | |
| + TPM_STS_RESPONSE_RETRY = 2, | |
| TPM_STS_READ_ZERO = 35, | |
| }; | |
| @@ -24786,6 +31020,21 @@ | |
| NR_INFO = 1, | |
| }; | |
| +enum topo_types { | |
| + INVALID_TYPE = 0, | |
| + SMT_TYPE = 1, | |
| + CORE_TYPE = 2, | |
| + MAX_TYPE_0B = 3, | |
| + MODULE_TYPE = 3, | |
| + AMD_CCD_TYPE = 3, | |
| + TILE_TYPE = 4, | |
| + AMD_SOCKET_TYPE = 4, | |
| + MAX_TYPE_80000026 = 5, | |
| + DIE_TYPE = 5, | |
| + DIEGRP_TYPE = 6, | |
| + MAX_TYPE_1F = 7, | |
| +}; | |
| + | |
| enum tp_func_state { | |
| TP_FUNC_0 = 0, | |
| TP_FUNC_1 = 1, | |
| @@ -24857,82 +31106,12 @@ | |
| TPM2_HT_TRANSIENT = 2147483648, | |
| }; | |
| -enum tpm2_properties { | |
| - TPM_PT_TOTAL_COMMANDS = 297, | |
| +enum tpm2_permanent_handles { | |
| + TPM2_RS_PW = 1073741833, | |
| }; | |
| -enum tpm2_pt_props { | |
| - TPM2_PT_NONE = 0, | |
| - TPM2_PT_GROUP = 256, | |
| - TPM2_PT_FIXED = 256, | |
| - TPM2_PT_FAMILY_INDICATOR = 256, | |
| - TPM2_PT_LEVEL = 257, | |
| - TPM2_PT_REVISION = 258, | |
| - TPM2_PT_DAY_OF_YEAR = 259, | |
| - TPM2_PT_YEAR = 260, | |
| - TPM2_PT_MANUFACTURER = 261, | |
| - TPM2_PT_VENDOR_STRING_1 = 262, | |
| - TPM2_PT_VENDOR_STRING_2 = 263, | |
| - TPM2_PT_VENDOR_STRING_3 = 264, | |
| - TPM2_PT_VENDOR_STRING_4 = 265, | |
| - TPM2_PT_VENDOR_TPM_TYPE = 266, | |
| - TPM2_PT_FIRMWARE_VERSION_1 = 267, | |
| - TPM2_PT_FIRMWARE_VERSION_2 = 268, | |
| - TPM2_PT_INPUT_BUFFER = 269, | |
| - TPM2_PT_HR_TRANSIENT_MIN = 270, | |
| - TPM2_PT_HR_PERSISTENT_MIN = 271, | |
| - TPM2_PT_HR_LOADED_MIN = 272, | |
| - TPM2_PT_ACTIVE_SESSIONS_MAX = 273, | |
| - TPM2_PT_PCR_COUNT = 274, | |
| - TPM2_PT_PCR_SELECT_MIN = 275, | |
| - TPM2_PT_CONTEXT_GAP_MAX = 276, | |
| - TPM2_PT_NV_COUNTERS_MAX = 278, | |
| - TPM2_PT_NV_INDEX_MAX = 279, | |
| - TPM2_PT_MEMORY = 280, | |
| - TPM2_PT_CLOCK_UPDATE = 281, | |
| - TPM2_PT_CONTEXT_HASH = 282, | |
| - TPM2_PT_CONTEXT_SYM = 283, | |
| - TPM2_PT_CONTEXT_SYM_SIZE = 284, | |
| - TPM2_PT_ORDERLY_COUNT = 285, | |
| - TPM2_PT_MAX_COMMAND_SIZE = 286, | |
| - TPM2_PT_MAX_RESPONSE_SIZE = 287, | |
| - TPM2_PT_MAX_DIGEST = 288, | |
| - TPM2_PT_MAX_OBJECT_CONTEXT = 289, | |
| - TPM2_PT_MAX_SESSION_CONTEXT = 290, | |
| - TPM2_PT_PS_FAMILY_INDICATOR = 291, | |
| - TPM2_PT_PS_LEVEL = 292, | |
| - TPM2_PT_PS_REVISION = 293, | |
| - TPM2_PT_PS_DAY_OF_YEAR = 294, | |
| - TPM2_PT_PS_YEAR = 295, | |
| - TPM2_PT_SPLIT_MAX = 296, | |
| - TPM2_PT_TOTAL_COMMANDS = 297, | |
| - TPM2_PT_LIBRARY_COMMANDS = 298, | |
| - TPM2_PT_VENDOR_COMMANDS = 299, | |
| - TPM2_PT_NV_BUFFER_MAX = 300, | |
| - TPM2_PT_MODES = 301, | |
| - TPM2_PT_MAX_CAP_BUFFER = 302, | |
| - TPM2_PT_VAR = 512, | |
| - TPM2_PT_PERMANENT = 512, | |
| - TPM2_PT_STARTUP_CLEAR = 513, | |
| - TPM2_PT_HR_NV_INDEX = 514, | |
| - TPM2_PT_HR_LOADED = 515, | |
| - TPM2_PT_HR_LOADED_AVAIL = 516, | |
| - TPM2_PT_HR_ACTIVE = 517, | |
| - TPM2_PT_HR_ACTIVE_AVAIL = 518, | |
| - TPM2_PT_HR_TRANSIENT_AVAIL = 519, | |
| - TPM2_PT_HR_PERSISTENT = 520, | |
| - TPM2_PT_HR_PERSISTENT_AVAIL = 521, | |
| - TPM2_PT_NV_COUNTERS = 522, | |
| - TPM2_PT_NV_COUNTERS_AVAIL = 523, | |
| - TPM2_PT_ALGORITHM_SET = 524, | |
| - TPM2_PT_LOADED_CURVES = 525, | |
| - TPM2_PT_LOCKOUT_COUNTER = 526, | |
| - TPM2_PT_MAX_AUTH_FAIL = 527, | |
| - TPM2_PT_LOCKOUT_INTERVAL = 528, | |
| - TPM2_PT_LOCKOUT_RECOVERY = 529, | |
| - TPM2_PT_NV_WRITE_RECOVERY = 530, | |
| - TPM2_PT_AUDIT_COUNTER_0 = 531, | |
| - TPM2_PT_AUDIT_COUNTER_1 = 532, | |
| +enum tpm2_properties { | |
| + TPM_PT_TOTAL_COMMANDS = 297, | |
| }; | |
| enum tpm2_return_codes { | |
| @@ -25003,6 +31182,7 @@ | |
| TPM_CHIP_FLAG_FIRMWARE_POWER_MANAGED = 64, | |
| TPM_CHIP_FLAG_FIRMWARE_UPGRADE = 128, | |
| TPM_CHIP_FLAG_SUSPENDED = 256, | |
| + TPM_CHIP_FLAG_HWRNG_DISABLED = 512, | |
| }; | |
| enum tpm_duration { | |
| @@ -25069,6 +31249,39 @@ | |
| TRACE_FILE_TIME_IN_NS = 4, | |
| }; | |
| +enum trace_iterator_bits { | |
| + TRACE_ITER_PRINT_PARENT_BIT = 0, | |
| + TRACE_ITER_SYM_OFFSET_BIT = 1, | |
| + TRACE_ITER_SYM_ADDR_BIT = 2, | |
| + TRACE_ITER_VERBOSE_BIT = 3, | |
| + TRACE_ITER_RAW_BIT = 4, | |
| + TRACE_ITER_HEX_BIT = 5, | |
| + TRACE_ITER_BIN_BIT = 6, | |
| + TRACE_ITER_BLOCK_BIT = 7, | |
| + TRACE_ITER_FIELDS_BIT = 8, | |
| + TRACE_ITER_PRINTK_BIT = 9, | |
| + TRACE_ITER_ANNOTATE_BIT = 10, | |
| + TRACE_ITER_USERSTACKTRACE_BIT = 11, | |
| + TRACE_ITER_SYM_USEROBJ_BIT = 12, | |
| + TRACE_ITER_PRINTK_MSGONLY_BIT = 13, | |
| + TRACE_ITER_CONTEXT_INFO_BIT = 14, | |
| + TRACE_ITER_LATENCY_FMT_BIT = 15, | |
| + TRACE_ITER_RECORD_CMD_BIT = 16, | |
| + TRACE_ITER_RECORD_TGID_BIT = 17, | |
| + TRACE_ITER_OVERWRITE_BIT = 18, | |
| + TRACE_ITER_STOP_ON_FREE_BIT = 19, | |
| + TRACE_ITER_IRQ_INFO_BIT = 20, | |
| + TRACE_ITER_MARKERS_BIT = 21, | |
| + TRACE_ITER_EVENT_FORK_BIT = 22, | |
| + TRACE_ITER_PAUSE_ON_TRACE_BIT = 23, | |
| + TRACE_ITER_HASH_PTR_BIT = 24, | |
| + TRACE_ITER_FUNCTION_BIT = 25, | |
| + TRACE_ITER_FUNC_FORK_BIT = 26, | |
| + TRACE_ITER_DISPLAY_GRAPH_BIT = 27, | |
| + TRACE_ITER_STACKTRACE_BIT = 28, | |
| + TRACE_ITER_LAST_BIT = 29, | |
| +}; | |
| + | |
| enum trace_iterator_flags { | |
| TRACE_ITER_PRINT_PARENT = 1, | |
| TRACE_ITER_SYM_OFFSET = 2, | |
| @@ -25136,20 +31349,6 @@ | |
| __TRACE_LAST_TYPE = 20, | |
| }; | |
| -enum tracer_ctrl_fields_select { | |
| - TRACE_STATUS = 1, | |
| -}; | |
| - | |
| -enum tracer_event_type { | |
| - TRACER_EVENT_TYPE_STRING = 0, | |
| - TRACER_EVENT_TYPE_TIMESTAMP = 255, | |
| - TRACER_EVENT_TYPE_UNRECOGNIZED = 256, | |
| -}; | |
| - | |
| -enum tracing_mode { | |
| - TRACE_TO_MEMORY = 1, | |
| -}; | |
| - | |
| enum track_item { | |
| TRACK_ALLOC = 0, | |
| TRACK_FREE = 1, | |
| @@ -25183,6 +31382,7 @@ | |
| TCP_WRITE_TIMER_DEFERRED = 3, | |
| TCP_DELACK_TIMER_DEFERRED = 4, | |
| TCP_MTU_REDUCED_DEFERRED = 5, | |
| + TCP_ACK_DEFERRED = 6, | |
| }; | |
| enum tsq_flags { | |
| @@ -25192,6 +31392,7 @@ | |
| TCPF_WRITE_TIMER_DEFERRED = 8, | |
| TCPF_DELACK_TIMER_DEFERRED = 16, | |
| TCPF_MTU_REDUCED_DEFERRED = 32, | |
| + TCPF_ACK_DEFERRED = 64, | |
| }; | |
| enum tsx_ctrl_states { | |
| @@ -25201,13 +31402,6 @@ | |
| TSX_CTRL_NOT_SUPPORTED = 3, | |
| }; | |
| -enum tt_ids { | |
| - TT_INSTR = 0, | |
| - TT_DATA = 1, | |
| - TT_GEN = 2, | |
| - TT_RESV = 3, | |
| -}; | |
| - | |
| enum ttu_flags { | |
| TTU_SPLIT_HUGE_PMD = 4, | |
| TTU_IGNORE_MLOCK = 8, | |
| @@ -25217,6 +31411,12 @@ | |
| TTU_RMAP_LOCKED = 128, | |
| }; | |
| +enum tty_flow_change { | |
| + TTY_FLOW_NO_CHANGE = 0, | |
| + TTY_THROTTLE_SAFE = 1, | |
| + TTY_UNTHROTTLE_SAFE = 2, | |
| +}; | |
| + | |
| enum tunable_id { | |
| ETHTOOL_ID_UNSPEC = 0, | |
| ETHTOOL_RX_COPYBREAK = 1, | |
| @@ -25246,16 +31446,13 @@ | |
| TUNNEL_ENCAP_MPLS = 3, | |
| }; | |
| -enum tx_queue_prio { | |
| - TX_QUEUE_PRIO_HIGH = 0, | |
| - TX_QUEUE_PRIO_LOW = 1, | |
| +enum txq_info_flags { | |
| + IEEE80211_TXQ_STOP = 0, | |
| + IEEE80211_TXQ_AMPDU = 1, | |
| + IEEE80211_TXQ_NO_AMSDU = 2, | |
| + IEEE80211_TXQ_DIRTY = 3, | |
| }; | |
| -typedef enum { | |
| - AD_TX_DUMMY = 0, | |
| - AD_TRANSMIT = 1, | |
| -} tx_states_t; | |
| - | |
| enum txtime_flags { | |
| SOF_TXTIME_DEADLINE_MODE = 1, | |
| SOF_TXTIME_REPORT_ERRORS = 2, | |
| @@ -25278,9 +31475,12 @@ | |
| enum ucode_state { | |
| UCODE_OK = 0, | |
| UCODE_NEW = 1, | |
| - UCODE_UPDATED = 2, | |
| - UCODE_NFOUND = 3, | |
| - UCODE_ERROR = 4, | |
| + UCODE_NEW_SAFE = 2, | |
| + UCODE_UPDATED = 3, | |
| + UCODE_NFOUND = 4, | |
| + UCODE_ERROR = 5, | |
| + UCODE_TIMEOUT = 6, | |
| + UCODE_OFFLINE = 7, | |
| }; | |
| enum ucount_type { | |
| @@ -25294,9 +31494,13 @@ | |
| UCOUNT_TIME_NAMESPACES = 7, | |
| UCOUNT_INOTIFY_INSTANCES = 8, | |
| UCOUNT_INOTIFY_WATCHES = 9, | |
| - UCOUNT_FANOTIFY_GROUPS = 10, | |
| - UCOUNT_FANOTIFY_MARKS = 11, | |
| - UCOUNT_COUNTS = 12, | |
| + UCOUNT_COUNTS = 10, | |
| +}; | |
| + | |
| +enum udp_conntrack { | |
| + UDP_CT_UNREPLIED = 0, | |
| + UDP_CT_REPLIED = 1, | |
| + UDP_CT_MAX = 2, | |
| }; | |
| enum udp_parsable_tunnel_type { | |
| @@ -25319,16 +31523,6 @@ | |
| UDP_TUNNEL_NIC_ENTRY_FROZEN = 8, | |
| }; | |
| -enum uhci_rh_state { | |
| - UHCI_RH_RESET = 0, | |
| - UHCI_RH_SUSPENDED = 1, | |
| - UHCI_RH_AUTO_STOPPED = 2, | |
| - UHCI_RH_RESUMING = 3, | |
| - UHCI_RH_SUSPENDING = 4, | |
| - UHCI_RH_RUNNING = 5, | |
| - UHCI_RH_RUNNING_NODEVS = 6, | |
| -}; | |
| - | |
| enum umh_disable_depth { | |
| UMH_ENABLED = 0, | |
| UMH_FREEZING = 1, | |
| @@ -25348,6 +31542,24 @@ | |
| UNCORE_ACCESS_MAX = 3, | |
| }; | |
| +enum unix_recv_queue_lock_class { | |
| + U_RECVQ_LOCK_NORMAL = 0, | |
| + U_RECVQ_LOCK_EMBRYO = 1, | |
| +}; | |
| + | |
| +enum unix_socket_lock_class { | |
| + U_LOCK_NORMAL = 0, | |
| + U_LOCK_SECOND = 1, | |
| + U_LOCK_DIAG = 2, | |
| + U_LOCK_GC_LISTENER = 3, | |
| +}; | |
| + | |
| +enum unix_vertex_index { | |
| + UNIX_VERTEX_INDEX_MARK1 = 0, | |
| + UNIX_VERTEX_INDEX_MARK2 = 1, | |
| + UNIX_VERTEX_INDEX_START = 2, | |
| +}; | |
| + | |
| enum uprobe_filter_ctx { | |
| UPROBE_FILTER_REGISTER = 0, | |
| UPROBE_FILTER_UNREGISTER = 1, | |
| @@ -25486,6 +31698,12 @@ | |
| UTF16_BIG_ENDIAN = 2, | |
| }; | |
| +enum utf8_normalization { | |
| + UTF8_NFDI = 0, | |
| + UTF8_NFDICF = 1, | |
| + UTF8_NMAX = 2, | |
| +}; | |
| + | |
| enum uts_proc { | |
| UTS_PROC_ARCH = 0, | |
| UTS_PROC_OSTYPE = 1, | |
| @@ -25501,6 +31719,54 @@ | |
| UV_X2APIC = 2, | |
| }; | |
| +enum v4l2_av1_segment_feature { | |
| + V4L2_AV1_SEG_LVL_ALT_Q = 0, | |
| + V4L2_AV1_SEG_LVL_ALT_LF_Y_V = 1, | |
| + V4L2_AV1_SEG_LVL_REF_FRAME = 5, | |
| + V4L2_AV1_SEG_LVL_REF_SKIP = 6, | |
| + V4L2_AV1_SEG_LVL_REF_GLOBALMV = 7, | |
| + V4L2_AV1_SEG_LVL_MAX = 8, | |
| +}; | |
| + | |
| +enum v4l2_fwnode_bus_type { | |
| + V4L2_FWNODE_BUS_TYPE_GUESS = 0, | |
| + V4L2_FWNODE_BUS_TYPE_CSI2_CPHY = 1, | |
| + V4L2_FWNODE_BUS_TYPE_CSI1 = 2, | |
| + V4L2_FWNODE_BUS_TYPE_CCP2 = 3, | |
| + V4L2_FWNODE_BUS_TYPE_CSI2_DPHY = 4, | |
| + V4L2_FWNODE_BUS_TYPE_PARALLEL = 5, | |
| + V4L2_FWNODE_BUS_TYPE_BT656 = 6, | |
| + V4L2_FWNODE_BUS_TYPE_DPI = 7, | |
| + NR_OF_V4L2_FWNODE_BUS_TYPE = 8, | |
| +}; | |
| + | |
| +enum v4l2_preemphasis { | |
| + V4L2_PREEMPHASIS_DISABLED = 0, | |
| + V4L2_PREEMPHASIS_50_uS = 1, | |
| + V4L2_PREEMPHASIS_75_uS = 2, | |
| +}; | |
| + | |
| +enum vc_ctl_state { | |
| + ESnormal = 0, | |
| + ESesc = 1, | |
| + ESsquare = 2, | |
| + ESgetpars = 3, | |
| + ESfunckey = 4, | |
| + EShash = 5, | |
| + ESsetG0 = 6, | |
| + ESsetG1 = 7, | |
| + ESpercent = 8, | |
| + EScsiignore = 9, | |
| + ESnonstd = 10, | |
| + ESpalette = 11, | |
| + ESosc = 12, | |
| + ESANSI_first = 12, | |
| + ESapc = 13, | |
| + ESpm = 14, | |
| + ESdcs = 15, | |
| + ESANSI_last = 15, | |
| +}; | |
| + | |
| enum vc_intensity { | |
| VCI_HALF_BRIGHT = 0, | |
| VCI_NORMAL = 1, | |
| @@ -25508,6 +31774,12 @@ | |
| VCI_MASK = 3, | |
| }; | |
| +enum vcpu_state { | |
| + vcpu_running = 0, | |
| + vcpu_halted = 1, | |
| + vcpu_hashed = 2, | |
| +}; | |
| + | |
| enum vdso_clock_mode { | |
| VDSO_CLOCKMODE_NONE = 0, | |
| VDSO_CLOCKMODE_TSC = 1, | |
| @@ -25522,8 +31794,44 @@ | |
| CHECK_TYPE = 1, | |
| }; | |
| +enum vesa_blank_mode { | |
| + VESA_NO_BLANKING = 0, | |
| + VESA_VSYNC_SUSPEND = 1, | |
| + VESA_HSYNC_SUSPEND = 2, | |
| + VESA_POWERDOWN = 3, | |
| + VESA_BLANK_MAX = 3, | |
| +}; | |
| + | |
| enum vhost_task_flags { | |
| VHOST_TASK_FLAGS_STOP = 0, | |
| + VHOST_TASK_FLAGS_KILLED = 1, | |
| +}; | |
| + | |
| +enum virtio_balloon_config_read { | |
| + VIRTIO_BALLOON_CONFIG_READ_CMD_ID = 0, | |
| +}; | |
| + | |
| +enum virtio_balloon_vq { | |
| + VIRTIO_BALLOON_VQ_INFLATE = 0, | |
| + VIRTIO_BALLOON_VQ_DEFLATE = 1, | |
| + VIRTIO_BALLOON_VQ_STATS = 2, | |
| + VIRTIO_BALLOON_VQ_FREE_PAGE = 3, | |
| + VIRTIO_BALLOON_VQ_REPORTING = 4, | |
| + VIRTIO_BALLOON_VQ_MAX = 5, | |
| +}; | |
| + | |
| +enum virtio_input_config_select { | |
| + VIRTIO_INPUT_CFG_UNSET = 0, | |
| + VIRTIO_INPUT_CFG_ID_NAME = 1, | |
| + VIRTIO_INPUT_CFG_ID_SERIAL = 2, | |
| + VIRTIO_INPUT_CFG_ID_DEVIDS = 3, | |
| + VIRTIO_INPUT_CFG_PROP_BITS = 16, | |
| + VIRTIO_INPUT_CFG_EV_BITS = 17, | |
| + VIRTIO_INPUT_CFG_ABS_INFO = 18, | |
| +}; | |
| + | |
| +enum virtio_vsock_event_id { | |
| + VIRTIO_VSOCK_EVENT_TRANSPORT_RESET = 0, | |
| }; | |
| enum virtio_vsock_op { | |
| @@ -25566,12 +31874,40 @@ | |
| VLAN_FLAG_BRIDGE_BINDING = 16, | |
| }; | |
| +enum vlan_ioctl_cmds { | |
| + ADD_VLAN_CMD = 0, | |
| + DEL_VLAN_CMD = 1, | |
| + SET_VLAN_INGRESS_PRIORITY_CMD = 2, | |
| + SET_VLAN_EGRESS_PRIORITY_CMD = 3, | |
| + GET_VLAN_INGRESS_PRIORITY_CMD = 4, | |
| + GET_VLAN_EGRESS_PRIORITY_CMD = 5, | |
| + SET_VLAN_NAME_TYPE_CMD = 6, | |
| + SET_VLAN_FLAG_CMD = 7, | |
| + GET_VLAN_REALDEV_NAME_CMD = 8, | |
| + GET_VLAN_VID_CMD = 9, | |
| +}; | |
| + | |
| +enum vlan_name_types { | |
| + VLAN_NAME_TYPE_PLUS_VID = 0, | |
| + VLAN_NAME_TYPE_RAW_PLUS_VID = 1, | |
| + VLAN_NAME_TYPE_PLUS_VID_NO_PAD = 2, | |
| + VLAN_NAME_TYPE_RAW_PLUS_VID_NO_PAD = 3, | |
| + VLAN_NAME_TYPE_HIGHEST = 4, | |
| +}; | |
| + | |
| enum vlan_protos { | |
| VLAN_PROTO_8021Q = 0, | |
| VLAN_PROTO_8021AD = 1, | |
| VLAN_PROTO_NUM = 2, | |
| }; | |
| +enum vm_entry_failure_code { | |
| + ENTRY_FAIL_DEFAULT = 0, | |
| + ENTRY_FAIL_PDPTE = 2, | |
| + ENTRY_FAIL_NMI = 3, | |
| + ENTRY_FAIL_VMCS_LINK_PTR = 4, | |
| +}; | |
| + | |
| enum vm_event_item { | |
| PGPGIN = 0, | |
| PGPGOUT = 1, | |
| @@ -25581,115 +31917,106 @@ | |
| PGALLOC_DMA32 = 5, | |
| PGALLOC_NORMAL = 6, | |
| PGALLOC_MOVABLE = 7, | |
| - PGALLOC_DEVICE = 8, | |
| - ALLOCSTALL_DMA = 9, | |
| - ALLOCSTALL_DMA32 = 10, | |
| - ALLOCSTALL_NORMAL = 11, | |
| - ALLOCSTALL_MOVABLE = 12, | |
| - ALLOCSTALL_DEVICE = 13, | |
| - PGSCAN_SKIP_DMA = 14, | |
| - PGSCAN_SKIP_DMA32 = 15, | |
| - PGSCAN_SKIP_NORMAL = 16, | |
| - PGSCAN_SKIP_MOVABLE = 17, | |
| - PGSCAN_SKIP_DEVICE = 18, | |
| - PGFREE = 19, | |
| - PGACTIVATE = 20, | |
| - PGDEACTIVATE = 21, | |
| - PGLAZYFREE = 22, | |
| - PGFAULT = 23, | |
| - PGMAJFAULT = 24, | |
| - PGLAZYFREED = 25, | |
| - PGREFILL = 26, | |
| - PGREUSE = 27, | |
| - PGSTEAL_KSWAPD = 28, | |
| - PGSTEAL_DIRECT = 29, | |
| - PGSTEAL_KHUGEPAGED = 30, | |
| - PGDEMOTE_KSWAPD = 31, | |
| - PGDEMOTE_DIRECT = 32, | |
| - PGDEMOTE_KHUGEPAGED = 33, | |
| - PGSCAN_KSWAPD = 34, | |
| - PGSCAN_DIRECT = 35, | |
| - PGSCAN_KHUGEPAGED = 36, | |
| - PGSCAN_DIRECT_THROTTLE = 37, | |
| - PGSCAN_ANON = 38, | |
| - PGSCAN_FILE = 39, | |
| - PGSTEAL_ANON = 40, | |
| - PGSTEAL_FILE = 41, | |
| - PGSCAN_ZONE_RECLAIM_FAILED = 42, | |
| - PGINODESTEAL = 43, | |
| - SLABS_SCANNED = 44, | |
| - KSWAPD_INODESTEAL = 45, | |
| - KSWAPD_LOW_WMARK_HIT_QUICKLY = 46, | |
| - KSWAPD_HIGH_WMARK_HIT_QUICKLY = 47, | |
| - PAGEOUTRUN = 48, | |
| - PGROTATED = 49, | |
| - DROP_PAGECACHE = 50, | |
| - DROP_SLAB = 51, | |
| - OOM_KILL = 52, | |
| - NUMA_PTE_UPDATES = 53, | |
| - NUMA_HUGE_PTE_UPDATES = 54, | |
| - NUMA_HINT_FAULTS = 55, | |
| - NUMA_HINT_FAULTS_LOCAL = 56, | |
| - NUMA_PAGE_MIGRATE = 57, | |
| - PGMIGRATE_SUCCESS = 58, | |
| - PGMIGRATE_FAIL = 59, | |
| - THP_MIGRATION_SUCCESS = 60, | |
| - THP_MIGRATION_FAIL = 61, | |
| - THP_MIGRATION_SPLIT = 62, | |
| - COMPACTMIGRATE_SCANNED = 63, | |
| - COMPACTFREE_SCANNED = 64, | |
| - COMPACTISOLATED = 65, | |
| - COMPACTSTALL = 66, | |
| - COMPACTFAIL = 67, | |
| - COMPACTSUCCESS = 68, | |
| - KCOMPACTD_WAKE = 69, | |
| - KCOMPACTD_MIGRATE_SCANNED = 70, | |
| - KCOMPACTD_FREE_SCANNED = 71, | |
| - HTLB_BUDDY_PGALLOC = 72, | |
| - HTLB_BUDDY_PGALLOC_FAIL = 73, | |
| - CMA_ALLOC_SUCCESS = 74, | |
| - CMA_ALLOC_FAIL = 75, | |
| - UNEVICTABLE_PGCULLED = 76, | |
| - UNEVICTABLE_PGSCANNED = 77, | |
| - UNEVICTABLE_PGRESCUED = 78, | |
| - UNEVICTABLE_PGMLOCKED = 79, | |
| - UNEVICTABLE_PGMUNLOCKED = 80, | |
| - UNEVICTABLE_PGCLEARED = 81, | |
| - UNEVICTABLE_PGSTRANDED = 82, | |
| - THP_FAULT_ALLOC = 83, | |
| - THP_FAULT_FALLBACK = 84, | |
| - THP_FAULT_FALLBACK_CHARGE = 85, | |
| - THP_COLLAPSE_ALLOC = 86, | |
| - THP_COLLAPSE_ALLOC_FAILED = 87, | |
| - THP_FILE_ALLOC = 88, | |
| - THP_FILE_FALLBACK = 89, | |
| - THP_FILE_FALLBACK_CHARGE = 90, | |
| - THP_FILE_MAPPED = 91, | |
| - THP_SPLIT_PAGE = 92, | |
| - THP_SPLIT_PAGE_FAILED = 93, | |
| - THP_DEFERRED_SPLIT_PAGE = 94, | |
| - THP_SPLIT_PMD = 95, | |
| - THP_SCAN_EXCEED_NONE_PTE = 96, | |
| - THP_SCAN_EXCEED_SWAP_PTE = 97, | |
| - THP_SCAN_EXCEED_SHARED_PTE = 98, | |
| - THP_SPLIT_PUD = 99, | |
| - THP_ZERO_PAGE_ALLOC = 100, | |
| - THP_ZERO_PAGE_ALLOC_FAILED = 101, | |
| - THP_SWPOUT = 102, | |
| - THP_SWPOUT_FALLBACK = 103, | |
| - BALLOON_INFLATE = 104, | |
| - BALLOON_DEFLATE = 105, | |
| - BALLOON_MIGRATE = 106, | |
| - SWAP_RA = 107, | |
| - SWAP_RA_HIT = 108, | |
| - KSM_SWPIN_COPY = 109, | |
| - COW_KSM = 110, | |
| - ZSWPIN = 111, | |
| - ZSWPOUT = 112, | |
| - ZSWPWB = 113, | |
| - DIRECT_MAP_LEVEL2_SPLIT = 114, | |
| - DIRECT_MAP_LEVEL3_SPLIT = 115, | |
| - NR_VM_EVENT_ITEMS = 116, | |
| + ALLOCSTALL_DMA = 8, | |
| + ALLOCSTALL_DMA32 = 9, | |
| + ALLOCSTALL_NORMAL = 10, | |
| + ALLOCSTALL_MOVABLE = 11, | |
| + PGSCAN_SKIP_DMA = 12, | |
| + PGSCAN_SKIP_DMA32 = 13, | |
| + PGSCAN_SKIP_NORMAL = 14, | |
| + PGSCAN_SKIP_MOVABLE = 15, | |
| + PGFREE = 16, | |
| + PGACTIVATE = 17, | |
| + PGDEACTIVATE = 18, | |
| + PGLAZYFREE = 19, | |
| + PGFAULT = 20, | |
| + PGMAJFAULT = 21, | |
| + PGLAZYFREED = 22, | |
| + PGREFILL = 23, | |
| + PGREUSE = 24, | |
| + PGSTEAL_KSWAPD = 25, | |
| + PGSTEAL_DIRECT = 26, | |
| + PGSTEAL_KHUGEPAGED = 27, | |
| + PGSCAN_KSWAPD = 28, | |
| + PGSCAN_DIRECT = 29, | |
| + PGSCAN_KHUGEPAGED = 30, | |
| + PGSCAN_DIRECT_THROTTLE = 31, | |
| + PGSCAN_ANON = 32, | |
| + PGSCAN_FILE = 33, | |
| + PGSTEAL_ANON = 34, | |
| + PGSTEAL_FILE = 35, | |
| + PGSCAN_ZONE_RECLAIM_FAILED = 36, | |
| + PGINODESTEAL = 37, | |
| + SLABS_SCANNED = 38, | |
| + KSWAPD_INODESTEAL = 39, | |
| + KSWAPD_LOW_WMARK_HIT_QUICKLY = 40, | |
| + KSWAPD_HIGH_WMARK_HIT_QUICKLY = 41, | |
| + PAGEOUTRUN = 42, | |
| + PGROTATED = 43, | |
| + DROP_PAGECACHE = 44, | |
| + DROP_SLAB = 45, | |
| + OOM_KILL = 46, | |
| + NUMA_PTE_UPDATES = 47, | |
| + NUMA_HUGE_PTE_UPDATES = 48, | |
| + NUMA_HINT_FAULTS = 49, | |
| + NUMA_HINT_FAULTS_LOCAL = 50, | |
| + NUMA_PAGE_MIGRATE = 51, | |
| + PGMIGRATE_SUCCESS = 52, | |
| + PGMIGRATE_FAIL = 53, | |
| + THP_MIGRATION_SUCCESS = 54, | |
| + THP_MIGRATION_FAIL = 55, | |
| + THP_MIGRATION_SPLIT = 56, | |
| + COMPACTMIGRATE_SCANNED = 57, | |
| + COMPACTFREE_SCANNED = 58, | |
| + COMPACTISOLATED = 59, | |
| + COMPACTSTALL = 60, | |
| + COMPACTFAIL = 61, | |
| + COMPACTSUCCESS = 62, | |
| + KCOMPACTD_WAKE = 63, | |
| + KCOMPACTD_MIGRATE_SCANNED = 64, | |
| + KCOMPACTD_FREE_SCANNED = 65, | |
| + HTLB_BUDDY_PGALLOC = 66, | |
| + HTLB_BUDDY_PGALLOC_FAIL = 67, | |
| + CMA_ALLOC_SUCCESS = 68, | |
| + CMA_ALLOC_FAIL = 69, | |
| + UNEVICTABLE_PGCULLED = 70, | |
| + UNEVICTABLE_PGSCANNED = 71, | |
| + UNEVICTABLE_PGRESCUED = 72, | |
| + UNEVICTABLE_PGMLOCKED = 73, | |
| + UNEVICTABLE_PGMUNLOCKED = 74, | |
| + UNEVICTABLE_PGCLEARED = 75, | |
| + UNEVICTABLE_PGSTRANDED = 76, | |
| + THP_FAULT_ALLOC = 77, | |
| + THP_FAULT_FALLBACK = 78, | |
| + THP_FAULT_FALLBACK_CHARGE = 79, | |
| + THP_COLLAPSE_ALLOC = 80, | |
| + THP_COLLAPSE_ALLOC_FAILED = 81, | |
| + THP_FILE_ALLOC = 82, | |
| + THP_FILE_FALLBACK = 83, | |
| + THP_FILE_FALLBACK_CHARGE = 84, | |
| + THP_FILE_MAPPED = 85, | |
| + THP_SPLIT_PAGE = 86, | |
| + THP_SPLIT_PAGE_FAILED = 87, | |
| + THP_DEFERRED_SPLIT_PAGE = 88, | |
| + THP_SPLIT_PMD = 89, | |
| + THP_SCAN_EXCEED_NONE_PTE = 90, | |
| + THP_SCAN_EXCEED_SWAP_PTE = 91, | |
| + THP_SCAN_EXCEED_SHARED_PTE = 92, | |
| + THP_SPLIT_PUD = 93, | |
| + THP_ZERO_PAGE_ALLOC = 94, | |
| + THP_ZERO_PAGE_ALLOC_FAILED = 95, | |
| + THP_SWPOUT = 96, | |
| + THP_SWPOUT_FALLBACK = 97, | |
| + BALLOON_INFLATE = 98, | |
| + BALLOON_DEFLATE = 99, | |
| + BALLOON_MIGRATE = 100, | |
| + SWAP_RA = 101, | |
| + SWAP_RA_HIT = 102, | |
| + KSM_SWPIN_COPY = 103, | |
| + COW_KSM = 104, | |
| + DIRECT_MAP_LEVEL2_SPLIT = 105, | |
| + DIRECT_MAP_LEVEL3_SPLIT = 106, | |
| + NR_VM_EVENT_ITEMS = 107, | |
| }; | |
| enum vm_fault_reason { | |
| @@ -25709,6 +32036,34 @@ | |
| VM_FAULT_HINDEX_MASK = 983040, | |
| }; | |
| +enum vm_instruction_error_number { | |
| + VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1, | |
| + VMXERR_VMCLEAR_INVALID_ADDRESS = 2, | |
| + VMXERR_VMCLEAR_VMXON_POINTER = 3, | |
| + VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4, | |
| + VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5, | |
| + VMXERR_VMRESUME_AFTER_VMXOFF = 6, | |
| + VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7, | |
| + VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8, | |
| + VMXERR_VMPTRLD_INVALID_ADDRESS = 9, | |
| + VMXERR_VMPTRLD_VMXON_POINTER = 10, | |
| + VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11, | |
| + VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12, | |
| + VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13, | |
| + VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15, | |
| + VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16, | |
| + VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17, | |
| + VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18, | |
| + VMXERR_VMCALL_NONCLEAR_VMCS = 19, | |
| + VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20, | |
| + VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22, | |
| + VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23, | |
| + VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24, | |
| + VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25, | |
| + VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26, | |
| + VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28, | |
| +}; | |
| + | |
| enum vma_resv_mode { | |
| VMA_NEEDS_RESV = 0, | |
| VMA_COMMIT_RESV = 1, | |
| @@ -25717,6 +32072,208 @@ | |
| VMA_DEL_RESV = 4, | |
| }; | |
| +enum vmcs_field { | |
| + VIRTUAL_PROCESSOR_ID = 0, | |
| + POSTED_INTR_NV = 2, | |
| + LAST_PID_POINTER_INDEX = 8, | |
| + GUEST_ES_SELECTOR = 2048, | |
| + GUEST_CS_SELECTOR = 2050, | |
| + GUEST_SS_SELECTOR = 2052, | |
| + GUEST_DS_SELECTOR = 2054, | |
| + GUEST_FS_SELECTOR = 2056, | |
| + GUEST_GS_SELECTOR = 2058, | |
| + GUEST_LDTR_SELECTOR = 2060, | |
| + GUEST_TR_SELECTOR = 2062, | |
| + GUEST_INTR_STATUS = 2064, | |
| + GUEST_PML_INDEX = 2066, | |
| + HOST_ES_SELECTOR = 3072, | |
| + HOST_CS_SELECTOR = 3074, | |
| + HOST_SS_SELECTOR = 3076, | |
| + HOST_DS_SELECTOR = 3078, | |
| + HOST_FS_SELECTOR = 3080, | |
| + HOST_GS_SELECTOR = 3082, | |
| + HOST_TR_SELECTOR = 3084, | |
| + IO_BITMAP_A = 8192, | |
| + IO_BITMAP_A_HIGH = 8193, | |
| + IO_BITMAP_B = 8194, | |
| + IO_BITMAP_B_HIGH = 8195, | |
| + MSR_BITMAP = 8196, | |
| + MSR_BITMAP_HIGH = 8197, | |
| + VM_EXIT_MSR_STORE_ADDR = 8198, | |
| + VM_EXIT_MSR_STORE_ADDR_HIGH = 8199, | |
| + VM_EXIT_MSR_LOAD_ADDR = 8200, | |
| + VM_EXIT_MSR_LOAD_ADDR_HIGH = 8201, | |
| + VM_ENTRY_MSR_LOAD_ADDR = 8202, | |
| + VM_ENTRY_MSR_LOAD_ADDR_HIGH = 8203, | |
| + PML_ADDRESS = 8206, | |
| + PML_ADDRESS_HIGH = 8207, | |
| + TSC_OFFSET = 8208, | |
| + TSC_OFFSET_HIGH = 8209, | |
| + VIRTUAL_APIC_PAGE_ADDR = 8210, | |
| + VIRTUAL_APIC_PAGE_ADDR_HIGH = 8211, | |
| + APIC_ACCESS_ADDR = 8212, | |
| + APIC_ACCESS_ADDR_HIGH = 8213, | |
| + POSTED_INTR_DESC_ADDR = 8214, | |
| + POSTED_INTR_DESC_ADDR_HIGH = 8215, | |
| + VM_FUNCTION_CONTROL = 8216, | |
| + VM_FUNCTION_CONTROL_HIGH = 8217, | |
| + EPT_POINTER = 8218, | |
| + EPT_POINTER_HIGH = 8219, | |
| + EOI_EXIT_BITMAP0 = 8220, | |
| + EOI_EXIT_BITMAP0_HIGH = 8221, | |
| + EOI_EXIT_BITMAP1 = 8222, | |
| + EOI_EXIT_BITMAP1_HIGH = 8223, | |
| + EOI_EXIT_BITMAP2 = 8224, | |
| + EOI_EXIT_BITMAP2_HIGH = 8225, | |
| + EOI_EXIT_BITMAP3 = 8226, | |
| + EOI_EXIT_BITMAP3_HIGH = 8227, | |
| + EPTP_LIST_ADDRESS = 8228, | |
| + EPTP_LIST_ADDRESS_HIGH = 8229, | |
| + VMREAD_BITMAP = 8230, | |
| + VMREAD_BITMAP_HIGH = 8231, | |
| + VMWRITE_BITMAP = 8232, | |
| + VMWRITE_BITMAP_HIGH = 8233, | |
| + XSS_EXIT_BITMAP = 8236, | |
| + XSS_EXIT_BITMAP_HIGH = 8237, | |
| + ENCLS_EXITING_BITMAP = 8238, | |
| + ENCLS_EXITING_BITMAP_HIGH = 8239, | |
| + TSC_MULTIPLIER = 8242, | |
| + TSC_MULTIPLIER_HIGH = 8243, | |
| + TERTIARY_VM_EXEC_CONTROL = 8244, | |
| + TERTIARY_VM_EXEC_CONTROL_HIGH = 8245, | |
| + PID_POINTER_TABLE = 8258, | |
| + PID_POINTER_TABLE_HIGH = 8259, | |
| + GUEST_PHYSICAL_ADDRESS = 9216, | |
| + GUEST_PHYSICAL_ADDRESS_HIGH = 9217, | |
| + VMCS_LINK_POINTER = 10240, | |
| + VMCS_LINK_POINTER_HIGH = 10241, | |
| + GUEST_IA32_DEBUGCTL = 10242, | |
| + GUEST_IA32_DEBUGCTL_HIGH = 10243, | |
| + GUEST_IA32_PAT = 10244, | |
| + GUEST_IA32_PAT_HIGH = 10245, | |
| + GUEST_IA32_EFER = 10246, | |
| + GUEST_IA32_EFER_HIGH = 10247, | |
| + GUEST_IA32_PERF_GLOBAL_CTRL = 10248, | |
| + GUEST_IA32_PERF_GLOBAL_CTRL_HIGH = 10249, | |
| + GUEST_PDPTR0 = 10250, | |
| + GUEST_PDPTR0_HIGH = 10251, | |
| + GUEST_PDPTR1 = 10252, | |
| + GUEST_PDPTR1_HIGH = 10253, | |
| + GUEST_PDPTR2 = 10254, | |
| + GUEST_PDPTR2_HIGH = 10255, | |
| + GUEST_PDPTR3 = 10256, | |
| + GUEST_PDPTR3_HIGH = 10257, | |
| + GUEST_BNDCFGS = 10258, | |
| + GUEST_BNDCFGS_HIGH = 10259, | |
| + GUEST_IA32_RTIT_CTL = 10260, | |
| + GUEST_IA32_RTIT_CTL_HIGH = 10261, | |
| + HOST_IA32_PAT = 11264, | |
| + HOST_IA32_PAT_HIGH = 11265, | |
| + HOST_IA32_EFER = 11266, | |
| + HOST_IA32_EFER_HIGH = 11267, | |
| + HOST_IA32_PERF_GLOBAL_CTRL = 11268, | |
| + HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 11269, | |
| + PIN_BASED_VM_EXEC_CONTROL = 16384, | |
| + CPU_BASED_VM_EXEC_CONTROL = 16386, | |
| + EXCEPTION_BITMAP = 16388, | |
| + PAGE_FAULT_ERROR_CODE_MASK = 16390, | |
| + PAGE_FAULT_ERROR_CODE_MATCH = 16392, | |
| + CR3_TARGET_COUNT = 16394, | |
| + VM_EXIT_CONTROLS = 16396, | |
| + VM_EXIT_MSR_STORE_COUNT = 16398, | |
| + VM_EXIT_MSR_LOAD_COUNT = 16400, | |
| + VM_ENTRY_CONTROLS = 16402, | |
| + VM_ENTRY_MSR_LOAD_COUNT = 16404, | |
| + VM_ENTRY_INTR_INFO_FIELD = 16406, | |
| + VM_ENTRY_EXCEPTION_ERROR_CODE = 16408, | |
| + VM_ENTRY_INSTRUCTION_LEN = 16410, | |
| + TPR_THRESHOLD = 16412, | |
| + SECONDARY_VM_EXEC_CONTROL = 16414, | |
| + PLE_GAP = 16416, | |
| + PLE_WINDOW = 16418, | |
| + NOTIFY_WINDOW = 16420, | |
| + VM_INSTRUCTION_ERROR = 17408, | |
| + VM_EXIT_REASON = 17410, | |
| + VM_EXIT_INTR_INFO = 17412, | |
| + VM_EXIT_INTR_ERROR_CODE = 17414, | |
| + IDT_VECTORING_INFO_FIELD = 17416, | |
| + IDT_VECTORING_ERROR_CODE = 17418, | |
| + VM_EXIT_INSTRUCTION_LEN = 17420, | |
| + VMX_INSTRUCTION_INFO = 17422, | |
| + GUEST_ES_LIMIT = 18432, | |
| + GUEST_CS_LIMIT = 18434, | |
| + GUEST_SS_LIMIT = 18436, | |
| + GUEST_DS_LIMIT = 18438, | |
| + GUEST_FS_LIMIT = 18440, | |
| + GUEST_GS_LIMIT = 18442, | |
| + GUEST_LDTR_LIMIT = 18444, | |
| + GUEST_TR_LIMIT = 18446, | |
| + GUEST_GDTR_LIMIT = 18448, | |
| + GUEST_IDTR_LIMIT = 18450, | |
| + GUEST_ES_AR_BYTES = 18452, | |
| + GUEST_CS_AR_BYTES = 18454, | |
| + GUEST_SS_AR_BYTES = 18456, | |
| + GUEST_DS_AR_BYTES = 18458, | |
| + GUEST_FS_AR_BYTES = 18460, | |
| + GUEST_GS_AR_BYTES = 18462, | |
| + GUEST_LDTR_AR_BYTES = 18464, | |
| + GUEST_TR_AR_BYTES = 18466, | |
| + GUEST_INTERRUPTIBILITY_INFO = 18468, | |
| + GUEST_ACTIVITY_STATE = 18470, | |
| + GUEST_SYSENTER_CS = 18474, | |
| + VMX_PREEMPTION_TIMER_VALUE = 18478, | |
| + HOST_IA32_SYSENTER_CS = 19456, | |
| + CR0_GUEST_HOST_MASK = 24576, | |
| + CR4_GUEST_HOST_MASK = 24578, | |
| + CR0_READ_SHADOW = 24580, | |
| + CR4_READ_SHADOW = 24582, | |
| + CR3_TARGET_VALUE0 = 24584, | |
| + CR3_TARGET_VALUE1 = 24586, | |
| + CR3_TARGET_VALUE2 = 24588, | |
| + CR3_TARGET_VALUE3 = 24590, | |
| + EXIT_QUALIFICATION = 25600, | |
| + GUEST_LINEAR_ADDRESS = 25610, | |
| + GUEST_CR0 = 26624, | |
| + GUEST_CR3 = 26626, | |
| + GUEST_CR4 = 26628, | |
| + GUEST_ES_BASE = 26630, | |
| + GUEST_CS_BASE = 26632, | |
| + GUEST_SS_BASE = 26634, | |
| + GUEST_DS_BASE = 26636, | |
| + GUEST_FS_BASE = 26638, | |
| + GUEST_GS_BASE = 26640, | |
| + GUEST_LDTR_BASE = 26642, | |
| + GUEST_TR_BASE = 26644, | |
| + GUEST_GDTR_BASE = 26646, | |
| + GUEST_IDTR_BASE = 26648, | |
| + GUEST_DR7 = 26650, | |
| + GUEST_RSP = 26652, | |
| + GUEST_RIP = 26654, | |
| + GUEST_RFLAGS = 26656, | |
| + GUEST_PENDING_DBG_EXCEPTIONS = 26658, | |
| + GUEST_SYSENTER_ESP = 26660, | |
| + GUEST_SYSENTER_EIP = 26662, | |
| + HOST_CR0 = 27648, | |
| + HOST_CR3 = 27650, | |
| + HOST_CR4 = 27652, | |
| + HOST_FS_BASE = 27654, | |
| + HOST_GS_BASE = 27656, | |
| + HOST_TR_BASE = 27658, | |
| + HOST_GDTR_BASE = 27660, | |
| + HOST_IDTR_BASE = 27662, | |
| + HOST_IA32_SYSENTER_ESP = 27664, | |
| + HOST_IA32_SYSENTER_EIP = 27666, | |
| + HOST_RSP = 27668, | |
| + HOST_RIP = 27670, | |
| +}; | |
| + | |
| +enum vmcs_field_width { | |
| + VMCS_FIELD_WIDTH_U16 = 0, | |
| + VMCS_FIELD_WIDTH_U64 = 1, | |
| + VMCS_FIELD_WIDTH_U32 = 2, | |
| + VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3, | |
| +}; | |
| + | |
| enum vmpressure_levels { | |
| VMPRESSURE_LOW = 0, | |
| VMPRESSURE_MEDIUM = 1, | |
| @@ -25757,22 +32314,6 @@ | |
| VMENTER_L1D_FLUSH_NOT_REQUIRED = 5, | |
| }; | |
| -enum vrm_version { | |
| - vr11 = 0, | |
| - vr12 = 1, | |
| - vr13 = 2, | |
| - imvp9 = 3, | |
| - amd625mv = 4, | |
| -}; | |
| - | |
| -enum vtime_state { | |
| - VTIME_INACTIVE = 0, | |
| - VTIME_IDLE = 1, | |
| - VTIME_SYS = 2, | |
| - VTIME_USER = 3, | |
| - VTIME_GUEST = 4, | |
| -}; | |
| - | |
| enum wb_reason { | |
| WB_REASON_BACKGROUND = 0, | |
| WB_REASON_VMSCAN = 1, | |
| @@ -25800,90 +32341,185 @@ | |
| WB_start_all = 3, | |
| }; | |
| -enum wbt_flags { | |
| - WBT_TRACKED = 1, | |
| - WBT_READ = 2, | |
| - WBT_KSWAPD = 4, | |
| - WBT_DISCARD = 8, | |
| - WBT_NR_BITS = 4, | |
| -}; | |
| - | |
| enum wd_read_status { | |
| WD_READ_SUCCESS = 0, | |
| WD_READ_UNSTABLE = 1, | |
| WD_READ_SKIP = 2, | |
| }; | |
| -enum wg_cmd { | |
| - WG_CMD_GET_DEVICE = 0, | |
| - WG_CMD_SET_DEVICE = 1, | |
| - __WG_CMD_MAX = 2, | |
| +enum which_selector { | |
| + FS = 0, | |
| + GS = 1, | |
| }; | |
| -enum wgallowedip_attribute { | |
| - WGALLOWEDIP_A_UNSPEC = 0, | |
| - WGALLOWEDIP_A_FAMILY = 1, | |
| - WGALLOWEDIP_A_IPADDR = 2, | |
| - WGALLOWEDIP_A_CIDR_MASK = 3, | |
| - __WGALLOWEDIP_A_LAST = 4, | |
| +enum wiphy_flags { | |
| + WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK = 1, | |
| + WIPHY_FLAG_SUPPORTS_MLO = 2, | |
| + WIPHY_FLAG_SPLIT_SCAN_6GHZ = 4, | |
| + WIPHY_FLAG_NETNS_OK = 8, | |
| + WIPHY_FLAG_PS_ON_BY_DEFAULT = 16, | |
| + WIPHY_FLAG_4ADDR_AP = 32, | |
| + WIPHY_FLAG_4ADDR_STATION = 64, | |
| + WIPHY_FLAG_CONTROL_PORT_PROTOCOL = 128, | |
| + WIPHY_FLAG_IBSS_RSN = 256, | |
| + WIPHY_FLAG_DISABLE_WEXT = 512, | |
| + WIPHY_FLAG_MESH_AUTH = 1024, | |
| + WIPHY_FLAG_SUPPORTS_EXT_KCK_32 = 2048, | |
| + WIPHY_FLAG_SUPPORTS_NSTR_NONPRIMARY = 4096, | |
| + WIPHY_FLAG_SUPPORTS_FW_ROAM = 8192, | |
| + WIPHY_FLAG_AP_UAPSD = 16384, | |
| + WIPHY_FLAG_SUPPORTS_TDLS = 32768, | |
| + WIPHY_FLAG_TDLS_EXTERNAL_SETUP = 65536, | |
| + WIPHY_FLAG_HAVE_AP_SME = 131072, | |
| + WIPHY_FLAG_REPORTS_OBSS = 262144, | |
| + WIPHY_FLAG_AP_PROBE_RESP_OFFLOAD = 524288, | |
| + WIPHY_FLAG_OFFCHAN_TX = 1048576, | |
| + WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL = 2097152, | |
| + WIPHY_FLAG_SUPPORTS_5_10_MHZ = 4194304, | |
| + WIPHY_FLAG_HAS_CHANNEL_SWITCH = 8388608, | |
| + WIPHY_FLAG_NOTIFY_REGDOM_BY_DRIVER = 16777216, | |
| + WIPHY_FLAG_CHANNEL_CHANGE_ON_BEACON = 33554432, | |
| }; | |
| -enum wgdevice_attribute { | |
| - WGDEVICE_A_UNSPEC = 0, | |
| - WGDEVICE_A_IFINDEX = 1, | |
| - WGDEVICE_A_IFNAME = 2, | |
| - WGDEVICE_A_PRIVATE_KEY = 3, | |
| - WGDEVICE_A_PUBLIC_KEY = 4, | |
| - WGDEVICE_A_FLAGS = 5, | |
| - WGDEVICE_A_LISTEN_PORT = 6, | |
| - WGDEVICE_A_FWMARK = 7, | |
| - WGDEVICE_A_PEERS = 8, | |
| - __WGDEVICE_A_LAST = 9, | |
| +enum wiphy_opmode_flag { | |
| + STA_OPMODE_MAX_BW_CHANGED = 1, | |
| + STA_OPMODE_SMPS_MODE_CHANGED = 2, | |
| + STA_OPMODE_N_SS_CHANGED = 4, | |
| }; | |
| -enum wgdevice_flag { | |
| - WGDEVICE_F_REPLACE_PEERS = 1, | |
| - __WGDEVICE_F_ALL = 1, | |
| +enum wiphy_params_flags { | |
| + WIPHY_PARAM_RETRY_SHORT = 1, | |
| + WIPHY_PARAM_RETRY_LONG = 2, | |
| + WIPHY_PARAM_FRAG_THRESHOLD = 4, | |
| + WIPHY_PARAM_RTS_THRESHOLD = 8, | |
| + WIPHY_PARAM_COVERAGE_CLASS = 16, | |
| + WIPHY_PARAM_DYN_ACK = 32, | |
| + WIPHY_PARAM_TXQ_LIMIT = 64, | |
| + WIPHY_PARAM_TXQ_MEMORY_LIMIT = 128, | |
| + WIPHY_PARAM_TXQ_QUANTUM = 256, | |
| }; | |
| -enum wgpeer_attribute { | |
| - WGPEER_A_UNSPEC = 0, | |
| - WGPEER_A_PUBLIC_KEY = 1, | |
| - WGPEER_A_PRESHARED_KEY = 2, | |
| - WGPEER_A_FLAGS = 3, | |
| - WGPEER_A_ENDPOINT = 4, | |
| - WGPEER_A_PERSISTENT_KEEPALIVE_INTERVAL = 5, | |
| - WGPEER_A_LAST_HANDSHAKE_TIME = 6, | |
| - WGPEER_A_RX_BYTES = 7, | |
| - WGPEER_A_TX_BYTES = 8, | |
| - WGPEER_A_ALLOWEDIPS = 9, | |
| - WGPEER_A_PROTOCOL_VERSION = 10, | |
| - __WGPEER_A_LAST = 11, | |
| +enum wiphy_vendor_command_flags { | |
| + WIPHY_VENDOR_CMD_NEED_WDEV = 1, | |
| + WIPHY_VENDOR_CMD_NEED_NETDEV = 2, | |
| + WIPHY_VENDOR_CMD_NEED_RUNNING = 4, | |
| }; | |
| -enum wgpeer_flag { | |
| - WGPEER_F_REMOVE_ME = 1, | |
| - WGPEER_F_REPLACE_ALLOWEDIPS = 2, | |
| - WGPEER_F_UPDATE_ONLY = 4, | |
| - __WGPEER_F_ALL = 7, | |
| +enum wiphy_wowlan_support_flags { | |
| + WIPHY_WOWLAN_ANY = 1, | |
| + WIPHY_WOWLAN_MAGIC_PKT = 2, | |
| + WIPHY_WOWLAN_DISCONNECT = 4, | |
| + WIPHY_WOWLAN_SUPPORTS_GTK_REKEY = 8, | |
| + WIPHY_WOWLAN_GTK_REKEY_FAILURE = 16, | |
| + WIPHY_WOWLAN_EAP_IDENTITY_REQ = 32, | |
| + WIPHY_WOWLAN_4WAY_HANDSHAKE = 64, | |
| + WIPHY_WOWLAN_RFKILL_RELEASE = 128, | |
| + WIPHY_WOWLAN_NET_DETECT = 256, | |
| }; | |
| -enum what { | |
| - PROC_EVENT_NONE = 0, | |
| - PROC_EVENT_FORK = 1, | |
| - PROC_EVENT_EXEC = 2, | |
| - PROC_EVENT_UID = 4, | |
| - PROC_EVENT_GID = 64, | |
| - PROC_EVENT_SID = 128, | |
| - PROC_EVENT_PTRACE = 256, | |
| - PROC_EVENT_COMM = 512, | |
| - PROC_EVENT_COREDUMP = 1073741824, | |
| - PROC_EVENT_EXIT = 2147483648, | |
| +enum work_bits { | |
| + WORK_STRUCT_PENDING_BIT = 0, | |
| + WORK_STRUCT_INACTIVE_BIT = 1, | |
| + WORK_STRUCT_PWQ_BIT = 2, | |
| + WORK_STRUCT_LINKED_BIT = 3, | |
| + WORK_STRUCT_FLAG_BITS = 4, | |
| + WORK_STRUCT_COLOR_SHIFT = 4, | |
| + WORK_STRUCT_COLOR_BITS = 4, | |
| + WORK_STRUCT_PWQ_SHIFT = 8, | |
| + WORK_OFFQ_FLAG_SHIFT = 4, | |
| + WORK_OFFQ_BH_BIT = 4, | |
| + WORK_OFFQ_FLAG_END = 5, | |
| + WORK_OFFQ_FLAG_BITS = 1, | |
| + WORK_OFFQ_DISABLE_SHIFT = 5, | |
| + WORK_OFFQ_DISABLE_BITS = 16, | |
| + WORK_OFFQ_POOL_SHIFT = 21, | |
| + WORK_OFFQ_LEFT = 43, | |
| + WORK_OFFQ_POOL_BITS = 31, | |
| }; | |
| -enum which_selector { | |
| - FS = 0, | |
| - GS = 1, | |
| +enum work_cancel_flags { | |
| + WORK_CANCEL_DELAYED = 1, | |
| + WORK_CANCEL_DISABLE = 2, | |
| +}; | |
| + | |
| +enum work_flags { | |
| + WORK_STRUCT_PENDING = 1, | |
| + WORK_STRUCT_INACTIVE = 2, | |
| + WORK_STRUCT_PWQ = 4, | |
| + WORK_STRUCT_LINKED = 8, | |
| + WORK_STRUCT_STATIC = 0, | |
| +}; | |
| + | |
| +enum worker_flags { | |
| + WORKER_DIE = 2, | |
| + WORKER_IDLE = 4, | |
| + WORKER_PREP = 8, | |
| + WORKER_CPU_INTENSIVE = 64, | |
| + WORKER_UNBOUND = 128, | |
| + WORKER_REBOUND = 256, | |
| + WORKER_NOT_RUNNING = 456, | |
| +}; | |
| + | |
| +enum worker_pool_flags { | |
| + POOL_BH = 1, | |
| + POOL_MANAGER_ACTIVE = 2, | |
| + POOL_DISASSOCIATED = 4, | |
| + POOL_BH_DRAINING = 8, | |
| +}; | |
| + | |
| +enum wq_affn_scope { | |
| + WQ_AFFN_DFL = 0, | |
| + WQ_AFFN_CPU = 1, | |
| + WQ_AFFN_SMT = 2, | |
| + WQ_AFFN_CACHE = 3, | |
| + WQ_AFFN_NUMA = 4, | |
| + WQ_AFFN_SYSTEM = 5, | |
| + WQ_AFFN_NR_TYPES = 6, | |
| +}; | |
| + | |
| +enum wq_consts { | |
| + WQ_MAX_ACTIVE = 512, | |
| + WQ_UNBOUND_MAX_ACTIVE = 512, | |
| + WQ_DFL_ACTIVE = 256, | |
| + WQ_DFL_MIN_ACTIVE = 8, | |
| +}; | |
| + | |
| +enum wq_flags { | |
| + WQ_BH = 1, | |
| + WQ_UNBOUND = 2, | |
| + WQ_FREEZABLE = 4, | |
| + WQ_MEM_RECLAIM = 8, | |
| + WQ_HIGHPRI = 16, | |
| + WQ_CPU_INTENSIVE = 32, | |
| + WQ_SYSFS = 64, | |
| + WQ_POWER_EFFICIENT = 128, | |
| + __WQ_DESTROYING = 32768, | |
| + __WQ_DRAINING = 65536, | |
| + __WQ_ORDERED = 131072, | |
| + __WQ_LEGACY = 262144, | |
| + __WQ_BH_ALLOWS = 17, | |
| +}; | |
| + | |
| +enum wq_internal_consts { | |
| + NR_STD_WORKER_POOLS = 2, | |
| + UNBOUND_POOL_HASH_ORDER = 6, | |
| + BUSY_WORKER_HASH_ORDER = 6, | |
| + MAX_IDLE_WORKERS_RATIO = 4, | |
| + IDLE_WORKER_TIMEOUT = 300000, | |
| + MAYDAY_INITIAL_TIMEOUT = 10, | |
| + MAYDAY_INTERVAL = 100, | |
| + CREATE_COOLDOWN = 1000, | |
| + RESCUER_NICE_LEVEL = -20, | |
| + HIGHPRI_NICE_LEVEL = -20, | |
| + WQ_NAME_LEN = 32, | |
| +}; | |
| + | |
| +enum wq_misc_consts { | |
| + WORK_NR_COLORS = 16, | |
| + WORK_CPU_UNBOUND = 128, | |
| + WORK_BUSY_PENDING = 1, | |
| + WORK_BUSY_RUNNING = 2, | |
| + WORKER_DESC_LEN = 24, | |
| }; | |
| enum writeback_stat_item { | |
| @@ -25897,6 +32533,32 @@ | |
| WB_SYNC_ALL = 1, | |
| }; | |
| +enum x509_actions { | |
| + ACT_x509_extract_key_data = 0, | |
| + ACT_x509_extract_name_segment = 1, | |
| + ACT_x509_note_OID = 2, | |
| + ACT_x509_note_issuer = 3, | |
| + ACT_x509_note_not_after = 4, | |
| + ACT_x509_note_not_before = 5, | |
| + ACT_x509_note_params = 6, | |
| + ACT_x509_note_serial = 7, | |
| + ACT_x509_note_sig_algo = 8, | |
| + ACT_x509_note_signature = 9, | |
| + ACT_x509_note_subject = 10, | |
| + ACT_x509_note_tbs_certificate = 11, | |
| + ACT_x509_process_extension = 12, | |
| + NR__x509_actions = 13, | |
| +}; | |
| + | |
| +enum x509_akid_actions { | |
| + ACT_x509_akid_note_kid = 0, | |
| + ACT_x509_akid_note_name = 1, | |
| + ACT_x509_akid_note_serial = 2, | |
| + ACT_x509_extract_name_segment___2 = 3, | |
| + ACT_x509_note_OID___2 = 4, | |
| + NR__x509_akid_actions = 5, | |
| +}; | |
| + | |
| enum x86_hardware_subarch { | |
| X86_SUBARCH_PC = 0, | |
| X86_SUBARCH_LGUEST = 1, | |
| @@ -25917,6 +32579,66 @@ | |
| X86_HYPER_ACRN = 7, | |
| }; | |
| +enum x86_intercept { | |
| + x86_intercept_none = 0, | |
| + x86_intercept_cr_read = 1, | |
| + x86_intercept_cr_write = 2, | |
| + x86_intercept_clts = 3, | |
| + x86_intercept_lmsw = 4, | |
| + x86_intercept_smsw = 5, | |
| + x86_intercept_dr_read = 6, | |
| + x86_intercept_dr_write = 7, | |
| + x86_intercept_lidt = 8, | |
| + x86_intercept_sidt = 9, | |
| + x86_intercept_lgdt = 10, | |
| + x86_intercept_sgdt = 11, | |
| + x86_intercept_lldt = 12, | |
| + x86_intercept_sldt = 13, | |
| + x86_intercept_ltr = 14, | |
| + x86_intercept_str = 15, | |
| + x86_intercept_rdtsc = 16, | |
| + x86_intercept_rdpmc = 17, | |
| + x86_intercept_pushf = 18, | |
| + x86_intercept_popf = 19, | |
| + x86_intercept_cpuid = 20, | |
| + x86_intercept_rsm = 21, | |
| + x86_intercept_iret = 22, | |
| + x86_intercept_intn = 23, | |
| + x86_intercept_invd = 24, | |
| + x86_intercept_pause = 25, | |
| + x86_intercept_hlt = 26, | |
| + x86_intercept_invlpg = 27, | |
| + x86_intercept_invlpga = 28, | |
| + x86_intercept_vmrun = 29, | |
| + x86_intercept_vmload = 30, | |
| + x86_intercept_vmsave = 31, | |
| + x86_intercept_vmmcall = 32, | |
| + x86_intercept_stgi = 33, | |
| + x86_intercept_clgi = 34, | |
| + x86_intercept_skinit = 35, | |
| + x86_intercept_rdtscp = 36, | |
| + x86_intercept_rdpid = 37, | |
| + x86_intercept_icebp = 38, | |
| + x86_intercept_wbinvd = 39, | |
| + x86_intercept_monitor = 40, | |
| + x86_intercept_mwait = 41, | |
| + x86_intercept_rdmsr = 42, | |
| + x86_intercept_wrmsr = 43, | |
| + x86_intercept_in = 44, | |
| + x86_intercept_ins = 45, | |
| + x86_intercept_out = 46, | |
| + x86_intercept_outs = 47, | |
| + x86_intercept_xsetbv = 48, | |
| + nr_x86_intercepts = 49, | |
| +}; | |
| + | |
| +enum x86_intercept_stage { | |
| + X86_ICTP_NONE = 0, | |
| + X86_ICPT_PRE_EXCEPT = 1, | |
| + X86_ICPT_POST_EXCEPT = 2, | |
| + X86_ICPT_POST_MEMACCESS = 3, | |
| +}; | |
| + | |
| enum x86_legacy_i8042_state { | |
| X86_LEGACY_I8042_PLATFORM_ABSENT = 0, | |
| X86_LEGACY_I8042_FIRMWARE_ABSENT = 1, | |
| @@ -25930,7 +32652,9 @@ | |
| X86_PF_RSVD = 8, | |
| X86_PF_INSTR = 16, | |
| X86_PF_PK = 32, | |
| + X86_PF_SHSTK = 64, | |
| X86_PF_SGX = 32768, | |
| + X86_PF_RMP = 2147483648, | |
| }; | |
| enum x86_regset_32 { | |
| @@ -25947,23 +32671,38 @@ | |
| REGSET64_FP = 1, | |
| REGSET64_IOPERM = 2, | |
| REGSET64_XSTATE = 3, | |
| + REGSET64_SSP = 4, | |
| }; | |
| -enum xa_lock_type { | |
| - XA_LOCK_IRQ = 1, | |
| - XA_LOCK_BH = 2, | |
| +enum x86_topology_domains { | |
| + TOPO_SMT_DOMAIN = 0, | |
| + TOPO_CORE_DOMAIN = 1, | |
| + TOPO_MODULE_DOMAIN = 2, | |
| + TOPO_TILE_DOMAIN = 3, | |
| + TOPO_DIE_DOMAIN = 4, | |
| + TOPO_DIEGRP_DOMAIN = 5, | |
| + TOPO_PKG_DOMAIN = 6, | |
| + TOPO_MAX_DOMAIN = 7, | |
| }; | |
| -enum xbtree_key_contig { | |
| - XBTREE_KEY_GAP = 0, | |
| - XBTREE_KEY_CONTIGUOUS = 1, | |
| - XBTREE_KEY_OVERLAP = 2, | |
| +enum x86_transfer_type { | |
| + X86_TRANSFER_NONE = 0, | |
| + X86_TRANSFER_CALL_JMP = 1, | |
| + X86_TRANSFER_RET = 2, | |
| + X86_TRANSFER_TASK_SWITCH = 3, | |
| }; | |
| -enum xbtree_recpacking { | |
| - XBTREE_RECPACKING_EMPTY = 0, | |
| - XBTREE_RECPACKING_SPARSE = 1, | |
| - XBTREE_RECPACKING_FULL = 2, | |
| +enum x86emul_mode { | |
| + X86EMUL_MODE_REAL = 0, | |
| + X86EMUL_MODE_VM86 = 1, | |
| + X86EMUL_MODE_PROT16 = 2, | |
| + X86EMUL_MODE_PROT32 = 3, | |
| + X86EMUL_MODE_PROT64 = 4, | |
| +}; | |
| + | |
| +enum xa_lock_type { | |
| + XA_LOCK_IRQ = 1, | |
| + XA_LOCK_BH = 2, | |
| }; | |
| enum xdp_action { | |
| @@ -25996,6 +32735,7 @@ | |
| XDP_RSS_L4_UDP = 32, | |
| XDP_RSS_L4_SCTP = 64, | |
| XDP_RSS_L4_IPSEC = 128, | |
| + XDP_RSS_L4_ICMP = 256, | |
| XDP_RSS_TYPE_NONE = 0, | |
| XDP_RSS_TYPE_L2 = 0, | |
| XDP_RSS_TYPE_L3_IPV4 = 1, | |
| @@ -26007,15 +32747,30 @@ | |
| XDP_RSS_TYPE_L4_IPV4_UDP = 41, | |
| XDP_RSS_TYPE_L4_IPV4_SCTP = 73, | |
| XDP_RSS_TYPE_L4_IPV4_IPSEC = 137, | |
| + XDP_RSS_TYPE_L4_IPV4_ICMP = 265, | |
| XDP_RSS_TYPE_L4_IPV6_TCP = 26, | |
| XDP_RSS_TYPE_L4_IPV6_UDP = 42, | |
| XDP_RSS_TYPE_L4_IPV6_SCTP = 74, | |
| XDP_RSS_TYPE_L4_IPV6_IPSEC = 138, | |
| + XDP_RSS_TYPE_L4_IPV6_ICMP = 266, | |
| XDP_RSS_TYPE_L4_IPV6_TCP_EX = 30, | |
| XDP_RSS_TYPE_L4_IPV6_UDP_EX = 46, | |
| XDP_RSS_TYPE_L4_IPV6_SCTP_EX = 78, | |
| }; | |
| +enum xdp_rx_metadata { | |
| + XDP_METADATA_KFUNC_RX_TIMESTAMP = 0, | |
| + XDP_METADATA_KFUNC_RX_HASH = 1, | |
| + XDP_METADATA_KFUNC_RX_VLAN_TAG = 2, | |
| + MAX_XDP_METADATA_KFUNC = 3, | |
| +}; | |
| + | |
| +enum xen_domain_type { | |
| + XEN_NATIVE = 0, | |
| + XEN_PV_DOMAIN = 1, | |
| + XEN_HVM_DOMAIN = 2, | |
| +}; | |
| + | |
| enum xfeature { | |
| XFEATURE_FP = 0, | |
| XFEATURE_SSE = 1, | |
| @@ -26028,8 +32783,8 @@ | |
| XFEATURE_PT_UNIMPLEMENTED_SO_FAR = 8, | |
| XFEATURE_PKRU = 9, | |
| XFEATURE_PASID = 10, | |
| - XFEATURE_RSRVD_COMP_11 = 11, | |
| - XFEATURE_RSRVD_COMP_12 = 12, | |
| + XFEATURE_CET_USER = 11, | |
| + XFEATURE_CET_KERNEL_UNUSED = 12, | |
| XFEATURE_RSRVD_COMP_13 = 13, | |
| XFEATURE_RSRVD_COMP_14 = 14, | |
| XFEATURE_LBR = 15, | |
| @@ -26085,7 +32840,8 @@ | |
| XFRMA_SET_MARK_MASK = 30, | |
| XFRMA_IF_ID = 31, | |
| XFRMA_MTIMER_THRESH = 32, | |
| - __XFRMA_MAX = 33, | |
| + XFRMA_SA_DIR = 33, | |
| + __XFRMA_MAX = 34, | |
| }; | |
| enum xfrm_nlgroups { | |
| @@ -26115,6 +32871,11 @@ | |
| XFRM_REPLAY_MODE_ESN = 2, | |
| }; | |
| +enum xfrm_sa_dir { | |
| + XFRM_SA_DIR_IN = 1, | |
| + XFRM_SA_DIR_OUT = 2, | |
| +}; | |
| + | |
| enum xfrm_sadattr_type_t { | |
| XFRMA_SAD_UNSPEC = 0, | |
| XFRMA_SAD_CNT = 1, | |
| @@ -26131,172 +32892,26 @@ | |
| __XFRMA_SPD_MAX = 5, | |
| }; | |
| -enum xfs_ag_resv_type { | |
| - XFS_AG_RESV_NONE = 0, | |
| - XFS_AG_RESV_AGFL = 1, | |
| - XFS_AG_RESV_METADATA = 2, | |
| - XFS_AG_RESV_RMAPBT = 3, | |
| -}; | |
| - | |
| -enum xfs_blft { | |
| - XFS_BLFT_UNKNOWN_BUF = 0, | |
| - XFS_BLFT_UDQUOT_BUF = 1, | |
| - XFS_BLFT_PDQUOT_BUF = 2, | |
| - XFS_BLFT_GDQUOT_BUF = 3, | |
| - XFS_BLFT_BTREE_BUF = 4, | |
| - XFS_BLFT_AGF_BUF = 5, | |
| - XFS_BLFT_AGFL_BUF = 6, | |
| - XFS_BLFT_AGI_BUF = 7, | |
| - XFS_BLFT_DINO_BUF = 8, | |
| - XFS_BLFT_SYMLINK_BUF = 9, | |
| - XFS_BLFT_DIR_BLOCK_BUF = 10, | |
| - XFS_BLFT_DIR_DATA_BUF = 11, | |
| - XFS_BLFT_DIR_FREE_BUF = 12, | |
| - XFS_BLFT_DIR_LEAF1_BUF = 13, | |
| - XFS_BLFT_DIR_LEAFN_BUF = 14, | |
| - XFS_BLFT_DA_NODE_BUF = 15, | |
| - XFS_BLFT_ATTR_LEAF_BUF = 16, | |
| - XFS_BLFT_ATTR_RMT_BUF = 17, | |
| - XFS_BLFT_SB_BUF = 18, | |
| - XFS_BLFT_RTBITMAP_BUF = 19, | |
| - XFS_BLFT_RTSUMMARY_BUF = 20, | |
| - XFS_BLFT_MAX_BUF = 32, | |
| -}; | |
| - | |
| -enum xfs_bmap_intent_type { | |
| - XFS_BMAP_MAP = 1, | |
| - XFS_BMAP_UNMAP = 2, | |
| -}; | |
| - | |
| -typedef enum { | |
| - XFS_BTNUM_BNOi = 0, | |
| - XFS_BTNUM_CNTi = 1, | |
| - XFS_BTNUM_RMAPi = 2, | |
| - XFS_BTNUM_BMAPi = 3, | |
| - XFS_BTNUM_INOi = 4, | |
| - XFS_BTNUM_FINOi = 5, | |
| - XFS_BTNUM_REFCi = 6, | |
| - XFS_BTNUM_MAX = 7, | |
| -} xfs_btnum_t; | |
| - | |
| -enum xfs_dacmp { | |
| - XFS_CMP_DIFFERENT = 0, | |
| - XFS_CMP_EXACT = 1, | |
| - XFS_CMP_CASE = 2, | |
| -}; | |
| - | |
| -enum xfs_dax_mode { | |
| - XFS_DAX_INODE = 0, | |
| - XFS_DAX_ALWAYS = 1, | |
| - XFS_DAX_NEVER = 2, | |
| -}; | |
| - | |
| -enum xfs_defer_ops_type { | |
| - XFS_DEFER_OPS_TYPE_BMAP = 0, | |
| - XFS_DEFER_OPS_TYPE_REFCOUNT = 1, | |
| - XFS_DEFER_OPS_TYPE_RMAP = 2, | |
| - XFS_DEFER_OPS_TYPE_FREE = 3, | |
| - XFS_DEFER_OPS_TYPE_AGFL_FREE = 4, | |
| - XFS_DEFER_OPS_TYPE_ATTR = 5, | |
| - XFS_DEFER_OPS_TYPE_MAX = 6, | |
| -}; | |
| - | |
| -enum xfs_delattr_state { | |
| - XFS_DAS_UNINIT = 0, | |
| - XFS_DAS_SF_ADD = 1, | |
| - XFS_DAS_SF_REMOVE = 2, | |
| - XFS_DAS_LEAF_ADD = 3, | |
| - XFS_DAS_LEAF_REMOVE = 4, | |
| - XFS_DAS_NODE_ADD = 5, | |
| - XFS_DAS_NODE_REMOVE = 6, | |
| - XFS_DAS_LEAF_SET_RMT = 7, | |
| - XFS_DAS_LEAF_ALLOC_RMT = 8, | |
| - XFS_DAS_LEAF_REPLACE = 9, | |
| - XFS_DAS_LEAF_REMOVE_OLD = 10, | |
| - XFS_DAS_LEAF_REMOVE_RMT = 11, | |
| - XFS_DAS_LEAF_REMOVE_ATTR = 12, | |
| - XFS_DAS_NODE_SET_RMT = 13, | |
| - XFS_DAS_NODE_ALLOC_RMT = 14, | |
| - XFS_DAS_NODE_REPLACE = 15, | |
| - XFS_DAS_NODE_REMOVE_OLD = 16, | |
| - XFS_DAS_NODE_REMOVE_RMT = 17, | |
| - XFS_DAS_NODE_REMOVE_ATTR = 18, | |
| - XFS_DAS_DONE = 19, | |
| -}; | |
| - | |
| -enum xfs_dinode_fmt { | |
| - XFS_DINODE_FMT_DEV = 0, | |
| - XFS_DINODE_FMT_LOCAL = 1, | |
| - XFS_DINODE_FMT_EXTENTS = 2, | |
| - XFS_DINODE_FMT_BTREE = 3, | |
| - XFS_DINODE_FMT_UUID = 4, | |
| -}; | |
| - | |
| -typedef enum { | |
| - XFS_EXT_NORM = 0, | |
| - XFS_EXT_UNWRITTEN = 1, | |
| -} xfs_exntst_t; | |
| - | |
| -enum xfs_fstrm_alloc { | |
| - XFS_PICK_USERDATA = 1, | |
| - XFS_PICK_LOWSPACE = 2, | |
| -}; | |
| - | |
| -enum xfs_icwalk_goal { | |
| - XFS_ICWALK_BLOCKGC = 1, | |
| - XFS_ICWALK_RECLAIM = 0, | |
| -}; | |
| - | |
| -typedef enum { | |
| - XFS_LOOKUP_EQi = 0, | |
| - XFS_LOOKUP_LEi = 1, | |
| - XFS_LOOKUP_GEi = 2, | |
| -} xfs_lookup_t; | |
| - | |
| -enum xfs_refc_adjust_op { | |
| - XFS_REFCOUNT_ADJUST_INCREASE = 1, | |
| - XFS_REFCOUNT_ADJUST_DECREASE = -1, | |
| - XFS_REFCOUNT_ADJUST_COW_ALLOC = 0, | |
| - XFS_REFCOUNT_ADJUST_COW_FREE = -1, | |
| -}; | |
| - | |
| -enum xfs_refc_domain { | |
| - XFS_REFC_DOMAIN_SHARED = 0, | |
| - XFS_REFC_DOMAIN_COW = 1, | |
| -}; | |
| - | |
| -enum xfs_refcount_intent_type { | |
| - XFS_REFCOUNT_INCREASE = 1, | |
| - XFS_REFCOUNT_DECREASE = 2, | |
| - XFS_REFCOUNT_ALLOC_COW = 3, | |
| - XFS_REFCOUNT_FREE_COW = 4, | |
| -}; | |
| - | |
| -enum xfs_rmap_intent_type { | |
| - XFS_RMAP_MAP = 0, | |
| - XFS_RMAP_MAP_SHARED = 1, | |
| - XFS_RMAP_UNMAP = 2, | |
| - XFS_RMAP_UNMAP_SHARED = 3, | |
| - XFS_RMAP_CONVERT = 4, | |
| - XFS_RMAP_CONVERT_SHARED = 5, | |
| - XFS_RMAP_ALLOC = 6, | |
| - XFS_RMAP_FREE = 7, | |
| +enum xprt_transports { | |
| + XPRT_TRANSPORT_UDP = 17, | |
| + XPRT_TRANSPORT_TCP = 6, | |
| + XPRT_TRANSPORT_BC_TCP = -2147483642, | |
| + XPRT_TRANSPORT_RDMA = 256, | |
| + XPRT_TRANSPORT_BC_RDMA = -2147483392, | |
| + XPRT_TRANSPORT_LOCAL = 257, | |
| + XPRT_TRANSPORT_TCP_TLS = 258, | |
| }; | |
| -enum xlog_iclog_state { | |
| - XLOG_STATE_ACTIVE = 0, | |
| - XLOG_STATE_WANT_SYNC = 1, | |
| - XLOG_STATE_SYNCING = 2, | |
| - XLOG_STATE_DONE_SYNC = 3, | |
| - XLOG_STATE_CALLBACK = 4, | |
| - XLOG_STATE_DIRTY = 5, | |
| +enum xprt_xid_rb_cmp { | |
| + XID_RB_EQUAL = 0, | |
| + XID_RB_LEFT = 1, | |
| + XID_RB_RIGHT = 2, | |
| }; | |
| -enum xlog_recover_reorder { | |
| - XLOG_REORDER_BUFFER_LIST = 0, | |
| - XLOG_REORDER_ITEM_LIST = 1, | |
| - XLOG_REORDER_INODE_BUFFER_LIST = 2, | |
| - XLOG_REORDER_CANCEL_LIST = 3, | |
| +enum xprtsec_policies { | |
| + RPC_XPRTSEC_NONE = 0, | |
| + RPC_XPRTSEC_TLS_ANON = 1, | |
| + RPC_XPRTSEC_TLS_X509 = 2, | |
| }; | |
| enum xps_map_type { | |
| @@ -26311,6 +32926,22 @@ | |
| XSTATE_COPY_XSAVE = 2, | |
| }; | |
| +enum xt_bpf_modes { | |
| + XT_BPF_MODE_BYTECODE = 0, | |
| + XT_BPF_MODE_FD_PINNED = 1, | |
| + XT_BPF_MODE_FD_ELF = 2, | |
| +}; | |
| + | |
| +enum xt_statistic_flags { | |
| + XT_STATISTIC_INVERT = 1, | |
| +}; | |
| + | |
| +enum xt_statistic_mode { | |
| + XT_STATISTIC_MODE_RANDOM = 0, | |
| + XT_STATISTIC_MODE_NTH = 1, | |
| + __XT_STATISTIC_MODE_MAX = 2, | |
| +}; | |
| + | |
| enum xz_check { | |
| XZ_CHECK_NONE = 0, | |
| XZ_CHECK_CRC32 = 1, | |
| @@ -26339,6 +32970,7 @@ | |
| enum zone_flags { | |
| ZONE_BOOSTED_WATERMARK = 0, | |
| ZONE_RECLAIM_ACTIVE = 1, | |
| + ZONE_BELOW_HIGH = 2, | |
| }; | |
| enum zone_stat_item { | |
| @@ -26352,9 +32984,8 @@ | |
| NR_ZONE_WRITE_PENDING = 6, | |
| NR_MLOCK = 7, | |
| NR_BOUNCE = 8, | |
| - NR_ZSPAGES = 9, | |
| - NR_FREE_CMA_PAGES = 10, | |
| - NR_VM_ZONE_STAT_ITEMS = 11, | |
| + NR_FREE_CMA_PAGES = 9, | |
| + NR_VM_ZONE_STAT_ITEMS = 10, | |
| }; | |
| enum zone_type { | |
| @@ -26362,8 +32993,7 @@ | |
| ZONE_DMA32 = 1, | |
| ZONE_NORMAL = 2, | |
| ZONE_MOVABLE = 3, | |
| - ZONE_DEVICE = 4, | |
| - __MAX_NR_ZONES = 5, | |
| + __MAX_NR_ZONES = 4, | |
| }; | |
| enum zone_watermarks { | |
| @@ -26374,25 +33004,6 @@ | |
| NR_WMARK = 4, | |
| }; | |
| -enum zpool_mapmode { | |
| - ZPOOL_MM_RW = 0, | |
| - ZPOOL_MM_RO = 1, | |
| - ZPOOL_MM_WO = 2, | |
| - ZPOOL_MM_DEFAULT = 0, | |
| -}; | |
| - | |
| -enum zs_mapmode { | |
| - ZS_MM_RW = 0, | |
| - ZS_MM_RO = 1, | |
| - ZS_MM_WO = 2, | |
| -}; | |
| - | |
| -enum zswap_init_type { | |
| - ZSWAP_UNINIT = 0, | |
| - ZSWAP_INIT_SUCCEED = 1, | |
| - ZSWAP_INIT_FAILED = 2, | |
| -}; | |
| - | |
| enum { | |
| BPF_F_INDEX_MASK = 4294967295ULL, | |
| BPF_F_CURRENT_CPU = 4294967295ULL, | |
| @@ -26478,30 +33089,6 @@ | |
| }; | |
| enum { | |
| - MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = 256ULL, | |
| - MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = 2048ULL, | |
| - MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = 8192ULL, | |
| - MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 34359738368ULL, | |
| - MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = 549755813888ULL, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 4096ULL, | |
| - MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 524288ULL, | |
| - MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = 4294967296ULL, | |
| - MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 68719476736ULL, | |
| -}; | |
| - | |
| -enum { | |
| - MLX5_TRIGGERED_CMD_COMP = 4294967296ULL, | |
| -}; | |
| - | |
| -enum { | |
| - NVME_CAP_CRMS_CRWMS = 576460752303423488ULL, | |
| - NVME_CAP_CRMS_CRIMS = 1152921504606846976ULL, | |
| -}; | |
| - | |
| -enum { | |
| PERF_TXN_ELISION = 1ULL, | |
| PERF_TXN_TRANSACTION = 2ULL, | |
| PERF_TXN_SYNC = 4ULL, | |
| @@ -26516,19 +33103,41 @@ | |
| }; | |
| enum { | |
| - VTIME_PER_SEC_SHIFT = 37ULL, | |
| - VTIME_PER_SEC = 137438953472ULL, | |
| - VTIME_PER_USEC = 137438ULL, | |
| - VTIME_PER_NSEC = 137ULL, | |
| - VRATE_MIN_PPM = 10000ULL, | |
| - VRATE_MAX_PPM = 100000000ULL, | |
| - VRATE_MIN = 1374ULL, | |
| - VRATE_CLAMP_ADJ_PCT = 4ULL, | |
| - AUTOP_CYCLE_NSEC = 10000000000ULL, | |
| -}; | |
| - | |
| -enum { | |
| - WG_NETDEV_FEATURES = 1126357076009ULL, | |
| + REQ_F_FIXED_FILE = 1ULL, | |
| + REQ_F_IO_DRAIN = 2ULL, | |
| + REQ_F_LINK = 4ULL, | |
| + REQ_F_HARDLINK = 8ULL, | |
| + REQ_F_FORCE_ASYNC = 16ULL, | |
| + REQ_F_BUFFER_SELECT = 32ULL, | |
| + REQ_F_CQE_SKIP = 64ULL, | |
| + REQ_F_FAIL = 256ULL, | |
| + REQ_F_INFLIGHT = 512ULL, | |
| + REQ_F_CUR_POS = 1024ULL, | |
| + REQ_F_NOWAIT = 2048ULL, | |
| + REQ_F_LINK_TIMEOUT = 4096ULL, | |
| + REQ_F_NEED_CLEANUP = 8192ULL, | |
| + REQ_F_POLLED = 16384ULL, | |
| + REQ_F_BUFFER_SELECTED = 32768ULL, | |
| + REQ_F_BUFFER_RING = 65536ULL, | |
| + REQ_F_REISSUE = 131072ULL, | |
| + REQ_F_SUPPORT_NOWAIT = 268435456ULL, | |
| + REQ_F_ISREG = 536870912ULL, | |
| + REQ_F_CREDS = 262144ULL, | |
| + REQ_F_REFCOUNT = 524288ULL, | |
| + REQ_F_ARM_LTIMEOUT = 1048576ULL, | |
| + REQ_F_ASYNC_DATA = 2097152ULL, | |
| + REQ_F_SKIP_LINK_CQES = 4194304ULL, | |
| + REQ_F_SINGLE_POLL = 8388608ULL, | |
| + REQ_F_DOUBLE_POLL = 16777216ULL, | |
| + REQ_F_APOLL_MULTISHOT = 33554432ULL, | |
| + REQ_F_CLEAR_POLLIN = 67108864ULL, | |
| + REQ_F_HASH_LOCKED = 134217728ULL, | |
| + REQ_F_POLL_NO_LAZY = 1073741824ULL, | |
| + REQ_F_CANCEL_SEQ = 2147483648ULL, | |
| + REQ_F_CAN_POLL = 4294967296ULL, | |
| + REQ_F_BL_EMPTY = 8589934592ULL, | |
| + REQ_F_BL_NO_RECYCLE = 17179869184ULL, | |
| + REQ_F_BUFFERS_COMMIT = 34359738368ULL, | |
| }; | |
| enum blake2b_iv { | |
| @@ -26542,20 +33151,82 @@ | |
| BLAKE2B_IV7 = 6620516959819538809ULL, | |
| }; | |
| -enum limits { | |
| - REKEY_AFTER_MESSAGES = 1152921504606846976ULL, | |
| - REJECT_AFTER_MESSAGES = 18446744073709543486ULL, | |
| - REKEY_TIMEOUT = 5ULL, | |
| - REKEY_TIMEOUT_JITTER_MAX_JIFFIES = 333ULL, | |
| - REKEY_AFTER_TIME = 120ULL, | |
| - REJECT_AFTER_TIME = 180ULL, | |
| - INITIATIONS_PER_SECOND = 50ULL, | |
| - MAX_PEERS_PER_DEVICE = 1048576ULL, | |
| - KEEPALIVE_TIMEOUT = 10ULL, | |
| - MAX_TIMER_HANDSHAKES = 18ULL, | |
| - MAX_QUEUED_INCOMING_HANDSHAKES = 4096ULL, | |
| - MAX_STAGED_PACKETS = 128ULL, | |
| - MAX_QUEUED_PACKETS = 1024ULL, | |
| +enum hmm_pfn_flags { | |
| + HMM_PFN_VALID = 9223372036854775808ULL, | |
| + HMM_PFN_WRITE = 4611686018427387904ULL, | |
| + HMM_PFN_ERROR = 2305843009213693952ULL, | |
| + HMM_PFN_ORDER_SHIFT = 56ULL, | |
| + HMM_PFN_REQ_FAULT = 9223372036854775808ULL, | |
| + HMM_PFN_REQ_WRITE = 4611686018427387904ULL, | |
| + HMM_PFN_FLAGS = 18374686479671623680ULL, | |
| +}; | |
| + | |
| +enum ib_uverbs_device_cap_flags { | |
| + IB_UVERBS_DEVICE_RESIZE_MAX_WR = 1ULL, | |
| + IB_UVERBS_DEVICE_BAD_PKEY_CNTR = 2ULL, | |
| + IB_UVERBS_DEVICE_BAD_QKEY_CNTR = 4ULL, | |
| + IB_UVERBS_DEVICE_RAW_MULTI = 8ULL, | |
| + IB_UVERBS_DEVICE_AUTO_PATH_MIG = 16ULL, | |
| + IB_UVERBS_DEVICE_CHANGE_PHY_PORT = 32ULL, | |
| + IB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE = 64ULL, | |
| + IB_UVERBS_DEVICE_CURR_QP_STATE_MOD = 128ULL, | |
| + IB_UVERBS_DEVICE_SHUTDOWN_PORT = 256ULL, | |
| + IB_UVERBS_DEVICE_PORT_ACTIVE_EVENT = 1024ULL, | |
| + IB_UVERBS_DEVICE_SYS_IMAGE_GUID = 2048ULL, | |
| + IB_UVERBS_DEVICE_RC_RNR_NAK_GEN = 4096ULL, | |
| + IB_UVERBS_DEVICE_SRQ_RESIZE = 8192ULL, | |
| + IB_UVERBS_DEVICE_N_NOTIFY_CQ = 16384ULL, | |
| + IB_UVERBS_DEVICE_MEM_WINDOW = 131072ULL, | |
| + IB_UVERBS_DEVICE_UD_IP_CSUM = 262144ULL, | |
| + IB_UVERBS_DEVICE_XRC = 1048576ULL, | |
| + IB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS = 2097152ULL, | |
| + IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A = 8388608ULL, | |
| + IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B = 16777216ULL, | |
| + IB_UVERBS_DEVICE_RC_IP_CSUM = 33554432ULL, | |
| + IB_UVERBS_DEVICE_RAW_IP_CSUM = 67108864ULL, | |
| + IB_UVERBS_DEVICE_MANAGED_FLOW_STEERING = 536870912ULL, | |
| + IB_UVERBS_DEVICE_RAW_SCATTER_FCS = 17179869184ULL, | |
| + IB_UVERBS_DEVICE_PCI_WRITE_END_PADDING = 68719476736ULL, | |
| + IB_UVERBS_DEVICE_FLUSH_GLOBAL = 274877906944ULL, | |
| + IB_UVERBS_DEVICE_FLUSH_PERSISTENT = 549755813888ULL, | |
| + IB_UVERBS_DEVICE_ATOMIC_WRITE = 1099511627776ULL, | |
| +}; | |
| + | |
| +enum ieee80211_bss_change { | |
| + BSS_CHANGED_ASSOC = 1LL, | |
| + BSS_CHANGED_ERP_CTS_PROT = 2LL, | |
| + BSS_CHANGED_ERP_PREAMBLE = 4LL, | |
| + BSS_CHANGED_ERP_SLOT = 8LL, | |
| + BSS_CHANGED_HT = 16LL, | |
| + BSS_CHANGED_BASIC_RATES = 32LL, | |
| + BSS_CHANGED_BEACON_INT = 64LL, | |
| + BSS_CHANGED_BSSID = 128LL, | |
| + BSS_CHANGED_BEACON = 256LL, | |
| + BSS_CHANGED_BEACON_ENABLED = 512LL, | |
| + BSS_CHANGED_CQM = 1024LL, | |
| + BSS_CHANGED_IBSS = 2048LL, | |
| + BSS_CHANGED_ARP_FILTER = 4096LL, | |
| + BSS_CHANGED_QOS = 8192LL, | |
| + BSS_CHANGED_IDLE = 16384LL, | |
| + BSS_CHANGED_SSID = 32768LL, | |
| + BSS_CHANGED_AP_PROBE_RESP = 65536LL, | |
| + BSS_CHANGED_PS = 131072LL, | |
| + BSS_CHANGED_TXPOWER = 262144LL, | |
| + BSS_CHANGED_P2P_PS = 524288LL, | |
| + BSS_CHANGED_BEACON_INFO = 1048576LL, | |
| + BSS_CHANGED_BANDWIDTH = 2097152LL, | |
| + BSS_CHANGED_OCB = 4194304LL, | |
| + BSS_CHANGED_MU_GROUPS = 8388608LL, | |
| + BSS_CHANGED_KEEP_ALIVE = 16777216LL, | |
| + BSS_CHANGED_MCAST_RATE = 33554432LL, | |
| + BSS_CHANGED_FTM_RESPONDER = 67108864LL, | |
| + BSS_CHANGED_TWT = 134217728LL, | |
| + BSS_CHANGED_HE_OBSS_PD = 268435456LL, | |
| + BSS_CHANGED_HE_BSS_COLOR = 536870912LL, | |
| + BSS_CHANGED_FILS_DISCOVERY = 1073741824LL, | |
| + BSS_CHANGED_UNSOL_BCAST_PROBE_RESP = -2147483648LL, | |
| + BSS_CHANGED_MLD_VALID_LINKS = 8589934592LL, | |
| + BSS_CHANGED_MLD_TTLM = 17179869184LL, | |
| }; | |
| enum mlx4_en_wol { | |
| @@ -26597,6 +33268,7 @@ | |
| IFF_NO_ADDRCONF = 1073741824ULL, | |
| IFF_TX_SKB_NO_LINEAR = 2147483648ULL, | |
| IFF_CHANGE_PROTO_DOWN = 4294967296ULL, | |
| + IFF_SEE_ALL_HWTSTAMP_REQUESTS = 8589934592ULL, | |
| }; | |
| enum perf_callchain_context { | |
| @@ -26609,43 +33281,17 @@ | |
| PERF_CONTEXT_MAX = 18446744073709547521ULL, | |
| }; | |
| -enum scx_consts { | |
| - SCX_OPS_NAME_LEN = 128ULL, | |
| - SCX_EXIT_REASON_LEN = 128ULL, | |
| - SCX_EXIT_BT_LEN = 64ULL, | |
| - SCX_EXIT_MSG_LEN = 1024ULL, | |
| - SCX_SLICE_DFL = 20000000ULL, | |
| - SCX_SLICE_INF = 18446744073709551615ULL, | |
| -}; | |
| +typedef _Bool bool; | |
| -enum scx_deq_flags { | |
| - SCX_DEQ_SLEEP = 1ULL, | |
| - SCX_DEQ_CORE_SCHED_EXEC = 4294967296ULL, | |
| -}; | |
| +typedef __int128 unsigned __u128; | |
| -enum scx_dsq_id_flags { | |
| - SCX_DSQ_FLAG_BUILTIN = 9223372036854775808ULL, | |
| - SCX_DSQ_FLAG_LOCAL_ON = 4611686018427387904ULL, | |
| - SCX_DSQ_INVALID = 9223372036854775808ULL, | |
| - SCX_DSQ_GLOBAL = 9223372036854775809ULL, | |
| - SCX_DSQ_LOCAL = 9223372036854775810ULL, | |
| - SCX_DSQ_LOCAL_ON = 13835058055282163712ULL, | |
| - SCX_DSQ_LOCAL_CPU_MASK = 4294967295ULL, | |
| -}; | |
| +typedef __u128 u128; | |
| -enum scx_enq_flags { | |
| - SCX_ENQ_WAKEUP = 1ULL, | |
| - SCX_ENQ_HEAD = 16ULL, | |
| - SCX_ENQ_PREEMPT = 4294967296ULL, | |
| - SCX_ENQ_REENQ = 1099511627776ULL, | |
| - SCX_ENQ_LAST = 2199023255552ULL, | |
| - SCX_ENQ_LOCAL = 4398046511104ULL, | |
| - __SCX_ENQ_INTERNAL_MASK = 18374686479671623680ULL, | |
| - SCX_ENQ_CLEAR_OPSS = 72057594037927936ULL, | |
| - SCX_ENQ_DSQ_PRIQ = 144115188075855872ULL, | |
| -}; | |
| +typedef u128 freelist_full_t; | |
| -typedef _Bool bool; | |
| +typedef char *__kernel_caddr_t; | |
| + | |
| +typedef __kernel_caddr_t caddr_t; | |
| typedef char acpi_bus_id[8]; | |
| @@ -26689,6 +33335,8 @@ | |
| typedef __s32 s32; | |
| +typedef s32 codel_tdiff_t; | |
| + | |
| typedef s32 compat_clock_t; | |
| typedef s32 compat_daddr_t; | |
| @@ -26713,22 +33361,22 @@ | |
| typedef int32_t key_serial_t; | |
| -typedef int32_t xfs_suminfo_t; | |
| - | |
| typedef s32 old_time32_t; | |
| typedef __s32 sctp_assoc_t; | |
| +typedef int cydp_t; | |
| + | |
| typedef int ext4_grpblk_t; | |
| +typedef int fpb_t; | |
| + | |
| typedef int fpi_t; | |
| typedef int initcall_entry_t; | |
| typedef int insn_value_t; | |
| -typedef int mhp_t; | |
| - | |
| typedef int mpi_size_t; | |
| typedef int pci_power_t; | |
| @@ -26739,7 +33387,7 @@ | |
| typedef const int tracepoint_ptr_t; | |
| -typedef long __kernel_long_t; | |
| +typedef long int __kernel_long_t; | |
| typedef __kernel_long_t __kernel_clock_t; | |
| @@ -26763,15 +33411,15 @@ | |
| typedef __kernel_suseconds_t suseconds_t; | |
| -typedef long mpi_limb_signed_t; | |
| +typedef long int mpi_limb_signed_t; | |
| -typedef long long __kernel_loff_t; | |
| +typedef long long int __kernel_loff_t; | |
| typedef __kernel_loff_t loff_t; | |
| -typedef long long __kernel_time64_t; | |
| +typedef long long int __kernel_time64_t; | |
| -typedef long long __s64; | |
| +typedef long long int __s64; | |
| typedef __s64 Elf64_Sxword; | |
| @@ -26781,573 +33429,547 @@ | |
| typedef s64 int64_t; | |
| -typedef int64_t xfs_csn_t; | |
| - | |
| -typedef int64_t xfs_fsize_t; | |
| - | |
| -typedef int64_t xfs_lsn_t; | |
| - | |
| -typedef int64_t xfs_srtblock_t; | |
| - | |
| typedef s64 ktime_t; | |
| typedef __s64 time64_t; | |
| -typedef __s64 xfs_daddr_t; | |
| - | |
| -typedef __s64 xfs_off_t; | |
| - | |
| -typedef xfs_off_t xfs_dir2_off_t; | |
| - | |
| -typedef long long qsize_t; | |
| - | |
| -typedef short __s16; | |
| - | |
| -typedef __s16 s16; | |
| - | |
| -typedef s16 int16_t; | |
| - | |
| -typedef int16_t S16; | |
| - | |
| -typedef signed char __s8; | |
| - | |
| -typedef __s8 s8; | |
| +typedef long long int qsize_t; | |
| -typedef s8 int8_t; | |
| +typedef long long unsigned int __u64; | |
| -typedef unsigned __int128 __uint128_t; | |
| +typedef __u64 Elf64_Addr; | |
| -typedef __uint128_t u128; | |
| +typedef __u64 Elf64_Off; | |
| -typedef unsigned char Byte; | |
| +typedef __u64 Elf64_Xword; | |
| -typedef unsigned char __u8; | |
| +typedef __u64 __addrpair; | |
| -typedef __u8 mtrr_type; | |
| +typedef __u64 __be64; | |
| -typedef __u8 u8; | |
| +typedef __u64 __le64; | |
| -typedef u8 acpi_adr_space_type; | |
| +typedef __le64 twa_addr_t; | |
| -typedef u8 blk_status_t; | |
| +typedef __u64 __virtio64; | |
| -typedef u8 dscp_t; | |
| +typedef __u64 blist_flags_t; | |
| -typedef u8 efi_bool_t; | |
| +typedef __u64 timeu64_t; | |
| -typedef u8 kprobe_opcode_t; | |
| +typedef __u64 u64; | |
| -typedef u8 u_int8_t; | |
| +typedef u64 acpi_bus_address; | |
| -typedef u8 uint8_t; | |
| +typedef u64 acpi_integer; | |
| -typedef uint8_t BYTE; | |
| +typedef u64 acpi_io_address; | |
| -typedef uint8_t U8; | |
| +typedef u64 acpi_physical_address; | |
| -typedef uint8_t xfs_dqtype_t; | |
| +typedef u64 acpi_size; | |
| -typedef u8 uprobe_opcode_t; | |
| +typedef u64 async_cookie_t; | |
| -typedef unsigned char cc_t; | |
| +typedef u64 blkcnt_t; | |
| -typedef unsigned char insn_byte_t; | |
| +typedef u64 compat_u64; | |
| -typedef unsigned char u_char; | |
| +typedef u64 dma_addr_t; | |
| -typedef unsigned char uch; | |
| +typedef dma_addr_t bus_dmamap_t; | |
| -typedef unsigned int FSE_CTable; | |
| +typedef u64 gfn_t; | |
| -typedef unsigned int FSE_DTable; | |
| +typedef u64 gpa_t; | |
| -typedef unsigned int IPos; | |
| +typedef u64 hfn_t; | |
| -typedef unsigned int UHWtype; | |
| +typedef hfn_t kvm_pfn_t; | |
| -typedef unsigned int __kernel_gid32_t; | |
| +typedef u64 hpa_t; | |
| -typedef __kernel_gid32_t gid_t; | |
| +typedef u64 io_req_flags_t; | |
| -typedef unsigned int __kernel_gid_t; | |
| +typedef u64 natural_width; | |
| -typedef unsigned int __kernel_mode_t; | |
| +typedef u64 netdev_features_t; | |
| -typedef __kernel_mode_t mode_t; | |
| +typedef u64 pci_bus_addr_t; | |
| -typedef unsigned int __kernel_uid32_t; | |
| +typedef u64 phys_addr_t; | |
| -typedef __kernel_uid32_t projid_t; | |
| +typedef phys_addr_t resource_size_t; | |
| -typedef __kernel_uid32_t qid_t; | |
| +typedef u64 sci_t; | |
| -typedef __kernel_uid32_t uid_t; | |
| +typedef u64 sector_t; | |
| -typedef unsigned int __kernel_uid_t; | |
| +typedef u64 *tdp_ptep_t; | |
| -typedef unsigned int __poll_t; | |
| +typedef u64 u_int64_t; | |
| -typedef unsigned int __u32; | |
| +typedef u64 uint64_t; | |
| -typedef __u32 Elf32_Addr; | |
| +typedef uint64_t U64; | |
| -typedef __u32 Elf32_Off; | |
| +typedef U64 ZSTD_VecMask; | |
| -typedef __u32 Elf32_Word; | |
| +typedef uint64_t vli_type; | |
| -typedef __u32 Elf64_Word; | |
| +typedef u64 unative_t; | |
| -typedef __u32 __be32; | |
| +typedef u64 upf_t; | |
| -typedef __u32 __le32; | |
| +typedef long long unsigned int cycles_t; | |
| -typedef __u32 __portpair; | |
| +typedef long long unsigned int ext4_fsblk_t; | |
| -typedef __u32 __virtio32; | |
| +typedef long unsigned int __kernel_old_dev_t; | |
| -typedef __u32 __wsum; | |
| +typedef long unsigned int __kernel_ulong_t; | |
| -typedef __u32 blk_mq_req_flags_t; | |
| +typedef __kernel_ulong_t __kernel_size_t; | |
| -typedef __u32 blk_opf_t; | |
| +typedef __kernel_size_t size_t; | |
| -typedef __u32 ext4_lblk_t; | |
| +typedef size_t HUF_CElt; | |
| -typedef __u32 req_flags_t; | |
| +typedef __kernel_ulong_t aio_context_t; | |
| -typedef __u32 u32; | |
| +typedef __kernel_ulong_t ino_t; | |
| -typedef u32 __compat_gid32_t; | |
| +typedef long unsigned int dax_entry_t; | |
| -typedef u32 __compat_uid32_t; | |
| +typedef long unsigned int efi_status_t; | |
| -typedef u32 __kernel_dev_t; | |
| +typedef long unsigned int elf_greg_t; | |
| -typedef __kernel_dev_t dev_t; | |
| +typedef elf_greg_t elf_gregset_t[27]; | |
| -typedef u32 acpi_event_status; | |
| +typedef long unsigned int gva_t; | |
| -typedef u32 acpi_mutex_handle; | |
| +typedef long unsigned int hva_t; | |
| -typedef u32 acpi_name; | |
| +typedef long unsigned int irq_hw_number_t; | |
| -typedef u32 acpi_object_type; | |
| +typedef long unsigned int kernel_ulong_t; | |
| -typedef u32 acpi_rsdesc_size; | |
| +typedef long unsigned int kimage_entry_t; | |
| -typedef u32 acpi_status; | |
| +typedef long unsigned int mce_banks_t[1]; | |
| -typedef u32 compat_aio_context_t; | |
| +typedef long unsigned int mpi_limb_t; | |
| -typedef u32 compat_caddr_t; | |
| +typedef mpi_limb_t UWtype; | |
| -typedef u32 compat_ino_t; | |
| +typedef mpi_limb_t *mpi_ptr_t; | |
| -typedef u32 compat_old_sigset_t; | |
| +typedef long unsigned int netmem_ref; | |
| -typedef u32 compat_sigset_word; | |
| +typedef long unsigned int old_sigset_t; | |
| -typedef u32 compat_size_t; | |
| +typedef long unsigned int p4dval_t; | |
| -typedef u32 compat_uint_t; | |
| +typedef long unsigned int perf_trace_t[1024]; | |
| -typedef u32 compat_ulong_t; | |
| +typedef long unsigned int pgdval_t; | |
| -typedef u32 compat_uptr_t; | |
| +typedef long unsigned int pgprotval_t; | |
| -typedef u32 depot_stack_handle_t; | |
| +typedef long unsigned int pmdval_t; | |
| -typedef u32 errseq_t; | |
| +typedef long unsigned int pte_marker; | |
| -typedef u32 ixgbe_autoneg_advertised; | |
| +typedef long unsigned int pteval_t; | |
| -typedef u32 ixgbe_link_speed; | |
| +typedef long unsigned int pudval_t; | |
| -typedef u32 nlink_t; | |
| +typedef long unsigned int uLong; | |
| -typedef u32 note_buf_t[92]; | |
| +typedef long unsigned int u_long; | |
| -typedef u32 phandle; | |
| +typedef long unsigned int uintptr_t; | |
| -typedef u32 phys_cpuid_t; | |
| +typedef uintptr_t uptrval; | |
| -typedef u32 rpc_authflavor_t; | |
| +typedef long unsigned int ulg; | |
| -typedef u32 u_int32_t; | |
| +typedef long unsigned int ulong; | |
| -typedef u32 uint32_t; | |
| +typedef long unsigned int vm_flags_t; | |
| -typedef uint32_t U32; | |
| +typedef short int __s16; | |
| -typedef U32 HUF_DTable; | |
| +typedef __s16 s16; | |
| -typedef U32 rankValCol_t[13]; | |
| +typedef s16 int16_t; | |
| -typedef uint32_t drbg_flag_t; | |
| +typedef int16_t S16; | |
| -typedef uint32_t key_perm_t; | |
| +typedef short unsigned int U16; | |
| -typedef uint32_t prid_t; | |
| +typedef short unsigned int __kernel_gid16_t; | |
| -typedef uint32_t xfs_aextnum_t; | |
| +typedef __kernel_gid16_t gid16_t; | |
| -typedef uint32_t xfs_agblock_t; | |
| +typedef short unsigned int __kernel_old_gid_t; | |
| -typedef uint32_t xfs_agino_t; | |
| +typedef __kernel_old_gid_t old_gid_t; | |
| -typedef uint32_t xfs_agnumber_t; | |
| +typedef short unsigned int __kernel_old_uid_t; | |
| -typedef uint32_t xfs_dablk_t; | |
| +typedef __kernel_old_uid_t old_uid_t; | |
| -typedef uint32_t xfs_dahash_t; | |
| +typedef short unsigned int __kernel_sa_family_t; | |
| -typedef uint32_t xfs_dir2_dataptr_t; | |
| +typedef __kernel_sa_family_t sa_family_t; | |
| -typedef uint32_t xfs_dir2_db_t; | |
| +typedef short unsigned int __kernel_uid16_t; | |
| -typedef uint32_t xfs_dqid_t; | |
| +typedef __kernel_uid16_t uid16_t; | |
| -typedef uint32_t xfs_extlen_t; | |
| +typedef short unsigned int __u16; | |
| -typedef uint32_t xfs_rtword_t; | |
| +typedef __u16 Elf32_Half; | |
| -typedef uint32_t xlog_tid_t; | |
| +typedef __u16 Elf64_Half; | |
| -typedef u32 unicode_t; | |
| +typedef __u16 __be16; | |
| -typedef u32 usb_port_location_t; | |
| +typedef __u16 __le16; | |
| -typedef u32 xdp_features_t; | |
| +typedef __u16 __sum16; | |
| -typedef __u32 xfs_dev_t; | |
| +typedef __u16 __virtio16; | |
| -typedef __u32 xfs_nlink_t; | |
| +typedef __u16 bitmap_counter_t; | |
| -typedef unsigned int blk_insert_t; | |
| +typedef __u16 comp_t; | |
| -typedef unsigned int blk_qc_t; | |
| +typedef __u16 port_id; | |
| -typedef unsigned int ext4_group_t; | |
| +typedef __u16 u16; | |
| -typedef unsigned int fmode_t; | |
| +typedef u16 __compat_gid_t; | |
| -typedef unsigned int gfp_t; | |
| +typedef u16 __compat_uid_t; | |
| -typedef unsigned int insn_attr_t; | |
| +typedef u16 acpi_owner_id; | |
| -typedef unsigned int ioasid_t; | |
| +typedef u16 acpi_rs_length; | |
| -typedef unsigned int iov_iter_extraction_t; | |
| +typedef u16 compat_dev_t; | |
| -typedef unsigned int isolate_mode_t; | |
| +typedef u16 compat_ipc_pid_t; | |
| -typedef unsigned int kasan_vmalloc_flags_t; | |
| +typedef u16 compat_mode_t; | |
| -typedef unsigned int pci_channel_state_t; | |
| +typedef u16 compat_nlink_t; | |
| -typedef unsigned int pci_ers_result_t; | |
| +typedef u16 compat_ushort_t; | |
| -typedef unsigned int pgtbl_mod_mask; | |
| +typedef u16 efi_char16_t; | |
| -typedef unsigned int sk_buff_data_t; | |
| +typedef u16 u_int16_t; | |
| -typedef unsigned int slab_flags_t; | |
| +typedef u16 ucs2_char_t; | |
| -typedef unsigned int speed_t; | |
| +typedef u16 uint16_t; | |
| -typedef unsigned int t_key; | |
| +typedef uint16_t U16___2; | |
| -typedef unsigned int tcflag_t; | |
| +typedef u16 wchar_t; | |
| -typedef unsigned int tid_t; | |
| +typedef short unsigned int pci_bus_flags_t; | |
| -typedef unsigned int uInt; | |
| +typedef short unsigned int pci_dev_flags_t; | |
| -typedef unsigned int u_int; | |
| +typedef short unsigned int u_short; | |
| -typedef unsigned int uffd_flags_t; | |
| +typedef short unsigned int umode_t; | |
| -typedef unsigned int uint; | |
| +typedef short unsigned int ush; | |
| -typedef uint xfs_dir2_data_aoff_t; | |
| +typedef ush Pos; | |
| -typedef unsigned int upstat_t; | |
| +typedef short unsigned int ushort; | |
| -typedef unsigned int vm_fault_t; | |
| +typedef short unsigned int vifi_t; | |
| -typedef unsigned int xa_mark_t; | |
| +typedef signed char __s8; | |
| -typedef unsigned int xfs_buf_flags_t; | |
| +typedef __s8 s8; | |
| -typedef unsigned int xfs_km_flags_t; | |
| +typedef s8 int8_t; | |
| -typedef unsigned int zap_flags_t; | |
| +typedef unsigned char Byte; | |
| -typedef unsigned long __kernel_ulong_t; | |
| +typedef unsigned char U8; | |
| -typedef __kernel_ulong_t __kernel_size_t; | |
| +typedef unsigned char __u8; | |
| -typedef __kernel_size_t size_t; | |
| +typedef __u8 mtrr_type; | |
| -typedef size_t HUF_CElt; | |
| +typedef __u8 u8; | |
| -typedef __kernel_ulong_t aio_context_t; | |
| +typedef u8 acpi_adr_space_type; | |
| -typedef __kernel_ulong_t ino_t; | |
| +typedef u8 blk_status_t; | |
| -typedef unsigned long dax_entry_t; | |
| +typedef u8 dscp_t; | |
| -typedef unsigned long efi_status_t; | |
| +typedef u8 efi_bool_t; | |
| -typedef unsigned long elf_greg_t; | |
| +typedef u8 kprobe_opcode_t; | |
| -typedef elf_greg_t elf_gregset_t[27]; | |
| +typedef u8 rmap_age_t; | |
| -typedef unsigned long irq_hw_number_t; | |
| +typedef u8 u_int8_t; | |
| -typedef unsigned long kernel_ulong_t; | |
| +typedef u8 uint8_t; | |
| -typedef unsigned long kimage_entry_t; | |
| +typedef uint8_t BYTE; | |
| -typedef unsigned long mce_banks_t[1]; | |
| +typedef uint8_t U8___2; | |
| -typedef unsigned long mpi_limb_t; | |
| +typedef uint8_t ahd_mode_state; | |
| -typedef mpi_limb_t UWtype; | |
| +typedef u8 uprobe_opcode_t; | |
| -typedef mpi_limb_t *mpi_ptr_t; | |
| +typedef __u8 virtio_net_ctrl_ack; | |
| -typedef unsigned long old_sigset_t; | |
| +typedef unsigned char cc_t; | |
| -typedef unsigned long p4dval_t; | |
| +typedef unsigned char cisdata_t; | |
| -typedef unsigned long perf_trace_t[1024]; | |
| +typedef unsigned char insn_byte_t; | |
| -typedef unsigned long pgdval_t; | |
| +typedef unsigned char u8___2; | |
| -typedef unsigned long pgprotval_t; | |
| +typedef unsigned char u_char; | |
| -typedef unsigned long pmdval_t; | |
| +typedef unsigned char uch; | |
| -typedef unsigned long pteval_t; | |
| +typedef unsigned int FSE_CTable; | |
| -typedef unsigned long pudval_t; | |
| +typedef unsigned int FSE_DTable; | |
| -typedef unsigned long uLong; | |
| +typedef unsigned int IPos; | |
| -typedef unsigned long u_long; | |
| +typedef unsigned int UHWtype; | |
| -typedef unsigned long uintptr_t; | |
| +typedef unsigned int __kernel_gid32_t; | |
| -typedef uintptr_t uptrval; | |
| +typedef __kernel_gid32_t gid_t; | |
| -typedef unsigned long ulg; | |
| +typedef unsigned int __kernel_gid_t; | |
| -typedef unsigned long ulong; | |
| +typedef unsigned int __kernel_mode_t; | |
| -typedef unsigned long vm_flags_t; | |
| +typedef __kernel_mode_t mode_t; | |
| -typedef unsigned long long __u64; | |
| +typedef unsigned int __kernel_uid32_t; | |
| -typedef __u64 Elf64_Addr; | |
| +typedef __kernel_uid32_t projid_t; | |
| -typedef __u64 Elf64_Off; | |
| +typedef __kernel_uid32_t qid_t; | |
| -typedef __u64 Elf64_Xword; | |
| +typedef __kernel_uid32_t uid_t; | |
| -typedef __u64 __addrpair; | |
| +typedef unsigned int __kernel_uid_t; | |
| -typedef __u64 __be64; | |
| +typedef unsigned int __poll_t; | |
| -typedef __be64 xfs_bmbt_ptr_t; | |
| +typedef unsigned int __u32; | |
| -typedef __be64 xfs_bmdr_ptr_t; | |
| +typedef __u32 Elf32_Addr; | |
| -typedef __be64 xfs_timestamp_t; | |
| +typedef __u32 Elf32_Off; | |
| -typedef __u64 __le64; | |
| +typedef __u32 Elf32_Word; | |
| -typedef __u64 __virtio64; | |
| +typedef __u32 Elf64_Word; | |
| -typedef __u64 blist_flags_t; | |
| +typedef __u32 __be32; | |
| -typedef __u64 timeu64_t; | |
| +typedef __be32 rpc_fraghdr; | |
| -typedef __u64 u64; | |
| +typedef __u32 __le32; | |
| -typedef u64 acpi_bus_address; | |
| +typedef __u32 __portpair; | |
| -typedef u64 acpi_integer; | |
| +typedef __u32 __virtio32; | |
| -typedef u64 acpi_io_address; | |
| +typedef __u32 __wsum; | |
| -typedef u64 acpi_physical_address; | |
| +typedef __u32 blk_mq_req_flags_t; | |
| -typedef u64 acpi_size; | |
| +typedef __u32 blk_opf_t; | |
| -typedef u64 async_cookie_t; | |
| +typedef __u32 comp2_t; | |
| -typedef u64 blkcnt_t; | |
| +typedef __u32 ext4_lblk_t; | |
| -typedef u64 compat_u64; | |
| +typedef __u32 req_flags_t; | |
| -typedef u64 dma_addr_t; | |
| +typedef __u32 swreg; | |
| -typedef u64 gfn_t; | |
| +typedef __u32 u32; | |
| -typedef u64 gpa_t; | |
| +typedef u32 __compat_gid32_t; | |
| -typedef u64 hfn_t; | |
| +typedef u32 __compat_uid32_t; | |
| -typedef hfn_t kvm_pfn_t; | |
| +typedef u32 __kernel_dev_t; | |
| -typedef u64 hpa_t; | |
| +typedef __kernel_dev_t dev_t; | |
| -typedef u64 netdev_features_t; | |
| +typedef u32 acpi_event_status; | |
| -typedef u64 pci_bus_addr_t; | |
| +typedef u32 acpi_mutex_handle; | |
| -typedef u64 phys_addr_t; | |
| +typedef u32 acpi_name; | |
| -typedef phys_addr_t resource_size_t; | |
| +typedef u32 acpi_object_type; | |
| -typedef u64 sci_t; | |
| +typedef u32 acpi_rsdesc_size; | |
| -typedef u64 sector_t; | |
| +typedef u32 acpi_status; | |
| -typedef u64 u_int64_t; | |
| +typedef u32 codel_time_t; | |
| -typedef u64 uint64_t; | |
| +typedef u32 compat_aio_context_t; | |
| -typedef uint64_t U64; | |
| +typedef u32 compat_caddr_t; | |
| -typedef U64 ZSTD_VecMask; | |
| +typedef u32 compat_ino_t; | |
| -typedef uint64_t vli_type; | |
| +typedef u32 compat_old_sigset_t; | |
| -typedef uint64_t xfs_bmbt_rec_base_t; | |
| +typedef u32 compat_sigset_word; | |
| -typedef uint64_t xfs_extnum_t; | |
| +typedef u32 compat_size_t; | |
| -typedef uint64_t xfs_filblks_t; | |
| +typedef u32 compat_uint_t; | |
| -typedef uint64_t xfs_fileoff_t; | |
| +typedef u32 compat_ulong_t; | |
| -typedef uint64_t xfs_fsblock_t; | |
| +typedef u32 compat_uptr_t; | |
| -typedef uint64_t xfs_inofree_t; | |
| +typedef u32 depot_flags_t; | |
| -typedef uint64_t xfs_log_timestamp_t; | |
| +typedef u32 depot_stack_handle_t; | |
| -typedef uint64_t xfs_qcnt_t; | |
| +typedef u32 errseq_t; | |
| -typedef uint64_t xfs_rfsblock_t; | |
| +typedef u32 ixgbe_autoneg_advertised; | |
| -typedef uint64_t xfs_rtblock_t; | |
| +typedef u32 ixgbe_link_speed; | |
| -typedef uint64_t xfs_ufsize_t; | |
| +typedef u32 nlink_t; | |
| -typedef u64 unative_t; | |
| +typedef u32 phandle; | |
| -typedef u64 upf_t; | |
| +typedef u32 phys_cpuid_t; | |
| -typedef unsigned long long cycles_t; | |
| +typedef u32 rpc_authflavor_t; | |
| -typedef unsigned long long ext4_fsblk_t; | |
| +typedef u32 u_int32_t; | |
| -typedef unsigned long long llu; | |
| +typedef u_int32_t U32; | |
| -typedef unsigned long long xfs_ino_t; | |
| +typedef u32 uint32_t; | |
| -typedef unsigned short __kernel_gid16_t; | |
| +typedef uint32_t U32___2; | |
| -typedef __kernel_gid16_t gid16_t; | |
| +typedef U32___2 HUF_DTable; | |
| -typedef unsigned short __kernel_old_gid_t; | |
| +typedef U32___2 rankValCol_t[13]; | |
| -typedef __kernel_old_gid_t old_gid_t; | |
| +typedef uint32_t bus_size_t; | |
| -typedef unsigned short __kernel_old_uid_t; | |
| +typedef uint32_t drbg_flag_t; | |
| -typedef __kernel_old_uid_t old_uid_t; | |
| +typedef uint32_t key_perm_t; | |
| -typedef unsigned short __kernel_sa_family_t; | |
| +typedef uint32_t sense_addr_t; | |
| -typedef __kernel_sa_family_t sa_family_t; | |
| +typedef u32 unicode_t; | |
| -typedef unsigned short __kernel_uid16_t; | |
| +typedef u32 usb_port_location_t; | |
| -typedef __kernel_uid16_t uid16_t; | |
| +typedef u32 xdp_features_t; | |
| -typedef unsigned short __u16; | |
| +typedef unsigned int autofs_wqt_t; | |
| -typedef __u16 Elf32_Half; | |
| +typedef unsigned int blk_insert_t; | |
| -typedef __u16 Elf64_Half; | |
| +typedef unsigned int blk_mode_t; | |
| -typedef __u16 __be16; | |
| +typedef unsigned int blk_qc_t; | |
| -typedef __u16 __le16; | |
| +typedef unsigned int ext4_group_t; | |
| -typedef __u16 __sum16; | |
| +typedef unsigned int fgf_t; | |
| -typedef __u16 __virtio16; | |
| +typedef unsigned int fmode_t; | |
| -typedef __u16 bitmap_counter_t; | |
| +typedef unsigned int fop_flags_t; | |
| -typedef __u16 ip_set_id_t; | |
| +typedef unsigned int gfp_t; | |
| -typedef __u16 port_id; | |
| +typedef unsigned int ieee80211_rx_result; | |
| -typedef __u16 u16; | |
| +typedef unsigned int ieee80211_tx_result; | |
| -typedef u16 __compat_gid_t; | |
| +typedef unsigned int insn_attr_t; | |
| -typedef u16 __compat_uid_t; | |
| +typedef unsigned int ioasid_t; | |
| -typedef u16 acpi_owner_id; | |
| +typedef unsigned int iov_iter_extraction_t; | |
| -typedef u16 acpi_rs_length; | |
| +typedef unsigned int isolate_mode_t; | |
| -typedef u16 blk_short_t; | |
| +typedef unsigned int kasan_vmalloc_flags_t; | |
| -typedef u16 compat_ipc_pid_t; | |
| +typedef unsigned int pci_channel_state_t; | |
| -typedef u16 compat_mode_t; | |
| +typedef unsigned int pci_ers_result_t; | |
| -typedef u16 compat_nlink_t; | |
| +typedef unsigned int pcie_reset_state_t; | |
| -typedef u16 compat_ushort_t; | |
| +typedef unsigned int pgtbl_mod_mask; | |
| -typedef u16 efi_char16_t; | |
| +typedef unsigned int sk_buff_data_t; | |
| -typedef u16 u_int16_t; | |
| +typedef unsigned int slab_flags_t; | |
| -typedef u16 ucs2_char_t; | |
| +typedef unsigned int speed_t; | |
| -typedef u16 uint16_t; | |
| +typedef unsigned int sse128_t[4]; | |
| -typedef uint16_t U16; | |
| +typedef unsigned int t_key; | |
| -typedef uint16_t xfs_dir2_data_off_t; | |
| +typedef unsigned int tcflag_t; | |
| -typedef u16 wchar_t; | |
| +typedef unsigned int tid_t; | |
| -typedef unsigned short pci_bus_flags_t; | |
| +typedef unsigned int uInt; | |
| -typedef unsigned short pci_dev_flags_t; | |
| +typedef unsigned int u_int; | |
| -typedef unsigned short u_short; | |
| +typedef unsigned int uffd_flags_t; | |
| -typedef unsigned short umode_t; | |
| +typedef unsigned int uint; | |
| -typedef unsigned short ush; | |
| +typedef unsigned int upstat_t; | |
| -typedef ush Pos; | |
| +typedef unsigned int vm_fault_t; | |
| -typedef unsigned short ushort; | |
| +typedef unsigned int xa_mark_t; | |
| -typedef unsigned short vifi_t; | |
| +typedef unsigned int zap_flags_t; | |
| struct IO_APIC_route_entry { | |
| union { | |
| @@ -27381,6 +34003,26 @@ | |
| }; | |
| }; | |
| +struct POSTSTATUS { | |
| + __le32 Post_Command; | |
| + __le32 Post_Address; | |
| +}; | |
| + | |
| +struct PartitionBlock { | |
| + __be32 pb_ID; | |
| + __be32 pb_SummedLongs; | |
| + __be32 pb_ChkSum; | |
| + __be32 pb_HostID; | |
| + __be32 pb_Next; | |
| + __be32 pb_Flags; | |
| + __be32 pb_Reserved1[2]; | |
| + __be32 pb_DevFlags; | |
| + __u8 pb_DriveName[32]; | |
| + __be32 pb_Reserved2[15]; | |
| + __be32 pb_Environment[17]; | |
| + __be32 pb_EReserved[15]; | |
| +}; | |
| + | |
| struct hlist_node { | |
| struct hlist_node *next; | |
| struct hlist_node **pprev; | |
| @@ -27419,13 +34061,34 @@ | |
| typedef struct qspinlock arch_spinlock_t; | |
| +struct lock_class_key; | |
| + | |
| +struct lock_class; | |
| + | |
| +struct lockdep_map { | |
| + struct lock_class_key *key; | |
| + struct lock_class *class_cache[2]; | |
| + const char *name; | |
| + u8 wait_type_outer; | |
| + u8 wait_type_inner; | |
| + u8 lock_type; | |
| +}; | |
| + | |
| struct raw_spinlock { | |
| arch_spinlock_t raw_lock; | |
| + unsigned int magic; | |
| + unsigned int owner_cpu; | |
| + void *owner; | |
| + struct lockdep_map dep_map; | |
| }; | |
| struct spinlock { | |
| union { | |
| struct raw_spinlock rlock; | |
| + struct { | |
| + u8 __padding[24]; | |
| + struct lockdep_map dep_map; | |
| + }; | |
| }; | |
| }; | |
| @@ -27491,6 +34154,17 @@ | |
| typedef struct {} netdevice_tracker; | |
| +struct lockdep_subclass_key { | |
| + char __one_byte; | |
| +}; | |
| + | |
| +struct lock_class_key { | |
| + union { | |
| + struct hlist_node hash_entry; | |
| + struct lockdep_subclass_key subkeys[8]; | |
| + }; | |
| +}; | |
| + | |
| struct Qdisc_ops; | |
| struct qdisc_size_table; | |
| @@ -27505,14 +34179,14 @@ | |
| unsigned int flags; | |
| u32 limit; | |
| const struct Qdisc_ops *ops; | |
| - struct qdisc_size_table __attribute__((btf_type_tag("rcu"))) *stab; | |
| + struct qdisc_size_table *stab; | |
| struct hlist_node hash; | |
| u32 handle; | |
| u32 parent; | |
| struct netdev_queue *dev_queue; | |
| - struct net_rate_estimator __attribute__((btf_type_tag("rcu"))) *rate_est; | |
| - struct gnet_stats_basic_sync __attribute__((btf_type_tag("percpu"))) *cpu_bstats; | |
| - struct gnet_stats_queue __attribute__((btf_type_tag("percpu"))) *cpu_qstats; | |
| + struct net_rate_estimator *rate_est; | |
| + struct gnet_stats_basic_sync *cpu_bstats; | |
| + struct gnet_stats_queue *cpu_qstats; | |
| int pad; | |
| refcount_t refcnt; | |
| long: 64; | |
| @@ -27522,8 +34196,9 @@ | |
| struct qdisc_skb_head q; | |
| struct gnet_stats_basic_sync bstats; | |
| struct gnet_stats_queue qstats; | |
| - unsigned long state; | |
| - unsigned long state2; | |
| + int owner; | |
| + long unsigned int state; | |
| + long unsigned int state2; | |
| struct Qdisc *next_sched; | |
| struct sk_buff_head skb_bad_txq; | |
| long: 64; | |
| @@ -27537,16 +34212,17 @@ | |
| spinlock_t seqlock; | |
| struct callback_head rcu; | |
| netdevice_tracker dev_tracker; | |
| + struct lock_class_key root_lock_key; | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| - long: 64; | |
| - long privdata[0]; | |
| + long int privdata[0]; | |
| }; | |
| struct Qdisc_class_common { | |
| u32 classid; | |
| + unsigned int filter_cnt; | |
| struct hlist_node hnode; | |
| }; | |
| @@ -27574,18 +34250,18 @@ | |
| struct Qdisc_class_ops { | |
| unsigned int flags; | |
| struct netdev_queue * (*select_queue)(struct Qdisc *, struct tcmsg *); | |
| - int (*graft)(struct Qdisc *, unsigned long, struct Qdisc *, struct Qdisc **, struct netlink_ext_ack *); | |
| - struct Qdisc * (*leaf)(struct Qdisc *, unsigned long); | |
| - void (*qlen_notify)(struct Qdisc *, unsigned long); | |
| - unsigned long (*find)(struct Qdisc *, u32); | |
| - int (*change)(struct Qdisc *, u32, u32, struct nlattr **, unsigned long *, struct netlink_ext_ack *); | |
| - int (*delete)(struct Qdisc *, unsigned long, struct netlink_ext_ack *); | |
| + int (*graft)(struct Qdisc *, long unsigned int, struct Qdisc *, struct Qdisc **, struct netlink_ext_ack *); | |
| + struct Qdisc * (*leaf)(struct Qdisc *, long unsigned int); | |
| + void (*qlen_notify)(struct Qdisc *, long unsigned int); | |
| + long unsigned int (*find)(struct Qdisc *, u32); | |
| + int (*change)(struct Qdisc *, u32, u32, struct nlattr **, long unsigned int *, struct netlink_ext_ack *); | |
| + int (*delete)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *); | |
| void (*walk)(struct Qdisc *, struct qdisc_walker *); | |
| - struct tcf_block * (*tcf_block)(struct Qdisc *, unsigned long, struct netlink_ext_ack *); | |
| - unsigned long (*bind_tcf)(struct Qdisc *, unsigned long, u32); | |
| - void (*unbind_tcf)(struct Qdisc *, unsigned long); | |
| - int (*dump)(struct Qdisc *, unsigned long, struct sk_buff *, struct tcmsg *); | |
| - int (*dump_stats)(struct Qdisc *, unsigned long, struct gnet_dump *); | |
| + struct tcf_block * (*tcf_block)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *); | |
| + long unsigned int (*bind_tcf)(struct Qdisc *, long unsigned int, u32); | |
| + void (*unbind_tcf)(struct Qdisc *, long unsigned int); | |
| + int (*dump)(struct Qdisc *, long unsigned int, struct sk_buff *, struct tcmsg *); | |
| + int (*dump_stats)(struct Qdisc *, long unsigned int, struct gnet_dump *); | |
| }; | |
| struct module; | |
| @@ -27615,6 +34291,119 @@ | |
| struct module *owner; | |
| }; | |
| +struct RR_CL_s { | |
| + __u8 location[8]; | |
| +}; | |
| + | |
| +struct RR_NM_s { | |
| + __u8 flags; | |
| + char name[0]; | |
| +}; | |
| + | |
| +struct RR_PL_s { | |
| + __u8 location[8]; | |
| +}; | |
| + | |
| +struct RR_PN_s { | |
| + __u8 dev_high[8]; | |
| + __u8 dev_low[8]; | |
| +}; | |
| + | |
| +struct RR_PX_s { | |
| + __u8 mode[8]; | |
| + __u8 n_links[8]; | |
| + __u8 uid[8]; | |
| + __u8 gid[8]; | |
| +}; | |
| + | |
| +struct RR_RR_s { | |
| + __u8 flags[1]; | |
| +}; | |
| + | |
| +struct SL_component { | |
| + __u8 flags; | |
| + __u8 len; | |
| + __u8 text[0]; | |
| +}; | |
| + | |
| +struct RR_SL_s { | |
| + __u8 flags; | |
| + struct SL_component link; | |
| +}; | |
| + | |
| +struct stamp { | |
| + __u8 time[7]; | |
| +}; | |
| + | |
| +struct RR_TF_s { | |
| + __u8 flags; | |
| + struct stamp times[0]; | |
| +}; | |
| + | |
| +struct RR_ZF_s { | |
| + __u8 algorithm[2]; | |
| + __u8 parms[2]; | |
| + __u8 real_size[8]; | |
| +}; | |
| + | |
| +struct RigidDiskBlock { | |
| + __be32 rdb_ID; | |
| + __be32 rdb_SummedLongs; | |
| + __be32 rdb_ChkSum; | |
| + __be32 rdb_HostID; | |
| + __be32 rdb_BlockBytes; | |
| + __be32 rdb_Flags; | |
| + __be32 rdb_BadBlockList; | |
| + __be32 rdb_PartitionList; | |
| + __be32 rdb_FileSysHeaderList; | |
| + __be32 rdb_DriveInit; | |
| + __be32 rdb_Reserved1[6]; | |
| + __be32 rdb_Cylinders; | |
| + __be32 rdb_Sectors; | |
| + __be32 rdb_Heads; | |
| + __be32 rdb_Interleave; | |
| + __be32 rdb_Park; | |
| + __be32 rdb_Reserved2[3]; | |
| + __be32 rdb_WritePreComp; | |
| + __be32 rdb_ReducedWrite; | |
| + __be32 rdb_StepRate; | |
| + __be32 rdb_Reserved3[5]; | |
| + __be32 rdb_RDBBlocksLo; | |
| + __be32 rdb_RDBBlocksHi; | |
| + __be32 rdb_LoCylinder; | |
| + __be32 rdb_HiCylinder; | |
| + __be32 rdb_CylBlocks; | |
| + __be32 rdb_AutoParkSeconds; | |
| + __be32 rdb_HighRDSKBlock; | |
| + __be32 rdb_Reserved4; | |
| + char rdb_DiskVendor[8]; | |
| + char rdb_DiskProduct[16]; | |
| + char rdb_DiskRevision[4]; | |
| + char rdb_ControllerVendor[8]; | |
| + char rdb_ControllerProduct[16]; | |
| + char rdb_ControllerRevision[4]; | |
| + __be32 rdb_Reserved5[10]; | |
| +}; | |
| + | |
| +struct SU_CE_s { | |
| + __u8 extent[8]; | |
| + __u8 offset[8]; | |
| + __u8 size[8]; | |
| +}; | |
| + | |
| +struct SU_ER_s { | |
| + __u8 len_id; | |
| + __u8 len_des; | |
| + __u8 len_src; | |
| + __u8 ext_ver; | |
| + __u8 data[0]; | |
| +}; | |
| + | |
| +struct SU_SP_s { | |
| + __u8 magic[2]; | |
| + __u8 skip; | |
| +}; | |
| + | |
| struct list_head { | |
| struct list_head *next; | |
| struct list_head *prev; | |
| @@ -27631,6 +34420,8 @@ | |
| raw_spinlock_t wait_lock; | |
| struct optimistic_spin_queue osq; | |
| struct list_head wait_list; | |
| + void *magic; | |
| + struct lockdep_map dep_map; | |
| }; | |
| struct wait_queue_head { | |
| @@ -27719,6 +34510,45 @@ | |
| typedef struct pm_message pm_message_t; | |
| +struct rb_node { | |
| + long unsigned int __rb_parent_color; | |
| + struct rb_node *rb_right; | |
| + struct rb_node *rb_left; | |
| +}; | |
| + | |
| +struct timerqueue_node { | |
| + struct rb_node node; | |
| + ktime_t expires; | |
| +}; | |
| + | |
| +struct hrtimer_clock_base; | |
| + | |
| +struct hrtimer { | |
| + struct timerqueue_node node; | |
| + ktime_t _softexpires; | |
| + enum hrtimer_restart (*function)(struct hrtimer *); | |
| + struct hrtimer_clock_base *base; | |
| + u8 state; | |
| + u8 is_rel; | |
| + u8 is_soft; | |
| + u8 is_hard; | |
| +}; | |
| + | |
| +struct work_struct; | |
| + | |
| +typedef void (*work_func_t)(struct work_struct *); | |
| + | |
| +struct work_struct { | |
| + atomic_long_t data; | |
| + struct list_head entry; | |
| + work_func_t func; | |
| + struct lockdep_map lockdep_map; | |
| +}; | |
| + | |
| +struct wakeup_source; | |
| + | |
| +struct wake_irq; | |
| + | |
| struct pm_subsys_data; | |
| struct device; | |
| @@ -27727,8 +34557,8 @@ | |
| struct dev_pm_info { | |
| pm_message_t power_state; | |
| - unsigned int can_wakeup: 1; | |
| - unsigned int async_suspend: 1; | |
| + bool can_wakeup: 1; | |
| + bool async_suspend: 1; | |
| bool in_dpm_list: 1; | |
| bool is_prepared: 1; | |
| bool is_suspended: 1; | |
| @@ -27739,7 +34569,44 @@ | |
| bool direct_complete: 1; | |
| u32 driver_flags; | |
| spinlock_t lock; | |
| - unsigned int should_wakeup: 1; | |
| + struct list_head entry; | |
| + struct completion completion; | |
| + struct wakeup_source *wakeup; | |
| + bool wakeup_path: 1; | |
| + bool syscore: 1; | |
| + bool no_pm_callbacks: 1; | |
| + bool async_in_progress: 1; | |
| + bool must_resume: 1; | |
| + bool may_skip_resume: 1; | |
| + struct hrtimer suspend_timer; | |
| + u64 timer_expires; | |
| + struct work_struct work; | |
| + wait_queue_head_t wait_queue; | |
| + struct wake_irq *wakeirq; | |
| + atomic_t usage_count; | |
| + atomic_t child_count; | |
| + unsigned int disable_depth: 3; | |
| + bool idle_notification: 1; | |
| + bool request_pending: 1; | |
| + bool deferred_resume: 1; | |
| + bool needs_force_resume: 1; | |
| + bool runtime_auto: 1; | |
| + bool ignore_children: 1; | |
| + bool no_callbacks: 1; | |
| + bool irq_safe: 1; | |
| + bool use_autosuspend: 1; | |
| + bool timer_autosuspends: 1; | |
| + bool memalloc_noio: 1; | |
| + unsigned int links_count; | |
| + enum rpm_request request; | |
| + enum rpm_status runtime_status; | |
| + enum rpm_status last_status; | |
| + int runtime_error; | |
| + int autosuspend_delay; | |
| + u64 last_busy; | |
| + u64 active_time; | |
| + u64 suspended_time; | |
| + u64 accounting_timestamp; | |
| struct pm_subsys_data *subsys_data; | |
| void (*set_latency_tolerance)(struct device *, s32); | |
| struct dev_pm_qos *qos; | |
| @@ -27866,22 +34733,23 @@ | |
| unsigned int host_eh_scheduled; | |
| unsigned int host_no; | |
| int eh_deadline; | |
| - unsigned long last_reset; | |
| + long unsigned int last_reset; | |
| unsigned int max_channel; | |
| unsigned int max_id; | |
| u64 max_lun; | |
| unsigned int unique_id; | |
| - unsigned short max_cmd_len; | |
| + short unsigned int max_cmd_len; | |
| int this_id; | |
| int can_queue; | |
| - short cmd_per_lun; | |
| - unsigned short sg_tablesize; | |
| - unsigned short sg_prot_tablesize; | |
| + short int cmd_per_lun; | |
| + short unsigned int sg_tablesize; | |
| + short unsigned int sg_prot_tablesize; | |
| unsigned int max_sectors; | |
| unsigned int opt_sectors; | |
| unsigned int max_segment_size; | |
| - unsigned long dma_boundary; | |
| - unsigned long virt_boundary_mask; | |
| + unsigned int dma_alignment; | |
| + long unsigned int dma_boundary; | |
| + long unsigned int virt_boundary_mask; | |
| unsigned int nr_hw_queues; | |
| unsigned int nr_maps; | |
| unsigned int active_mode: 2; | |
| @@ -27892,16 +34760,18 @@ | |
| unsigned int eh_noresume: 1; | |
| unsigned int no_write_same: 1; | |
| unsigned int host_tagset: 1; | |
| + unsigned int queuecommand_may_block: 1; | |
| unsigned int short_inquiry: 1; | |
| unsigned int no_scsi2_lun_in_cdb: 1; | |
| + unsigned int no_highmem: 1; | |
| char work_q_name[20]; | |
| struct workqueue_struct *work_q; | |
| struct workqueue_struct *tmf_work_q; | |
| unsigned int max_host_blocked; | |
| unsigned int prot_capabilities; | |
| unsigned char prot_guard_type; | |
| - unsigned long base; | |
| - unsigned long io_port; | |
| + long unsigned int base; | |
| + long unsigned int io_port; | |
| unsigned char n_io_port; | |
| unsigned char dma_channel; | |
| unsigned int irq; | |
| @@ -27910,9 +34780,293 @@ | |
| struct device shost_dev; | |
| void *shost_data; | |
| struct device *dma_dev; | |
| - unsigned long hostdata[0]; | |
| + int rpm_autosuspend_delay; | |
| + long unsigned int hostdata[0]; | |
| +}; | |
| + | |
| +struct Symbios_host { | |
| + u_short type; | |
| + u_short device_id; | |
| + u_short vendor_id; | |
| + u_char bus_nr; | |
| + u_char device_fn; | |
| + u_short word8; | |
| + u_short flags; | |
| + u_short io_port; | |
| +}; | |
| + | |
| +struct Symbios_target { | |
| + u_char flags; | |
| + u_char rsvd; | |
| + u_char bus_width; | |
| + u_char sync_offset; | |
| + u_short sync_period; | |
| + u_short timeout; | |
| +}; | |
| + | |
| +struct Symbios_scam { | |
| + u_short id; | |
| + u_short method; | |
| + u_short status; | |
| + u_char target_id; | |
| + u_char rsvd; | |
| +}; | |
| + | |
| +struct Symbios_nvram { | |
| + u_short type; | |
| + u_short byte_count; | |
| + u_short checksum; | |
| + u_char v_major; | |
| + u_char v_minor; | |
| + u32 boot_crc; | |
| + u_short flags; | |
| + u_short flags1; | |
| + u_short term_state; | |
| + u_short rmvbl_flags; | |
| + u_char host_id; | |
| + u_char num_hba; | |
| + u_char num_devices; | |
| + u_char max_scam_devices; | |
| + u_char num_valid_scam_devices; | |
| + u_char flags2; | |
| + struct Symbios_host host[4]; | |
| + struct Symbios_target target[16]; | |
| + struct Symbios_scam scam[4]; | |
| + u_char spare_devices[120]; | |
| + u_char trailer[6]; | |
| +}; | |
| + | |
| +typedef struct Symbios_nvram Symbios_nvram; | |
| + | |
| +typedef struct Symbios_target Symbios_target; | |
| + | |
| +struct TAG_TW_SG_Entry { | |
| + twa_addr_t address; | |
| + __le32 length; | |
| +} __attribute__((packed)); | |
| + | |
| +typedef struct TAG_TW_SG_Entry TW_SG_Entry; | |
| + | |
| +struct TAG_TW_Command_Apache { | |
| + u8 opcode__reserved; | |
| + u8 unit; | |
| + __le16 request_id__lunl; | |
| + u8 status; | |
| + u8 sgl_offset; | |
| + __le16 sgl_entries__lunh; | |
| + u8 cdb[16]; | |
| + TW_SG_Entry sg_list[72]; | |
| + u8 padding[8]; | |
| +}; | |
| + | |
| +typedef struct TAG_TW_Command_Apache TW_Command_Apache; | |
| + | |
| +struct TAG_TW_Command_Apache_Header { | |
| + unsigned char sense_data[18]; | |
| + struct { | |
| + u8 reserved[4]; | |
| + __le16 error; | |
| + u8 padding; | |
| + u8 severity__reserved; | |
| + } status_block; | |
| + unsigned char err_specific_desc[98]; | |
| + struct { | |
| + u8 size_header; | |
| + u8 reserved[2]; | |
| + u8 size_sense; | |
| + } header_desc; | |
| +}; | |
| + | |
| +typedef struct TAG_TW_Command_Apache_Header TW_Command_Apache_Header; | |
| + | |
| +struct TW_Command { | |
| + u8 opcode__sgloffset; | |
| + u8 size; | |
| + u8 request_id; | |
| + u8 unit__hostid; | |
| + u8 status; | |
| + u8 flags; | |
| + union { | |
| + __le16 block_count; | |
| + __le16 parameter_count; | |
| + } byte6_offset; | |
| + union { | |
| + struct { | |
| + __le32 lba; | |
| + TW_SG_Entry sgl[41]; | |
| + twa_addr_t padding; | |
| + } io; | |
| + struct { | |
| + TW_SG_Entry sgl[41]; | |
| + __le32 padding; | |
| + twa_addr_t padding2; | |
| + } param; | |
| + } byte8_offset; | |
| +}; | |
| + | |
| +typedef struct TW_Command TW_Command; | |
| + | |
| +struct TAG_TW_Command_Full { | |
| + TW_Command_Apache_Header header; | |
| + union { | |
| + TW_Command oldcommand; | |
| + TW_Command_Apache newcommand; | |
| + } command; | |
| +}; | |
| + | |
| +typedef struct TAG_TW_Command_Full TW_Command_Full; | |
| + | |
| +struct TAG_TW_Compatibility_Info { | |
| + char driver_version[32]; | |
| + short unsigned int working_srl; | |
| + short unsigned int working_branch; | |
| + short unsigned int working_build; | |
| + short unsigned int driver_srl_high; | |
| + short unsigned int driver_branch_high; | |
| + short unsigned int driver_build_high; | |
| + short unsigned int driver_srl_low; | |
| + short unsigned int driver_branch_low; | |
| + short unsigned int driver_build_low; | |
| + short unsigned int fw_on_ctlr_srl; | |
| + short unsigned int fw_on_ctlr_branch; | |
| + short unsigned int fw_on_ctlr_build; | |
| }; | |
| +typedef struct TAG_TW_Compatibility_Info TW_Compatibility_Info; | |
| + | |
| +struct pci_dev; | |
| + | |
| +struct scsi_cmnd; | |
| + | |
| +struct TAG_TW_Event; | |
| + | |
| +typedef struct TAG_TW_Event TW_Event; | |
| + | |
| +struct TAG_TW_Device_Extension { | |
| + u32 *base_addr; | |
| + long unsigned int *generic_buffer_virt[256]; | |
| + dma_addr_t generic_buffer_phys[256]; | |
| + TW_Command_Full *command_packet_virt[256]; | |
| + dma_addr_t command_packet_phys[256]; | |
| + struct pci_dev *tw_pci_dev; | |
| + struct scsi_cmnd *srb[256]; | |
| + unsigned char free_queue[256]; | |
| + unsigned char free_head; | |
| + unsigned char free_tail; | |
| + unsigned char pending_queue[256]; | |
| + unsigned char pending_head; | |
| + unsigned char pending_tail; | |
| + int state[256]; | |
| + unsigned int posted_request_count; | |
| + unsigned int max_posted_request_count; | |
| + unsigned int pending_request_count; | |
| + unsigned int max_pending_request_count; | |
| + unsigned int max_sgl_entries; | |
| + unsigned int sgl_entries; | |
| + unsigned int num_resets; | |
| + unsigned int sector_count; | |
| + unsigned int max_sector_count; | |
| + unsigned int aen_count; | |
| + struct Scsi_Host *host; | |
| + long int flags; | |
| + int reset_print; | |
| + TW_Event *event_queue[256]; | |
| + unsigned char error_index; | |
| + unsigned char event_queue_wrapped; | |
| + unsigned int error_sequence_id; | |
| + int ioctl_sem_lock; | |
| + ktime_t ioctl_time; | |
| + int chrdev_request_id; | |
| + wait_queue_head_t ioctl_wqueue; | |
| + struct mutex ioctl_lock; | |
| + char aen_clobber; | |
| + TW_Compatibility_Info tw_compat_info; | |
| +}; | |
| + | |
| +typedef struct TAG_TW_Device_Extension TW_Device_Extension; | |
| + | |
| +struct TAG_TW_Event { | |
| + unsigned int sequence_id; | |
| + unsigned int time_stamp_sec; | |
| + short unsigned int aen_code; | |
| + unsigned char severity; | |
| + unsigned char retrieved; | |
| + unsigned char repeat_count; | |
| + unsigned char parameter_len; | |
| + unsigned char parameter_data[98]; | |
| +}; | |
| + | |
| +struct TAG_TW_Initconnect { | |
| + u8 opcode__reserved; | |
| + u8 size; | |
| + u8 request_id; | |
| + u8 res2; | |
| + u8 status; | |
| + u8 flags; | |
| + __le16 message_credits; | |
| + __le32 features; | |
| + __le16 fw_srl; | |
| + __le16 fw_arch_id; | |
| + __le16 fw_branch; | |
| + __le16 fw_build; | |
| + __le32 result; | |
| +}; | |
| + | |
| +typedef struct TAG_TW_Initconnect TW_Initconnect; | |
| + | |
| +struct TAG_TW_Ioctl_Driver_Command { | |
| + unsigned int control_code; | |
| + unsigned int status; | |
| + unsigned int unique_id; | |
| + unsigned int sequence_id; | |
| + unsigned int os_specific; | |
| + unsigned int buffer_length; | |
| +}; | |
| + | |
| +typedef struct TAG_TW_Ioctl_Driver_Command TW_Ioctl_Driver_Command; | |
| + | |
| +struct TAG_TW_Ioctl_Apache { | |
| + TW_Ioctl_Driver_Command driver_command; | |
| + char padding[488]; | |
| + TW_Command_Full firmware_command; | |
| + char data_buffer[0]; | |
| +}; | |
| + | |
| +typedef struct TAG_TW_Ioctl_Apache TW_Ioctl_Buf_Apache; | |
| + | |
| +struct TAG_TW_Lock { | |
| + long unsigned int timeout_msec; | |
| + long unsigned int time_remaining_msec; | |
| + long unsigned int force_flag; | |
| +}; | |
| + | |
| +typedef struct TAG_TW_Lock TW_Lock; | |
| + | |
| +struct TAG_twa_message_type { | |
| + unsigned int code; | |
| + char *text; | |
| +}; | |
| + | |
| +typedef struct TAG_twa_message_type twa_message_type; | |
| + | |
| +struct Tekram_target { | |
| + u_char flags; | |
| + u_char sync_index; | |
| + u_short word2; | |
| +}; | |
| + | |
| +struct Tekram_nvram { | |
| + struct Tekram_target target[16]; | |
| + u_char host_id; | |
| + u_char flags; | |
| + u_char boot_delay_index; | |
| + u_char max_tags_index; | |
| + u_short flags1; | |
| + u_short spare[29]; | |
| +}; | |
| + | |
| +typedef struct Tekram_nvram Tekram_nvram; | |
| + | |
| typedef struct { | |
| unsigned int windowLog; | |
| unsigned int chainLog; | |
| @@ -27931,11 +35085,11 @@ | |
| typedef struct { | |
| ZSTD_paramSwitch_e enableLdm; | |
| - U32 hashLog; | |
| - U32 bucketSizeLog; | |
| - U32 minMatchLength; | |
| - U32 hashRateLog; | |
| - U32 windowLog; | |
| + U32___2 hashLog; | |
| + U32___2 bucketSizeLog; | |
| + U32___2 minMatchLength; | |
| + U32___2 hashRateLog; | |
| + U32___2 windowLog; | |
| } ldmParams_t; | |
| typedef void * (*ZSTD_allocFunction)(void *, size_t); | |
| @@ -27972,6 +35126,11 @@ | |
| ZSTD_paramSwitch_e useRowMatchFinder; | |
| int deterministicRefPrefix; | |
| ZSTD_customMem customMem; | |
| + ZSTD_paramSwitch_e prefetchCDictTables; | |
| + int enableMatchFinderFallback; | |
| + int useSequenceProducer; | |
| + size_t maxBlockSize; | |
| + ZSTD_paramSwitch_e searchForExternalRepcodes; | |
| }; | |
| typedef struct ZSTD_CCtx_params_s ZSTD_CCtx_params; | |
| @@ -27983,6 +35142,7 @@ | |
| void *tableEnd; | |
| void *tableValidEnd; | |
| void *allocStart; | |
| + void *initOnceStart; | |
| BYTE allocFailed; | |
| int workspaceOversizedDuration; | |
| ZSTD_cwksp_alloc_phase_e phase; | |
| @@ -28032,43 +35192,43 @@ | |
| size_t maxNbSeq; | |
| size_t maxNbLit; | |
| ZSTD_longLengthType_e longLengthType; | |
| - U32 longLengthPos; | |
| + U32___2 longLengthPos; | |
| } seqStore_t; | |
| typedef struct { | |
| const BYTE *nextSrc; | |
| const BYTE *base; | |
| const BYTE *dictBase; | |
| - U32 dictLimit; | |
| - U32 lowLimit; | |
| - U32 nbOverflowCorrections; | |
| + U32___2 dictLimit; | |
| + U32___2 lowLimit; | |
| + U32___2 nbOverflowCorrections; | |
| } ZSTD_window_t; | |
| typedef struct { | |
| - U32 offset; | |
| - U32 checksum; | |
| + U32___2 offset; | |
| + U32___2 checksum; | |
| } ldmEntry_t; | |
| typedef struct { | |
| const BYTE *split; | |
| - U32 hash; | |
| - U32 checksum; | |
| + U32___2 hash; | |
| + U32___2 checksum; | |
| ldmEntry_t *bucket; | |
| } ldmMatchCandidate_t; | |
| typedef struct { | |
| ZSTD_window_t window; | |
| ldmEntry_t *hashTable; | |
| - U32 loadedDictEnd; | |
| + U32___2 loadedDictEnd; | |
| BYTE *bucketOffsets; | |
| size_t splitIndices[64]; | |
| ldmMatchCandidate_t matchCandidates[64]; | |
| } ldmState_t; | |
| typedef struct { | |
| - U32 offset; | |
| - U32 litLength; | |
| - U32 matchLength; | |
| + U32___2 offset; | |
| + U32___2 litLength; | |
| + U32___2 matchLength; | |
| } rawSeq; | |
| typedef struct { | |
| @@ -28100,20 +35260,20 @@ | |
| typedef struct { | |
| ZSTD_entropyCTables_t entropy; | |
| - U32 rep[3]; | |
| + U32___2 rep[3]; | |
| } ZSTD_compressedBlockState_t; | |
| typedef struct { | |
| - U32 off; | |
| - U32 len; | |
| + U32___2 off; | |
| + U32___2 len; | |
| } ZSTD_match_t; | |
| typedef struct { | |
| int price; | |
| - U32 off; | |
| - U32 mlen; | |
| - U32 litlen; | |
| - U32 rep[3]; | |
| + U32___2 off; | |
| + U32___2 mlen; | |
| + U32___2 litlen; | |
| + U32___2 rep[3]; | |
| } ZSTD_optimal_t; | |
| typedef struct { | |
| @@ -28123,14 +35283,14 @@ | |
| unsigned int *offCodeFreq; | |
| ZSTD_match_t *matchTable; | |
| ZSTD_optimal_t *priceTable; | |
| - U32 litSum; | |
| - U32 litLengthSum; | |
| - U32 matchLengthSum; | |
| - U32 offCodeSum; | |
| - U32 litSumBasePrice; | |
| - U32 litLengthSumBasePrice; | |
| - U32 matchLengthSumBasePrice; | |
| - U32 offCodeSumBasePrice; | |
| + U32___2 litSum; | |
| + U32___2 litLengthSum; | |
| + U32___2 matchLengthSum; | |
| + U32___2 offCodeSum; | |
| + U32___2 litSumBasePrice; | |
| + U32___2 litLengthSumBasePrice; | |
| + U32___2 matchLengthSumBasePrice; | |
| + U32___2 offCodeSumBasePrice; | |
| ZSTD_OptPrice_e priceType; | |
| const ZSTD_entropyCTables_t *symbolCosts; | |
| ZSTD_paramSwitch_e literalCompressionMode; | |
| @@ -28142,21 +35302,25 @@ | |
| struct ZSTD_matchState_t { | |
| ZSTD_window_t window; | |
| - U32 loadedDictEnd; | |
| - U32 nextToUpdate; | |
| - U32 hashLog3; | |
| - U32 rowHashLog; | |
| - U16 *tagTable; | |
| - U32 hashCache[8]; | |
| - U32 *hashTable; | |
| - U32 *hashTable3; | |
| - U32 *chainTable; | |
| - U32 forceNonContiguous; | |
| + U32___2 loadedDictEnd; | |
| + U32___2 nextToUpdate; | |
| + U32___2 hashLog3; | |
| + U32___2 rowHashLog; | |
| + BYTE *tagTable; | |
| + U32___2 hashCache[8]; | |
| + U64 hashSalt; | |
| + U32___2 hashSaltEntropy; | |
| + U32___2 *hashTable; | |
| + U32___2 *hashTable3; | |
| + U32___2 *chainTable; | |
| + U32___2 forceNonContiguous; | |
| int dedicatedDictSearch; | |
| optState_t opt; | |
| const ZSTD_matchState_t *dictMatchState; | |
| ZSTD_compressionParameters cParams; | |
| const rawSeqStore_t *ldmSeqStore; | |
| + int prefetchCDictTables; | |
| + int lazySkipping; | |
| }; | |
| typedef struct { | |
| @@ -28219,10 +35383,19 @@ | |
| seqStore_t secondHalfSeqStore; | |
| seqStore_t currSeqStore; | |
| seqStore_t nextSeqStore; | |
| - U32 partitions[196]; | |
| + U32___2 partitions[196]; | |
| ZSTD_entropyCTablesMetadata_t entropyMetadata; | |
| } ZSTD_blockSplitCtx; | |
| +typedef size_t ZSTD_sequenceProducer_F(void *, ZSTD_Sequence *, size_t, const void *, size_t, const void *, size_t, int, size_t); | |
| + | |
| +typedef struct { | |
| + void *mState; | |
| + ZSTD_sequenceProducer_F *mFinder; | |
| + ZSTD_Sequence *seqBuffer; | |
| + size_t seqBufferCapacity; | |
| +} ZSTD_externalMatchCtx; | |
| + | |
| struct ZSTD_CCtx_s { | |
| ZSTD_compressionStage_e stage; | |
| int cParamsChanged; | |
| @@ -28230,13 +35403,13 @@ | |
| ZSTD_CCtx_params requestedParams; | |
| ZSTD_CCtx_params appliedParams; | |
| ZSTD_CCtx_params simpleApiParams; | |
| - U32 dictID; | |
| + U32___2 dictID; | |
| size_t dictContentSize; | |
| ZSTD_cwksp workspace; | |
| size_t blockSize; | |
| - unsigned long long pledgedSrcSizePlusOne; | |
| - unsigned long long consumedSrcSize; | |
| - unsigned long long producedCSize; | |
| + long long unsigned int pledgedSrcSizePlusOne; | |
| + long long unsigned int consumedSrcSize; | |
| + long long unsigned int producedCSize; | |
| struct xxh64_state xxhState; | |
| ZSTD_customMem customMem; | |
| ZSTD_threadPool *pool; | |
| @@ -28250,7 +35423,7 @@ | |
| size_t maxNbLdmSequences; | |
| rawSeqStore_t externSeqStore; | |
| ZSTD_blockState_t blockState; | |
| - U32 *entropyWorkspace; | |
| + U32___2 *entropyWorkspace; | |
| ZSTD_buffered_policy_e bufferedPolicy; | |
| char *inBuff; | |
| size_t inBuffSize; | |
| @@ -28262,13 +35435,15 @@ | |
| size_t outBuffContentSize; | |
| size_t outBuffFlushedSize; | |
| ZSTD_cStreamStage streamStage; | |
| - U32 frameEnded; | |
| + U32___2 frameEnded; | |
| ZSTD_inBuffer expectedInBuffer; | |
| + size_t stableIn_notConsumed; | |
| size_t expectedOutBufferSize; | |
| ZSTD_localDict localDict; | |
| const ZSTD_CDict *cdict; | |
| ZSTD_prefixDict prefixDict; | |
| ZSTD_blockSplitCtx blockSplitCtx; | |
| + ZSTD_externalMatchCtx externalMatchCtx; | |
| }; | |
| typedef struct ZSTD_CCtx_s ZSTD_CCtx; | |
| @@ -28283,21 +35458,21 @@ | |
| const void *dictContent; | |
| size_t dictContentSize; | |
| ZSTD_dictContentType_e dictContentType; | |
| - U32 *entropyWorkspace; | |
| + U32___2 *entropyWorkspace; | |
| ZSTD_cwksp workspace; | |
| ZSTD_matchState_t matchState; | |
| ZSTD_compressedBlockState_t cBlockState; | |
| ZSTD_customMem customMem; | |
| - U32 dictID; | |
| + U32___2 dictID; | |
| int compressionLevel; | |
| ZSTD_paramSwitch_e useRowMatchFinder; | |
| }; | |
| typedef struct { | |
| - U16 nextState; | |
| + U16___2 nextState; | |
| BYTE nbAdditionalBits; | |
| BYTE nbBits; | |
| - U32 baseValue; | |
| + U32___2 baseValue; | |
| } ZSTD_seqSymbol; | |
| typedef struct { | |
| @@ -28305,18 +35480,20 @@ | |
| ZSTD_seqSymbol OFTable[257]; | |
| ZSTD_seqSymbol MLTable[513]; | |
| HUF_DTable hufTable[4097]; | |
| - U32 rep[3]; | |
| - U32 workspace[157]; | |
| + U32___2 rep[3]; | |
| + U32___2 workspace[157]; | |
| } ZSTD_entropyDTables_t; | |
| typedef struct { | |
| - unsigned long long frameContentSize; | |
| - unsigned long long windowSize; | |
| + long long unsigned int frameContentSize; | |
| + long long unsigned int windowSize; | |
| unsigned int blockSizeMax; | |
| ZSTD_frameType_e frameType; | |
| unsigned int headerSize; | |
| unsigned int dictID; | |
| unsigned int checksumFlag; | |
| + unsigned int _reserved1; | |
| + unsigned int _reserved2; | |
| } ZSTD_frameHeader; | |
| struct ZSTD_DDict_s; | |
| @@ -28343,7 +35520,7 @@ | |
| const ZSTD_seqSymbol *OFTptr; | |
| const HUF_DTable *HUFptr; | |
| ZSTD_entropyDTables_t entropy; | |
| - U32 workspace[640]; | |
| + U32___2 workspace[640]; | |
| const void *previousDstEnd; | |
| const void *prefixStart; | |
| const void *virtualStart; | |
| @@ -28354,13 +35531,13 @@ | |
| U64 decodedSize; | |
| blockType_e bType; | |
| ZSTD_dStage stage; | |
| - U32 litEntropy; | |
| - U32 fseEntropy; | |
| + U32___2 litEntropy; | |
| + U32___2 fseEntropy; | |
| struct xxh64_state xxhState; | |
| size_t headerSize; | |
| ZSTD_format_e format; | |
| ZSTD_forceIgnoreChecksum_e forceIgnoreChecksum; | |
| - U32 validateChecksum; | |
| + U32___2 validateChecksum; | |
| const BYTE *litPtr; | |
| ZSTD_customMem customMem; | |
| size_t litSize; | |
| @@ -28369,11 +35546,12 @@ | |
| int bmi2; | |
| ZSTD_DDict *ddictLocal; | |
| const ZSTD_DDict *ddict; | |
| - U32 dictID; | |
| + U32___2 dictID; | |
| int ddictIsCold; | |
| ZSTD_dictUses_e dictUses; | |
| ZSTD_DDictHashSet *ddictSet; | |
| ZSTD_refMultipleDDicts_e refMultipleDDicts; | |
| + int disableHufAsm; | |
| ZSTD_dStreamStage streamStage; | |
| char *inBuff; | |
| size_t inBuffSize; | |
| @@ -28384,7 +35562,7 @@ | |
| size_t outStart; | |
| size_t outEnd; | |
| size_t lhSize; | |
| - U32 hostageByte; | |
| + U32___2 hostageByte; | |
| int noForwardProgress; | |
| ZSTD_bufferMode_e outBufferMode; | |
| ZSTD_outBuffer expectedOutBuffer; | |
| @@ -28409,8 +35587,8 @@ | |
| const void *dictContent; | |
| size_t dictSize; | |
| ZSTD_entropyDTables_t entropy; | |
| - U32 dictID; | |
| - U32 entropyPresent; | |
| + U32___2 dictID; | |
| + U32___2 entropyPresent; | |
| ZSTD_customMem cMem; | |
| }; | |
| @@ -28418,12 +35596,1684 @@ | |
| typedef ZSTD_outBuffer zstd_out_buffer; | |
| +struct _CONFIG_PAGE_HEADER { | |
| + U8 PageVersion; | |
| + U8 PageLength; | |
| + U8 PageNumber; | |
| + U8 PageType; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_HEADER CONFIG_PAGE_HEADER; | |
| + | |
| +struct _ATTO_DEVICE_INFO { | |
| + u8 Offset; | |
| + u8 Period; | |
| + u16 ATTOFlags; | |
| +}; | |
| + | |
| +typedef struct _ATTO_DEVICE_INFO ATTO_DEVICE_INFO; | |
| + | |
| +struct _ATTO_CONFIG_PAGE_SCSI_PORT_2 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + u16 PortFlags; | |
| + u16 Unused1; | |
| + u32 Unused2; | |
| + ATTO_DEVICE_INFO DeviceSettings[16]; | |
| +}; | |
| + | |
| +typedef struct _ATTO_CONFIG_PAGE_SCSI_PORT_2 ATTO_SCSIPortPage2_t; | |
| + | |
| +typedef struct _ATTO_DEVICE_INFO ATTODeviceInfo_t; | |
| + | |
| +struct _CONFIG_EXTENDED_PAGE_HEADER { | |
| + U8 PageVersion; | |
| + U8 Reserved1; | |
| + U8 PageNumber; | |
| + U8 PageType; | |
| + U16 ExtPageLength; | |
| + U8 ExtPageType; | |
| + U8 Reserved2; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_EXTENDED_PAGE_HEADER CONFIG_EXTENDED_PAGE_HEADER; | |
| + | |
| +typedef struct _CONFIG_EXTENDED_PAGE_HEADER ConfigExtendedPageHeader_t; | |
| + | |
| +struct _U64 { | |
| + U32 Low; | |
| + U32 High; | |
| +}; | |
| + | |
| +typedef struct _U64 U64___2; | |
| + | |
| +struct _CONFIG_PAGE_FC_DEVICE_0 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U64___2 WWNN; | |
| + U64___2 WWPN; | |
| + U32 PortIdentifier; | |
| + U8 Protocol; | |
| + U8 Flags; | |
| + U16 BBCredit; | |
| + U16 MaxRxFrameSize; | |
| + U8 ADISCHardALPA; | |
| + U8 PortNumber; | |
| + U8 FcPhLowestVersion; | |
| + U8 FcPhHighestVersion; | |
| + U8 CurrentTargetID; | |
| + U8 CurrentBus; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_FC_DEVICE_0 FCDevicePage0_t; | |
| + | |
| +struct _CONFIG_PAGE_FC_PORT_0 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U32 Flags; | |
| + U8 MPIPortNumber; | |
| + U8 LinkType; | |
| + U8 PortState; | |
| + U8 Reserved; | |
| + U32 PortIdentifier; | |
| + U64___2 WWNN; | |
| + U64___2 WWPN; | |
| + U32 SupportedServiceClass; | |
| + U32 SupportedSpeeds; | |
| + U32 CurrentSpeed; | |
| + U32 MaxFrameSize; | |
| + U64___2 FabricWWNN; | |
| + U64___2 FabricWWPN; | |
| + U32 DiscoveredPortsCount; | |
| + U32 MaxInitiators; | |
| + U8 MaxAliasesSupported; | |
| + U8 MaxHardAliasesSupported; | |
| + U8 NumCurrentAliases; | |
| + U8 Reserved1; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_FC_PORT_0 FCPortPage0_t; | |
| + | |
| +struct _CONFIG_PAGE_FC_PORT_1 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U32 Flags; | |
| + U64___2 NoSEEPROMWWNN; | |
| + U64___2 NoSEEPROMWWPN; | |
| + U8 HardALPA; | |
| + U8 LinkConfig; | |
| + U8 TopologyConfig; | |
| + U8 AltConnector; | |
| + U8 NumRequestedAliases; | |
| + U8 RR_TOV; | |
| + U8 InitiatorDeviceTimeout; | |
| + U8 InitiatorIoPendTimeout; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_FC_PORT_1 FCPortPage1_t; | |
| + | |
| +typedef struct _CONFIG_PAGE_HEADER ConfigPageHeader_t; | |
| + | |
| +struct _CONFIG_PAGE_IOC_1 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U32 Flags; | |
| + U32 CoalescingTimeout; | |
| + U8 CoalescingDepth; | |
| + U8 PCISlotNum; | |
| + U8 Reserved[2]; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_IOC_1 IOCPage1_t; | |
| + | |
| +struct _CONFIG_PAGE_IOC_2_RAID_VOL { | |
| + U8 VolumeID; | |
| + U8 VolumeBus; | |
| + U8 VolumeIOC; | |
| + U8 VolumePageNumber; | |
| + U8 VolumeType; | |
| + U8 Flags; | |
| + U16 Reserved3; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL CONFIG_PAGE_IOC_2_RAID_VOL; | |
| + | |
| +struct _CONFIG_PAGE_IOC_2 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U32 CapabilitiesFlags; | |
| + U8 NumActiveVolumes; | |
| + U8 MaxVolumes; | |
| + U8 NumActivePhysDisks; | |
| + U8 MaxPhysDisks; | |
| + CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[1]; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_IOC_2 IOCPage2_t; | |
| + | |
| +struct _IOC_3_PHYS_DISK { | |
| + U8 PhysDiskID; | |
| + U8 PhysDiskBus; | |
| + U8 PhysDiskIOC; | |
| + U8 PhysDiskNum; | |
| +}; | |
| + | |
| +typedef struct _IOC_3_PHYS_DISK IOC_3_PHYS_DISK; | |
| + | |
| +struct _CONFIG_PAGE_IOC_3 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U8 NumPhysDisks; | |
| + U8 Reserved1; | |
| + U16 Reserved2; | |
| + IOC_3_PHYS_DISK PhysDisk[1]; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_IOC_3 IOCPage3_t; | |
| + | |
| +struct _IOC_4_SEP { | |
| + U8 SEPTargetID; | |
| + U8 SEPBus; | |
| + U16 Reserved; | |
| +}; | |
| + | |
| +typedef struct _IOC_4_SEP IOC_4_SEP; | |
| + | |
| +struct _CONFIG_PAGE_IOC_4 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U8 ActiveSEP; | |
| + U8 MaxSEP; | |
| + U16 Reserved1; | |
| + IOC_4_SEP SEP[1]; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_IOC_4 IOCPage4_t; | |
| + | |
| +struct _MPI_ADAPTER_INFO { | |
| + U8 PciBusNumber; | |
| + U8 PciDeviceAndFunctionNumber; | |
| + U16 AdapterFlags; | |
| +}; | |
| + | |
| +typedef struct _MPI_ADAPTER_INFO MPI_ADAPTER_INFO; | |
| + | |
| +struct _CONFIG_PAGE_IO_UNIT_2 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U32 Flags; | |
| + U32 BiosVersion; | |
| + MPI_ADAPTER_INFO AdapterOrder[4]; | |
| + U32 Reserved1; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_IO_UNIT_2 IOUnitPage2_t; | |
| + | |
| +struct _CONFIG_PAGE_LAN_0 { | |
| + ConfigPageHeader_t Header; | |
| + U16 TxRxModes; | |
| + U16 Reserved; | |
| + U32 PacketPrePad; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_LAN_0 LANPage0_t; | |
| + | |
| +struct _CONFIG_PAGE_LAN_1 { | |
| + ConfigPageHeader_t Header; | |
| + U16 Reserved; | |
| + U8 CurrentDeviceState; | |
| + U8 Reserved1; | |
| + U32 MinPacketSize; | |
| + U32 MaxPacketSize; | |
| + U32 HardwareAddressLow; | |
| + U32 HardwareAddressHigh; | |
| + U32 MaxWireSpeedLow; | |
| + U32 MaxWireSpeedHigh; | |
| + U32 BucketsRemaining; | |
| + U32 MaxReplySize; | |
| + U32 NegWireSpeedLow; | |
| + U32 NegWireSpeedHigh; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_LAN_1 LANPage1_t; | |
| + | |
| +struct _CONFIG_PAGE_MANUFACTURING_0 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U8 ChipName[16]; | |
| + U8 ChipRevision[8]; | |
| + U8 BoardName[16]; | |
| + U8 BoardAssembly[16]; | |
| + U8 BoardTracerNumber[16]; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_MANUFACTURING_0 ManufacturingPage0_t; | |
| + | |
| +struct _RAID_PHYS_DISK0_SETTINGS { | |
| + U8 SepID; | |
| + U8 SepBus; | |
| + U8 HotSparePool; | |
| + U8 PhysDiskSettings; | |
| +}; | |
| + | |
| +typedef struct _RAID_PHYS_DISK0_SETTINGS RAID_PHYS_DISK0_SETTINGS; | |
| + | |
| +struct _RAID_PHYS_DISK_INQUIRY_DATA { | |
| + U8 VendorID[8]; | |
| + U8 ProductID[16]; | |
| + U8 ProductRevLevel[4]; | |
| + U8 Info[32]; | |
| +}; | |
| + | |
| +typedef struct _RAID_PHYS_DISK_INQUIRY_DATA RAID_PHYS_DISK0_INQUIRY_DATA; | |
| + | |
| +struct _RAID_PHYS_DISK0_STATUS { | |
| + U8 Flags; | |
| + U8 State; | |
| + U16 Reserved; | |
| +}; | |
| + | |
| +typedef struct _RAID_PHYS_DISK0_STATUS RAID_PHYS_DISK0_STATUS; | |
| + | |
| +struct _RAID_PHYS_DISK0_ERROR_DATA { | |
| + U8 ErrorCdbByte; | |
| + U8 ErrorSenseKey; | |
| + U16 Reserved; | |
| + U16 ErrorCount; | |
| + U8 ErrorASC; | |
| + U8 ErrorASCQ; | |
| + U16 SmartCount; | |
| + U8 SmartASC; | |
| + U8 SmartASCQ; | |
| +}; | |
| + | |
| +typedef struct _RAID_PHYS_DISK0_ERROR_DATA RAID_PHYS_DISK0_ERROR_DATA; | |
| + | |
| +struct _CONFIG_PAGE_RAID_PHYS_DISK_0 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U8 PhysDiskID; | |
| + U8 PhysDiskBus; | |
| + U8 PhysDiskIOC; | |
| + U8 PhysDiskNum; | |
| + RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; | |
| + U32 Reserved1; | |
| + U8 ExtDiskIdentifier[8]; | |
| + U8 DiskIdentifier[16]; | |
| + RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; | |
| + RAID_PHYS_DISK0_STATUS PhysDiskStatus; | |
| + U32 MaxLBA; | |
| + RAID_PHYS_DISK0_ERROR_DATA ErrorData; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 RaidPhysDiskPage0_t; | |
| + | |
| +typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 *pRaidPhysDiskPage0_t; | |
| + | |
| +struct _RAID_PHYS_DISK1_PATH { | |
| + U8 PhysDiskID; | |
| + U8 PhysDiskBus; | |
| + U16 Reserved1; | |
| + U64___2 WWID; | |
| + U64___2 OwnerWWID; | |
| + U8 OwnerIdentifier; | |
| + U8 Reserved2; | |
| + U16 Flags; | |
| +}; | |
| + | |
| +typedef struct _RAID_PHYS_DISK1_PATH RAID_PHYS_DISK1_PATH; | |
| + | |
| +struct _CONFIG_PAGE_RAID_PHYS_DISK_1 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U8 NumPhysDiskPaths; | |
| + U8 PhysDiskNum; | |
| + U16 Reserved2; | |
| + U32 Reserved1; | |
| + RAID_PHYS_DISK1_PATH Path[1]; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1 RaidPhysDiskPage1_t; | |
| + | |
| +typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1 *pRaidPhysDiskPage1_t; | |
| + | |
| +struct _RAID_VOL0_STATUS { | |
| + U8 Flags; | |
| + U8 State; | |
| + U16 Reserved; | |
| +}; | |
| + | |
| +typedef struct _RAID_VOL0_STATUS RAID_VOL0_STATUS; | |
| + | |
| +struct _RAID_VOL0_SETTINGS { | |
| + U16 Settings; | |
| + U8 HotSparePool; | |
| + U8 Reserved; | |
| +}; | |
| + | |
| +typedef struct _RAID_VOL0_SETTINGS RAID_VOL0_SETTINGS; | |
| + | |
| +struct _RAID_VOL0_PHYS_DISK { | |
| + U16 Reserved; | |
| + U8 PhysDiskMap; | |
| + U8 PhysDiskNum; | |
| +}; | |
| + | |
| +typedef struct _RAID_VOL0_PHYS_DISK RAID_VOL0_PHYS_DISK; | |
| + | |
| +struct _CONFIG_PAGE_RAID_VOL_0 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U8 VolumeID; | |
| + U8 VolumeBus; | |
| + U8 VolumeIOC; | |
| + U8 VolumeType; | |
| + RAID_VOL0_STATUS VolumeStatus; | |
| + RAID_VOL0_SETTINGS VolumeSettings; | |
| + U32 MaxLBA; | |
| + U32 MaxLBAHigh; | |
| + U32 StripeSize; | |
| + U32 Reserved2; | |
| + U32 Reserved3; | |
| + U8 NumPhysDisks; | |
| + U8 DataScrubRate; | |
| + U8 ResyncRate; | |
| + U8 InactiveStatus; | |
| + RAID_VOL0_PHYS_DISK PhysDisk[1]; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_RAID_VOL_0 *pRaidVolumePage0_t; | |
| + | |
| +struct _CONFIG_PAGE_SAS_DEVICE_0 { | |
| + CONFIG_EXTENDED_PAGE_HEADER Header; | |
| + U16 Slot; | |
| + U16 EnclosureHandle; | |
| + U64___2 SASAddress; | |
| + U16 ParentDevHandle; | |
| + U8 PhyNum; | |
| + U8 AccessStatus; | |
| + U16 DevHandle; | |
| + U8 TargetID; | |
| + U8 Bus; | |
| + U32 DeviceInfo; | |
| + U16 Flags; | |
| + U8 PhysicalPort; | |
| + U8 Reserved2; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_SAS_DEVICE_0 SasDevicePage0_t; | |
| + | |
| +struct _CONFIG_PAGE_SAS_ENCLOSURE_0 { | |
| + CONFIG_EXTENDED_PAGE_HEADER Header; | |
| + U32 Reserved1; | |
| + U64___2 EnclosureLogicalID; | |
| + U16 Flags; | |
| + U16 EnclosureHandle; | |
| + U16 NumSlots; | |
| + U16 StartSlot; | |
| + U8 StartTargetID; | |
| + U8 StartBus; | |
| + U8 SEPTargetID; | |
| + U8 SEPBus; | |
| + U32 Reserved2; | |
| + U32 Reserved3; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0 SasEnclosurePage0_t; | |
| + | |
| +struct _CONFIG_PAGE_SAS_EXPANDER_0 { | |
| + CONFIG_EXTENDED_PAGE_HEADER Header; | |
| + U8 PhysicalPort; | |
| + U8 Reserved1; | |
| + U16 EnclosureHandle; | |
| + U64___2 SASAddress; | |
| + U32 DiscoveryStatus; | |
| + U16 DevHandle; | |
| + U16 ParentDevHandle; | |
| + U16 ExpanderChangeCount; | |
| + U16 ExpanderRouteIndexes; | |
| + U8 NumPhys; | |
| + U8 SASLevel; | |
| + U8 Flags; | |
| + U8 Reserved3; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_SAS_EXPANDER_0 SasExpanderPage0_t; | |
| + | |
| +struct _CONFIG_PAGE_SAS_EXPANDER_1 { | |
| + CONFIG_EXTENDED_PAGE_HEADER Header; | |
| + U8 PhysicalPort; | |
| + U8 Reserved1; | |
| + U16 Reserved2; | |
| + U8 NumPhys; | |
| + U8 Phy; | |
| + U16 NumTableEntriesProgrammed; | |
| + U8 ProgrammedLinkRate; | |
| + U8 HwLinkRate; | |
| + U16 AttachedDevHandle; | |
| + U32 PhyInfo; | |
| + U32 AttachedDeviceInfo; | |
| + U16 OwnerDevHandle; | |
| + U8 ChangeCount; | |
| + U8 NegotiatedLinkRate; | |
| + U8 PhyIdentifier; | |
| + U8 AttachedPhyIdentifier; | |
| + U8 Reserved3; | |
| + U8 DiscoveryInfo; | |
| + U32 Reserved4; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_SAS_EXPANDER_1 SasExpanderPage1_t; | |
| + | |
| +struct _MPI_SAS_IO_UNIT0_PHY_DATA { | |
| + U8 Port; | |
| + U8 PortFlags; | |
| + U8 PhyFlags; | |
| + U8 NegotiatedLinkRate; | |
| + U32 ControllerPhyDeviceInfo; | |
| + U16 AttachedDeviceHandle; | |
| + U16 ControllerDevHandle; | |
| + U32 DiscoveryStatus; | |
| +}; | |
| + | |
| +typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA MPI_SAS_IO_UNIT0_PHY_DATA; | |
| + | |
| +struct _CONFIG_PAGE_SAS_IO_UNIT_0 { | |
| + CONFIG_EXTENDED_PAGE_HEADER Header; | |
| + U16 NvdataVersionDefault; | |
| + U16 NvdataVersionPersistent; | |
| + U8 NumPhys; | |
| + U8 Reserved2; | |
| + U16 Reserved3; | |
| + MPI_SAS_IO_UNIT0_PHY_DATA PhyData[1]; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0 SasIOUnitPage0_t; | |
| + | |
| +struct _MPI_SAS_IO_UNIT1_PHY_DATA { | |
| + U8 Port; | |
| + U8 PortFlags; | |
| + U8 PhyFlags; | |
| + U8 MaxMinLinkRate; | |
| + U32 ControllerPhyDeviceInfo; | |
| + U16 MaxTargetPortConnectTime; | |
| + U16 Reserved1; | |
| +}; | |
| + | |
| +typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA MPI_SAS_IO_UNIT1_PHY_DATA; | |
| + | |
| +struct _CONFIG_PAGE_SAS_IO_UNIT_1 { | |
| + CONFIG_EXTENDED_PAGE_HEADER Header; | |
| + U16 ControlFlags; | |
| + U16 MaxNumSATATargets; | |
| + U16 AdditionalControlFlags; | |
| + U16 Reserved1; | |
| + U8 NumPhys; | |
| + U8 SATAMaxQDepth; | |
| + U8 ReportDeviceMissingDelay; | |
| + U8 IODeviceMissingDelay; | |
| + MPI_SAS_IO_UNIT1_PHY_DATA PhyData[1]; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1 SasIOUnitPage1_t; | |
| + | |
| +struct _CONFIG_PAGE_SAS_PHY_0 { | |
| + CONFIG_EXTENDED_PAGE_HEADER Header; | |
| + U16 OwnerDevHandle; | |
| + U16 Reserved1; | |
| + U64___2 SASAddress; | |
| + U16 AttachedDevHandle; | |
| + U8 AttachedPhyIdentifier; | |
| + U8 Reserved2; | |
| + U32 AttachedDeviceInfo; | |
| + U8 ProgrammedLinkRate; | |
| + U8 HwLinkRate; | |
| + U8 ChangeCount; | |
| + U8 Flags; | |
| + U32 PhyInfo; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_SAS_PHY_0 SasPhyPage0_t; | |
| + | |
| +struct _CONFIG_PAGE_SAS_PHY_1 { | |
| + CONFIG_EXTENDED_PAGE_HEADER Header; | |
| + U32 Reserved1; | |
| + U32 InvalidDwordCount; | |
| + U32 RunningDisparityErrorCount; | |
| + U32 LossDwordSynchCount; | |
| + U32 PhyResetProblemCount; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_SAS_PHY_1 SasPhyPage1_t; | |
| + | |
| +struct _CONFIG_PAGE_SCSI_DEVICE_0 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U32 NegotiatedParameters; | |
| + U32 Information; | |
| +}; | |
| + | |
| +struct _CONFIG_PAGE_SCSI_DEVICE_1 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U32 RequestedParameters; | |
| + U32 Reserved; | |
| + U32 Configuration; | |
| +}; | |
| + | |
| +struct _CONFIG_PAGE_SCSI_PORT_0 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U32 Capabilities; | |
| + U32 PhysicalInterface; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_SCSI_PORT_0 SCSIPortPage0_t; | |
| + | |
| +struct _MPI_DEVICE_INFO { | |
| + U8 Timeout; | |
| + U8 SyncFactor; | |
| + U16 DeviceFlags; | |
| +}; | |
| + | |
| +typedef struct _MPI_DEVICE_INFO MPI_DEVICE_INFO; | |
| + | |
| +struct _CONFIG_PAGE_SCSI_PORT_2 { | |
| + CONFIG_PAGE_HEADER Header; | |
| + U32 PortFlags; | |
| + U32 PortSettings; | |
| + MPI_DEVICE_INFO DeviceSettings[16]; | |
| +}; | |
| + | |
| +typedef struct _CONFIG_PAGE_SCSI_PORT_2 SCSIPortPage2_t; | |
| + | |
| +struct _EVENT_DATA_QUEUE_FULL { | |
| + U8 TargetID; | |
| + U8 Bus; | |
| + U16 CurrentDepth; | |
| +}; | |
| + | |
| +typedef struct _EVENT_DATA_QUEUE_FULL EventDataQueueFull_t; | |
| + | |
| +struct _EVENT_DATA_RAID { | |
| + U8 VolumeID; | |
| + U8 VolumeBus; | |
| + U8 ReasonCode; | |
| + U8 PhysDiskNum; | |
| + U8 ASC; | |
| + U8 ASCQ; | |
| + U16 Reserved; | |
| + U32 SettingsStatus; | |
| +}; | |
| + | |
| +typedef struct _EVENT_DATA_RAID EVENT_DATA_RAID; | |
| + | |
| +typedef struct _EVENT_DATA_RAID MpiEventDataRaid_t; | |
| + | |
| +struct _EVENT_DATA_SAS_BROADCAST_PRIMITIVE { | |
| + U8 PhyNum; | |
| + U8 Port; | |
| + U8 PortWidth; | |
| + U8 Primitive; | |
| +}; | |
| + | |
| +typedef struct _EVENT_DATA_SAS_BROADCAST_PRIMITIVE EVENT_DATA_SAS_BROADCAST_PRIMITIVE; | |
| + | |
| +struct _EVENT_DATA_SAS_DEVICE_STATUS_CHANGE { | |
| + U8 TargetID; | |
| + U8 Bus; | |
| + U8 ReasonCode; | |
| + U8 Reserved; | |
| + U8 ASC; | |
| + U8 ASCQ; | |
| + U16 DevHandle; | |
| + U32 DeviceInfo; | |
| + U16 ParentDevHandle; | |
| + U8 PhyNum; | |
| + U8 Reserved1; | |
| + U64___2 SASAddress; | |
| + U8 LUN[8]; | |
| + U16 TaskTag; | |
| + U16 Reserved2; | |
| +}; | |
| + | |
| +typedef struct _EVENT_DATA_SAS_DEVICE_STATUS_CHANGE EVENT_DATA_SAS_DEVICE_STATUS_CHANGE; | |
| + | |
| +typedef struct _EVENT_DATA_SAS_DEVICE_STATUS_CHANGE MpiEventDataSasDeviceStatusChange_t; | |
| + | |
| +struct _EVENT_DATA_SAS_DISCOVERY { | |
| + U32 DiscoveryStatus; | |
| + U32 Reserved1; | |
| +}; | |
| + | |
| +typedef struct _EVENT_DATA_SAS_DISCOVERY EventDataSasDiscovery_t; | |
| + | |
| +struct _EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE { | |
| + U8 ReasonCode; | |
| + U8 Reserved1; | |
| + U16 Reserved2; | |
| + U8 PhysicalPort; | |
| + U8 Reserved3; | |
| + U16 EnclosureHandle; | |
| + U64___2 SASAddress; | |
| + U32 DiscoveryStatus; | |
| + U16 DevHandle; | |
| + U16 ParentDevHandle; | |
| + U16 ExpanderChangeCount; | |
| + U16 ExpanderRouteIndexes; | |
| + U8 NumPhys; | |
| + U8 SASLevel; | |
| + U8 Flags; | |
| + U8 Reserved4; | |
| +}; | |
| + | |
| +typedef struct _EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE MpiEventDataSasExpanderStatusChange_t; | |
| + | |
| +struct _EVENT_DATA_SAS_PHY_LINK_STATUS { | |
| + U8 PhyNum; | |
| + U8 LinkRates; | |
| + U16 DevHandle; | |
| + U64___2 SASAddress; | |
| +}; | |
| + | |
| +typedef struct _EVENT_DATA_SAS_PHY_LINK_STATUS MpiEventDataSasPhyLinkStatus_t; | |
| + | |
| +struct _FWUploadTCSGE { | |
| + U8 Reserved; | |
| + U8 ContextSize; | |
| + U8 DetailsLength; | |
| + U8 Flags; | |
| + U32 Reserved1; | |
| + U32 ImageOffset; | |
| + U32 ImageSize; | |
| +}; | |
| + | |
| +typedef struct _FWUploadTCSGE FWUploadTCSGE_t; | |
| + | |
| +struct _FcCfgData { | |
| + struct { | |
| + FCPortPage1_t *data; | |
| + dma_addr_t dma; | |
| + int pg_sz; | |
| + } fc_port_page1[2]; | |
| +}; | |
| + | |
| +typedef struct _FcCfgData FcCfgData; | |
| + | |
| +struct _IPS_SUBSYS { | |
| + uint32_t param[128]; | |
| +}; | |
| + | |
| +typedef struct _IPS_SUBSYS IPS_SUBSYS; | |
| + | |
| +struct _IR2_PD_INFO { | |
| + U16 DeviceHandle; | |
| + U8 TruncEnclosureHandle; | |
| + U8 TruncatedSlot; | |
| +}; | |
| + | |
| +typedef struct _IR2_PD_INFO IR2_PD_INFO; | |
| + | |
| +struct _IR2_STATE_CHANGED { | |
| + U16 PreviousState; | |
| + U16 NewState; | |
| +}; | |
| + | |
| +typedef struct _IR2_STATE_CHANGED IR2_STATE_CHANGED; | |
| + | |
| +typedef struct _MPI_DEVICE_INFO MpiDeviceInfo_t; | |
| + | |
| +union _MPI_IR2_RC_EVENT_DATA { | |
| + IR2_STATE_CHANGED StateChanged; | |
| + U32 Lba; | |
| + IR2_PD_INFO PdInfo; | |
| +}; | |
| + | |
| +typedef union _MPI_IR2_RC_EVENT_DATA MPI_IR2_RC_EVENT_DATA; | |
| + | |
| +struct _MPI_EVENT_DATA_IR2 { | |
| + U8 TargetID; | |
| + U8 Bus; | |
| + U8 ReasonCode; | |
| + U8 PhysDiskNum; | |
| + MPI_IR2_RC_EVENT_DATA IR2EventData; | |
| +}; | |
| + | |
| +typedef struct _MPI_EVENT_DATA_IR2 MPI_EVENT_DATA_IR2; | |
| + | |
| +struct _MPI_EXT_IMAGE_HEADER { | |
| + U8 ImageType; | |
| + U8 Reserved; | |
| + U16 Reserved1; | |
| + U32 Checksum; | |
| + U32 ImageSize; | |
| + U32 NextImageHeaderOffset; | |
| + U32 LoadStartAddress; | |
| + U32 Reserved2; | |
| +}; | |
| + | |
| +typedef struct _MPI_EXT_IMAGE_HEADER MpiExtImageHeader_t; | |
| + | |
| +struct _MPI_FW_VERSION_STRUCT { | |
| + U8 Dev; | |
| + U8 Unit; | |
| + U8 Minor; | |
| + U8 Major; | |
| +}; | |
| + | |
| +typedef struct _MPI_FW_VERSION_STRUCT MPI_FW_VERSION_STRUCT; | |
| + | |
| +union _MPI_FW_VERSION { | |
| + MPI_FW_VERSION_STRUCT Struct; | |
| + U32 Word; | |
| +}; | |
| + | |
| +typedef union _MPI_FW_VERSION MPI_FW_VERSION; | |
| + | |
| +struct _MPI_FW_HEADER { | |
| + U32 ArmBranchInstruction0; | |
| + U32 Signature0; | |
| + U32 Signature1; | |
| + U32 Signature2; | |
| + U32 ArmBranchInstruction1; | |
| + U32 ArmBranchInstruction2; | |
| + U32 Reserved; | |
| + U32 Checksum; | |
| + U16 VendorId; | |
| + U16 ProductId; | |
| + MPI_FW_VERSION FWVersion; | |
| + U32 SeqCodeVersion; | |
| + U32 ImageSize; | |
| + U32 NextImageHeaderOffset; | |
| + U32 LoadStartAddress; | |
| + U32 IopResetVectorValue; | |
| + U32 IopResetRegAddr; | |
| + U32 VersionNameWhat; | |
| + U8 VersionName[32]; | |
| + U32 VendorNameWhat; | |
| + U8 VendorName[32]; | |
| +}; | |
| + | |
| +typedef struct _MPI_FW_HEADER MpiFwHeader_t; | |
| + | |
| +typedef void (*MPT_ADD_SGE)(void *, u32, dma_addr_t); | |
| + | |
| +typedef void (*MPT_ADD_CHAIN)(void *, u8, u16, dma_addr_t); | |
| + | |
| +struct _SpiCfgData { | |
| + u32 PortFlags; | |
| + int *nvram; | |
| + IOCPage4_t *pIocPg4; | |
| + dma_addr_t IocPg4_dma; | |
| + int IocPg4Sz; | |
| + u8 minSyncFactor; | |
| + u8 maxSyncOffset; | |
| + u8 maxBusWidth; | |
| + u8 busType; | |
| + u8 sdp1version; | |
| + u8 sdp1length; | |
| + u8 sdp0version; | |
| + u8 sdp0length; | |
| + u8 dvScheduled; | |
| + u8 noQas; | |
| + u8 Saf_Te; | |
| + u8 bus_reset; | |
| + u8 rsvd[1]; | |
| +}; | |
| + | |
| +typedef struct _SpiCfgData SpiCfgData; | |
| + | |
| +struct _RaidCfgData { | |
| + IOCPage2_t *pIocPg2; | |
| + IOCPage3_t *pIocPg3; | |
| + struct mutex inactive_list_mutex; | |
| + struct list_head inactive_list; | |
| +}; | |
| + | |
| +typedef struct _RaidCfgData RaidCfgData; | |
| + | |
| +struct _SasCfgData { | |
| + u8 ptClear; | |
| +}; | |
| + | |
| +typedef struct _SasCfgData SasCfgData; | |
| + | |
| +struct _SGE_SIMPLE_UNION { | |
| + U32 FlagsLength; | |
| + union { | |
| + U32 Address32; | |
| + U64___2 Address64; | |
| + } u; | |
| +}; | |
| + | |
| +typedef struct _SGE_SIMPLE_UNION SGE_SIMPLE_UNION; | |
| + | |
| +struct _MSG_IOC_FACTS_REPLY { | |
| + U16 MsgVersion; | |
| + U8 MsgLength; | |
| + U8 Function; | |
| + U16 HeaderVersion; | |
| + U8 IOCNumber; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U16 IOCExceptions; | |
| + U16 IOCStatus; | |
| + U32 IOCLogInfo; | |
| + U8 MaxChainDepth; | |
| + U8 WhoInit; | |
| + U8 BlockSize; | |
| + U8 Flags; | |
| + U16 ReplyQueueDepth; | |
| + U16 RequestFrameSize; | |
| + U16 Reserved_0101_FWVersion; | |
| + U16 ProductID; | |
| + U32 CurrentHostMfaHighAddr; | |
| + U16 GlobalCredits; | |
| + U8 NumberOfPorts; | |
| + U8 EventState; | |
| + U32 CurrentSenseBufferHighAddr; | |
| + U16 CurReplyFrameSize; | |
| + U8 MaxDevices; | |
| + U8 MaxBuses; | |
| + U32 FWImageSize; | |
| + U32 IOCCapabilities; | |
| + MPI_FW_VERSION FWVersion; | |
| + U16 HighPriorityQueueDepth; | |
| + U16 Reserved2; | |
| + SGE_SIMPLE_UNION HostPageBufferSGE; | |
| + U32 ReplyFifoHostSignalingAddr; | |
| +}; | |
| + | |
| +typedef struct _MSG_IOC_FACTS_REPLY IOCFactsReply_t; | |
| + | |
| +struct _MSG_PORT_FACTS_REPLY { | |
| + U16 Reserved; | |
| + U8 MsgLength; | |
| + U8 Function; | |
| + U16 Reserved1; | |
| + U8 PortNumber; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U16 Reserved2; | |
| + U16 IOCStatus; | |
| + U32 IOCLogInfo; | |
| + U8 Reserved3; | |
| + U8 PortType; | |
| + U16 MaxDevices; | |
| + U16 PortSCSIID; | |
| + U16 ProtocolFlags; | |
| + U16 MaxPostedCmdBuffers; | |
| + U16 MaxPersistentIDs; | |
| + U16 MaxLanBuckets; | |
| + U8 MaxInitiators; | |
| + U8 Reserved4; | |
| + U32 Reserved5; | |
| +}; | |
| + | |
| +typedef struct _MSG_PORT_FACTS_REPLY PortFactsReply_t; | |
| + | |
| +struct _MPT_MGMT { | |
| + struct mutex mutex; | |
| + struct completion done; | |
| + u8 reply[128]; | |
| + u8 sense[64]; | |
| + u8 status; | |
| + int completion_code; | |
| + u32 msg_context; | |
| +}; | |
| + | |
| +typedef struct _MPT_MGMT MPT_MGMT; | |
| + | |
| +typedef void (*MPT_SCHEDULE_TARGET_RESET)(void *); | |
| + | |
| +struct _MPT_SCSI_HOST; | |
| + | |
| +typedef struct _MPT_SCSI_HOST MPT_SCSI_HOST; | |
| + | |
| +typedef void (*MPT_FLUSH_RUNNING_CMDS)(MPT_SCSI_HOST *); | |
| + | |
| +struct timer_list { | |
| + struct hlist_node entry; | |
| + long unsigned int expires; | |
| + void (*function)(struct timer_list *); | |
| + u32 flags; | |
| + struct lockdep_map lockdep_map; | |
| +}; | |
| + | |
| +struct delayed_work { | |
| + struct work_struct work; | |
| + struct timer_list timer; | |
| + struct workqueue_struct *wq; | |
| + int cpu; | |
| +}; | |
| + | |
| +struct _SYSIF_REGS; | |
| + | |
| +typedef struct _SYSIF_REGS SYSIF_REGS; | |
| + | |
| +struct _MPT_FRAME_HDR; | |
| + | |
| +typedef struct _MPT_FRAME_HDR MPT_FRAME_HDR; | |
| + | |
| +struct proc_dir_entry; | |
| + | |
| +struct _mpt_ioctl_events; | |
| + | |
| +struct net_device; | |
| + | |
| +struct mptsas_portinfo; | |
| + | |
| +struct _MPT_ADAPTER { | |
| + int id; | |
| + int pci_irq; | |
| + char name[32]; | |
| + const char *prod_name; | |
| + char board_name[16]; | |
| + char board_assembly[16]; | |
| + char board_tracer[16]; | |
| + u16 nvdata_version_persistent; | |
| + u16 nvdata_version_default; | |
| + int debug_level; | |
| + u8 io_missing_delay; | |
| + u16 device_missing_delay; | |
| + SYSIF_REGS *chip; | |
| + SYSIF_REGS *pio_chip; | |
| + u8 bus_type; | |
| + u32 mem_phys; | |
| + u32 pio_mem_phys; | |
| + int mem_size; | |
| + int number_of_buses; | |
| + int devices_per_bus; | |
| + int alloc_total; | |
| + u32 last_state; | |
| + int active; | |
| + u8 *alloc; | |
| + dma_addr_t alloc_dma; | |
| + u32 alloc_sz; | |
| + MPT_FRAME_HDR *reply_frames; | |
| + u32 reply_frames_low_dma; | |
| + int reply_depth; | |
| + int reply_sz; | |
| + int num_chain; | |
| + MPT_ADD_SGE add_sge; | |
| + MPT_ADD_CHAIN add_chain; | |
| + int *ReqToChain; | |
| + int *RequestNB; | |
| + int *ChainToChain; | |
| + u8 *ChainBuffer; | |
| + dma_addr_t ChainBufferDMA; | |
| + struct list_head FreeChainQ; | |
| + spinlock_t FreeChainQlock; | |
| + dma_addr_t req_frames_dma; | |
| + MPT_FRAME_HDR *req_frames; | |
| + u32 req_frames_low_dma; | |
| + int req_depth; | |
| + int req_sz; | |
| + spinlock_t FreeQlock; | |
| + struct list_head FreeQ; | |
| + u8 *sense_buf_pool; | |
| + dma_addr_t sense_buf_pool_dma; | |
| + u32 sense_buf_low_dma; | |
| + u8 *HostPageBuffer; | |
| + u32 HostPageBuffer_sz; | |
| + dma_addr_t HostPageBuffer_dma; | |
| + struct pci_dev *pcidev; | |
| + int bars; | |
| + int msi_enable; | |
| + u8 *memmap; | |
| + struct Scsi_Host *sh; | |
| + SpiCfgData spi_data; | |
| + RaidCfgData raid_data; | |
| + SasCfgData sas_data; | |
| + FcCfgData fc_data; | |
| + struct proc_dir_entry *ioc_dentry; | |
| + struct _MPT_ADAPTER *alt_ioc; | |
| + u32 biosVersion; | |
| + int eventTypes; | |
| + int eventContext; | |
| + int eventLogSize; | |
| + struct _mpt_ioctl_events *events; | |
| + u8 *cached_fw; | |
| + dma_addr_t cached_fw_dma; | |
| + int hs_reply_idx; | |
| + u32 pad0; | |
| + u32 NB_for_64_byte_frame; | |
| + u32 hs_req[32]; | |
| + u16 hs_reply[64]; | |
| + IOCFactsReply_t facts; | |
| + PortFactsReply_t pfacts[2]; | |
| + FCPortPage0_t fc_port_page0[2]; | |
| + LANPage0_t lan_cnfg_page0; | |
| + LANPage1_t lan_cnfg_page1; | |
| + u8 ir_firmware; | |
| + int errata_flag_1064; | |
| + int aen_event_read_flag; | |
| + u8 FirstWhoInit; | |
| + u8 upload_fw; | |
| + u8 NBShiftFactor; | |
| + u8 pad1[4]; | |
| + u8 DoneCtx; | |
| + u8 TaskCtx; | |
| + u8 InternalCtx; | |
| + struct list_head list; | |
| + struct net_device *netdev; | |
| + struct list_head sas_topology; | |
| + struct mutex sas_topology_mutex; | |
| + struct workqueue_struct *fw_event_q; | |
| + struct list_head fw_event_list; | |
| + spinlock_t fw_event_lock; | |
| + u8 fw_events_off; | |
| + char fw_event_q_name[20]; | |
| + struct mutex sas_discovery_mutex; | |
| + u8 sas_discovery_runtime; | |
| + u8 sas_discovery_ignore_events; | |
| + struct mptsas_portinfo *hba_port_info; | |
| + u64 hba_port_sas_addr; | |
| + u16 hba_port_num_phy; | |
| + struct list_head sas_device_info_list; | |
| + struct mutex sas_device_info_mutex; | |
| + u8 old_sas_discovery_protocal; | |
| + u8 sas_discovery_quiesce_io; | |
| + int sas_index; | |
| + MPT_MGMT sas_mgmt; | |
| + MPT_MGMT mptbase_cmds; | |
| + MPT_MGMT internal_cmds; | |
| + MPT_MGMT taskmgmt_cmds; | |
| + MPT_MGMT ioctl_cmds; | |
| + spinlock_t taskmgmt_lock; | |
| + int taskmgmt_in_progress; | |
| + u8 taskmgmt_quiesce_io; | |
| + u8 ioc_reset_in_progress; | |
| + u8 reset_status; | |
| + u8 wait_on_reset_completion; | |
| + MPT_SCHEDULE_TARGET_RESET schedule_target_reset; | |
| + MPT_FLUSH_RUNNING_CMDS schedule_dead_ioc_flush_running_cmds; | |
| + struct work_struct fc_setup_reset_work; | |
| + struct list_head fc_rports; | |
| + struct work_struct fc_lsc_work; | |
| + u8 fc_link_speed[2]; | |
| + spinlock_t fc_rescan_work_lock; | |
| + struct work_struct fc_rescan_work; | |
| + char fc_rescan_work_q_name[20]; | |
| + struct workqueue_struct *fc_rescan_work_q; | |
| + long unsigned int hard_resets; | |
| + long unsigned int soft_resets; | |
| + long unsigned int timeouts; | |
| + struct scsi_cmnd **ScsiLookup; | |
| + spinlock_t scsi_lookup_lock; | |
| + u64 dma_mask; | |
| + u32 broadcast_aen_busy; | |
| + char reset_work_q_name[20]; | |
| + struct workqueue_struct *reset_work_q; | |
| + struct delayed_work fault_reset_work; | |
| + u8 sg_addr_size; | |
| + u8 in_rescan; | |
| + u8 SGE_size; | |
| +}; | |
| + | |
| +typedef struct _MPT_ADAPTER MPT_ADAPTER; | |
| + | |
| +struct _MSG_REQUEST_HEADER { | |
| + U8 Reserved[2]; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U8 Reserved1[3]; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| +}; | |
| + | |
| +typedef struct _MSG_REQUEST_HEADER MPIHeader_t; | |
| + | |
| +struct _SGE_CHAIN_UNION { | |
| + U16 Length; | |
| + U8 NextChainOffset; | |
| + U8 Flags; | |
| + union { | |
| + U32 Address32; | |
| + U64___2 Address64; | |
| + } u; | |
| +}; | |
| + | |
| +typedef struct _SGE_CHAIN_UNION SGE_CHAIN_UNION; | |
| + | |
| +struct _SGE_IO_UNION { | |
| + union { | |
| + SGE_SIMPLE_UNION Simple; | |
| + SGE_CHAIN_UNION Chain; | |
| + } u; | |
| +}; | |
| + | |
| +typedef struct _SGE_IO_UNION SGE_IO_UNION; | |
| + | |
| +struct _MSG_SCSI_IO_REQUEST { | |
| + U8 TargetID; | |
| + U8 Bus; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U8 CDBLength; | |
| + U8 SenseBufferLength; | |
| + U8 Reserved; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U8 LUN[8]; | |
| + U32 Control; | |
| + U8 CDB[16]; | |
| + U32 DataLength; | |
| + U32 SenseBufferLowAddr; | |
| + SGE_IO_UNION SGL; | |
| +}; | |
| + | |
| +typedef struct _MSG_SCSI_IO_REQUEST SCSIIORequest_t; | |
| + | |
| +struct _MSG_SCSI_IO_REPLY { | |
| + U8 TargetID; | |
| + U8 Bus; | |
| + U8 MsgLength; | |
| + U8 Function; | |
| + U8 CDBLength; | |
| + U8 SenseBufferLength; | |
| + U8 Reserved; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U8 SCSIStatus; | |
| + U8 SCSIState; | |
| + U16 IOCStatus; | |
| + U32 IOCLogInfo; | |
| + U32 TransferCount; | |
| + U32 SenseCount; | |
| + U32 ResponseInfo; | |
| + U16 TaskTag; | |
| + U16 Reserved1; | |
| +}; | |
| + | |
| +typedef struct _MSG_SCSI_IO_REPLY SCSIIOReply_t; | |
| + | |
| +struct _MSG_CONFIG_REPLY { | |
| + U8 Action; | |
| + U8 Reserved; | |
| + U8 MsgLength; | |
| + U8 Function; | |
| + U16 ExtPageLength; | |
| + U8 ExtPageType; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U8 Reserved2[2]; | |
| + U16 IOCStatus; | |
| + U32 IOCLogInfo; | |
| + CONFIG_PAGE_HEADER Header; | |
| +}; | |
| + | |
| +typedef struct _MSG_CONFIG_REPLY ConfigReply_t; | |
| + | |
| +struct _MSG_DEFAULT_REPLY { | |
| + U8 Reserved[2]; | |
| + U8 MsgLength; | |
| + U8 Function; | |
| + U8 Reserved1[3]; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U8 Reserved2[2]; | |
| + U16 IOCStatus; | |
| + U32 IOCLogInfo; | |
| +}; | |
| + | |
| +typedef struct _MSG_DEFAULT_REPLY MPIDefaultReply_t; | |
| + | |
| +union _MPT_FRAME_TRACKER { | |
| + struct { | |
| + struct list_head list; | |
| + u32 arg1; | |
| + u32 pad; | |
| + void *argp1; | |
| + } linkage; | |
| + struct { | |
| + u32 __hdr[2]; | |
| + union { | |
| + u32 MsgContext; | |
| + struct { | |
| + u16 req_idx; | |
| + u8 cb_idx; | |
| + u8 rsvd; | |
| + } fld; | |
| + } msgctxu; | |
| + } hwhdr; | |
| +}; | |
| + | |
| +typedef union _MPT_FRAME_TRACKER MPT_FRAME_TRACKER; | |
| + | |
| +struct _MPT_FRAME_HDR { | |
| + union { | |
| + MPIHeader_t hdr; | |
| + SCSIIORequest_t scsireq; | |
| + SCSIIOReply_t sreply; | |
| + ConfigReply_t configreply; | |
| + MPIDefaultReply_t reply; | |
| + MPT_FRAME_TRACKER frame; | |
| + } u; | |
| +}; | |
| + | |
| +struct _MPT_SCSI_HOST { | |
| + struct _MPT_ADAPTER *ioc; | |
| + ushort sel_timeout[255]; | |
| + char *info_kbuf; | |
| + long int last_queue_full; | |
| + u16 spi_pending; | |
| + struct list_head target_reset_list; | |
| +}; | |
| + | |
| +struct _MSG_CONFIG { | |
| + U8 Action; | |
| + U8 Reserved; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U16 ExtPageLength; | |
| + U8 ExtPageType; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U8 Reserved2[8]; | |
| + CONFIG_PAGE_HEADER Header; | |
| + U32 PageAddress; | |
| + SGE_IO_UNION PageBufferSGE; | |
| +}; | |
| + | |
| +typedef struct _MSG_CONFIG Config_t; | |
| + | |
| +struct _MSG_EVENT_ACK { | |
| + U8 Reserved[2]; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U8 Reserved1[3]; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U32 Event; | |
| + U32 EventContext; | |
| +}; | |
| + | |
| +typedef struct _MSG_EVENT_ACK EventAck_t; | |
| + | |
| +struct _MSG_EVENT_NOTIFY { | |
| + U8 Switch; | |
| + U8 Reserved; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U8 Reserved1[3]; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| +}; | |
| + | |
| +typedef struct _MSG_EVENT_NOTIFY EventNotification_t; | |
| + | |
| +struct _MSG_EVENT_NOTIFY_REPLY { | |
| + U16 EventDataLength; | |
| + U8 MsgLength; | |
| + U8 Function; | |
| + U8 Reserved1[2]; | |
| + U8 AckRequired; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U8 Reserved2[2]; | |
| + U16 IOCStatus; | |
| + U32 IOCLogInfo; | |
| + U32 Event; | |
| + U32 EventContext; | |
| + U32 Data[0]; | |
| +}; | |
| + | |
| +typedef struct _MSG_EVENT_NOTIFY_REPLY EventNotificationReply_t; | |
| + | |
| +struct _SGE_TRANSACTION_UNION { | |
| + U8 Reserved; | |
| + U8 ContextSize; | |
| + U8 DetailsLength; | |
| + U8 Flags; | |
| + union { | |
| + U32 TransactionContext32[1]; | |
| + U32 TransactionContext64[2]; | |
| + U32 TransactionContext96[3]; | |
| + U32 TransactionContext128[4]; | |
| + } u; | |
| + U32 TransactionDetails[1]; | |
| +}; | |
| + | |
| +typedef struct _SGE_TRANSACTION_UNION SGE_TRANSACTION_UNION; | |
| + | |
| +struct _SGE_MPI_UNION { | |
| + union { | |
| + SGE_SIMPLE_UNION Simple; | |
| + SGE_CHAIN_UNION Chain; | |
| + SGE_TRANSACTION_UNION Transaction; | |
| + } u; | |
| +}; | |
| + | |
| +typedef struct _SGE_MPI_UNION SGE_MPI_UNION; | |
| + | |
| +struct _MSG_FW_UPLOAD { | |
| + U8 ImageType; | |
| + U8 Reserved; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U8 Reserved1[3]; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + SGE_MPI_UNION SGL; | |
| +}; | |
| + | |
| +typedef struct _MSG_FW_UPLOAD FWUpload_t; | |
| + | |
| +struct _MSG_FW_UPLOAD_REPLY { | |
| + U8 ImageType; | |
| + U8 Reserved; | |
| + U8 MsgLength; | |
| + U8 Function; | |
| + U8 Reserved1[3]; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U16 Reserved2; | |
| + U16 IOCStatus; | |
| + U32 IOCLogInfo; | |
| + U32 ActualImageSize; | |
| +}; | |
| + | |
| +typedef struct _MSG_FW_UPLOAD_REPLY FWUploadReply_t; | |
| + | |
| +struct _MSG_IOC_FACTS { | |
| + U8 Reserved[2]; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U8 Reserved1[3]; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| +}; | |
| + | |
| +typedef struct _MSG_IOC_FACTS IOCFacts_t; | |
| + | |
| +struct _MSG_IOC_INIT { | |
| + U8 WhoInit; | |
| + U8 Reserved; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U8 Flags; | |
| + U8 MaxDevices; | |
| + U8 MaxBuses; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U16 ReplyFrameSize; | |
| + U8 Reserved1[2]; | |
| + U32 HostMfaHighAddr; | |
| + U32 SenseBufferHighAddr; | |
| + U32 ReplyFifoHostSignalingAddr; | |
| + SGE_SIMPLE_UNION HostPageBufferSGE; | |
| + U16 MsgVersion; | |
| + U16 HeaderVersion; | |
| +}; | |
| + | |
| +typedef struct _MSG_IOC_INIT IOCInit_t; | |
| + | |
| +typedef struct _MSG_IOC_INIT *pIOCInit_t; | |
| + | |
| +struct _MSG_PORT_ENABLE { | |
| + U8 Reserved[2]; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U8 Reserved1[2]; | |
| + U8 PortNumber; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| +}; | |
| + | |
| +typedef struct _MSG_PORT_ENABLE PortEnable_t; | |
| + | |
| +struct _MSG_PORT_FACTS { | |
| + U8 Reserved[2]; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U8 Reserved1[2]; | |
| + U8 PortNumber; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| +}; | |
| + | |
| +typedef struct _MSG_PORT_FACTS PortFacts_t; | |
| + | |
| +struct _MSG_RAID_ACTION { | |
| + U8 Action; | |
| + U8 Reserved1; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U8 VolumeID; | |
| + U8 VolumeBus; | |
| + U8 PhysDiskNum; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U32 Reserved2; | |
| + U32 ActionDataWord; | |
| + SGE_SIMPLE_UNION ActionDataSGE; | |
| +}; | |
| + | |
| +typedef struct _MSG_RAID_ACTION MpiRaidActionRequest_t; | |
| + | |
| +struct _MSG_RAID_ACTION_REPLY { | |
| + U8 Action; | |
| + U8 Reserved; | |
| + U8 MsgLength; | |
| + U8 Function; | |
| + U8 VolumeID; | |
| + U8 VolumeBus; | |
| + U8 PhysDiskNum; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U16 ActionStatus; | |
| + U16 IOCStatus; | |
| + U32 IOCLogInfo; | |
| + U32 VolumeStatus; | |
| + U32 ActionData; | |
| +}; | |
| + | |
| +typedef struct _MSG_RAID_ACTION_REPLY MpiRaidActionReply_t; | |
| + | |
| +struct _MSG_SAS_IOUNIT_CONTROL_REPLY { | |
| + U8 Operation; | |
| + U8 Reserved1; | |
| + U8 MsgLength; | |
| + U8 Function; | |
| + U16 DevHandle; | |
| + U8 IOCParameter; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U16 Reserved4; | |
| + U16 IOCStatus; | |
| + U32 IOCLogInfo; | |
| +}; | |
| + | |
| +typedef struct _MSG_SAS_IOUNIT_CONTROL_REPLY SasIoUnitControlReply_t; | |
| + | |
| +struct _MSG_SAS_IOUNIT_CONTROL_REQUEST { | |
| + U8 Operation; | |
| + U8 Reserved1; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U16 DevHandle; | |
| + U8 IOCParameter; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U8 TargetID; | |
| + U8 Bus; | |
| + U8 PhyNum; | |
| + U8 PrimFlags; | |
| + U32 Primitive; | |
| + U64___2 SASAddress; | |
| + U32 IOCParameterValue; | |
| +}; | |
| + | |
| +typedef struct _MSG_SAS_IOUNIT_CONTROL_REQUEST SasIoUnitControlRequest_t; | |
| + | |
| +struct _MSG_SCSI_TASK_MGMT { | |
| + U8 TargetID; | |
| + U8 Bus; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U8 Reserved; | |
| + U8 TaskType; | |
| + U8 Reserved1; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U8 LUN[8]; | |
| + U32 Reserved2[7]; | |
| + U32 TaskMsgContext; | |
| +}; | |
| + | |
| +typedef struct _MSG_SCSI_TASK_MGMT SCSITaskMgmt_t; | |
| + | |
| +struct _MSG_SCSI_TASK_MGMT_REPLY { | |
| + U8 TargetID; | |
| + U8 Bus; | |
| + U8 MsgLength; | |
| + U8 Function; | |
| + U8 ResponseCode; | |
| + U8 TaskType; | |
| + U8 Reserved1; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U8 Reserved2[2]; | |
| + U16 IOCStatus; | |
| + U32 IOCLogInfo; | |
| + U32 TerminationCount; | |
| +}; | |
| + | |
| +typedef struct _MSG_SCSI_TASK_MGMT_REPLY SCSITaskMgmtReply_t; | |
| + | |
| +struct _MSG_SEP_REQUEST { | |
| + U8 TargetID; | |
| + U8 Bus; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U8 Action; | |
| + U8 Flags; | |
| + U8 Reserved1; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U32 SlotStatus; | |
| + U32 Reserved2; | |
| + U32 Reserved3; | |
| + U32 Reserved4; | |
| + U16 Slot; | |
| + U16 EnclosureHandle; | |
| +}; | |
| + | |
| +typedef struct _MSG_SEP_REQUEST SEPRequest_t; | |
| + | |
| +struct _MSG_SMP_PASSTHROUGH_REPLY { | |
| + U8 PassthroughFlags; | |
| + U8 PhysicalPort; | |
| + U8 MsgLength; | |
| + U8 Function; | |
| + U16 ResponseDataLength; | |
| + U8 Reserved1; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U8 Reserved2; | |
| + U8 SASStatus; | |
| + U16 IOCStatus; | |
| + U32 IOCLogInfo; | |
| + U32 Reserved3; | |
| + U8 ResponseData[4]; | |
| +}; | |
| + | |
| +typedef struct _MSG_SMP_PASSTHROUGH_REPLY SmpPassthroughReply_t; | |
| + | |
| +struct _MSG_SMP_PASSTHROUGH_REQUEST { | |
| + U8 PassthroughFlags; | |
| + U8 PhysicalPort; | |
| + U8 ChainOffset; | |
| + U8 Function; | |
| + U16 RequestDataLength; | |
| + U8 ConnectionRate; | |
| + U8 MsgFlags; | |
| + U32 MsgContext; | |
| + U32 Reserved1; | |
| + U64___2 SASAddress; | |
| + U32 Reserved2; | |
| + U32 Reserved3; | |
| + SGE_SIMPLE_UNION SGL; | |
| +}; | |
| + | |
| +typedef struct _MSG_SMP_PASSTHROUGH_REQUEST SmpPassthroughRequest_t; | |
| + | |
| +struct _SGE_CHAIN32 { | |
| + U16 Length; | |
| + U8 NextChainOffset; | |
| + U8 Flags; | |
| + U32 Address; | |
| +}; | |
| + | |
| +typedef struct _SGE_CHAIN32 SGEChain32_t; | |
| + | |
| +struct _SGE_CHAIN64 { | |
| + U16 Length; | |
| + U8 NextChainOffset; | |
| + U8 Flags; | |
| + U64___2 Address; | |
| +}; | |
| + | |
| +typedef struct _SGE_CHAIN64 SGEChain64_t; | |
| + | |
| +struct _SGE_SIMPLE32 { | |
| + U32 FlagsLength; | |
| + U32 Address; | |
| +}; | |
| + | |
| +typedef struct _SGE_SIMPLE32 SGESimple32_t; | |
| + | |
| +struct _SGE_SIMPLE64 { | |
| + U32 FlagsLength; | |
| + U64___2 Address; | |
| +}; | |
| + | |
| +typedef struct _SGE_SIMPLE64 SGESimple64_t; | |
| + | |
| +struct _SYSIF_REGS { | |
| + u32 Doorbell; | |
| + u32 WriteSequence; | |
| + u32 Diagnostic; | |
| + u32 TestBase; | |
| + u32 DiagRwData; | |
| + u32 DiagRwAddress; | |
| + u32 Reserved1[6]; | |
| + u32 IntStatus; | |
| + u32 IntMask; | |
| + u32 Reserved2[2]; | |
| + u32 RequestFifo; | |
| + u32 ReplyFifo; | |
| + u32 RequestHiPriFifo; | |
| + u32 Reserved3; | |
| + u32 HostIndex; | |
| + u32 Reserved4[15]; | |
| + u32 Fubar; | |
| + u32 Reserved5[1050]; | |
| + u32 Reset_1078; | |
| +}; | |
| + | |
| +struct _VirtTarget; | |
| + | |
| +typedef struct _VirtTarget VirtTarget; | |
| + | |
| +struct _VirtDevice { | |
| + VirtTarget *vtarget; | |
| + u8 configured_lun; | |
| + u64 lun; | |
| +}; | |
| + | |
| +typedef struct _VirtDevice VirtDevice; | |
| + | |
| +struct scsi_target; | |
| + | |
| +struct _VirtTarget { | |
| + struct scsi_target *starget; | |
| + u8 tflags; | |
| + u8 ioc_id; | |
| + u8 id; | |
| + u8 channel; | |
| + u8 minSyncFactor; | |
| + u8 maxOffset; | |
| + u8 maxWidth; | |
| + u8 negoFlags; | |
| + u8 raidVolume; | |
| + u8 type; | |
| + u8 deleted; | |
| + u8 inDMD; | |
| + u32 num_luns; | |
| +}; | |
| + | |
| typedef struct { | |
| - unsigned long sig[1]; | |
| + long unsigned int sig[1]; | |
| } sigset_t; | |
| struct __aio_sigset { | |
| - const sigset_t __attribute__((btf_type_tag("user"))) *sigmask; | |
| + const sigset_t *sigmask; | |
| size_t sigsetsize; | |
| }; | |
| @@ -28432,6 +37282,28 @@ | |
| s32 raddr; | |
| } __attribute__((packed)); | |
| +struct __bridge_info { | |
| + __u64 designated_root; | |
| + __u64 bridge_id; | |
| + __u32 root_path_cost; | |
| + __u32 max_age; | |
| + __u32 hello_time; | |
| + __u32 forward_delay; | |
| + __u32 bridge_max_age; | |
| + __u32 bridge_hello_time; | |
| + __u32 bridge_forward_delay; | |
| + __u8 topology_change; | |
| + __u8 topology_change_detected; | |
| + __u8 root_port; | |
| + __u8 stp_enabled; | |
| + __u32 ageing_time; | |
| + __u32 gc_interval; | |
| + __u32 hello_timer_value; | |
| + __u32 tcn_timer_value; | |
| + __u32 topology_change_timer_value; | |
| + __u32 gc_timer_value; | |
| +}; | |
| + | |
| struct llist_node { | |
| struct llist_node *next; | |
| }; | |
| @@ -28471,11 +37343,33 @@ | |
| compat_size_t sigsetsize; | |
| }; | |
| -struct __fat_dirent { | |
| - long d_ino; | |
| - __kernel_off_t d_off; | |
| - unsigned short d_reclen; | |
| - char d_name[256]; | |
| +struct __fb_timings { | |
| + u32 dclk; | |
| + u32 hfreq; | |
| + u32 vfreq; | |
| + u32 hactive; | |
| + u32 vactive; | |
| + u32 hblank; | |
| + u32 vblank; | |
| + u32 htotal; | |
| + u32 vtotal; | |
| +}; | |
| + | |
| +struct __fdb_entry { | |
| + __u8 mac_addr[6]; | |
| + __u8 port_no; | |
| + __u8 is_local; | |
| + __u32 ageing_timer_value; | |
| + __u8 port_hi; | |
| + __u8 pad0; | |
| + __u16 unused; | |
| +}; | |
| + | |
| +struct tracepoint; | |
| + | |
| +struct __find_tracepoint_cb_data { | |
| + const char *tp_name; | |
| + struct tracepoint *tpoint; | |
| }; | |
| struct genradix_root; | |
| @@ -28484,11 +37378,6 @@ | |
| struct genradix_root *root; | |
| }; | |
| -struct __group_domain_type { | |
| - struct device *dev; | |
| - unsigned int type; | |
| -}; | |
| - | |
| struct pmu; | |
| struct cgroup; | |
| @@ -28518,8 +37407,8 @@ | |
| __u32 flags; | |
| struct in6_addr laddr; | |
| struct in6_addr raddr; | |
| - __be16 i_flags; | |
| - __be16 o_flags; | |
| + long unsigned int i_flags[1]; | |
| + long unsigned int o_flags[1]; | |
| __be32 i_key; | |
| __be32 o_key; | |
| __u32 fwmark; | |
| @@ -28531,7 +37420,7 @@ | |
| struct __kernel_timespec { | |
| __kernel_time64_t tv_sec; | |
| - long long tv_nsec; | |
| + long long int tv_nsec; | |
| }; | |
| struct __kernel_itimerspec { | |
| @@ -28551,7 +37440,7 @@ | |
| struct __kernel_old_timespec { | |
| __kernel_old_time_t tv_sec; | |
| - long tv_nsec; | |
| + long int tv_nsec; | |
| }; | |
| struct __kernel_sock_timeval { | |
| @@ -28571,29 +37460,29 @@ | |
| struct __kernel_timex_timeval { | |
| __kernel_time64_t tv_sec; | |
| - long long tv_usec; | |
| + long long int tv_usec; | |
| }; | |
| struct __kernel_timex { | |
| unsigned int modes; | |
| - long long offset; | |
| - long long freq; | |
| - long long maxerror; | |
| - long long esterror; | |
| + long long int offset; | |
| + long long int freq; | |
| + long long int maxerror; | |
| + long long int esterror; | |
| int status; | |
| - long long constant; | |
| - long long precision; | |
| - long long tolerance; | |
| + long long int constant; | |
| + long long int precision; | |
| + long long int tolerance; | |
| struct __kernel_timex_timeval time; | |
| - long long tick; | |
| - long long ppsfreq; | |
| - long long jitter; | |
| + long long int tick; | |
| + long long int ppsfreq; | |
| + long long int jitter; | |
| int shift; | |
| - long long stabil; | |
| - long long jitcnt; | |
| - long long calcnt; | |
| - long long errcnt; | |
| - long long stbcnt; | |
| + long long int stabil; | |
| + long long int jitcnt; | |
| + long long int calcnt; | |
| + long long int errcnt; | |
| + long long int stbcnt; | |
| int tai; | |
| long: 64; | |
| long: 64; | |
| @@ -28611,93 +37500,39 @@ | |
| }; | |
| struct __large_struct { | |
| - unsigned long buf[100]; | |
| + long unsigned int buf[100]; | |
| }; | |
| struct __old_kernel_stat { | |
| - unsigned short st_dev; | |
| - unsigned short st_ino; | |
| - unsigned short st_mode; | |
| - unsigned short st_nlink; | |
| - unsigned short st_uid; | |
| - unsigned short st_gid; | |
| - unsigned short st_rdev; | |
| + short unsigned int st_dev; | |
| + short unsigned int st_ino; | |
| + short unsigned int st_mode; | |
| + short unsigned int st_nlink; | |
| + short unsigned int st_uid; | |
| + short unsigned int st_gid; | |
| + short unsigned int st_rdev; | |
| unsigned int st_size; | |
| unsigned int st_atime; | |
| unsigned int st_mtime; | |
| unsigned int st_ctime; | |
| }; | |
| -typedef struct { | |
| - __u8 b[16]; | |
| -} uuid_t; | |
| - | |
| -struct __pldm_timestamp { | |
| - u8 b[13]; | |
| -}; | |
| - | |
| -struct __pldm_header { | |
| - uuid_t id; | |
| - u8 revision; | |
| - __le16 size; | |
| - struct __pldm_timestamp release_date; | |
| - __le16 component_bitmap_len; | |
| - u8 version_type; | |
| - u8 version_len; | |
| - u8 version_string[0]; | |
| -} __attribute__((packed)); | |
| - | |
| -struct __pldmfw_component_area { | |
| - __le16 component_image_count; | |
| - u8 components[0]; | |
| -}; | |
| - | |
| -struct __pldmfw_component_info { | |
| - __le16 classification; | |
| - __le16 identifier; | |
| - __le32 comparison_stamp; | |
| - __le16 options; | |
| - __le16 activation_method; | |
| - __le32 location_offset; | |
| - __le32 size; | |
| - u8 version_type; | |
| - u8 version_len; | |
| - u8 version_string[0]; | |
| -} __attribute__((packed)); | |
| - | |
| -struct __pldmfw_desc_tlv { | |
| - __le16 type; | |
| - __le16 size; | |
| - u8 data[0]; | |
| -}; | |
| - | |
| -struct __pldmfw_record_area { | |
| - u8 record_count; | |
| - u8 records[0]; | |
| -}; | |
| - | |
| -struct __pldmfw_record_info { | |
| - __le16 record_len; | |
| - u8 descriptor_count; | |
| - __le32 device_update_flags; | |
| - u8 version_type; | |
| - u8 version_len; | |
| - __le16 package_data_len; | |
| - u8 variable_record_data[0]; | |
| -} __attribute__((packed)); | |
| - | |
| -struct work_struct; | |
| - | |
| -typedef void (*work_func_t)(struct work_struct *); | |
| - | |
| -struct work_struct { | |
| - atomic_long_t data; | |
| - struct list_head entry; | |
| - work_func_t func; | |
| +struct __port_info { | |
| + __u64 designated_root; | |
| + __u64 designated_bridge; | |
| + __u16 port_id; | |
| + __u16 designated_port; | |
| + __u32 path_cost; | |
| + __u32 designated_cost; | |
| + __u8 state; | |
| + __u8 top_change_ack; | |
| + __u8 config_pending; | |
| + __u8 unused0; | |
| + __u32 message_age_timer_value; | |
| + __u32 forward_delay_timer_value; | |
| + __u32 hold_timer_value; | |
| }; | |
| -struct net_device; | |
| - | |
| struct __rt6_probe_work { | |
| struct work_struct work; | |
| struct in6_addr target; | |
| @@ -28797,102 +37632,9 @@ | |
| typedef __builtin_va_list va_list; | |
| -struct __xfsstats { | |
| - uint32_t xs_allocx; | |
| - uint32_t xs_allocb; | |
| - uint32_t xs_freex; | |
| - uint32_t xs_freeb; | |
| - uint32_t xs_abt_lookup; | |
| - uint32_t xs_abt_compare; | |
| - uint32_t xs_abt_insrec; | |
| - uint32_t xs_abt_delrec; | |
| - uint32_t xs_blk_mapr; | |
| - uint32_t xs_blk_mapw; | |
| - uint32_t xs_blk_unmap; | |
| - uint32_t xs_add_exlist; | |
| - uint32_t xs_del_exlist; | |
| - uint32_t xs_look_exlist; | |
| - uint32_t xs_cmp_exlist; | |
| - uint32_t xs_bmbt_lookup; | |
| - uint32_t xs_bmbt_compare; | |
| - uint32_t xs_bmbt_insrec; | |
| - uint32_t xs_bmbt_delrec; | |
| - uint32_t xs_dir_lookup; | |
| - uint32_t xs_dir_create; | |
| - uint32_t xs_dir_remove; | |
| - uint32_t xs_dir_getdents; | |
| - uint32_t xs_trans_sync; | |
| - uint32_t xs_trans_async; | |
| - uint32_t xs_trans_empty; | |
| - uint32_t xs_ig_attempts; | |
| - uint32_t xs_ig_found; | |
| - uint32_t xs_ig_frecycle; | |
| - uint32_t xs_ig_missed; | |
| - uint32_t xs_ig_dup; | |
| - uint32_t xs_ig_reclaims; | |
| - uint32_t xs_ig_attrchg; | |
| - uint32_t xs_log_writes; | |
| - uint32_t xs_log_blocks; | |
| - uint32_t xs_log_noiclogs; | |
| - uint32_t xs_log_force; | |
| - uint32_t xs_log_force_sleep; | |
| - uint32_t xs_try_logspace; | |
| - uint32_t xs_sleep_logspace; | |
| - uint32_t xs_push_ail; | |
| - uint32_t xs_push_ail_success; | |
| - uint32_t xs_push_ail_pushbuf; | |
| - uint32_t xs_push_ail_pinned; | |
| - uint32_t xs_push_ail_locked; | |
| - uint32_t xs_push_ail_flushing; | |
| - uint32_t xs_push_ail_restarts; | |
| - uint32_t xs_push_ail_flush; | |
| - uint32_t xs_xstrat_quick; | |
| - uint32_t xs_xstrat_split; | |
| - uint32_t xs_write_calls; | |
| - uint32_t xs_read_calls; | |
| - uint32_t xs_attr_get; | |
| - uint32_t xs_attr_set; | |
| - uint32_t xs_attr_remove; | |
| - uint32_t xs_attr_list; | |
| - uint32_t xs_iflush_count; | |
| - uint32_t xs_icluster_flushcnt; | |
| - uint32_t xs_icluster_flushinode; | |
| - uint32_t vn_active; | |
| - uint32_t vn_alloc; | |
| - uint32_t vn_get; | |
| - uint32_t vn_hold; | |
| - uint32_t vn_rele; | |
| - uint32_t vn_reclaim; | |
| - uint32_t vn_remove; | |
| - uint32_t vn_free; | |
| - uint32_t xb_get; | |
| - uint32_t xb_create; | |
| - uint32_t xb_get_locked; | |
| - uint32_t xb_get_locked_waited; | |
| - uint32_t xb_busy_locked; | |
| - uint32_t xb_miss_locked; | |
| - uint32_t xb_page_retries; | |
| - uint32_t xb_page_found; | |
| - uint32_t xb_get_read; | |
| - uint32_t xs_abtb_2[15]; | |
| - uint32_t xs_abtc_2[15]; | |
| - uint32_t xs_bmbt_2[15]; | |
| - uint32_t xs_ibt_2[15]; | |
| - uint32_t xs_fibt_2[15]; | |
| - uint32_t xs_rmap_2[15]; | |
| - uint32_t xs_refcbt_2[15]; | |
| - uint32_t xs_qm_dqreclaims; | |
| - uint32_t xs_qm_dqreclaim_misses; | |
| - uint32_t xs_qm_dquot_dups; | |
| - uint32_t xs_qm_dqcachemisses; | |
| - uint32_t xs_qm_dqcachehits; | |
| - uint32_t xs_qm_dqwants; | |
| - uint32_t xs_qm_dquot; | |
| - uint32_t xs_qm_dquot_unused; | |
| - uint64_t xs_xstrat_bytes; | |
| - uint64_t xs_write_bytes; | |
| - uint64_t xs_read_bytes; | |
| - uint64_t defer_relog; | |
| +struct __x86_intercept { | |
| + u32 exit_code; | |
| + enum x86_intercept_stage stage; | |
| }; | |
| struct _bpf_dtab_netdev { | |
| @@ -28902,7 +37644,15 @@ | |
| struct _cache_table { | |
| unsigned char descriptor; | |
| char cache_type; | |
| - short size; | |
| + short int size; | |
| +}; | |
| + | |
| +struct _ciss_lun { | |
| + u8 tid[3]; | |
| + u8 bus; | |
| + u8 level3[2]; | |
| + u8 level2[2]; | |
| + u8 node_ident[16]; | |
| }; | |
| union _cpuid4_leaf_eax { | |
| @@ -28929,7 +37679,7 @@ | |
| union _cpuid4_leaf_ecx { | |
| struct { | |
| - unsigned int number_of_sets; | |
| + unsigned int number_of_sets: 32; | |
| } split; | |
| u32 full; | |
| }; | |
| @@ -28941,54 +37691,10 @@ | |
| union _cpuid4_leaf_ebx ebx; | |
| union _cpuid4_leaf_ecx ecx; | |
| unsigned int id; | |
| - unsigned long size; | |
| + long unsigned int size; | |
| struct amd_northbridge *nb; | |
| }; | |
| -struct jump_entry; | |
| - | |
| -struct static_key_mod; | |
| - | |
| -struct static_key { | |
| - atomic_t enabled; | |
| - union { | |
| - unsigned long type; | |
| - struct jump_entry *entries; | |
| - struct static_key_mod *next; | |
| - }; | |
| -}; | |
| - | |
| -struct static_key_true { | |
| - struct static_key key; | |
| -}; | |
| - | |
| -struct static_key_false { | |
| - struct static_key key; | |
| -}; | |
| - | |
| -struct _ddebug { | |
| - const char *modname; | |
| - const char *function; | |
| - const char *filename; | |
| - const char *format; | |
| - unsigned int lineno: 18; | |
| - unsigned int class_id: 6; | |
| - unsigned int flags: 8; | |
| - union { | |
| - struct static_key_true dd_key_true; | |
| - struct static_key_false dd_key_false; | |
| - } key; | |
| -}; | |
| - | |
| -struct ddebug_class_map; | |
| - | |
| -struct _ddebug_info { | |
| - struct _ddebug *descs; | |
| - struct ddebug_class_map *classes; | |
| - unsigned int num_descs; | |
| - unsigned int num_classes; | |
| -}; | |
| - | |
| struct _flow_keys_digest_data { | |
| __be16 n_proto; | |
| u8 ip_proto; | |
| @@ -29106,6 +37812,80 @@ | |
| typedef struct _gpt_mbr_record gpt_mbr_record; | |
| +struct resource { | |
| + resource_size_t start; | |
| + resource_size_t end; | |
| + const char *name; | |
| + long unsigned int flags; | |
| + long unsigned int desc; | |
| + struct resource *parent; | |
| + struct resource *sibling; | |
| + struct resource *child; | |
| +}; | |
| + | |
| +struct intel_gtt_driver; | |
| + | |
| +struct page; | |
| + | |
| +struct _intel_private { | |
| + const struct intel_gtt_driver *driver; | |
| + struct pci_dev *pcidev; | |
| + struct pci_dev *bridge_dev; | |
| + u8 *registers; | |
| + phys_addr_t gtt_phys_addr; | |
| + u32 PGETBL_save; | |
| + u32 *gtt; | |
| + bool clear_fake_agp; | |
| + int num_dcache_entries; | |
| + void *i9xx_flush_page; | |
| + char *i81x_gtt_table; | |
| + struct resource ifp_resource; | |
| + int resource_valid; | |
| + struct page *scratch_page; | |
| + phys_addr_t scratch_page_dma; | |
| + int refcount; | |
| + unsigned int needs_dmar: 1; | |
| + phys_addr_t gma_bus_addr; | |
| + resource_size_t stolen_size; | |
| + unsigned int gtt_total_entries; | |
| + unsigned int gtt_mappable_entries; | |
| +}; | |
| + | |
| +struct _internal_cmd { | |
| + char *data; | |
| + dma_addr_t data_dma; | |
| + int size; | |
| + u8 cmd; | |
| + u8 channel; | |
| + u8 id; | |
| + u64 lun; | |
| + u8 flags; | |
| + u8 physDiskNum; | |
| + u8 rsvd2; | |
| + u8 rsvd; | |
| +}; | |
| + | |
| +typedef struct _internal_cmd INTERNAL_CMD; | |
| + | |
| +struct kvm_io_device_ops; | |
| + | |
| +struct kvm_io_device { | |
| + const struct kvm_io_device_ops *ops; | |
| +}; | |
| + | |
| +struct eventfd_ctx; | |
| + | |
| +struct _ioeventfd { | |
| + struct list_head list; | |
| + u64 addr; | |
| + int length; | |
| + struct eventfd_ctx *eventfd; | |
| + u64 datamatch; | |
| + struct kvm_io_device dev; | |
| + u8 bus_idx; | |
| + bool wildcard; | |
| +}; | |
| + | |
| struct kvm_stats_desc { | |
| __u32 flags; | |
| __s16 exponent; | |
| @@ -29130,6 +37910,56 @@ | |
| typedef struct _legacy_mbr legacy_mbr; | |
| +struct _mpt_ioctl_events { | |
| + u32 event; | |
| + u32 eventContext; | |
| + u32 data[2]; | |
| +}; | |
| + | |
| +struct _r7 { | |
| + __le32 init_struct_revision; | |
| + __le32 no_of_msix_vectors; | |
| + __le32 fsrev; | |
| + __le32 comm_header_address; | |
| + __le32 fast_io_comm_area_address; | |
| + __le32 adapter_fibs_physical_address; | |
| + __le32 adapter_fibs_virtual_address; | |
| + __le32 adapter_fibs_size; | |
| + __le32 adapter_fib_align; | |
| + __le32 printfbuf; | |
| + __le32 printfbufsiz; | |
| + __le32 host_phys_mem_pages; | |
| + __le32 host_elapsed_seconds; | |
| + __le32 init_flags; | |
| + __le32 max_io_commands; | |
| + __le32 max_io_size; | |
| + __le32 max_fib_size; | |
| + __le32 max_num_aif; | |
| + __le32 host_rrq_addr_low; | |
| + __le32 host_rrq_addr_high; | |
| +}; | |
| + | |
| +struct _rrq { | |
| + __le32 host_addr_low; | |
| + __le32 host_addr_high; | |
| + __le16 msix_id; | |
| + __le16 element_count; | |
| + __le16 comp_thresh; | |
| + __le16 unused; | |
| +}; | |
| + | |
| +struct _r8 { | |
| + __le32 init_struct_revision; | |
| + __le32 rr_queue_count; | |
| + __le32 host_elapsed_seconds; | |
| + __le32 init_flags; | |
| + __le32 max_io_size; | |
| + __le32 max_num_aif; | |
| + __le32 reserved1; | |
| + __le32 reserved2; | |
| + struct _rrq rrq[1]; | |
| +}; | |
| + | |
| struct mlx4_net_trans_rule_hw_eth { | |
| u8 size; | |
| u8 rsvd; | |
| @@ -29219,28 +38049,14 @@ | |
| int accum_len; | |
| }; | |
| -struct timer_list { | |
| - struct hlist_node entry; | |
| - unsigned long expires; | |
| - void (*function)(struct timer_list *); | |
| - u32 flags; | |
| -}; | |
| - | |
| -struct delayed_work { | |
| - struct work_struct work; | |
| - struct timer_list timer; | |
| - struct workqueue_struct *wq; | |
| - int cpu; | |
| -}; | |
| - | |
| struct _thermal_state { | |
| u64 next_check; | |
| u64 last_interrupt_time; | |
| struct delayed_work therm_work; | |
| - unsigned long count; | |
| - unsigned long last_count; | |
| - unsigned long max_time_ms; | |
| - unsigned long total_time_ms; | |
| + long unsigned int count; | |
| + long unsigned int last_count; | |
| + long unsigned int max_time_ms; | |
| + long unsigned int total_time_ms; | |
| bool rate_control_active; | |
| bool new_event; | |
| u8 level; | |
| @@ -29258,6 +38074,973 @@ | |
| char info[128]; | |
| }; | |
| +struct _x_config_parms { | |
| + union { | |
| + ConfigExtendedPageHeader_t *ehdr; | |
| + ConfigPageHeader_t *hdr; | |
| + } cfghdr; | |
| + dma_addr_t physAddr; | |
| + u32 pageAddr; | |
| + u16 status; | |
| + u8 action; | |
| + u8 dir; | |
| + u8 timeout; | |
| +}; | |
| + | |
| +typedef struct _x_config_parms CONFIGPARMS; | |
| + | |
| +struct a4tech_sc { | |
| + long unsigned int quirks; | |
| + unsigned int hw_wheel; | |
| + __s32 delayed_value; | |
| +}; | |
| + | |
| +struct aac_adapter_info { | |
| + __le32 platform; | |
| + __le32 cpu; | |
| + __le32 subcpu; | |
| + __le32 clock; | |
| + __le32 execmem; | |
| + __le32 buffermem; | |
| + __le32 totalmem; | |
| + __le32 kernelrev; | |
| + __le32 kernelbuild; | |
| + __le32 monitorrev; | |
| + __le32 monitorbuild; | |
| + __le32 hwrev; | |
| + __le32 hwbuild; | |
| + __le32 biosrev; | |
| + __le32 biosbuild; | |
| + __le32 cluster; | |
| + __le32 clusterchannelmask; | |
| + __le32 serial[2]; | |
| + __le32 battery; | |
| + __le32 options; | |
| + __le32 OEM; | |
| +}; | |
| + | |
| +struct aac_aifcmd { | |
| + __le32 command; | |
| + __le32 seqnum; | |
| + u8 data[0]; | |
| +}; | |
| + | |
| +struct aac_blockdevinfo { | |
| + __le32 block_size; | |
| + __le32 logical_phys_map; | |
| + u8 identifier[16]; | |
| +}; | |
| + | |
| +struct aac_bus_info { | |
| + __le32 Command; | |
| + __le32 ObjType; | |
| + __le32 MethodId; | |
| + __le32 ObjectId; | |
| + __le32 CtlCmd; | |
| +}; | |
| + | |
| +struct aac_bus_info_response { | |
| + __le32 Status; | |
| + __le32 ObjType; | |
| + __le32 MethodId; | |
| + __le32 ObjectId; | |
| + __le32 CtlCmd; | |
| + __le32 ProbeComplete; | |
| + __le32 BusCount; | |
| + __le32 TargetsPerBus; | |
| + u8 InitiatorBusId[10]; | |
| + u8 BusValid[10]; | |
| +}; | |
| + | |
| +struct aac_ciss_identify_pd { | |
| + u8 scsi_bus; | |
| + u8 scsi_id; | |
| + u16 block_size; | |
| + u32 total_blocks; | |
| + u32 reserved_blocks; | |
| + u8 model[40]; | |
| + u8 serial_number[40]; | |
| + u8 firmware_revision[8]; | |
| + u8 scsi_inquiry_bits; | |
| + u8 compaq_drive_stamp; | |
| + u8 last_failure_reason; | |
| + u8 flags; | |
| + u8 more_flags; | |
| + u8 scsi_lun; | |
| + u8 yet_more_flags; | |
| + u8 even_more_flags; | |
| + u32 spi_speed_rules; | |
| + u8 phys_connector[2]; | |
| + u8 phys_box_on_bus; | |
| + u8 phys_bay_in_box; | |
| + u32 rpm; | |
| + u8 device_type; | |
| + u8 sata_version; | |
| + u64 big_total_block_count; | |
| + u64 ris_starting_lba; | |
| + u32 ris_size; | |
| + u8 wwid[20]; | |
| + u8 controller_phy_map[32]; | |
| + u16 phy_count; | |
| + u8 phy_connected_dev_type[256]; | |
| + u8 phy_to_drive_bay_num[256]; | |
| + u16 phy_to_attached_dev_index[256]; | |
| + u8 box_index; | |
| + u8 spitfire_support; | |
| + u16 extra_physical_drive_flags; | |
| + u8 negotiated_link_rate[256]; | |
| + u8 phy_to_phy_map[256]; | |
| + u8 redundant_path_present_map; | |
| + u8 redundant_path_failure_map; | |
| + u8 active_path_number; | |
| + u16 alternate_paths_phys_connector[8]; | |
| + u8 alternate_paths_phys_box_on_port[8]; | |
| + u8 multi_lun_device_lun_count; | |
| + u8 minimum_good_fw_revision[8]; | |
| + u8 unique_inquiry_bytes[20]; | |
| + u8 current_temperature_degreesC; | |
| + u8 temperature_threshold_degreesC; | |
| + u8 max_temperature_degreesC; | |
| + u8 logical_blocks_per_phys_block_exp; | |
| + u16 current_queue_depth_limit; | |
| + u8 switch_name[10]; | |
| + u16 switch_port; | |
| + u8 alternate_paths_switch_name[40]; | |
| + u8 alternate_paths_switch_port[8]; | |
| + u16 power_on_hours; | |
| + u16 percent_endurance_used; | |
| + u8 drive_authentication; | |
| + u8 smart_carrier_authentication; | |
| + u8 smart_carrier_app_fw_version; | |
| + u8 smart_carrier_bootloader_fw_version; | |
| + u8 SanitizeSecureEraseSupport; | |
| + u8 DriveKeyFlags; | |
| + u8 encryption_key_name[64]; | |
| + u32 misc_drive_flags; | |
| + u16 dek_index; | |
| + u16 drive_encryption_flags; | |
| + u8 sanitize_maximum_time[6]; | |
| + u8 connector_info_mode; | |
| + u8 connector_info_number[4]; | |
| + u8 long_connector_name[64]; | |
| + u8 device_unique_identifier[16]; | |
| + u8 padto_2K[17]; | |
| +} __attribute__((packed)); | |
| + | |
| +struct aac_ciss_phys_luns_resp { | |
| + u8 list_length[4]; | |
| + u8 resp_flag; | |
| + u8 reserved[3]; | |
| + struct _ciss_lun lun[1]; | |
| +}; | |
| + | |
| +struct aac_close { | |
| + __le32 command; | |
| + __le32 cid; | |
| +}; | |
| + | |
| +struct aac_cmd_priv { | |
| + int (*callback)(struct scsi_cmnd *); | |
| + int status; | |
| + enum aac_cmd_owner owner; | |
| + bool sent_command; | |
| +}; | |
| + | |
| +struct aac_commit_config { | |
| + __le32 command; | |
| + __le32 type; | |
| +}; | |
| + | |
| +struct aac_common { | |
| + u32 irq_mod; | |
| + u32 peak_fibs; | |
| + u32 zero_fibs; | |
| + u32 fib_timeouts; | |
| +}; | |
| + | |
| +struct aac_delete_disk { | |
| + u32 disknum; | |
| + u32 cnum; | |
| +}; | |
| + | |
| +typedef irqreturn_t (*irq_handler_t)(int, void *); | |
| + | |
| +struct aac_dev; | |
| + | |
| +struct fib; | |
| + | |
| +struct adapter_ops { | |
| + void (*adapter_interrupt)(struct aac_dev *); | |
| + void (*adapter_notify)(struct aac_dev *, u32); | |
| + void (*adapter_disable_int)(struct aac_dev *); | |
| + void (*adapter_enable_int)(struct aac_dev *); | |
| + int (*adapter_sync_cmd)(struct aac_dev *, u32, u32, u32, u32, u32, u32, u32, u32 *, u32 *, u32 *, u32 *, u32 *); | |
| + int (*adapter_check_health)(struct aac_dev *); | |
| + int (*adapter_restart)(struct aac_dev *, int, u8); | |
| + void (*adapter_start)(struct aac_dev *); | |
| + int (*adapter_ioremap)(struct aac_dev *, u32); | |
| + irq_handler_t adapter_intr; | |
| + int (*adapter_deliver)(struct fib *); | |
| + int (*adapter_bounds)(struct aac_dev *, struct scsi_cmnd *, u64); | |
| + int (*adapter_read)(struct fib *, struct scsi_cmnd *, u64, u32); | |
| + int (*adapter_write)(struct fib *, struct scsi_cmnd *, u64, u32, int); | |
| + int (*adapter_scsi)(struct fib *, struct scsi_cmnd *); | |
| + int (*adapter_comm)(struct aac_dev *, int); | |
| +}; | |
| + | |
| +struct aac_supplement_adapter_info { | |
| + u8 adapter_type_text[18]; | |
| + u8 pad[2]; | |
| + __le32 flash_memory_byte_size; | |
| + __le32 flash_image_id; | |
| + __le32 max_number_ports; | |
| + __le32 version; | |
| + __le32 feature_bits; | |
| + u8 slot_number; | |
| + u8 reserved_pad0[3]; | |
| + u8 build_date[12]; | |
| + __le32 current_number_ports; | |
| + struct { | |
| + u8 assembly_pn[8]; | |
| + u8 fru_pn[8]; | |
| + u8 battery_fru_pn[8]; | |
| + u8 ec_version_string[8]; | |
| + u8 tsid[12]; | |
| + } vpd_info; | |
| + __le32 flash_firmware_revision; | |
| + __le32 flash_firmware_build; | |
| + __le32 raid_type_morph_options; | |
| + __le32 flash_firmware_boot_revision; | |
| + __le32 flash_firmware_boot_build; | |
| + u8 mfg_pcba_serial_no[12]; | |
| + u8 mfg_wwn_name[8]; | |
| + __le32 supported_options2; | |
| + __le32 struct_expansion; | |
| + __le32 feature_bits3; | |
| + __le32 supported_performance_modes; | |
| + u8 host_bus_type; | |
| + u8 host_bus_width; | |
| + u16 host_bus_speed; | |
| + u8 max_rrc_drives; | |
| + u8 max_disk_xtasks; | |
| + u8 cpld_ver_loaded; | |
| + u8 cpld_ver_in_flash; | |
| + __le64 max_rrc_capacity; | |
| + __le32 compiled_max_hist_log_level; | |
| + u8 custom_board_name[12]; | |
| + u16 supported_cntlr_mode; | |
| + u16 reserved_for_future16; | |
| + __le32 supported_options3; | |
| + __le16 virt_device_bus; | |
| + __le16 virt_device_target; | |
| + __le16 virt_device_lun; | |
| + __le16 unused; | |
| + __le32 reserved_for_future_growth[68]; | |
| +}; | |
| + | |
| +struct msix_entry { | |
| + u32 vector; | |
| + u16 entry; | |
| +}; | |
| + | |
| +struct aac_msix_ctx { | |
| + int vector_no; | |
| + struct aac_dev *dev; | |
| +}; | |
| + | |
| +struct aac_hba_map_info { | |
| + __le32 rmw_nexus; | |
| + u8 devtype; | |
| + s8 reset_state; | |
| + u16 qd_limit; | |
| + u32 scan_counter; | |
| + struct aac_ciss_identify_pd *safw_identify_resp; | |
| +}; | |
| + | |
| +struct hw_fib; | |
| + | |
| +struct aac_queue_block; | |
| + | |
| +union aac_init; | |
| + | |
| +struct fsa_dev_info; | |
| + | |
| +struct sa_registers; | |
| + | |
| +struct rx_registers; | |
| + | |
| +struct rkt_registers; | |
| + | |
| +struct src_registers; | |
| + | |
| +struct rx_inbound; | |
| + | |
| +struct aac_dev { | |
| + struct list_head entry; | |
| + const char *name; | |
| + int id; | |
| + unsigned int max_fib_size; | |
| + unsigned int sg_tablesize; | |
| + unsigned int max_num_aif; | |
| + unsigned int max_cmd_size; | |
| + dma_addr_t hw_fib_pa; | |
| + struct hw_fib *hw_fib_va; | |
| + struct hw_fib *aif_base_va; | |
| + struct fib *fibs; | |
| + struct fib *free_fib; | |
| + spinlock_t fib_lock; | |
| + struct mutex ioctl_mutex; | |
| + struct mutex scan_mutex; | |
| + struct aac_queue_block *queues; | |
| + struct list_head fib_list; | |
| + struct adapter_ops a_ops; | |
| + long unsigned int fsrev; | |
| + resource_size_t base_start; | |
| + resource_size_t dbg_base; | |
| + resource_size_t base_size; | |
| + resource_size_t dbg_size; | |
| + union aac_init *init; | |
| + dma_addr_t init_pa; | |
| + __le32 *host_rrq; | |
| + dma_addr_t host_rrq_pa; | |
| + u32 host_rrq_idx[32]; | |
| + atomic_t rrq_outstanding[32]; | |
| + u32 fibs_pushed_no; | |
| + struct pci_dev *pdev; | |
| + void *printfbuf; | |
| + void *comm_addr; | |
| + dma_addr_t comm_phys; | |
| + size_t comm_size; | |
| + struct Scsi_Host *scsi_host_ptr; | |
| + int maximum_num_containers; | |
| + int maximum_num_physicals; | |
| + int maximum_num_channels; | |
| + struct fsa_dev_info *fsa_dev; | |
| + struct task_struct *thread; | |
| + struct delayed_work safw_rescan_work; | |
| + struct delayed_work src_reinit_aif_worker; | |
| + int cardtype; | |
| + spinlock_t iq_lock; | |
| + union { | |
| + struct sa_registers *sa; | |
| + struct rx_registers *rx; | |
| + struct rkt_registers *rkt; | |
| + struct { | |
| + struct src_registers *bar0; | |
| + char *bar1; | |
| + } src; | |
| + } regs; | |
| + volatile void *base; | |
| + volatile void *dbg_base_mapped; | |
| + volatile struct rx_inbound *IndexRegs; | |
| + u32 OIMR; | |
| + u32 aif_thread; | |
| + struct aac_adapter_info adapter_info; | |
| + struct aac_supplement_adapter_info supplement_adapter_info; | |
| + u8 nondasd_support; | |
| + u8 jbod; | |
| + u8 cache_protected; | |
| + u8 dac_support; | |
| + u8 needs_dac; | |
| + u8 raid_scsi_mode; | |
| + u8 comm_interface; | |
| + u8 raw_io_interface; | |
| + u8 raw_io_64; | |
| + u8 printf_enabled; | |
| + u8 in_reset; | |
| + u8 in_soft_reset; | |
| + u8 msi; | |
| + u8 sa_firmware; | |
| + int management_fib_count; | |
| + spinlock_t manage_lock; | |
| + spinlock_t sync_lock; | |
| + int sync_mode; | |
| + struct fib *sync_fib; | |
| + struct list_head sync_fib_list; | |
| + u32 doorbell_mask; | |
| + u32 max_msix; | |
| + u32 vector_cap; | |
| + int msi_enabled; | |
| + atomic_t msix_counter; | |
| + u32 scan_counter; | |
| + struct msix_entry msixentry[32]; | |
| + struct aac_msix_ctx aac_msix[32]; | |
| + struct aac_hba_map_info hba_map[1280]; | |
| + struct aac_ciss_phys_luns_resp *safw_phys_luns; | |
| + u8 adapter_shutdown; | |
| + u32 handle_pci_error; | |
| + bool init_reset; | |
| + u8 soft_reset_support; | |
| +}; | |
| + | |
| +struct aac_driver_ident { | |
| + int (*init)(struct aac_dev *); | |
| + char *name; | |
| + char *vname; | |
| + char *model; | |
| + u16 channels; | |
| + int quirks; | |
| +}; | |
| + | |
| +struct aac_entry { | |
| + __le32 size; | |
| + __le32 addr; | |
| +}; | |
| + | |
| +struct aac_fib_context { | |
| + s16 type; | |
| + s16 size; | |
| + u32 unique; | |
| + ulong jiffies; | |
| + struct list_head next; | |
| + struct completion completion; | |
| + int wait; | |
| + long unsigned int count; | |
| + struct list_head fib_list; | |
| +}; | |
| + | |
| +struct aac_fib_xporthdr { | |
| + __le64 HostAddress; | |
| + __le32 Size; | |
| + __le32 Handle; | |
| + __le64 Reserved[2]; | |
| +}; | |
| + | |
| +struct aac_fibhdr { | |
| + __le32 XferState; | |
| + __le16 Command; | |
| + u8 StructType; | |
| + u8 Unused; | |
| + __le16 Size; | |
| + __le16 SenderSize; | |
| + __le32 SenderFibAddress; | |
| + union { | |
| + __le32 ReceiverFibAddress; | |
| + __le32 SenderFibAddressHigh; | |
| + __le32 TimeStamp; | |
| + } u; | |
| + __le32 Handle; | |
| + u32 Previous; | |
| + u32 Next; | |
| +}; | |
| + | |
| +struct aac_fsinfo { | |
| + __le32 fsTotalSize; | |
| + __le32 fsBlockSize; | |
| + __le32 fsFragSize; | |
| + __le32 fsMaxExtendSize; | |
| + __le32 fsSpaceUnits; | |
| + __le32 fsMaxNumFiles; | |
| + __le32 fsNumFreeFiles; | |
| + __le32 fsInodeDensity; | |
| +}; | |
| + | |
| +struct aac_get_config_status { | |
| + __le32 command; | |
| + __le32 type; | |
| + __le32 parm1; | |
| + __le32 parm2; | |
| + __le32 parm3; | |
| + __le32 parm4; | |
| + __le32 parm5; | |
| + __le32 count; | |
| +}; | |
| + | |
| +struct aac_get_config_status_resp { | |
| + __le32 response; | |
| + __le32 dummy0; | |
| + __le32 status; | |
| + __le32 parm1; | |
| + __le32 parm2; | |
| + __le32 parm3; | |
| + __le32 parm4; | |
| + __le32 parm5; | |
| + struct { | |
| + __le32 action; | |
| + __le16 flags; | |
| + __le16 count; | |
| + } data; | |
| +}; | |
| + | |
| +struct aac_get_container_count { | |
| + __le32 command; | |
| + __le32 type; | |
| +}; | |
| + | |
| +struct aac_get_container_count_resp { | |
| + __le32 response; | |
| + __le32 dummy0; | |
| + __le32 MaxContainers; | |
| + __le32 ContainerSwitchEntries; | |
| + __le32 MaxPartitions; | |
| + __le32 MaxSimpleVolumes; | |
| +}; | |
| + | |
| +struct aac_get_name { | |
| + __le32 command; | |
| + __le32 type; | |
| + __le32 cid; | |
| + __le32 parm1; | |
| + __le32 parm2; | |
| + __le32 parm3; | |
| + __le32 parm4; | |
| + __le32 count; | |
| +}; | |
| + | |
| +struct aac_get_name_resp { | |
| + __le32 dummy0; | |
| + __le32 dummy1; | |
| + __le32 status; | |
| + __le32 parm1; | |
| + __le32 parm2; | |
| + __le32 parm3; | |
| + __le32 parm4; | |
| + __le32 parm5; | |
| + u8 data[17]; | |
| +}; | |
| + | |
| +struct aac_get_serial { | |
| + __le32 command; | |
| + __le32 type; | |
| + __le32 cid; | |
| +}; | |
| + | |
| +struct aac_get_serial_resp { | |
| + __le32 dummy0; | |
| + __le32 dummy1; | |
| + __le32 status; | |
| + __le32 uid; | |
| +}; | |
| + | |
| +struct aac_hba_sgl { | |
| + u32 addr_lo; | |
| + u32 addr_hi; | |
| + u32 len; | |
| + u32 flags; | |
| +}; | |
| + | |
| +struct aac_hba_cmd_req { | |
| + u8 iu_type; | |
| + u8 byte1; | |
| + u8 reply_qid; | |
| + u8 reserved1; | |
| + __le32 it_nexus; | |
| + __le32 request_id; | |
| + __le32 tweak_value_lo; | |
| + u8 cdb[16]; | |
| + u8 lun[8]; | |
| + __le32 data_length; | |
| + u8 attr_prio; | |
| + u8 emb_data_desc_count; | |
| + __le16 dek_index; | |
| + __le32 error_ptr_lo; | |
| + __le32 error_ptr_hi; | |
| + __le32 error_length; | |
| + __le32 tweak_value_hi; | |
| + struct aac_hba_sgl sge[92]; | |
| +}; | |
| + | |
| +struct aac_hba_info { | |
| + u8 driver_name[50]; | |
| + u8 adapter_number; | |
| + u8 system_io_bus_number; | |
| + u8 device_number; | |
| + u32 function_number; | |
| + u32 vendor_id; | |
| + u32 device_id; | |
| + u32 sub_vendor_id; | |
| + u32 sub_system_id; | |
| + u32 mapped_base_address_size; | |
| + u32 base_physical_address_high_part; | |
| + u32 base_physical_address_low_part; | |
| + u32 max_command_size; | |
| + u32 max_fib_size; | |
| + u32 max_scatter_gather_from_os; | |
| + u32 max_scatter_gather_to_fw; | |
| + u32 max_outstanding_fibs; | |
| + u32 queue_start_threshold; | |
| + u32 queue_dump_threshold; | |
| + u32 max_io_size_queued; | |
| + u32 outstanding_io; | |
| + u32 firmware_build_number; | |
| + u32 bios_build_number; | |
| + u32 driver_build_number; | |
| + u32 serial_number_high_part; | |
| + u32 serial_number_low_part; | |
| + u32 supported_options; | |
| + u32 feature_bits; | |
| + u32 currentnumber_ports; | |
| + u8 new_comm_interface: 1; | |
| + u8 new_commands_supported: 1; | |
| + u8 disable_passthrough: 1; | |
| + u8 expose_non_dasd: 1; | |
| + u8 queue_allowed: 1; | |
| + u8 bled_check_enabled: 1; | |
| + u8 reserved1: 1; | |
| + u8 reserted2: 1; | |
| + u32 reserved3[10]; | |
| +}; | |
| + | |
| +struct aac_hba_reset_req { | |
| + u8 iu_type; | |
| + u8 reset_type; | |
| + u8 reply_qid; | |
| + u8 reserved1; | |
| + __le32 it_nexus; | |
| + __le32 request_id; | |
| + __le32 error_ptr_lo; | |
| + __le32 error_ptr_hi; | |
| + __le32 error_length; | |
| +}; | |
| + | |
| +struct aac_hba_resp { | |
| + u8 iu_type; | |
| + u8 reserved1[3]; | |
| + __le32 request_identifier; | |
| + __le32 reserved2; | |
| + u8 service_response; | |
| + u8 status; | |
| + u8 datapres; | |
| + u8 sense_response_data_len; | |
| + __le32 residual_count; | |
| + u8 sense_response_buf[32]; | |
| +}; | |
| + | |
| +struct aac_hba_tm_req { | |
| + u8 iu_type; | |
| + u8 reply_qid; | |
| + u8 tmf; | |
| + u8 reserved1; | |
| + __le32 it_nexus; | |
| + u8 lun[8]; | |
| + __le32 request_id; | |
| + __le32 reserved2; | |
| + __le32 managed_request_id; | |
| + __le32 reserved3; | |
| + __le32 error_ptr_lo; | |
| + __le32 error_ptr_hi; | |
| + __le32 error_length; | |
| +}; | |
| + | |
| +struct creation_info { | |
| + u8 buildnum; | |
| + u8 usec; | |
| + u8 via; | |
| + u8 year; | |
| + __le32 date; | |
| + __le32 serial[2]; | |
| +}; | |
| + | |
| +union aac_contentinfo { | |
| + struct aac_fsinfo filesys; | |
| + struct aac_blockdevinfo bdevinfo; | |
| +}; | |
| + | |
| +struct aac_mntent { | |
| + __le32 oid; | |
| + u8 name[16]; | |
| + struct creation_info create_info; | |
| + __le32 capacity; | |
| + __le32 vol; | |
| + __le32 obj; | |
| + __le32 state; | |
| + union aac_contentinfo fileinfo; | |
| + __le32 altoid; | |
| + __le32 capacityhigh; | |
| +}; | |
| + | |
| +struct aac_mount { | |
| + __le32 status; | |
| + __le32 type; | |
| + __le32 count; | |
| + struct aac_mntent mnt[1]; | |
| +}; | |
| + | |
| +struct aac_native_hba { | |
| + union { | |
| + struct aac_hba_cmd_req cmd; | |
| + struct aac_hba_tm_req tmr; | |
| + u8 cmd_bytes[1536]; | |
| + } cmd; | |
| + union { | |
| + struct aac_hba_resp err; | |
| + u8 resp_bytes[512]; | |
| + } resp; | |
| +}; | |
| + | |
| +struct aac_pause { | |
| + __le32 command; | |
| + __le32 type; | |
| + __le32 timeout; | |
| + __le32 min; | |
| + __le32 noRescan; | |
| + __le32 parm3; | |
| + __le32 parm4; | |
| + __le32 count; | |
| +}; | |
| + | |
| +struct aac_pci_info { | |
| + u32 bus; | |
| + u32 slot; | |
| +}; | |
| + | |
| +struct aac_power_management { | |
| + __le32 command; | |
| + __le32 type; | |
| + __le32 sub; | |
| + __le32 cid; | |
| + __le32 parm; | |
| +}; | |
| + | |
| +struct aac_qhdr { | |
| + __le64 header_addr; | |
| + __le32 *producer; | |
| + __le32 *consumer; | |
| +}; | |
| + | |
| +struct aac_query_disk { | |
| + s32 cnum; | |
| + s32 bus; | |
| + s32 id; | |
| + s32 lun; | |
| + u32 valid; | |
| + u32 locked; | |
| + u32 deleted; | |
| + s32 instance; | |
| + s8 name[10]; | |
| + u32 unmapped; | |
| +}; | |
| + | |
| +struct aac_query_mount { | |
| + __le32 command; | |
| + __le32 type; | |
| + __le32 count; | |
| +}; | |
| + | |
| +struct aac_queue { | |
| + u64 logical; | |
| + struct aac_entry *base; | |
| + struct aac_qhdr headers; | |
| + u32 entries; | |
| + wait_queue_head_t qfull; | |
| + wait_queue_head_t cmdready; | |
| + spinlock_t *lock; | |
| + spinlock_t lockdata; | |
| + struct list_head cmdq; | |
| + atomic_t numpending; | |
| + struct aac_dev *dev; | |
| +}; | |
| + | |
| +struct aac_queue_block { | |
| + struct aac_queue queue[8]; | |
| +}; | |
| + | |
| +struct sgentryraw { | |
| + __le32 next; | |
| + __le32 prev; | |
| + __le32 addr[2]; | |
| + __le32 count; | |
| + __le32 flags; | |
| +}; | |
| + | |
| +struct sgmapraw { | |
| + __le32 count; | |
| + struct sgentryraw sg[1]; | |
| +}; | |
| + | |
| +struct aac_raw_io { | |
| + __le32 block[2]; | |
| + __le32 count; | |
| + __le16 cid; | |
| + __le16 flags; | |
| + __le16 bpTotal; | |
| + __le16 bpComplete; | |
| + struct sgmapraw sg; | |
| +}; | |
| + | |
| +struct sge_ieee1212 { | |
| + u32 addrLow; | |
| + u32 addrHigh; | |
| + u32 length; | |
| + u32 flags; | |
| +}; | |
| + | |
| +struct aac_raw_io2 { | |
| + __le32 blockLow; | |
| + __le32 blockHigh; | |
| + __le32 byteCount; | |
| + __le16 cid; | |
| + __le16 flags; | |
| + __le32 sgeFirstSize; | |
| + __le32 sgeNominalSize; | |
| + u8 sgeCnt; | |
| + u8 bpTotal; | |
| + u8 bpComplete; | |
| + u8 sgeFirstIndex; | |
| + u8 unused[4]; | |
| + struct sge_ieee1212 sge[0]; | |
| +}; | |
| + | |
| +struct sgentry { | |
| + __le32 addr; | |
| + __le32 count; | |
| +}; | |
| + | |
| +struct sgmap { | |
| + __le32 count; | |
| + struct sgentry sg[1]; | |
| +}; | |
| + | |
| +struct aac_read { | |
| + __le32 command; | |
| + __le32 cid; | |
| + __le32 block; | |
| + __le32 count; | |
| + struct sgmap sg; | |
| +}; | |
| + | |
| +struct sgentry64 { | |
| + __le32 addr[2]; | |
| + __le32 count; | |
| +}; | |
| + | |
| +struct sgmap64 { | |
| + __le32 count; | |
| + struct sgentry64 sg[1]; | |
| +}; | |
| + | |
| +struct aac_read64 { | |
| + __le32 command; | |
| + __le16 cid; | |
| + __le16 sector_count; | |
| + __le32 block; | |
| + __le16 pad; | |
| + __le16 flags; | |
| + struct sgmap64 sg; | |
| +}; | |
| + | |
| +struct aac_read_reply { | |
| + __le32 status; | |
| + __le32 count; | |
| +}; | |
| + | |
| +struct aac_reset_iop { | |
| + u8 reset_type; | |
| +}; | |
| + | |
| +struct aac_srb { | |
| + __le32 function; | |
| + __le32 channel; | |
| + __le32 id; | |
| + __le32 lun; | |
| + __le32 timeout; | |
| + __le32 flags; | |
| + __le32 count; | |
| + __le32 retry_limit; | |
| + __le32 cdb_size; | |
| + u8 cdb[16]; | |
| + struct sgmap sg; | |
| +}; | |
| + | |
| +struct aac_srb_reply { | |
| + __le32 status; | |
| + __le32 srb_status; | |
| + __le32 scsi_status; | |
| + __le32 data_xfer_length; | |
| + __le32 sense_data_size; | |
| + u8 sense_data[30]; | |
| +}; | |
| + | |
| +struct aac_srb_unit { | |
| + struct aac_srb srb; | |
| + struct aac_srb_reply srb_reply; | |
| +}; | |
| + | |
| +struct aac_synchronize { | |
| + __le32 command; | |
| + __le32 type; | |
| + __le32 cid; | |
| + __le32 parm1; | |
| + __le32 parm2; | |
| + __le32 parm3; | |
| + __le32 parm4; | |
| + __le32 count; | |
| +}; | |
| + | |
| +struct aac_synchronize_reply { | |
| + __le32 dummy0; | |
| + __le32 dummy1; | |
| + __le32 status; | |
| + __le32 parm1; | |
| + __le32 parm2; | |
| + __le32 parm3; | |
| + __le32 parm4; | |
| + __le32 parm5; | |
| + u8 data[16]; | |
| +}; | |
| + | |
| +struct aac_write { | |
| + __le32 command; | |
| + __le32 cid; | |
| + __le32 block; | |
| + __le32 count; | |
| + __le32 stable; | |
| + struct sgmap sg; | |
| +}; | |
| + | |
| +struct aac_write64 { | |
| + __le32 command; | |
| + __le16 cid; | |
| + __le16 sector_count; | |
| + __le32 block; | |
| + __le16 pad; | |
| + __le16 flags; | |
| + struct sgmap64 sg; | |
| +}; | |
| + | |
| +struct ssp_frame_hdr { | |
| + u8 frame_type; | |
| + u8 hashed_dest_addr[3]; | |
| + u8 _r_a; | |
| + u8 hashed_src_addr[3]; | |
| + __be16 _r_b; | |
| + u8 changing_data_ptr: 1; | |
| + u8 retransmit: 1; | |
| + u8 retry_data_frames: 1; | |
| + u8 _r_c: 5; | |
| + u8 num_fill_bytes: 2; | |
| + u8 _r_d: 6; | |
| + u32 _r_e; | |
| + __be16 tag; | |
| + __be16 tptt; | |
| + __be32 data_offs; | |
| +}; | |
| + | |
| +struct ssp_tmf_iu { | |
| + u8 lun[8]; | |
| + u16 _r_a; | |
| + u8 tmf; | |
| + u8 _r_b; | |
| + __be16 tag; | |
| + u8 _r_c[14]; | |
| +}; | |
| + | |
| +struct abort_task { | |
| + u8 proto_conn_rate; | |
| + __le32 _r_a; | |
| + struct ssp_frame_hdr ssp_frame; | |
| + struct ssp_tmf_iu ssp_task; | |
| + __le16 sister_scb; | |
| + __le16 conn_handle; | |
| + u8 flags; | |
| + u8 _r_b; | |
| + u8 retry_count; | |
| + u8 _r_c[5]; | |
| + __le16 index; | |
| + __le16 itnl_to; | |
| + u8 _r_d[44]; | |
| +} __attribute__((packed)); | |
| + | |
| typedef struct {} netns_tracker; | |
| struct net; | |
| @@ -29267,14 +39050,45 @@ | |
| netns_tracker ns_tracker; | |
| }; | |
| -struct inet6_dev; | |
| - | |
| struct ac6_iter_state { | |
| struct seq_net_private p; | |
| struct net_device *dev; | |
| - struct inet6_dev *idev; | |
| }; | |
| +struct access_coordinate { | |
| + unsigned int read_bandwidth; | |
| + unsigned int write_bandwidth; | |
| + unsigned int read_latency; | |
| + unsigned int write_latency; | |
| +}; | |
| + | |
| +struct acct { | |
| + char ac_flag; | |
| + char ac_version; | |
| + __u16 ac_uid16; | |
| + __u16 ac_gid16; | |
| + __u16 ac_tty; | |
| + __u32 ac_btime; | |
| + comp_t ac_utime; | |
| + comp_t ac_stime; | |
| + comp_t ac_etime; | |
| + comp_t ac_mem; | |
| + comp_t ac_io; | |
| + comp_t ac_rw; | |
| + comp_t ac_minflt; | |
| + comp_t ac_majflt; | |
| + comp_t ac_swaps; | |
| + __u16 ac_ahz; | |
| + __u32 ac_exitcode; | |
| + char ac_comm[17]; | |
| + __u8 ac_etime_hi; | |
| + __u16 ac_etime_lo; | |
| + __u32 ac_uid; | |
| + __u32 ac_gid; | |
| +}; | |
| + | |
| +typedef struct acct acct_t; | |
| + | |
| struct ack_sample { | |
| u32 pkts_acked; | |
| s32 rtt_us; | |
| @@ -29398,14 +39212,6 @@ | |
| acpi_physical_address end_address; | |
| }; | |
| -struct acpi_bert_region { | |
| - u32 block_status; | |
| - u32 raw_data_offset; | |
| - u32 raw_data_length; | |
| - u32 data_length; | |
| - u32 error_severity; | |
| -}; | |
| - | |
| struct acpi_bit_register_info { | |
| u8 parent_register; | |
| u8 bit_position; | |
| @@ -29435,6 +39241,12 @@ | |
| void (*setup)(struct device *); | |
| }; | |
| +struct acpi_cdat_header { | |
| + u8 type; | |
| + u8 reserved; | |
| + u16 length; | |
| +}; | |
| + | |
| struct acpi_cedt_header { | |
| u8 type; | |
| u8 reserved; | |
| @@ -29455,23 +39267,6 @@ | |
| u32 interleave_targets[0]; | |
| } __attribute__((packed)); | |
| -struct acpi_cedt_chbs { | |
| - struct acpi_cedt_header header; | |
| - u32 uid; | |
| - u32 cxl_version; | |
| - u32 reserved; | |
| - u64 base; | |
| - u64 length; | |
| -}; | |
| - | |
| -struct acpi_cedt_cxims { | |
| - struct acpi_cedt_header header; | |
| - u16 reserved1; | |
| - u8 hbig; | |
| - u8 nr_xormaps; | |
| - u64 xormap_list[0]; | |
| -}; | |
| - | |
| struct acpi_comment_node { | |
| char *comment; | |
| struct acpi_comment_node *next; | |
| @@ -29511,6 +39306,23 @@ | |
| u64 loop_timeout; | |
| }; | |
| +struct cpumask { | |
| + long unsigned int bits[2]; | |
| +}; | |
| + | |
| +typedef struct cpumask cpumask_var_t[1]; | |
| + | |
| +struct acpi_pct_register; | |
| + | |
| +struct acpi_cpufreq_data { | |
| + unsigned int resume; | |
| + unsigned int cpu_feature; | |
| + unsigned int acpi_perf_cpu; | |
| + cpumask_var_t freqdomain_cpus; | |
| + void (*cpu_freq_write)(struct acpi_pct_register *, u32); | |
| + u32 (*cpu_freq_read)(struct acpi_pct_register *); | |
| +}; | |
| + | |
| struct acpi_create_field_info { | |
| struct acpi_namespace_node *region_node; | |
| struct acpi_namespace_node *field_node; | |
| @@ -29558,6 +39370,9 @@ | |
| struct attribute { | |
| const char *name; | |
| umode_t mode; | |
| + bool ignore_lockdep: 1; | |
| + struct lock_class_key *key; | |
| + struct lock_class_key skey; | |
| }; | |
| struct address_space; | |
| @@ -29573,6 +39388,7 @@ | |
| struct address_space * (*f_mapping)(); | |
| ssize_t (*read)(struct file *, struct kobject *, struct bin_attribute *, char *, loff_t, size_t); | |
| ssize_t (*write)(struct file *, struct kobject *, struct bin_attribute *, char *, loff_t, size_t); | |
| + loff_t (*llseek)(struct file *, struct kobject *, struct bin_attribute *, loff_t, int); | |
| int (*mmap)(struct file *, struct kobject *, struct bin_attribute *, struct vm_area_struct *); | |
| }; | |
| @@ -29604,12 +39420,12 @@ | |
| }; | |
| struct acpi_data_node { | |
| + struct list_head sibling; | |
| const char *name; | |
| acpi_handle handle; | |
| struct fwnode_handle fwnode; | |
| struct fwnode_handle *parent; | |
| struct acpi_device_data data; | |
| - struct list_head sibling; | |
| struct kobject kobj; | |
| struct completion kobj_done; | |
| }; | |
| @@ -29634,6 +39450,8 @@ | |
| acpi_handle supplier; | |
| acpi_handle consumer; | |
| bool honor_dep; | |
| + bool met; | |
| + bool free_when_met; | |
| }; | |
| struct acpi_device_id { | |
| @@ -29712,6 +39530,7 @@ | |
| }; | |
| struct acpi_device_power_state { | |
| + struct list_head resources; | |
| struct { | |
| u8 valid: 1; | |
| u8 explicit_set: 1; | |
| @@ -29719,7 +39538,6 @@ | |
| } flags; | |
| int power; | |
| int latency; | |
| - struct list_head resources; | |
| }; | |
| struct acpi_device_power { | |
| @@ -29739,8 +39557,6 @@ | |
| struct device *dev; | |
| }; | |
| -struct wakeup_source; | |
| - | |
| struct acpi_device_wakeup { | |
| acpi_handle gpe_device; | |
| u64 gpe_number; | |
| @@ -29754,7 +39570,7 @@ | |
| }; | |
| struct acpi_device_perf_flags { | |
| - u8 reserved; | |
| + u8 reserved: 8; | |
| }; | |
| struct acpi_device_perf_state; | |
| @@ -29766,8 +39582,6 @@ | |
| struct acpi_device_perf_state *states; | |
| }; | |
| -struct proc_dir_entry; | |
| - | |
| struct acpi_device_dir { | |
| struct proc_dir_entry *entry; | |
| }; | |
| @@ -29776,6 +39590,8 @@ | |
| struct acpi_hotplug_context; | |
| +struct acpi_device_software_nodes; | |
| + | |
| struct acpi_gpio_mapping; | |
| struct acpi_device { | |
| @@ -29795,6 +39611,7 @@ | |
| struct acpi_device_data data; | |
| struct acpi_scan_handler *handler; | |
| struct acpi_hotplug_context *hp; | |
| + struct acpi_device_software_nodes *swnodes; | |
| const struct acpi_gpio_mapping *driver_gpios; | |
| void *driver_data; | |
| struct device dev; | |
| @@ -29808,7 +39625,7 @@ | |
| struct xarray { | |
| spinlock_t xa_lock; | |
| gfp_t xa_flags; | |
| - void __attribute__((btf_type_tag("rcu"))) *xa_head; | |
| + void *xa_head; | |
| }; | |
| struct ida { | |
| @@ -29871,19 +39688,64 @@ | |
| }; | |
| struct acpi_device_physical_node { | |
| - unsigned int node_id; | |
| struct list_head node; | |
| struct device *dev; | |
| + unsigned int node_id; | |
| bool put_online: 1; | |
| }; | |
| struct acpi_device_properties { | |
| + struct list_head list; | |
| const guid_t *guid; | |
| union acpi_object *properties; | |
| - struct list_head list; | |
| void **bufs; | |
| }; | |
| +struct property_entry { | |
| + const char *name; | |
| + size_t length; | |
| + bool is_inline; | |
| + enum dev_prop_type type; | |
| + union { | |
| + const void *pointer; | |
| + union { | |
| + u8 u8_data[8]; | |
| + u16 u16_data[4]; | |
| + u32 u32_data[2]; | |
| + u64 u64_data[1]; | |
| + const char *str[1]; | |
| + } value; | |
| + }; | |
| +}; | |
| + | |
| +struct software_node; | |
| + | |
| +struct software_node_ref_args { | |
| + const struct software_node *node; | |
| + unsigned int nargs; | |
| + u64 args[8]; | |
| +}; | |
| + | |
| +struct acpi_device_software_node_port { | |
| + char port_name[9]; | |
| + u32 data_lanes[8]; | |
| + u32 lane_polarities[9]; | |
| + u64 link_frequencies[8]; | |
| + unsigned int port_nr; | |
| + bool crs_csi2_local; | |
| + struct property_entry port_props[2]; | |
| + struct property_entry ep_props[8]; | |
| + struct software_node_ref_args remote_ep[1]; | |
| +}; | |
| + | |
| +struct acpi_device_software_nodes { | |
| + struct property_entry dev_props[6]; | |
| + struct software_node *nodes; | |
| + const struct software_node **nodeptrs; | |
| + struct acpi_device_software_node_port *ports; | |
| + unsigned int num_ports; | |
| +}; | |
| + | |
| struct acpi_table_desc; | |
| struct acpi_evaluate_info; | |
| @@ -29905,12 +39767,12 @@ | |
| struct device *dev; | |
| struct dma_chan * (*acpi_dma_xlate)(struct acpi_dma_spec *, struct acpi_dma *); | |
| void *data; | |
| - unsigned short base_request_line; | |
| - unsigned short end_request_line; | |
| + short unsigned int base_request_line; | |
| + short unsigned int end_request_line; | |
| }; | |
| typedef struct { | |
| - unsigned long bits[1]; | |
| + long unsigned int bits[1]; | |
| } dma_cap_mask_t; | |
| typedef bool (*dma_filter_fn)(struct dma_chan *, void *); | |
| @@ -30035,7 +39897,6 @@ | |
| unsigned int flags; | |
| struct acpi_device_ops ops; | |
| struct device_driver drv; | |
| - struct module *owner; | |
| }; | |
| struct transaction; | |
| @@ -30045,18 +39906,18 @@ | |
| acpi_handle address_space_handler_holder; | |
| int gpe; | |
| int irq; | |
| - unsigned long command_addr; | |
| - unsigned long data_addr; | |
| + long unsigned int command_addr; | |
| + long unsigned int data_addr; | |
| bool global_lock; | |
| - unsigned long flags; | |
| - unsigned long reference_count; | |
| + long unsigned int flags; | |
| + long unsigned int reference_count; | |
| struct mutex mutex; | |
| wait_queue_head_t wait; | |
| struct list_head list; | |
| struct transaction *curr; | |
| spinlock_t lock; | |
| struct work_struct work; | |
| - unsigned long timestamp; | |
| + long unsigned int timestamp; | |
| enum acpi_ec_event_state event_state; | |
| unsigned int events_to_process; | |
| unsigned int events_in_progress; | |
| @@ -30068,7 +39929,7 @@ | |
| struct transaction { | |
| const u8 *wdata; | |
| u8 *rdata; | |
| - unsigned short irq_count; | |
| + short unsigned int irq_count; | |
| u8 command; | |
| u8 wi; | |
| u8 ri; | |
| @@ -30097,13 +39958,6 @@ | |
| struct kref kref; | |
| }; | |
| -struct acpi_einj_trigger { | |
| - u32 header_size; | |
| - u32 revision; | |
| - u32 table_size; | |
| - u32 entry_count; | |
| -}; | |
| - | |
| union acpi_operand_object; | |
| union acpi_predefined_info; | |
| @@ -30223,6 +40077,12 @@ | |
| acpi_handle handle; | |
| }; | |
| +struct acpi_ged_handler_info { | |
| + struct acpi_ged_handler_info *next; | |
| + u32 int_id; | |
| + struct acpi_namespace_node *evt_method; | |
| +}; | |
| + | |
| struct acpi_generic_address { | |
| u8 space_id; | |
| u8 bit_width; | |
| @@ -30370,15 +40230,13 @@ | |
| struct gpio_desc *desc; | |
| }; | |
| -typedef irqreturn_t (*irq_handler_t)(int, void *); | |
| - | |
| struct acpi_gpio_event { | |
| struct list_head node; | |
| acpi_handle handle; | |
| irq_handler_t handler; | |
| unsigned int pin; | |
| unsigned int irq; | |
| - unsigned long irqflags; | |
| + long unsigned int irqflags; | |
| bool irq_is_wake; | |
| bool irq_requested; | |
| struct gpio_desc *desc; | |
| @@ -30428,7 +40286,7 @@ | |
| struct acpi_handle_list { | |
| u32 count; | |
| - acpi_handle handles[10]; | |
| + acpi_handle *handles; | |
| }; | |
| struct acpi_hardware_id { | |
| @@ -30436,143 +40294,23 @@ | |
| const char *id; | |
| }; | |
| -struct acpi_hest_header { | |
| - u16 type; | |
| - u16 source_id; | |
| -}; | |
| - | |
| -struct acpi_hest_notify { | |
| - u8 type; | |
| - u8 length; | |
| - u16 config_write_enable; | |
| - u32 poll_interval; | |
| - u32 vector; | |
| - u32 polling_threshold_value; | |
| - u32 polling_threshold_window; | |
| - u32 error_threshold_value; | |
| - u32 error_threshold_window; | |
| -}; | |
| - | |
| -struct acpi_hest_generic { | |
| - struct acpi_hest_header header; | |
| - u16 related_source_id; | |
| - u8 reserved; | |
| - u8 enabled; | |
| - u32 records_to_preallocate; | |
| - u32 max_sections_per_record; | |
| - u32 max_raw_data_length; | |
| - struct acpi_generic_address error_status_address; | |
| - struct acpi_hest_notify notify; | |
| - u32 error_block_length; | |
| -}; | |
| - | |
| -struct acpi_hest_generic_data { | |
| - u8 section_type[16]; | |
| - u32 error_severity; | |
| - u16 revision; | |
| - u8 validation_bits; | |
| - u8 flags; | |
| - u32 error_data_length; | |
| - u8 fru_id[16]; | |
| - u8 fru_text[20]; | |
| -}; | |
| - | |
| -struct acpi_hest_generic_data_v300 { | |
| - u8 section_type[16]; | |
| - u32 error_severity; | |
| - u16 revision; | |
| - u8 validation_bits; | |
| - u8 flags; | |
| - u32 error_data_length; | |
| - u8 fru_id[16]; | |
| - u8 fru_text[20]; | |
| - u64 time_stamp; | |
| -}; | |
| - | |
| -struct acpi_hest_generic_status { | |
| - u32 block_status; | |
| - u32 raw_data_offset; | |
| - u32 raw_data_length; | |
| - u32 data_length; | |
| - u32 error_severity; | |
| -}; | |
| - | |
| -struct acpi_hest_generic_v2 { | |
| - struct acpi_hest_header header; | |
| - u16 related_source_id; | |
| - u8 reserved; | |
| - u8 enabled; | |
| - u32 records_to_preallocate; | |
| - u32 max_sections_per_record; | |
| - u32 max_raw_data_length; | |
| - struct acpi_generic_address error_status_address; | |
| - struct acpi_hest_notify notify; | |
| - u32 error_block_length; | |
| - struct acpi_generic_address read_ack_register; | |
| - u64 read_ack_preserve; | |
| - u64 read_ack_write; | |
| -} __attribute__((packed)); | |
| - | |
| -struct acpi_hest_ia_corrected { | |
| - struct acpi_hest_header header; | |
| - u16 reserved1; | |
| - u8 flags; | |
| - u8 enabled; | |
| - u32 records_to_preallocate; | |
| - u32 max_sections_per_record; | |
| - struct acpi_hest_notify notify; | |
| - u8 num_hardware_banks; | |
| - u8 reserved2[3]; | |
| -}; | |
| - | |
| -struct acpi_hest_ia_deferred_check { | |
| - struct acpi_hest_header header; | |
| - u16 reserved1; | |
| - u8 flags; | |
| - u8 enabled; | |
| - u32 records_to_preallocate; | |
| - u32 max_sections_per_record; | |
| - struct acpi_hest_notify notify; | |
| - u8 num_hardware_banks; | |
| - u8 reserved2[3]; | |
| -}; | |
| - | |
| -struct acpi_hest_ia_error_bank { | |
| - u8 bank_number; | |
| - u8 clear_status_on_init; | |
| - u8 status_format; | |
| - u8 reserved; | |
| - u32 control_register; | |
| - u64 control_data; | |
| - u32 status_register; | |
| - u32 address_register; | |
| - u32 misc_register; | |
| -} __attribute__((packed)); | |
| - | |
| -struct acpi_hest_ia_machine_check { | |
| - struct acpi_hest_header header; | |
| - u16 reserved1; | |
| - u8 flags; | |
| - u8 enabled; | |
| - u32 records_to_preallocate; | |
| - u32 max_sections_per_record; | |
| - u64 global_capability_data; | |
| - u64 global_control_data; | |
| - u8 num_hardware_banks; | |
| - u8 reserved3[7]; | |
| -}; | |
| - | |
| struct acpi_hmat_structure { | |
| u16 type; | |
| u16 reserved; | |
| u32 length; | |
| }; | |
| +typedef int (*acpi_hp_notify)(struct acpi_device *, u32); | |
| + | |
| +typedef void (*acpi_hp_uevent)(struct acpi_device *, u32); | |
| + | |
| +typedef void (*acpi_hp_fixup)(struct acpi_device *); | |
| + | |
| struct acpi_hotplug_context { | |
| struct acpi_device *self; | |
| - int (*notify)(struct acpi_device *, u32); | |
| - void (*uevent)(struct acpi_device *, u32); | |
| - void (*fixup)(struct acpi_device *); | |
| + acpi_hp_notify notify; | |
| + acpi_hp_uevent uevent; | |
| + acpi_hp_fixup fixup; | |
| }; | |
| struct acpi_hotplug_profile { | |
| @@ -30634,7 +40372,7 @@ | |
| acpi_physical_address phys; | |
| acpi_size size; | |
| union { | |
| - unsigned long refcount; | |
| + long unsigned int refcount; | |
| struct rcu_work rwork; | |
| } track; | |
| }; | |
| @@ -30834,6 +40572,18 @@ | |
| u32 global_irq; | |
| }; | |
| +struct acpi_madt_rintc { | |
| + struct acpi_subtable_header header; | |
| + u8 version; | |
| + u8 reserved; | |
| + u32 flags; | |
| + u64 hart_id; | |
| + u32 uid; | |
| + u32 ext_intc_id; | |
| + u64 imsic_addr; | |
| + u32 imsic_size; | |
| +} __attribute__((packed)); | |
| + | |
| struct acpi_mcfg_allocation { | |
| u64 address; | |
| u16 pci_segment; | |
| @@ -31537,19 +41287,6 @@ | |
| u16 function; | |
| }; | |
| -struct resource { | |
| - resource_size_t start; | |
| - resource_size_t end; | |
| - const char *name; | |
| - unsigned long flags; | |
| - unsigned long desc; | |
| - struct resource *parent; | |
| - struct resource *sibling; | |
| - struct resource *child; | |
| -}; | |
| - | |
| -struct pci_dev; | |
| - | |
| struct acpi_pci_ioapic { | |
| acpi_handle root_handle; | |
| acpi_handle handle; | |
| @@ -31776,7 +41513,7 @@ | |
| union acpi_subtable_headers; | |
| -typedef int (*acpi_tbl_entry_handler)(union acpi_subtable_headers *, const unsigned long); | |
| +typedef int (*acpi_tbl_entry_handler)(union acpi_subtable_headers *, const long unsigned int); | |
| struct acpi_probe_entry { | |
| __u8 id[5]; | |
| @@ -31831,12 +41568,6 @@ | |
| u64 num_processors; | |
| }; | |
| -struct cpumask { | |
| - unsigned long bits[8]; | |
| -}; | |
| - | |
| -typedef struct cpumask cpumask_var_t[1]; | |
| - | |
| struct acpi_processor_tx { | |
| u16 power; | |
| u16 performance; | |
| @@ -32422,14 +42153,21 @@ | |
| u32 num_readers; | |
| }; | |
| +struct acpi_s2idle_dev_ops { | |
| + struct list_head list_node; | |
| + void (*prepare)(); | |
| + void (*check)(); | |
| + void (*restore)(); | |
| +}; | |
| + | |
| struct acpi_scan_clear_dep_work { | |
| struct work_struct work; | |
| struct acpi_device *adev; | |
| }; | |
| struct acpi_scan_handler { | |
| - const struct acpi_device_id *ids; | |
| struct list_head list_node; | |
| + const struct acpi_device_id *ids; | |
| bool (*match)(const char *, const struct acpi_device_id **); | |
| int (*attach)(struct acpi_device *, const struct acpi_device_id *); | |
| void (*detach)(struct acpi_device *); | |
| @@ -32470,19 +42208,6 @@ | |
| acpi_object_converter object_converter; | |
| }; | |
| -struct spi_controller; | |
| - | |
| -struct acpi_spi_lookup { | |
| - struct spi_controller *ctlr; | |
| - u32 max_speed_hz; | |
| - u32 mode; | |
| - int irq; | |
| - u8 bits_per_word; | |
| - u8 chip_select; | |
| - int n; | |
| - int index; | |
| -}; | |
| - | |
| struct acpi_srat_cpu_affinity { | |
| struct acpi_subtable_header header; | |
| u8 proximity_domain_lo; | |
| @@ -32537,7 +42262,7 @@ | |
| enum acpi_subtable_type type; | |
| }; | |
| -typedef int (*acpi_tbl_entry_handler_arg)(union acpi_subtable_headers *, void *, const unsigned long); | |
| +typedef int (*acpi_tbl_entry_handler_arg)(union acpi_subtable_headers *, void *, const long unsigned int); | |
| struct acpi_subtable_proc { | |
| int id; | |
| @@ -32626,21 +42351,6 @@ | |
| u8 id[0]; | |
| } __attribute__((packed)); | |
| -struct acpi_table_einj { | |
| - struct acpi_table_header header; | |
| - u32 header_length; | |
| - u8 flags; | |
| - u8 reserved[3]; | |
| - u32 entries; | |
| -}; | |
| - | |
| -struct acpi_table_erst { | |
| - struct acpi_table_header header; | |
| - u32 header_length; | |
| - u32 reserved; | |
| - u32 entries; | |
| -}; | |
| - | |
| struct acpi_table_facs { | |
| char signature[4]; | |
| u32 length; | |
| @@ -32714,11 +42424,6 @@ | |
| u64 hypervisor_id; | |
| } __attribute__((packed)); | |
| -struct acpi_table_hest { | |
| - struct acpi_table_header header; | |
| - u32 error_source_count; | |
| -}; | |
| - | |
| struct acpi_table_hpet { | |
| struct acpi_table_header header; | |
| u32 id; | |
| @@ -32771,7 +42476,7 @@ | |
| struct acpi_table_slit { | |
| struct acpi_table_header header; | |
| u64 locality_count; | |
| - u8 entry[1]; | |
| + u8 entry[0]; | |
| } __attribute__((packed)); | |
| struct acpi_table_spcr { | |
| @@ -32837,55 +42542,23 @@ | |
| }; | |
| }; | |
| -struct acpi_thermal_flags { | |
| - u8 cooling_mode: 1; | |
| - u8 devices: 1; | |
| - u8 reserved: 6; | |
| -}; | |
| - | |
| -struct acpi_thermal_state { | |
| - u8 critical: 1; | |
| - u8 hot: 1; | |
| - u8 passive: 1; | |
| - u8 active: 1; | |
| - u8 reserved: 4; | |
| - int active_index; | |
| -}; | |
| - | |
| -struct acpi_thermal_state_flags { | |
| - u8 valid: 1; | |
| - u8 enabled: 1; | |
| - u8 reserved: 6; | |
| -}; | |
| - | |
| -struct acpi_thermal_critical { | |
| - struct acpi_thermal_state_flags flags; | |
| - unsigned long temperature; | |
| -}; | |
| - | |
| -struct acpi_thermal_hot { | |
| - struct acpi_thermal_state_flags flags; | |
| - unsigned long temperature; | |
| +struct acpi_thermal_trip { | |
| + long unsigned int temp_dk; | |
| + struct acpi_handle_list devices; | |
| }; | |
| struct acpi_thermal_passive { | |
| - struct acpi_thermal_state_flags flags; | |
| - unsigned long temperature; | |
| - unsigned long tc1; | |
| - unsigned long tc2; | |
| - unsigned long tsp; | |
| - struct acpi_handle_list devices; | |
| + struct acpi_thermal_trip trip; | |
| + long unsigned int tc1; | |
| + long unsigned int tc2; | |
| + long unsigned int delay; | |
| }; | |
| struct acpi_thermal_active { | |
| - struct acpi_thermal_state_flags flags; | |
| - unsigned long temperature; | |
| - struct acpi_handle_list devices; | |
| + struct acpi_thermal_trip trip; | |
| }; | |
| struct acpi_thermal_trips { | |
| - struct acpi_thermal_critical critical; | |
| - struct acpi_thermal_hot hot; | |
| struct acpi_thermal_passive passive; | |
| struct acpi_thermal_active active[10]; | |
| }; | |
| @@ -32895,14 +42568,11 @@ | |
| struct acpi_thermal { | |
| struct acpi_device *device; | |
| acpi_bus_id name; | |
| - unsigned long temperature; | |
| - unsigned long last_temperature; | |
| - unsigned long polling_frequency; | |
| + long unsigned int temp_dk; | |
| + long unsigned int last_temp_dk; | |
| + long unsigned int polling_frequency; | |
| volatile u8 zombie; | |
| - struct acpi_thermal_flags flags; | |
| - struct acpi_thermal_state state; | |
| struct acpi_thermal_trips trips; | |
| - struct acpi_handle_list devices; | |
| struct thermal_zone_device *thermal_zone; | |
| int kelvin_offset; | |
| struct work_struct thermal_check_work; | |
| @@ -32910,6 +42580,12 @@ | |
| refcount_t thermal_check_count; | |
| }; | |
| +struct acpi_thermal_bind_data { | |
| + struct thermal_zone_device *thermal; | |
| + struct thermal_cooling_device *cdev; | |
| + bool bind; | |
| +}; | |
| + | |
| struct acpi_thread_state { | |
| void *next; | |
| u8 descriptor_type; | |
| @@ -33013,26 +42689,6 @@ | |
| acpi_parse_upwards ascending_callback; | |
| }; | |
| -struct acpi_whea_header { | |
| - u8 action; | |
| - u8 instruction; | |
| - u8 flags; | |
| - u8 reserved; | |
| - struct acpi_generic_address register_region; | |
| - u64 value; | |
| - u64 mask; | |
| -}; | |
| - | |
| -struct acpihid_map_entry { | |
| - struct list_head list; | |
| - u8 uid[256]; | |
| - u8 hid[9]; | |
| - u32 devid; | |
| - u32 root_devid; | |
| - bool cmd_line; | |
| - struct iommu_group *group; | |
| -}; | |
| - | |
| struct pnp_dev; | |
| struct acpipnp_parse_option_s { | |
| @@ -33041,8 +42697,8 @@ | |
| }; | |
| struct action_cache { | |
| - unsigned long allow_native[8]; | |
| - unsigned long allow_compat[8]; | |
| + long unsigned int allow_native[8]; | |
| + long unsigned int allow_compat[8]; | |
| }; | |
| struct action_devres { | |
| @@ -33057,154 +42713,16 @@ | |
| s32 maxoctets; | |
| }; | |
| -struct mac_addr { | |
| - u8 mac_addr_value[6]; | |
| -}; | |
| - | |
| -struct ad_system { | |
| - u16 sys_priority; | |
| - struct mac_addr sys_mac_addr; | |
| -}; | |
| - | |
| -struct bond_3ad_stats { | |
| - atomic64_t lacpdu_rx; | |
| - atomic64_t lacpdu_tx; | |
| - atomic64_t lacpdu_unknown_rx; | |
| - atomic64_t lacpdu_illegal_rx; | |
| - atomic64_t marker_rx; | |
| - atomic64_t marker_tx; | |
| - atomic64_t marker_resp_rx; | |
| - atomic64_t marker_resp_tx; | |
| - atomic64_t marker_unknown_rx; | |
| -}; | |
| - | |
| -struct ad_bond_info { | |
| - struct ad_system system; | |
| - struct bond_3ad_stats stats; | |
| - atomic_t agg_select_timer; | |
| - u16 aggregator_identifier; | |
| -}; | |
| - | |
| -struct port; | |
| - | |
| -struct slave; | |
| - | |
| -struct aggregator { | |
| - struct mac_addr aggregator_mac_address; | |
| - u16 aggregator_identifier; | |
| - bool is_individual; | |
| - u16 actor_admin_aggregator_key; | |
| - u16 actor_oper_aggregator_key; | |
| - struct mac_addr partner_system; | |
| - u16 partner_system_priority; | |
| - u16 partner_oper_aggregator_key; | |
| - u16 receive_state; | |
| - u16 transmit_state; | |
| - struct port *lag_ports; | |
| - struct slave *slave; | |
| - u16 is_active; | |
| - u16 num_of_ports; | |
| -}; | |
| - | |
| -struct port_params { | |
| - struct mac_addr system; | |
| - u16 system_priority; | |
| - u16 key; | |
| - u16 port_number; | |
| - u16 port_priority; | |
| - u16 port_state; | |
| -}; | |
| - | |
| -struct lacpdu { | |
| - u8 subtype; | |
| - u8 version_number; | |
| - u8 tlv_type_actor_info; | |
| - u8 actor_information_length; | |
| - __be16 actor_system_priority; | |
| - struct mac_addr actor_system; | |
| - __be16 actor_key; | |
| - __be16 actor_port_priority; | |
| - __be16 actor_port; | |
| - u8 actor_state; | |
| - u8 reserved_3_1[3]; | |
| - u8 tlv_type_partner_info; | |
| - u8 partner_information_length; | |
| - __be16 partner_system_priority; | |
| - struct mac_addr partner_system; | |
| - __be16 partner_key; | |
| - __be16 partner_port_priority; | |
| - __be16 partner_port; | |
| - u8 partner_state; | |
| - u8 reserved_3_2[3]; | |
| - u8 tlv_type_collector_info; | |
| - u8 collector_information_length; | |
| - __be16 collector_max_delay; | |
| - u8 reserved_12[12]; | |
| - u8 tlv_type_terminator; | |
| - u8 terminator_length; | |
| - u8 reserved_50[50]; | |
| -}; | |
| - | |
| -struct port { | |
| - u16 actor_port_number; | |
| - u16 actor_port_priority; | |
| - struct mac_addr actor_system; | |
| - u16 actor_system_priority; | |
| - u16 actor_port_aggregator_identifier; | |
| - bool ntt; | |
| - u16 actor_admin_port_key; | |
| - u16 actor_oper_port_key; | |
| - u8 actor_admin_port_state; | |
| - u8 actor_oper_port_state; | |
| - struct port_params partner_admin; | |
| - struct port_params partner_oper; | |
| - bool is_enabled; | |
| - u16 sm_vars; | |
| - rx_states_t sm_rx_state; | |
| - u16 sm_rx_timer_counter; | |
| - periodic_states_t sm_periodic_state; | |
| - u16 sm_periodic_timer_counter; | |
| - mux_states_t sm_mux_state; | |
| - u16 sm_mux_timer_counter; | |
| - tx_states_t sm_tx_state; | |
| - u16 sm_tx_timer_counter; | |
| - u16 sm_churn_actor_timer_counter; | |
| - u16 sm_churn_partner_timer_counter; | |
| - u32 churn_actor_count; | |
| - u32 churn_partner_count; | |
| - churn_state_t sm_churn_actor_state; | |
| - churn_state_t sm_churn_partner_state; | |
| - struct slave *slave; | |
| - struct aggregator *aggregator; | |
| - struct port *next_port_in_aggregator; | |
| - u32 transaction_id; | |
| - struct lacpdu lacpdu; | |
| -}; | |
| - | |
| -struct ad_slave_info { | |
| - struct aggregator aggregator; | |
| - struct port port; | |
| - struct bond_3ad_stats stats; | |
| - u16 id; | |
| -}; | |
| - | |
| -struct addr_ctx { | |
| - u64 ret_addr; | |
| - u32 tmp; | |
| - u16 nid; | |
| - u8 inst_id; | |
| -}; | |
| - | |
| struct rw_semaphore { | |
| atomic_long_t count; | |
| atomic_long_t owner; | |
| struct optimistic_spin_queue osq; | |
| raw_spinlock_t wait_lock; | |
| struct list_head wait_list; | |
| + void *magic; | |
| + struct lockdep_map dep_map; | |
| }; | |
| -struct rb_node; | |
| - | |
| struct rb_root { | |
| struct rb_node *rb_node; | |
| }; | |
| @@ -33222,21 +42740,18 @@ | |
| struct rw_semaphore invalidate_lock; | |
| gfp_t gfp_mask; | |
| atomic_t i_mmap_writable; | |
| - atomic_t nr_thps; | |
| struct rb_root_cached i_mmap; | |
| - struct rw_semaphore i_mmap_rwsem; | |
| - unsigned long nrpages; | |
| - unsigned long writeback_index; | |
| + long unsigned int nrpages; | |
| + long unsigned int writeback_index; | |
| const struct address_space_operations *a_ops; | |
| - unsigned long flags; | |
| + long unsigned int flags; | |
| errseq_t wb_err; | |
| - spinlock_t private_lock; | |
| - struct list_head private_list; | |
| - void *private_data; | |
| + spinlock_t i_private_lock; | |
| + struct list_head i_private_list; | |
| + struct rw_semaphore i_mmap_rwsem; | |
| + void *i_private_data; | |
| }; | |
| -struct page; | |
| - | |
| struct writeback_control; | |
| struct folio; | |
| @@ -33266,12 +42781,24 @@ | |
| int (*launder_folio)(struct folio *); | |
| bool (*is_partially_uptodate)(struct folio *, size_t, size_t); | |
| void (*is_dirty_writeback)(struct folio *, bool *, bool *); | |
| - int (*error_remove_page)(struct address_space *, struct page *); | |
| + int (*error_remove_folio)(struct address_space *, struct folio *); | |
| int (*swap_activate)(struct swap_info_struct *, struct file *, sector_t *); | |
| void (*swap_deactivate)(struct file *); | |
| int (*swap_rw)(struct kiocb *, struct iov_iter *); | |
| }; | |
| +struct adjust_trip_data { | |
| + struct acpi_thermal *tz; | |
| + u32 event; | |
| +}; | |
| + | |
| +struct advisor_ctx { | |
| + ktime_t start_scan; | |
| + long unsigned int scan_time; | |
| + long unsigned int change; | |
| + long long unsigned int cpu_time; | |
| +}; | |
| + | |
| struct crypto_aead; | |
| struct aead_request; | |
| @@ -33289,6 +42816,17 @@ | |
| struct crypto_alg base; | |
| }; | |
| +struct crypto_engine; | |
| + | |
| +struct crypto_engine_op { | |
| + int (*do_one_request)(struct crypto_engine *, void *); | |
| +}; | |
| + | |
| +struct aead_engine_alg { | |
| + struct aead_alg base; | |
| + struct crypto_engine_op op; | |
| +}; | |
| + | |
| struct crypto_sync_skcipher; | |
| struct aead_geniv_ctx { | |
| @@ -33309,6 +42847,7 @@ | |
| struct hlist_node list; | |
| struct crypto_spawn *spawns; | |
| }; | |
| + struct work_struct free_work; | |
| void *__ctx[0]; | |
| }; | |
| @@ -33323,30 +42862,6 @@ | |
| }; | |
| }; | |
| -struct crypto_spawn { | |
| - struct list_head list; | |
| - struct crypto_alg *alg; | |
| - union { | |
| - struct crypto_instance *inst; | |
| - struct crypto_spawn *next; | |
| - }; | |
| - const struct crypto_type *frontend; | |
| - u32 mask; | |
| - bool dead; | |
| - bool registered; | |
| -}; | |
| - | |
| -struct crypto_aead_spawn { | |
| - struct crypto_spawn base; | |
| -}; | |
| - | |
| -struct cryptd_queue; | |
| - | |
| -struct aead_instance_ctx { | |
| - struct crypto_aead_spawn aead_spawn; | |
| - struct cryptd_queue *queue; | |
| -}; | |
| - | |
| struct aead_request { | |
| struct crypto_async_request base; | |
| unsigned int assoclen; | |
| @@ -33357,105 +42872,14 @@ | |
| void *__ctx[0]; | |
| }; | |
| -struct aer_header_log_regs { | |
| - unsigned int dw0; | |
| - unsigned int dw1; | |
| - unsigned int dw2; | |
| - unsigned int dw3; | |
| -}; | |
| - | |
| -struct aer_capability_regs { | |
| - u32 header; | |
| - u32 uncor_status; | |
| - u32 uncor_mask; | |
| - u32 uncor_severity; | |
| - u32 cor_status; | |
| - u32 cor_mask; | |
| - u32 cap_control; | |
| - struct aer_header_log_regs header_log; | |
| - u32 root_command; | |
| - u32 root_status; | |
| - u16 cor_err_source; | |
| - u16 uncor_err_source; | |
| -}; | |
| - | |
| -struct aer_err_info { | |
| - struct pci_dev *dev[5]; | |
| - int error_dev_num; | |
| - unsigned int id: 16; | |
| - unsigned int severity: 2; | |
| - unsigned int __pad1: 5; | |
| - unsigned int multi_error_valid: 1; | |
| - unsigned int first_error: 5; | |
| - unsigned int __pad2: 2; | |
| - unsigned int tlp_header_valid: 1; | |
| - unsigned int status; | |
| - unsigned int mask; | |
| - struct aer_header_log_regs tlp; | |
| -}; | |
| - | |
| -struct aer_err_source { | |
| - unsigned int status; | |
| - unsigned int id; | |
| -}; | |
| - | |
| -struct aer_recover_entry { | |
| - u8 bus; | |
| - u8 devfn; | |
| - u16 domain; | |
| - int severity; | |
| - struct aer_capability_regs *regs; | |
| -}; | |
| - | |
| -struct aer_rpc { | |
| - struct pci_dev *rpd; | |
| - struct { | |
| - union { | |
| - struct __kfifo kfifo; | |
| - struct aer_err_source *type; | |
| - const struct aer_err_source *const_type; | |
| - char (*rectype)[0]; | |
| - struct aer_err_source *ptr; | |
| - const struct aer_err_source *ptr_const; | |
| - }; | |
| - struct aer_err_source buf[128]; | |
| - } aer_fifo; | |
| -}; | |
| - | |
| -struct aer_stats { | |
| - u64 dev_cor_errs[16]; | |
| - u64 dev_fatal_errs[27]; | |
| - u64 dev_nonfatal_errs[27]; | |
| - u64 dev_total_cor_errs; | |
| - u64 dev_total_fatal_errs; | |
| - u64 dev_total_nonfatal_errs; | |
| - u64 rootport_total_cor_errs; | |
| - u64 rootport_total_fatal_errs; | |
| - u64 rootport_total_nonfatal_errs; | |
| -}; | |
| - | |
| -struct crypto_aes_ctx { | |
| - u32 key_enc[60]; | |
| - u32 key_dec[60]; | |
| - u32 key_length; | |
| -}; | |
| - | |
| -struct aesni_rfc4106_gcm_ctx { | |
| - u8 hash_subkey[16]; | |
| - struct crypto_aes_ctx aes_key_expanded; | |
| - u8 nonce[4]; | |
| - long: 64; | |
| -}; | |
| - | |
| -struct aesni_xts_ctx { | |
| - u8 raw_tweak_ctx[484]; | |
| - long: 64; | |
| - u8 raw_crypt_ctx[484]; | |
| - long: 64; | |
| +struct sg_table { | |
| + struct scatterlist *sgl; | |
| + unsigned int nents; | |
| + unsigned int orig_nents; | |
| }; | |
| struct scatterlist { | |
| - unsigned long page_link; | |
| + long unsigned int page_link; | |
| unsigned int offset; | |
| unsigned int length; | |
| dma_addr_t dma_address; | |
| @@ -33464,9 +42888,9 @@ | |
| }; | |
| struct af_alg_sgl { | |
| - struct scatterlist sg[17]; | |
| - struct page *pages[16]; | |
| - unsigned int npages; | |
| + struct sg_table sgt; | |
| + struct scatterlist sgl[17]; | |
| + bool need_unpin; | |
| }; | |
| struct af_alg_rsgl { | |
| @@ -33518,6 +42942,7 @@ | |
| struct af_alg_ctx { | |
| struct list_head tsgl_list; | |
| void *iv; | |
| + void *state; | |
| size_t aead_assoclen; | |
| struct crypto_wait wait; | |
| size_t used; | |
| @@ -33527,6 +42952,7 @@ | |
| bool enc; | |
| bool init; | |
| unsigned int len; | |
| + unsigned int inflight; | |
| }; | |
| struct af_alg_iv { | |
| @@ -33543,7 +42969,7 @@ | |
| typedef struct { | |
| union { | |
| void *kernel; | |
| - void __attribute__((btf_type_tag("user"))) *user; | |
| + void *user; | |
| }; | |
| bool is_kernel: 1; | |
| } sockptr_t; | |
| @@ -33593,14 +43019,124 @@ | |
| struct component_match *match; | |
| }; | |
| -struct aghdr_init_data { | |
| - xfs_agblock_t agno; | |
| - xfs_extlen_t agsize; | |
| - struct list_head buffer_list; | |
| - xfs_rfsblock_t nfree; | |
| - xfs_daddr_t daddr; | |
| - size_t numblks; | |
| - xfs_btnum_t type; | |
| +struct agp_3_5_dev { | |
| + struct list_head list; | |
| + u8 capndx; | |
| + u32 maxbw; | |
| + struct pci_dev *dev; | |
| +}; | |
| + | |
| +struct agp_version; | |
| + | |
| +struct agp_bridge_driver; | |
| + | |
| +struct vm_operations_struct; | |
| + | |
| +struct agp_bridge_data { | |
| + const struct agp_version *version; | |
| + const struct agp_bridge_driver *driver; | |
| + const struct vm_operations_struct *vm_ops; | |
| + void *previous_size; | |
| + void *current_size; | |
| + void *dev_private_data; | |
| + struct pci_dev *dev; | |
| + u32 *gatt_table; | |
| + u32 *gatt_table_real; | |
| + long unsigned int scratch_page; | |
| + struct page *scratch_page_page; | |
| + dma_addr_t scratch_page_dma; | |
| + long unsigned int gart_bus_addr; | |
| + long unsigned int gatt_bus_addr; | |
| + u32 mode; | |
| + long unsigned int *key_list; | |
| + atomic_t current_memory_agp; | |
| + atomic_t agp_in_use; | |
| + int max_memory_agp; | |
| + int aperture_size_idx; | |
| + int capndx; | |
| + int flags; | |
| + char major_version; | |
| + char minor_version; | |
| + struct list_head list; | |
| + u32 apbase_config; | |
| + struct list_head mapped_list; | |
| + spinlock_t mapped_lock; | |
| +}; | |
| + | |
| +struct gatt_mask; | |
| + | |
| +struct agp_memory; | |
| + | |
| +struct agp_bridge_driver { | |
| + struct module *owner; | |
| + const void *aperture_sizes; | |
| + int num_aperture_sizes; | |
| + enum aper_size_type size_type; | |
| + bool cant_use_aperture; | |
| + bool needs_scratch_page; | |
| + const struct gatt_mask *masks; | |
| + int (*fetch_size)(); | |
| + int (*configure)(); | |
| + void (*agp_enable)(struct agp_bridge_data *, u32); | |
| + void (*cleanup)(); | |
| + void (*tlb_flush)(struct agp_memory *); | |
| + long unsigned int (*mask_memory)(struct agp_bridge_data *, dma_addr_t, int); | |
| + void (*cache_flush)(); | |
| + int (*create_gatt_table)(struct agp_bridge_data *); | |
| + int (*free_gatt_table)(struct agp_bridge_data *); | |
| + int (*insert_memory)(struct agp_memory *, off_t, int); | |
| + int (*remove_memory)(struct agp_memory *, off_t, int); | |
| + struct agp_memory * (*alloc_by_type)(size_t, int); | |
| + void (*free_by_type)(struct agp_memory *); | |
| + struct page * (*agp_alloc_page)(struct agp_bridge_data *); | |
| + int (*agp_alloc_pages)(struct agp_bridge_data *, struct agp_memory *, size_t); | |
| + void (*agp_destroy_page)(struct page *, int); | |
| + void (*agp_destroy_pages)(struct agp_memory *); | |
| + int (*agp_type_to_mask_type)(struct agp_bridge_data *, int); | |
| +}; | |
| + | |
| +struct agp_device_ids { | |
| + short unsigned int device_id; | |
| + enum chipset_type chipset; | |
| + const char *chipset_name; | |
| + int (*chipset_setup)(struct pci_dev *); | |
| +}; | |
| + | |
| +struct agp_version { | |
| + u16 major; | |
| + u16 minor; | |
| +}; | |
| + | |
| +struct agp_kern_info { | |
| + struct agp_version version; | |
| + struct pci_dev *device; | |
| + enum chipset_type chipset; | |
| + long unsigned int mode; | |
| + long unsigned int aper_base; | |
| + size_t aper_size; | |
| + int max_memory; | |
| + int current_memory; | |
| + bool cant_use_aperture; | |
| + long unsigned int page_mask; | |
| + const struct vm_operations_struct *vm_ops; | |
| +}; | |
| + | |
| +struct agp_memory { | |
| + struct agp_memory *next; | |
| + struct agp_memory *prev; | |
| + struct agp_bridge_data *bridge; | |
| + struct page **pages; | |
| + size_t page_count; | |
| + int key; | |
| + int num_scratch_pages; | |
| + off_t pg_start; | |
| + u32 type; | |
| + u32 physical; | |
| + bool is_bound; | |
| + bool is_flushed; | |
| + struct list_head mapped_list; | |
| + struct scatterlist *sg_list; | |
| + int num_sg; | |
| }; | |
| struct hash_alg_common { | |
| @@ -33628,6 +43164,11 @@ | |
| struct hash_alg_common halg; | |
| }; | |
| +struct ahash_engine_alg { | |
| + struct ahash_alg base; | |
| + struct crypto_engine_op op; | |
| +}; | |
| + | |
| struct ahash_instance { | |
| void (*free)(struct ahash_instance *); | |
| union { | |
| @@ -33648,6 +43189,234 @@ | |
| void *__ctx[0]; | |
| }; | |
| +struct ahc_aic7770_softc { | |
| + uint8_t busspd; | |
| + uint8_t bustime; | |
| +}; | |
| + | |
| +struct ahc_devinfo { | |
| + int our_scsiid; | |
| + int target_offset; | |
| + uint16_t target_mask; | |
| + u_int target; | |
| + u_int lun; | |
| + char channel; | |
| + role_t role; | |
| +}; | |
| + | |
| +struct ahc_dma_seg { | |
| + uint32_t addr; | |
| + uint32_t len; | |
| +}; | |
| + | |
| +struct ahc_hard_error_entry { | |
| + uint8_t errno; | |
| + const char *errmesg; | |
| +}; | |
| + | |
| +struct ahc_transinfo { | |
| + uint8_t protocol_version; | |
| + uint8_t transport_version; | |
| + uint8_t width; | |
| + uint8_t period; | |
| + uint8_t offset; | |
| + uint8_t ppr_options; | |
| +}; | |
| + | |
| +struct ahc_initiator_tinfo { | |
| + uint8_t scsirate; | |
| + struct ahc_transinfo curr; | |
| + struct ahc_transinfo goal; | |
| + struct ahc_transinfo user; | |
| +}; | |
| + | |
| +struct ahc_linux_device { | |
| + int active; | |
| + int openings; | |
| + u_int qfrozen; | |
| + u_long commands_issued; | |
| + u_int tag_success_count; | |
| + ahc_linux_dev_flags flags; | |
| + u_int maxtags; | |
| + u_int tags_on_last_queuefull; | |
| + u_int last_queuefull_same_count; | |
| + u_int commands_since_idle_or_otag; | |
| +}; | |
| + | |
| +struct ahc_linux_dma_tag { | |
| + bus_size_t alignment; | |
| + bus_size_t boundary; | |
| + bus_size_t maxsize; | |
| +}; | |
| + | |
| +typedef struct ahc_linux_dma_tag *bus_dma_tag_t; | |
| + | |
| +struct ahc_softc; | |
| + | |
| +typedef int ahc_device_setup_t(struct ahc_softc *); | |
| + | |
| +struct ahc_pci_identity { | |
| + uint64_t full_id; | |
| + uint64_t id_mask; | |
| + const char *name; | |
| + ahc_device_setup_t *setup; | |
| +}; | |
| + | |
| +struct ahc_pci_softc { | |
| + uint32_t devconfig; | |
| + uint16_t targcrccnt; | |
| + uint8_t command; | |
| + uint8_t csize_lattime; | |
| + uint8_t optionmode; | |
| + uint8_t crccontrol1; | |
| + uint8_t dscommand0; | |
| + uint8_t dspcistatus; | |
| + uint8_t scbbaddr; | |
| + uint8_t dff_thrsh; | |
| +}; | |
| + | |
| +struct ahc_phase_table_entry { | |
| + uint8_t phase; | |
| + uint8_t mesg_out; | |
| + char *phasemsg; | |
| +}; | |
| + | |
| +struct ahc_platform_data { | |
| + struct scsi_target *starget[16]; | |
| + spinlock_t spin_lock; | |
| + u_int qfrozen; | |
| + struct completion *eh_done; | |
| + struct Scsi_Host *host; | |
| + uint32_t irq; | |
| + uint32_t bios_address; | |
| + resource_size_t mem_busaddr; | |
| +}; | |
| + | |
| +struct ahc_reg_parse_entry { | |
| + char *name; | |
| + uint8_t value; | |
| + uint8_t mask; | |
| +}; | |
| + | |
| +typedef struct ahc_reg_parse_entry ahc_reg_parse_entry_t; | |
| + | |
| +typedef union { | |
| + u_long ioport; | |
| + volatile uint8_t *maddr; | |
| +} bus_space_handle_t; | |
| + | |
| +struct scb; | |
| + | |
| +struct scb_tailq { | |
| + struct scb *tqh_first; | |
| + struct scb **tqh_last; | |
| +}; | |
| + | |
| +union ahc_bus_softc { | |
| + struct ahc_aic7770_softc aic7770_softc; | |
| + struct ahc_pci_softc pci_softc; | |
| +}; | |
| + | |
| +typedef struct pci_dev *ahc_dev_softc_t; | |
| + | |
| +typedef void (*ahc_bus_intr_t)(struct ahc_softc *); | |
| + | |
| +typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *); | |
| + | |
| +struct ahc_tmode_lstate; | |
| + | |
| +struct scb_data; | |
| + | |
| +struct ahc_tmode_tstate; | |
| + | |
| +struct seeprom_config; | |
| + | |
| +struct cs; | |
| + | |
| +struct target_cmd; | |
| + | |
| +struct ahc_softc { | |
| + bus_space_tag_t tag; | |
| + bus_space_handle_t bsh; | |
| + struct scb_data *scb_data; | |
| + struct scb *next_queued_scb; | |
| + struct { | |
| + struct scb *lh_first; | |
| + } pending_scbs; | |
| + u_int untagged_queue_lock; | |
| + struct scb_tailq untagged_queues[16]; | |
| + union ahc_bus_softc bus_softc; | |
| + struct ahc_platform_data *platform_data; | |
| + ahc_dev_softc_t dev_softc; | |
| + struct device *dev; | |
| + ahc_bus_intr_t bus_intr; | |
| + ahc_bus_chip_init_t bus_chip_init; | |
| + struct ahc_tmode_tstate *enabled_targets[16]; | |
| + struct ahc_tmode_lstate *black_hole; | |
| + struct ahc_tmode_lstate *pending_device; | |
| + ahc_chip chip; | |
| + ahc_feature features; | |
| + ahc_bug bugs; | |
| + ahc_flag flags; | |
| + struct seeprom_config *seep_config; | |
| + uint8_t unpause; | |
| + uint8_t pause; | |
| + uint8_t qoutfifonext; | |
| + uint8_t qinfifonext; | |
| + uint8_t *qoutfifo; | |
| + uint8_t *qinfifo; | |
| + struct cs *critical_sections; | |
| + u_int num_critical_sections; | |
| + char channel; | |
| + char channel_b; | |
| + uint8_t our_id; | |
| + uint8_t our_id_b; | |
| + int unsolicited_ints; | |
| + struct target_cmd *targetcmds; | |
| + uint8_t tqinfifonext; | |
| + uint8_t seqctl; | |
| + uint8_t send_msg_perror; | |
| + ahc_msg_type msg_type; | |
| + uint8_t msgout_buf[12]; | |
| + uint8_t msgin_buf[12]; | |
| + u_int msgout_len; | |
| + u_int msgout_index; | |
| + u_int msgin_index; | |
| + bus_dma_tag_t parent_dmat; | |
| + bus_dma_tag_t shared_data_dmat; | |
| + bus_dmamap_t shared_data_dmamap; | |
| + dma_addr_t shared_data_busaddr; | |
| + dma_addr_t dma_bug_buf; | |
| + u_int enabled_luns; | |
| + u_int init_level; | |
| + u_int pci_cachesize; | |
| + u_int pci_target_perr_count; | |
| + u_int instruction_ram_size; | |
| + const char *description; | |
| + char *name; | |
| + int unit; | |
| + int seltime; | |
| + int seltime_b; | |
| + uint16_t user_discenable; | |
| + uint16_t user_tagenable; | |
| +}; | |
| + | |
| +struct ahc_syncrate { | |
| + u_int sxfr_u2; | |
| + u_int sxfr; | |
| + uint8_t period; | |
| + const char *rate; | |
| +}; | |
| + | |
| +struct ahc_tmode_tstate { | |
| + struct ahc_tmode_lstate *enabled_luns[64]; | |
| + struct ahc_initiator_tinfo transinfo[16]; | |
| + uint16_t auto_negotiate; | |
| + uint16_t ultraenb; | |
| + uint16_t discenable; | |
| + uint16_t tagenable; | |
| +}; | |
| + | |
| struct ahci_cmd_hdr { | |
| __le32 opts; | |
| __le32 status; | |
| @@ -33661,9 +43430,9 @@ | |
| struct ahci_em_priv { | |
| enum sw_activity blink_policy; | |
| struct timer_list timer; | |
| - unsigned long saved_activity; | |
| - unsigned long activity; | |
| - unsigned long led_state; | |
| + long unsigned int saved_activity; | |
| + long unsigned int activity; | |
| + long unsigned int led_state; | |
| struct ata_link *link; | |
| }; | |
| @@ -33740,16 +43509,307 @@ | |
| __le32 flags_size; | |
| }; | |
| +struct ahd_completion { | |
| + uint16_t tag; | |
| + uint8_t sg_status; | |
| + uint8_t valid_tag; | |
| +}; | |
| + | |
| +struct ahd_devinfo { | |
| + int our_scsiid; | |
| + int target_offset; | |
| + uint16_t target_mask; | |
| + u_int target; | |
| + u_int lun; | |
| + char channel; | |
| + role_t role; | |
| +}; | |
| + | |
| +struct ahd_dma64_seg { | |
| + uint64_t addr; | |
| + uint32_t len; | |
| + uint32_t pad; | |
| +}; | |
| + | |
| +struct ahd_dma_seg { | |
| + uint32_t addr; | |
| + uint32_t len; | |
| +}; | |
| + | |
| +struct ahd_hard_error_entry { | |
| + uint8_t errno; | |
| + const char *errmesg; | |
| +}; | |
| + | |
| +struct ahd_transinfo { | |
| + uint8_t protocol_version; | |
| + uint8_t transport_version; | |
| + uint8_t width; | |
| + uint8_t period; | |
| + uint8_t offset; | |
| + uint8_t ppr_options; | |
| +}; | |
| + | |
| +struct ahd_initiator_tinfo { | |
| + struct ahd_transinfo curr; | |
| + struct ahd_transinfo goal; | |
| + struct ahd_transinfo user; | |
| +}; | |
| + | |
| +struct ahd_linux_device { | |
| + struct { | |
| + struct ahd_linux_device *tqe_next; | |
| + struct ahd_linux_device **tqe_prev; | |
| + } links; | |
| + int active; | |
| + int openings; | |
| + u_int qfrozen; | |
| + u_long commands_issued; | |
| + u_int tag_success_count; | |
| + ahd_linux_dev_flags flags; | |
| + struct timer_list timer; | |
| + u_int maxtags; | |
| + u_int tags_on_last_queuefull; | |
| + u_int last_queuefull_same_count; | |
| + u_int commands_since_idle_or_otag; | |
| +}; | |
| + | |
| +struct ahd_linux_dma_tag { | |
| + bus_size_t alignment; | |
| + bus_size_t boundary; | |
| + bus_size_t maxsize; | |
| +}; | |
| + | |
| +typedef struct ahd_linux_dma_tag *bus_dma_tag_t___2; | |
| + | |
| +struct ahd_linux_iocell_opts { | |
| + uint8_t precomp; | |
| + uint8_t slewrate; | |
| + uint8_t amplitude; | |
| +}; | |
| + | |
| +struct ahd_softc; | |
| + | |
| +typedef int ahd_device_setup_t(struct ahd_softc *); | |
| + | |
| +struct ahd_pci_identity { | |
| + uint64_t full_id; | |
| + uint64_t id_mask; | |
| + const char *name; | |
| + ahd_device_setup_t *setup; | |
| +}; | |
| + | |
| +struct ahd_phase_table_entry { | |
| + uint8_t phase; | |
| + uint8_t mesg_out; | |
| + const char *phasemsg; | |
| +}; | |
| + | |
| +struct ahd_platform_data { | |
| + struct scsi_target *starget[16]; | |
| + spinlock_t spin_lock; | |
| + struct completion *eh_done; | |
| + struct Scsi_Host *host; | |
| + uint32_t irq; | |
| + uint32_t bios_address; | |
| + resource_size_t mem_busaddr; | |
| +}; | |
| + | |
| +struct ahd_reg_parse_entry { | |
| + char *name; | |
| + uint8_t value; | |
| + uint8_t mask; | |
| +}; | |
| + | |
| +typedef struct ahd_reg_parse_entry ahd_reg_parse_entry_t; | |
| + | |
| +struct scb___2; | |
| + | |
| +struct scb_tailq___2 { | |
| + struct scb___2 *tqh_first; | |
| + struct scb___2 **tqh_last; | |
| +}; | |
| + | |
| +struct scb_list { | |
| + struct scb___2 *lh_first; | |
| +}; | |
| + | |
| +struct map_node; | |
| + | |
| +struct scb_data___2 { | |
| + struct scb_tailq___2 free_scbs; | |
| + struct scb_list free_scb_lists[1024]; | |
| + struct scb_list any_dev_free_scb_list; | |
| + struct scb___2 *scbindex[512]; | |
| + bus_dma_tag_t___2 hscb_dmat; | |
| + bus_dma_tag_t___2 sg_dmat; | |
| + bus_dma_tag_t___2 sense_dmat; | |
| + struct { | |
| + struct map_node *slh_first; | |
| + } hscb_maps; | |
| + struct { | |
| + struct map_node *slh_first; | |
| + } sg_maps; | |
| + struct { | |
| + struct map_node *slh_first; | |
| + } sense_maps; | |
| + int scbs_left; | |
| + int sgs_left; | |
| + int sense_left; | |
| + uint16_t numscbs; | |
| + uint16_t maxhscbs; | |
| + uint8_t init_level; | |
| +}; | |
| + | |
| +typedef struct pci_dev *ahd_dev_softc_t; | |
| + | |
| +typedef void (*ahd_bus_intr_t)(struct ahd_softc *); | |
| + | |
| +struct ahd_tmode_lstate; | |
| + | |
| +struct map_node { | |
| + bus_dmamap_t dmamap; | |
| + dma_addr_t physaddr; | |
| + uint8_t *vaddr; | |
| + struct { | |
| + struct map_node *sle_next; | |
| + } links; | |
| +}; | |
| + | |
| +struct ahd_suspend_channel_state { | |
| + uint8_t scsiseq; | |
| + uint8_t sxfrctl0; | |
| + uint8_t sxfrctl1; | |
| + uint8_t simode0; | |
| + uint8_t simode1; | |
| + uint8_t seltimer; | |
| + uint8_t seqctl; | |
| +}; | |
| + | |
| +struct ahd_suspend_pci_state { | |
| + uint32_t devconfig; | |
| + uint8_t command; | |
| + uint8_t csize_lattime; | |
| +}; | |
| + | |
| +struct ahd_suspend_state { | |
| + struct ahd_suspend_channel_state channel[2]; | |
| + struct ahd_suspend_pci_state pci_state; | |
| + uint8_t optionmode; | |
| + uint8_t dscommand0; | |
| + uint8_t dspcistatus; | |
| + uint8_t crccontrol1; | |
| + uint8_t scbbaddr; | |
| + uint8_t dff_thrsh; | |
| + uint8_t *scratch_ram; | |
| + uint8_t *btt; | |
| +}; | |
| + | |
| +struct hardware_scb; | |
| + | |
| +struct ahd_tmode_tstate; | |
| + | |
| +struct ahd_softc { | |
| + bus_space_tag_t tags[2]; | |
| + bus_space_handle_t bshs[2]; | |
| + struct scb_data___2 scb_data; | |
| + struct hardware_scb *next_queued_hscb; | |
| + struct map_node *next_queued_hscb_map; | |
| + struct { | |
| + struct scb___2 *lh_first; | |
| + } pending_scbs; | |
| + ahd_mode dst_mode; | |
| + ahd_mode src_mode; | |
| + ahd_mode saved_dst_mode; | |
| + ahd_mode saved_src_mode; | |
| + struct ahd_platform_data *platform_data; | |
| + ahd_dev_softc_t dev_softc; | |
| + ahd_bus_intr_t bus_intr; | |
| + struct ahd_tmode_tstate *enabled_targets[16]; | |
| + struct ahd_tmode_lstate *black_hole; | |
| + struct ahd_tmode_lstate *pending_device; | |
| + struct timer_list stat_timer; | |
| + u_int cmdcmplt_bucket; | |
| + uint32_t cmdcmplt_counts[4]; | |
| + uint32_t cmdcmplt_total; | |
| + ahd_chip chip; | |
| + ahd_feature features; | |
| + ahd_bug bugs; | |
| + ahd_flag flags; | |
| + struct seeprom_config *seep_config; | |
| + struct ahd_completion *qoutfifo; | |
| + uint16_t qoutfifonext; | |
| + uint16_t qoutfifonext_valid_tag; | |
| + uint16_t qinfifonext; | |
| + uint16_t qinfifo[512]; | |
| + uint16_t qfreeze_cnt; | |
| + uint8_t unpause; | |
| + uint8_t pause; | |
| + struct cs *critical_sections; | |
| + u_int num_critical_sections; | |
| + uint8_t *overrun_buf; | |
| + struct { | |
| + struct ahd_softc *tqe_next; | |
| + struct ahd_softc **tqe_prev; | |
| + } links; | |
| + char channel; | |
| + uint8_t our_id; | |
| + struct target_cmd *targetcmds; | |
| + uint8_t tqinfifonext; | |
| + uint8_t hs_mailbox; | |
| + uint8_t send_msg_perror; | |
| + ahd_msg_flags msg_flags; | |
| + ahd_msg_type msg_type; | |
| + uint8_t msgout_buf[12]; | |
| + uint8_t msgin_buf[12]; | |
| + u_int msgout_len; | |
| + u_int msgout_index; | |
| + u_int msgin_index; | |
| + bus_dma_tag_t___2 parent_dmat; | |
| + bus_dma_tag_t___2 shared_data_dmat; | |
| + struct map_node shared_data_map; | |
| + struct ahd_suspend_state suspend_state; | |
| + u_int enabled_luns; | |
| + u_int init_level; | |
| + u_int pci_cachesize; | |
| + uint8_t iocell_opts[4]; | |
| + u_int stack_size; | |
| + uint16_t *saved_stack; | |
| + const char *description; | |
| + const char *bus_description; | |
| + char *name; | |
| + int unit; | |
| + int seltime; | |
| + u_int int_coalescing_timer; | |
| + u_int int_coalescing_maxcmds; | |
| + u_int int_coalescing_mincmds; | |
| + u_int int_coalescing_threshold; | |
| + u_int int_coalescing_stop_threshold; | |
| + uint16_t user_discenable; | |
| + uint16_t user_tagenable; | |
| +}; | |
| + | |
| +struct ahd_tmode_tstate { | |
| + struct ahd_tmode_lstate *enabled_luns[256]; | |
| + struct ahd_initiator_tinfo transinfo[16]; | |
| + uint16_t auto_negotiate; | |
| + uint16_t discenable; | |
| + uint16_t tagenable; | |
| +}; | |
| + | |
| struct wait_page_queue; | |
| struct kiocb { | |
| struct file *ki_filp; | |
| loff_t ki_pos; | |
| - void (*ki_complete)(struct kiocb *, long); | |
| + void (*ki_complete)(struct kiocb *, long int); | |
| void *private; | |
| int ki_flags; | |
| u16 ki_ioprio; | |
| + union { | |
| struct wait_page_queue *ki_waitq; | |
| + ssize_t (*dio_complete)(void *); | |
| + }; | |
| }; | |
| struct cred; | |
| @@ -33794,8 +43854,6 @@ | |
| struct kioctx; | |
| -struct eventfd_ctx; | |
| - | |
| struct aio_kiocb { | |
| union { | |
| struct file *ki_filp; | |
| @@ -33839,6 +43897,21 @@ | |
| struct io_event io_events[0]; | |
| }; | |
| +struct aio_waiter { | |
| + struct wait_queue_entry w; | |
| + size_t min_nr; | |
| +}; | |
| + | |
| +struct airtime_info { | |
| + u64 rx_airtime; | |
| + u64 tx_airtime; | |
| + long unsigned int last_active; | |
| + s32 deficit; | |
| + atomic_t aql_tx_pending; | |
| + u32 aql_limit_low; | |
| + u32 aql_limit_high; | |
| +}; | |
| + | |
| struct akcipher_request; | |
| struct crypto_akcipher; | |
| @@ -33856,6 +43929,11 @@ | |
| struct crypto_alg base; | |
| }; | |
| +struct akcipher_engine_alg { | |
| + struct akcipher_alg base; | |
| + struct crypto_engine_op op; | |
| +}; | |
| + | |
| struct akcipher_instance { | |
| void (*free)(struct akcipher_instance *); | |
| union { | |
| @@ -33876,30 +43954,6 @@ | |
| void *__ctx[0]; | |
| }; | |
| -struct rb_node { | |
| - unsigned long __rb_parent_color; | |
| - struct rb_node *rb_right; | |
| - struct rb_node *rb_left; | |
| -}; | |
| - | |
| -struct timerqueue_node { | |
| - struct rb_node node; | |
| - ktime_t expires; | |
| -}; | |
| - | |
| -struct hrtimer_clock_base; | |
| - | |
| -struct hrtimer { | |
| - struct timerqueue_node node; | |
| - ktime_t _softexpires; | |
| - enum hrtimer_restart (*function)(struct hrtimer *); | |
| - struct hrtimer_clock_base *base; | |
| - u8 state; | |
| - u8 is_rel; | |
| - u8 is_soft; | |
| - u8 is_hard; | |
| -}; | |
| - | |
| struct alarm { | |
| struct timerqueue_node node; | |
| struct hrtimer timer; | |
| @@ -33923,27 +43977,6 @@ | |
| clockid_t base_clockid; | |
| }; | |
| -struct tlb_client_info; | |
| - | |
| -struct rlb_client_info; | |
| - | |
| -struct alb_bond_info { | |
| - struct tlb_client_info *tx_hashtbl; | |
| - u32 unbalanced_load; | |
| - atomic_t tx_rebalance_counter; | |
| - int lp_counter; | |
| - int rlb_enabled; | |
| - struct rlb_client_info *rx_hashtbl; | |
| - u32 rx_hashtbl_used_head; | |
| - u8 rx_ntt; | |
| - struct slave *rx_slave; | |
| - u8 primary_is_promisc; | |
| - u32 rlb_promisc_timeout_counter; | |
| - u32 rlb_update_delay_counter; | |
| - u32 rlb_update_retry_counter; | |
| - u8 rlb_rebalance; | |
| -}; | |
| - | |
| typedef struct { | |
| struct net *net; | |
| } possible_net_t; | |
| @@ -33976,7 +44009,7 @@ | |
| __u16 skc_num; | |
| }; | |
| }; | |
| - unsigned short skc_family; | |
| + short unsigned int skc_family; | |
| volatile unsigned char skc_state; | |
| unsigned char skc_reuse: 4; | |
| unsigned char skc_reuseport: 1; | |
| @@ -33993,7 +44026,7 @@ | |
| struct in6_addr skc_v6_rcv_saddr; | |
| atomic64_t skc_cookie; | |
| union { | |
| - unsigned long skc_flags; | |
| + long unsigned int skc_flags; | |
| struct sock *skc_listener; | |
| struct inet_timewait_death_row *skc_tw_dr; | |
| }; | |
| @@ -34002,8 +44035,8 @@ | |
| struct hlist_node skc_node; | |
| struct hlist_nulls_node skc_nulls_node; | |
| }; | |
| - unsigned short skc_tx_queue_mapping; | |
| - unsigned short skc_rx_queue_mapping; | |
| + short unsigned int skc_tx_queue_mapping; | |
| + short unsigned int skc_rx_queue_mapping; | |
| union { | |
| int skc_incoming_cpu; | |
| u32 skc_rcv_wnd; | |
| @@ -34022,6 +44055,7 @@ | |
| spinlock_t slock; | |
| int owned; | |
| wait_queue_head_t wq; | |
| + struct lockdep_map dep_map; | |
| } socket_lock_t; | |
| struct page_frag { | |
| @@ -34045,6 +44079,10 @@ | |
| typedef struct { | |
| arch_rwlock_t raw_lock; | |
| + unsigned int magic; | |
| + unsigned int owner_cpu; | |
| + void *owner; | |
| + struct lockdep_map dep_map; | |
| } rwlock_t; | |
| typedef struct { | |
| @@ -34054,7 +44092,6 @@ | |
| struct sock_cgroup_data { | |
| struct cgroup *cgroup; | |
| u32 classid; | |
| - u16 prioidx; | |
| }; | |
| struct dst_entry; | |
| @@ -34063,26 +44100,23 @@ | |
| struct socket_wq; | |
| -struct xfrm_policy; | |
| - | |
| -struct pid; | |
| - | |
| struct socket; | |
| struct mem_cgroup; | |
| +struct xfrm_policy; | |
| + | |
| +struct pid; | |
| + | |
| struct sock_reuseport; | |
| struct bpf_local_storage; | |
| struct sock { | |
| struct sock_common __sk_common; | |
| - struct dst_entry __attribute__((btf_type_tag("rcu"))) *sk_rx_dst; | |
| - int sk_rx_dst_ifindex; | |
| - u32 sk_rx_dst_cookie; | |
| - socket_lock_t sk_lock; | |
| + __u8 __cacheline_group_begin__sock_write_rx[0]; | |
| atomic_t sk_drops; | |
| - int sk_rcvlowat; | |
| + __s32 sk_peek_off; | |
| struct sk_buff_head sk_error_queue; | |
| struct sk_buff_head sk_receive_queue; | |
| struct { | |
| @@ -34091,96 +44125,110 @@ | |
| struct sk_buff *head; | |
| struct sk_buff *tail; | |
| } sk_backlog; | |
| - int sk_forward_alloc; | |
| - u32 sk_reserved_mem; | |
| + __u8 __cacheline_group_end__sock_write_rx[0]; | |
| + __u8 __cacheline_group_begin__sock_read_rx[0]; | |
| + struct dst_entry *sk_rx_dst; | |
| + int sk_rx_dst_ifindex; | |
| + u32 sk_rx_dst_cookie; | |
| unsigned int sk_ll_usec; | |
| unsigned int sk_napi_id; | |
| + u16 sk_busy_poll_budget; | |
| + u8 sk_prefer_busy_poll; | |
| + u8 sk_userlocks; | |
| int sk_rcvbuf; | |
| - int sk_wait_pending; | |
| - struct sk_filter __attribute__((btf_type_tag("rcu"))) *sk_filter; | |
| + struct sk_filter *sk_filter; | |
| union { | |
| - struct socket_wq __attribute__((btf_type_tag("rcu"))) *sk_wq; | |
| + struct socket_wq *sk_wq; | |
| struct socket_wq *sk_wq_raw; | |
| }; | |
| - struct xfrm_policy __attribute__((btf_type_tag("rcu"))) *sk_policy[2]; | |
| - struct dst_entry __attribute__((btf_type_tag("rcu"))) *sk_dst_cache; | |
| + void (*sk_data_ready)(struct sock *); | |
| + long int sk_rcvtimeo; | |
| + int sk_rcvlowat; | |
| + __u8 __cacheline_group_end__sock_read_rx[0]; | |
| + __u8 __cacheline_group_begin__sock_read_rxtx[0]; | |
| + int sk_err; | |
| + struct socket *sk_socket; | |
| + struct mem_cgroup *sk_memcg; | |
| + struct xfrm_policy *sk_policy[2]; | |
| + __u8 __cacheline_group_end__sock_read_rxtx[0]; | |
| + __u8 __cacheline_group_begin__sock_write_rxtx[0]; | |
| + socket_lock_t sk_lock; | |
| + u32 sk_reserved_mem; | |
| + int sk_forward_alloc; | |
| + u32 sk_tsflags; | |
| + __u8 __cacheline_group_end__sock_write_rxtx[0]; | |
| + __u8 __cacheline_group_begin__sock_write_tx[0]; | |
| + int sk_write_pending; | |
| atomic_t sk_omem_alloc; | |
| int sk_sndbuf; | |
| int sk_wmem_queued; | |
| refcount_t sk_wmem_alloc; | |
| - unsigned long sk_tsq_flags; | |
| + long unsigned int sk_tsq_flags; | |
| union { | |
| struct sk_buff *sk_send_head; | |
| struct rb_root tcp_rtx_queue; | |
| }; | |
| struct sk_buff_head sk_write_queue; | |
| - __s32 sk_peek_off; | |
| - int sk_write_pending; | |
| - __u32 sk_dst_pending_confirm; | |
| + u32 sk_dst_pending_confirm; | |
| u32 sk_pacing_status; | |
| - long sk_sndtimeo; | |
| - struct timer_list sk_timer; | |
| - __u32 sk_priority; | |
| - __u32 sk_mark; | |
| - unsigned long sk_pacing_rate; | |
| - unsigned long sk_max_pacing_rate; | |
| struct page_frag sk_frag; | |
| + struct timer_list sk_timer; | |
| + long unsigned int sk_pacing_rate; | |
| + atomic_t sk_zckey; | |
| + atomic_t sk_tskey; | |
| + __u8 __cacheline_group_end__sock_write_tx[0]; | |
| + __u8 __cacheline_group_begin__sock_read_tx[0]; | |
| + long unsigned int sk_max_pacing_rate; | |
| + long int sk_sndtimeo; | |
| + u32 sk_priority; | |
| + u32 sk_mark; | |
| + struct dst_entry *sk_dst_cache; | |
| netdev_features_t sk_route_caps; | |
| - int sk_gso_type; | |
| + u16 sk_gso_type; | |
| + u16 sk_gso_max_segs; | |
| unsigned int sk_gso_max_size; | |
| gfp_t sk_allocation; | |
| - __u32 sk_txhash; | |
| + u32 sk_txhash; | |
| + u8 sk_pacing_shift; | |
| + bool sk_use_task_frag; | |
| + __u8 __cacheline_group_end__sock_read_tx[0]; | |
| u8 sk_gso_disabled: 1; | |
| u8 sk_kern_sock: 1; | |
| u8 sk_no_check_tx: 1; | |
| u8 sk_no_check_rx: 1; | |
| - u8 sk_userlocks: 4; | |
| - u8 sk_pacing_shift; | |
| + u8 sk_shutdown; | |
| u16 sk_type; | |
| u16 sk_protocol; | |
| - u16 sk_gso_max_segs; | |
| - unsigned long sk_lingertime; | |
| + long unsigned int sk_lingertime; | |
| struct proto *sk_prot_creator; | |
| rwlock_t sk_callback_lock; | |
| - int sk_err; | |
| int sk_err_soft; | |
| u32 sk_ack_backlog; | |
| u32 sk_max_ack_backlog; | |
| kuid_t sk_uid; | |
| - u8 sk_txrehash; | |
| - u8 sk_prefer_busy_poll; | |
| - u16 sk_busy_poll_budget; | |
| spinlock_t sk_peer_lock; | |
| int sk_bind_phc; | |
| struct pid *sk_peer_pid; | |
| const struct cred *sk_peer_cred; | |
| - long sk_rcvtimeo; | |
| ktime_t sk_stamp; | |
| - atomic_t sk_tskey; | |
| - atomic_t sk_zckey; | |
| - u32 sk_tsflags; | |
| - u8 sk_shutdown; | |
| + int sk_disconnects; | |
| + u8 sk_txrehash; | |
| u8 sk_clockid; | |
| u8 sk_txtime_deadline_mode: 1; | |
| u8 sk_txtime_report_errors: 1; | |
| u8 sk_txtime_unused: 6; | |
| - bool sk_use_task_frag; | |
| - struct socket *sk_socket; | |
| void *sk_user_data; | |
| void *sk_security; | |
| struct sock_cgroup_data sk_cgrp_data; | |
| - struct mem_cgroup *sk_memcg; | |
| void (*sk_state_change)(struct sock *); | |
| - void (*sk_data_ready)(struct sock *); | |
| void (*sk_write_space)(struct sock *); | |
| void (*sk_error_report)(struct sock *); | |
| int (*sk_backlog_rcv)(struct sock *, struct sk_buff *); | |
| void (*sk_destruct)(struct sock *); | |
| - struct sock_reuseport __attribute__((btf_type_tag("rcu"))) *sk_reuseport_cb; | |
| - struct bpf_local_storage __attribute__((btf_type_tag("rcu"))) *sk_bpf_storage; | |
| + struct sock_reuseport *sk_reuseport_cb; | |
| + struct bpf_local_storage *sk_bpf_storage; | |
| struct callback_head sk_rcu; | |
| netns_tracker ns_tracker; | |
| - struct hlist_node sk_bind2_node; | |
| }; | |
| struct alg_sock { | |
| @@ -34217,7 +44265,7 @@ | |
| }; | |
| typedef struct { | |
| - unsigned long bits[1]; | |
| + long unsigned int bits[1]; | |
| } nodemask_t; | |
| struct zonelist; | |
| @@ -34233,133 +44281,124 @@ | |
| bool spread_dirty_pages; | |
| }; | |
| -struct allowedips_node; | |
| - | |
| -struct allowedips { | |
| - struct allowedips_node __attribute__((btf_type_tag("rcu"))) *root4; | |
| - struct allowedips_node __attribute__((btf_type_tag("rcu"))) *root6; | |
| - u64 seq; | |
| +struct codetag { | |
| + unsigned int flags; | |
| + unsigned int lineno; | |
| + const char *modname; | |
| + const char *function; | |
| + const char *filename; | |
| }; | |
| -struct wg_peer; | |
| +struct alloc_tag_counters; | |
| -struct allowedips_node { | |
| - struct wg_peer __attribute__((btf_type_tag("rcu"))) *peer; | |
| - struct allowedips_node __attribute__((btf_type_tag("rcu"))) *bit[2]; | |
| - u8 cidr; | |
| - u8 bit_at_a; | |
| - u8 bit_at_b; | |
| - u8 bitlen; | |
| - long: 0; | |
| - u8 bits[16]; | |
| - unsigned long parent_bit_packed; | |
| - union { | |
| - struct list_head peer_list; | |
| - struct callback_head rcu; | |
| - }; | |
| +struct alloc_tag { | |
| + struct codetag ct; | |
| + struct alloc_tag_counters *counters; | |
| }; | |
| -struct alt_instr { | |
| - s32 instr_offset; | |
| - s32 repl_offset; | |
| - union { | |
| - struct { | |
| - u32 cpuid: 16; | |
| - u32 flags: 16; | |
| - }; | |
| - u32 ft_flags; | |
| +struct alloc_tag_counters { | |
| + u64 bytes; | |
| + u64 calls; | |
| }; | |
| - u8 instrlen; | |
| - u8 replacementlen; | |
| -} __attribute__((packed)); | |
| -struct amd64_family_flags { | |
| - __u64 zn_regs_v2: 1; | |
| - __u64 __reserved: 63; | |
| +struct alps_bitmap_point { | |
| + int start_bit; | |
| + int num_bits; | |
| }; | |
| -struct chip_select { | |
| - u32 csbases[8]; | |
| - u32 csbases_sec[8]; | |
| - u8 b_cnt; | |
| - u32 csmasks[8]; | |
| - u32 csmasks_sec[8]; | |
| - u8 m_cnt; | |
| +struct input_mt_pos { | |
| + s16 x; | |
| + s16 y; | |
| }; | |
| -struct reg_pair { | |
| - u32 lo; | |
| - u32 hi; | |
| +struct alps_fields { | |
| + unsigned int x_map; | |
| + unsigned int y_map; | |
| + unsigned int fingers; | |
| + int pressure; | |
| + struct input_mt_pos st; | |
| + struct input_mt_pos mt[4]; | |
| + unsigned int first_mp: 1; | |
| + unsigned int is_mp: 1; | |
| + unsigned int left: 1; | |
| + unsigned int right: 1; | |
| + unsigned int middle: 1; | |
| + unsigned int ts_left: 1; | |
| + unsigned int ts_right: 1; | |
| + unsigned int ts_middle: 1; | |
| }; | |
| -struct dram_range { | |
| - struct reg_pair base; | |
| - struct reg_pair lim; | |
| -}; | |
| +struct psmouse; | |
| -struct error_injection { | |
| - u32 section; | |
| - u32 word; | |
| - u32 bit_map; | |
| -}; | |
| +struct input_dev; | |
| -struct low_ops; | |
| +struct alps_nibble_commands; | |
| -struct amd64_umc; | |
| +struct alps_data { | |
| + struct psmouse *psmouse; | |
| + struct input_dev *dev2; | |
| + struct input_dev *dev3; | |
| + char phys2[32]; | |
| + char phys3[32]; | |
| + struct delayed_work dev3_register_work; | |
| + const struct alps_nibble_commands *nibble_commands; | |
| + int addr_command; | |
| + u16 proto_version; | |
| + u8 byte0; | |
| + u8 mask0; | |
| + u8 dev_id[3]; | |
| + u8 fw_ver[3]; | |
| + int flags; | |
| + int x_max; | |
| + int y_max; | |
| + int x_bits; | |
| + int y_bits; | |
| + unsigned int x_res; | |
| + unsigned int y_res; | |
| + int (*hw_init)(struct psmouse *); | |
| + void (*process_packet)(struct psmouse *); | |
| + int (*decode_fields)(struct alps_fields *, unsigned char *, struct psmouse *); | |
| + void (*set_abs_params)(struct alps_data *, struct input_dev *); | |
| + int prev_fin; | |
| + int multi_packet; | |
| + int second_touch; | |
| + unsigned char multi_data[6]; | |
| + struct alps_fields f; | |
| + u8 quirks; | |
| + struct timer_list timer; | |
| +}; | |
| -struct amd64_pvt { | |
| - struct low_ops *ops; | |
| - struct pci_dev *F1; | |
| - struct pci_dev *F2; | |
| - struct pci_dev *F3; | |
| - u16 mc_node_id; | |
| - u8 fam; | |
| - u8 model; | |
| - u8 stepping; | |
| - int ext_model; | |
| - u32 dclr0; | |
| - u32 dclr1; | |
| - u32 dchr0; | |
| - u32 dchr1; | |
| - u32 nbcap; | |
| - u32 nbcfg; | |
| - u32 ext_nbcfg; | |
| - u32 dhar; | |
| - u32 dbam0; | |
| - u32 dbam1; | |
| - struct chip_select csels[12]; | |
| - struct dram_range ranges[8]; | |
| - u64 top_mem; | |
| - u64 top_mem2; | |
| - u32 dct_sel_lo; | |
| - u32 dct_sel_hi; | |
| - u32 online_spare; | |
| - u8 ecc_sym_sz; | |
| - const char *ctl_name; | |
| - u16 f1_id; | |
| - u16 f2_id; | |
| - u8 max_mcs; | |
| - struct amd64_family_flags flags; | |
| - struct error_injection injection; | |
| - enum mem_type dram_type; | |
| - struct amd64_umc *umc; | |
| +struct alps_protocol_info { | |
| + u16 version; | |
| + u8 byte0; | |
| + u8 mask0; | |
| + unsigned int flags; | |
| }; | |
| -struct amd64_umc { | |
| - u32 dimm_cfg; | |
| - u32 umc_cfg; | |
| - u32 sdp_ctrl; | |
| - u32 ecc_ctrl; | |
| - u32 umc_cap_hi; | |
| - enum mem_type dram_type; | |
| +struct alps_model_info { | |
| + u8 signature[3]; | |
| + struct alps_protocol_info protocol_info; | |
| }; | |
| -struct amd768_priv { | |
| - void *iobase; | |
| - struct pci_dev *pcidev; | |
| - u32 pmbase; | |
| +struct alps_nibble_commands { | |
| + int command; | |
| + unsigned char data; | |
| }; | |
| +struct alt_instr { | |
| + s32 instr_offset; | |
| + s32 repl_offset; | |
| + union { | |
| + struct { | |
| + u32 cpuid: 16; | |
| + u32 flags: 16; | |
| + }; | |
| + u32 ft_flags; | |
| + }; | |
| + u8 instrlen; | |
| + u8 replacementlen; | |
| +} __attribute__((packed)); | |
| + | |
| struct amd_aperf_mperf { | |
| u64 aperf; | |
| u64 mperf; | |
| @@ -34389,6 +44428,11 @@ | |
| u32 nominal_perf; | |
| u32 lowest_nonlinear_perf; | |
| u32 lowest_perf; | |
| + u32 prefcore_ranking; | |
| + u32 min_limit_perf; | |
| + u32 max_limit_perf; | |
| + u32 min_limit_freq; | |
| + u32 max_limit_freq; | |
| u32 max_freq; | |
| u32 min_freq; | |
| u32 nominal_freq; | |
| @@ -34397,6 +44441,7 @@ | |
| struct amd_aperf_mperf prev; | |
| u64 freq; | |
| bool boost_supported; | |
| + bool hw_prefcore; | |
| s16 epp_policy; | |
| s16 epp_cached; | |
| u32 policy; | |
| @@ -34404,192 +44449,12 @@ | |
| bool suspended; | |
| }; | |
| -struct amd_decoder_ops { | |
| - bool (*mc0_mce)(u16, u8); | |
| - bool (*mc1_mce)(u16, u8); | |
| - bool (*mc2_mce)(u16, u8); | |
| -}; | |
| - | |
| struct amd_hostbridge { | |
| u32 bus; | |
| u32 slot; | |
| u32 device; | |
| }; | |
| -struct iommu_flush_ops; | |
| - | |
| -struct io_pgtable_cfg { | |
| - unsigned long quirks; | |
| - unsigned long pgsize_bitmap; | |
| - unsigned int ias; | |
| - unsigned int oas; | |
| - bool coherent_walk; | |
| - const struct iommu_flush_ops *tlb; | |
| - struct device *iommu_dev; | |
| - union { | |
| - struct { | |
| - u64 ttbr; | |
| - struct { | |
| - u32 ips: 3; | |
| - u32 tg: 2; | |
| - u32 sh: 2; | |
| - u32 orgn: 2; | |
| - u32 irgn: 2; | |
| - u32 tsz: 6; | |
| - } tcr; | |
| - u64 mair; | |
| - } arm_lpae_s1_cfg; | |
| - struct { | |
| - u64 vttbr; | |
| - struct { | |
| - u32 ps: 3; | |
| - u32 tg: 2; | |
| - u32 sh: 2; | |
| - u32 orgn: 2; | |
| - u32 irgn: 2; | |
| - u32 sl: 2; | |
| - u32 tsz: 6; | |
| - } vtcr; | |
| - } arm_lpae_s2_cfg; | |
| - struct { | |
| - u32 ttbr; | |
| - u32 tcr; | |
| - u32 nmrr; | |
| - u32 prrr; | |
| - } arm_v7s_cfg; | |
| - struct { | |
| - u64 transtab; | |
| - u64 memattr; | |
| - } arm_mali_lpae_cfg; | |
| - struct { | |
| - u64 ttbr[4]; | |
| - u32 n_ttbrs; | |
| - } apple_dart_cfg; | |
| - }; | |
| -}; | |
| - | |
| -struct iommu_iotlb_gather; | |
| - | |
| -struct io_pgtable_ops { | |
| - int (*map_pages)(struct io_pgtable_ops *, unsigned long, phys_addr_t, size_t, size_t, int, gfp_t, size_t *); | |
| - size_t (*unmap_pages)(struct io_pgtable_ops *, unsigned long, size_t, size_t, struct iommu_iotlb_gather *); | |
| - phys_addr_t (*iova_to_phys)(struct io_pgtable_ops *, unsigned long); | |
| -}; | |
| - | |
| -struct io_pgtable { | |
| - enum io_pgtable_fmt fmt; | |
| - void *cookie; | |
| - struct io_pgtable_cfg cfg; | |
| - struct io_pgtable_ops ops; | |
| -}; | |
| - | |
| -struct amd_io_pgtable { | |
| - struct io_pgtable_cfg pgtbl_cfg; | |
| - struct io_pgtable iop; | |
| - int mode; | |
| - u64 *root; | |
| - atomic64_t pt_root; | |
| - u64 *pgd; | |
| -}; | |
| - | |
| -struct iommu_ops; | |
| - | |
| -struct iommu_device { | |
| - struct list_head list; | |
| - const struct iommu_ops *ops; | |
| - struct fwnode_handle *fwnode; | |
| - struct device *dev; | |
| - u32 max_pasids; | |
| -}; | |
| - | |
| -struct amd_iommu_pci_seg; | |
| - | |
| -struct amd_irte_ops; | |
| - | |
| -struct amd_iommu { | |
| - struct list_head list; | |
| - int index; | |
| - raw_spinlock_t lock; | |
| - struct pci_dev *dev; | |
| - struct pci_dev *root_pdev; | |
| - u64 mmio_phys; | |
| - u64 mmio_phys_end; | |
| - u8 *mmio_base; | |
| - u32 cap; | |
| - u8 acpi_flags; | |
| - u64 features; | |
| - u64 features2; | |
| - bool is_iommu_v2; | |
| - u16 devid; | |
| - u16 cap_ptr; | |
| - struct amd_iommu_pci_seg *pci_seg; | |
| - u64 exclusion_start; | |
| - u64 exclusion_length; | |
| - u8 *cmd_buf; | |
| - u32 cmd_buf_head; | |
| - u32 cmd_buf_tail; | |
| - u8 *evt_buf; | |
| - u8 *ppr_log; | |
| - u8 *ga_log; | |
| - u8 *ga_log_tail; | |
| - bool int_enabled; | |
| - bool need_sync; | |
| - struct iommu_device iommu; | |
| - u32 stored_addr_lo; | |
| - u32 stored_addr_hi; | |
| - u32 stored_l1[108]; | |
| - u32 stored_l2[131]; | |
| - u8 max_banks; | |
| - u8 max_counters; | |
| - struct irq_domain *ir_domain; | |
| - struct amd_irte_ops *irte_ops; | |
| - u32 flags; | |
| - volatile u64 *cmd_sem; | |
| - u64 cmd_sem_val; | |
| -}; | |
| - | |
| -struct amd_iommu_device_info { | |
| - int max_pasids; | |
| - u32 flags; | |
| -}; | |
| - | |
| -struct amd_iommu_event_desc { | |
| - struct device_attribute attr; | |
| - const char *event; | |
| -}; | |
| - | |
| -struct amd_iommu_fault { | |
| - u64 address; | |
| - u32 pasid; | |
| - u32 sbdf; | |
| - u16 tag; | |
| - u16 flags; | |
| -}; | |
| - | |
| -struct llist_head { | |
| - struct llist_node *first; | |
| -}; | |
| - | |
| -struct dev_table_entry; | |
| - | |
| -struct irq_remap_table; | |
| - | |
| -struct amd_iommu_pci_seg { | |
| - struct list_head list; | |
| - struct llist_head dev_data_list; | |
| - u16 id; | |
| - u16 last_bdf; | |
| - u32 dev_table_size; | |
| - u32 alias_table_size; | |
| - u32 rlookup_table_size; | |
| - struct dev_table_entry *dev_table; | |
| - struct amd_iommu **rlookup_table; | |
| - struct irq_remap_table **irq_lookup_table; | |
| - struct dev_table_entry *old_dev_tbl_cpy; | |
| - u16 *alias_table; | |
| - struct list_head unity_map; | |
| -}; | |
| - | |
| struct vcpu_data; | |
| struct amd_iommu_pi_data { | |
| @@ -34601,107 +44466,18 @@ | |
| void *ir_data; | |
| }; | |
| -struct irq_2_irte { | |
| - u16 devid; | |
| - u16 index; | |
| -}; | |
| - | |
| -struct x86_msi_addr_lo { | |
| - union { | |
| - struct { | |
| - u32 reserved_0: 2; | |
| - u32 dest_mode_logical: 1; | |
| - u32 redirect_hint: 1; | |
| - u32 reserved_1: 1; | |
| - u32 virt_destid_8_14: 7; | |
| - u32 destid_0_7: 8; | |
| - u32 base_address: 12; | |
| - }; | |
| - struct { | |
| - u32 dmar_reserved_0: 2; | |
| - u32 dmar_index_15: 1; | |
| - u32 dmar_subhandle_valid: 1; | |
| - u32 dmar_format: 1; | |
| - u32 dmar_index_0_14: 15; | |
| - u32 dmar_base_address: 12; | |
| - }; | |
| - }; | |
| -}; | |
| - | |
| -typedef struct x86_msi_addr_lo arch_msi_msg_addr_lo_t; | |
| - | |
| -struct x86_msi_addr_hi { | |
| - u32 reserved: 8; | |
| - u32 destid_8_31: 24; | |
| -}; | |
| - | |
| -typedef struct x86_msi_addr_hi arch_msi_msg_addr_hi_t; | |
| - | |
| -struct x86_msi_data { | |
| - union { | |
| - struct { | |
| - u32 vector: 8; | |
| - u32 delivery_mode: 3; | |
| - u32 dest_mode_logical: 1; | |
| - u32 reserved: 2; | |
| - u32 active_low: 1; | |
| - u32 is_level: 1; | |
| - }; | |
| - u32 dmar_subhandle; | |
| - }; | |
| -}; | |
| - | |
| -typedef struct x86_msi_data arch_msi_msg_data_t; | |
| - | |
| -struct msi_msg { | |
| - union { | |
| - u32 address_lo; | |
| - arch_msi_msg_addr_lo_t arch_addr_lo; | |
| - }; | |
| - union { | |
| - u32 address_hi; | |
| - arch_msi_msg_addr_hi_t arch_addr_hi; | |
| - }; | |
| - union { | |
| - u32 data; | |
| - arch_msi_msg_data_t arch_data; | |
| - }; | |
| -}; | |
| - | |
| -struct irq_cfg; | |
| - | |
| -struct amd_ir_data { | |
| - u32 cached_ga_tag; | |
| - struct amd_iommu *iommu; | |
| - struct irq_2_irte irq_2_irte; | |
| - struct msi_msg msi_entry; | |
| - void *entry; | |
| - void *ref; | |
| - struct irq_cfg *cfg; | |
| - int ga_vector; | |
| - u64 ga_root_ptr; | |
| - u32 ga_tag; | |
| -}; | |
| - | |
| -struct amd_irte_ops { | |
| - void (*prepare)(void *, u32, bool, u8, u32, int); | |
| - void (*activate)(struct amd_iommu *, void *, u16, u16); | |
| - void (*deactivate)(struct amd_iommu *, void *, u16, u16); | |
| - void (*set_affinity)(struct amd_iommu *, void *, u16, u16, u8, u32); | |
| - void * (*get)(struct irq_remap_table *, int); | |
| - void (*set_allocated)(struct irq_remap_table *, int); | |
| - bool (*is_allocated)(struct irq_remap_table *, int); | |
| - void (*clear_allocated)(struct irq_remap_table *, int); | |
| -}; | |
| - | |
| struct amd_l3_cache { | |
| unsigned int indices; | |
| u8 subcaches[4]; | |
| }; | |
| +struct amd_lps0_hid_device_data { | |
| + const bool check_off_by_one; | |
| +}; | |
| + | |
| struct event_constraint { | |
| union { | |
| - unsigned long idxmsk[1]; | |
| + long unsigned int idxmsk[1]; | |
| u64 idxmsk64; | |
| }; | |
| u64 code; | |
| @@ -34743,19 +44519,97 @@ | |
| struct amd_northbridge *nb; | |
| }; | |
| -typedef struct cpumask cpumask_t; | |
| +struct amd_svm_iommu_ir { | |
| + struct list_head node; | |
| + void *data; | |
| +}; | |
| + | |
| +union amd_uncore_info; | |
| + | |
| +struct amd_uncore_pmu; | |
| struct amd_uncore { | |
| - int id; | |
| + union amd_uncore_info *info; | |
| + struct amd_uncore_pmu *pmus; | |
| + unsigned int num_pmus; | |
| + bool init_done; | |
| + void (*scan)(struct amd_uncore *, unsigned int); | |
| + int (*init)(struct amd_uncore *, unsigned int); | |
| + void (*move)(struct amd_uncore *, unsigned int); | |
| + void (*free)(struct amd_uncore *, unsigned int); | |
| +}; | |
| + | |
| +struct amd_uncore_ctx { | |
| int refcnt; | |
| int cpu; | |
| + struct perf_event **events; | |
| + struct hlist_node node; | |
| +}; | |
| + | |
| +typedef struct cpumask cpumask_t; | |
| + | |
| +struct perf_cpu_pmu_context; | |
| + | |
| +struct mm_struct; | |
| + | |
| +struct perf_event_pmu_context; | |
| + | |
| +struct kmem_cache; | |
| + | |
| +struct perf_output_handle; | |
| + | |
| +struct pmu { | |
| + struct list_head entry; | |
| + struct module *module; | |
| + struct device *dev; | |
| + struct device *parent; | |
| + const struct attribute_group **attr_groups; | |
| + const struct attribute_group **attr_update; | |
| + const char *name; | |
| + int type; | |
| + int capabilities; | |
| + int *pmu_disable_count; | |
| + struct perf_cpu_pmu_context *cpu_pmu_context; | |
| + atomic_t exclusive_cnt; | |
| + int task_ctx_nr; | |
| + int hrtimer_interval_ms; | |
| + unsigned int nr_addr_filters; | |
| + void (*pmu_enable)(struct pmu *); | |
| + void (*pmu_disable)(struct pmu *); | |
| + int (*event_init)(struct perf_event *); | |
| + void (*event_mapped)(struct perf_event *, struct mm_struct *); | |
| + void (*event_unmapped)(struct perf_event *, struct mm_struct *); | |
| + int (*add)(struct perf_event *, int); | |
| + void (*del)(struct perf_event *, int); | |
| + void (*start)(struct perf_event *, int); | |
| + void (*stop)(struct perf_event *, int); | |
| + void (*read)(struct perf_event *); | |
| + void (*start_txn)(struct pmu *, unsigned int); | |
| + int (*commit_txn)(struct pmu *); | |
| + void (*cancel_txn)(struct pmu *); | |
| + int (*event_idx)(struct perf_event *); | |
| + void (*sched_task)(struct perf_event_pmu_context *, bool); | |
| + struct kmem_cache *task_ctx_cache; | |
| + void (*swap_task_ctx)(struct perf_event_pmu_context *, struct perf_event_pmu_context *); | |
| + void * (*setup_aux)(struct perf_event *, void **, int, bool); | |
| + void (*free_aux)(void *); | |
| + long int (*snapshot_aux)(struct perf_event *, struct perf_output_handle *, long unsigned int); | |
| + int (*addr_filters_validate)(struct list_head *); | |
| + void (*addr_filters_sync)(struct perf_event *); | |
| + int (*aux_output_match)(struct perf_event *); | |
| + bool (*filter)(struct pmu *, int); | |
| + int (*check_period)(struct perf_event *, u64); | |
| +}; | |
| + | |
| +struct amd_uncore_pmu { | |
| + char name[16]; | |
| int num_counters; | |
| int rdpmc_base; | |
| u32 msr_base; | |
| - cpumask_t *active_mask; | |
| - struct pmu *pmu; | |
| - struct perf_event **events; | |
| - struct hlist_node node; | |
| + int group; | |
| + cpumask_t active_mask; | |
| + struct pmu pmu; | |
| + struct amd_uncore_ctx **ctx; | |
| }; | |
| struct aml_resource_address { | |
| @@ -35151,7 +45005,7 @@ | |
| const struct attribute_group *grp; | |
| struct device_attribute **attrs; | |
| int (*match)(struct attribute_container *, struct device *); | |
| - unsigned long flags; | |
| + long unsigned int flags; | |
| }; | |
| struct anon_transport_class { | |
| @@ -35163,8 +45017,8 @@ | |
| struct anon_vma *root; | |
| struct rw_semaphore rwsem; | |
| atomic_t refcount; | |
| - unsigned long num_children; | |
| - unsigned long num_active_vmas; | |
| + long unsigned int num_children; | |
| + long unsigned int num_active_vmas; | |
| struct anon_vma *parent; | |
| struct rb_root_cached rb_root; | |
| }; | |
| @@ -35174,7 +45028,7 @@ | |
| struct anon_vma *anon_vma; | |
| struct list_head same_vma; | |
| struct rb_node rb; | |
| - unsigned long rb_subtree_last; | |
| + long unsigned int rb_subtree_last; | |
| }; | |
| struct anon_vma_name { | |
| @@ -35182,8 +45036,6 @@ | |
| char name[0]; | |
| }; | |
| -struct property_entry; | |
| - | |
| struct apd_private_data; | |
| struct apd_device_desc { | |
| @@ -35200,48 +45052,49 @@ | |
| const struct apd_device_desc *dev_desc; | |
| }; | |
| -struct apei_exec_ins_type; | |
| - | |
| -struct apei_exec_context { | |
| - u32 ip; | |
| - u64 value; | |
| - u64 var1; | |
| - u64 var2; | |
| - u64 src_base; | |
| - u64 dst_base; | |
| - struct apei_exec_ins_type *ins_table; | |
| - u32 instructions; | |
| - struct acpi_whea_header *action_table; | |
| - u32 entries; | |
| +struct aper_size_info_16 { | |
| + int size; | |
| + int num_entries; | |
| + int page_order; | |
| + u16 size_value; | |
| }; | |
| -typedef int (*apei_exec_ins_func_t)(struct apei_exec_context *, struct acpi_whea_header *); | |
| +struct aper_size_info_32 { | |
| + int size; | |
| + int num_entries; | |
| + int page_order; | |
| + u32 size_value; | |
| +}; | |
| -struct apei_exec_ins_type { | |
| - u32 flags; | |
| - apei_exec_ins_func_t run; | |
| +struct aper_size_info_8 { | |
| + int size; | |
| + int num_entries; | |
| + int page_order; | |
| + u8 size_value; | |
| }; | |
| -struct apei_res { | |
| - struct list_head list; | |
| - unsigned long start; | |
| - unsigned long end; | |
| +struct aper_size_info_fixed { | |
| + int size; | |
| + int num_entries; | |
| + int page_order; | |
| }; | |
| -struct apei_resources { | |
| - struct list_head iomem; | |
| - struct list_head ioport; | |
| +struct aper_size_info_lvl2 { | |
| + int size; | |
| + int num_entries; | |
| + u32 size_value; | |
| }; | |
| struct seqcount { | |
| unsigned int sequence; | |
| + struct lockdep_map dep_map; | |
| }; | |
| typedef struct seqcount seqcount_t; | |
| struct aperfmperf { | |
| seqcount_t seq; | |
| - unsigned long last_update; | |
| + long unsigned int last_update; | |
| u64 acnt; | |
| u64 mcnt; | |
| u64 aperf; | |
| @@ -35261,13 +45114,9 @@ | |
| int status; | |
| }; | |
| -struct physid_mask; | |
| - | |
| -typedef struct physid_mask physid_mask_t; | |
| - | |
| struct apic { | |
| - void (*eoi_write)(u32, u32); | |
| - void (*native_eoi_write)(u32, u32); | |
| + void (*eoi)(); | |
| + void (*native_eoi)(); | |
| void (*write)(u32, u32); | |
| u32 (*read)(u32); | |
| void (*wait_icr_idle)(); | |
| @@ -35278,29 +45127,21 @@ | |
| void (*send_IPI_allbutself)(int); | |
| void (*send_IPI_all)(int); | |
| void (*send_IPI_self)(int); | |
| - u32 disable_esr; | |
| - enum apic_delivery_modes delivery_mode; | |
| - bool dest_mode_logical; | |
| + u32 disable_esr: 1; | |
| + u32 dest_mode_logical: 1; | |
| + u32 x2apic_set_max_apicid: 1; | |
| + u32 nmi_to_offline_cpu: 1; | |
| u32 (*calc_dest_apicid)(unsigned int); | |
| u64 (*icr_read)(); | |
| void (*icr_write)(u32, u32); | |
| + u32 max_apic_id; | |
| int (*probe)(); | |
| int (*acpi_madt_oem_check)(char *, char *); | |
| - int (*apic_id_valid)(u32); | |
| - int (*apic_id_registered)(); | |
| - bool (*check_apicid_used)(physid_mask_t *, int); | |
| void (*init_apic_ldr)(); | |
| - void (*ioapic_phys_id_map)(physid_mask_t *, physid_mask_t *); | |
| - void (*setup_apic_routing)(); | |
| - int (*cpu_present_to_apicid)(int); | |
| - void (*apicid_to_cpu_present)(int, physid_mask_t *); | |
| - int (*check_phys_apicid_present)(int); | |
| - int (*phys_pkg_id)(int, int); | |
| - u32 (*get_apic_id)(unsigned long); | |
| - u32 (*set_apic_id)(unsigned int); | |
| - int (*wakeup_secondary_cpu)(int, unsigned long); | |
| - int (*wakeup_secondary_cpu_64)(int, unsigned long); | |
| - void (*inquire_remote_apic)(int); | |
| + u32 (*cpu_present_to_apicid)(int); | |
| + u32 (*get_apic_id)(u32); | |
| + int (*wakeup_secondary_cpu)(u32, long unsigned int); | |
| + int (*wakeup_secondary_cpu_64)(u32, long unsigned int); | |
| char *name; | |
| }; | |
| @@ -35323,6 +45164,23 @@ | |
| unsigned int has_reserved: 1; | |
| }; | |
| +struct apic_override { | |
| + void (*eoi)(); | |
| + void (*native_eoi)(); | |
| + void (*write)(u32, u32); | |
| + u32 (*read)(u32); | |
| + void (*send_IPI)(int, int); | |
| + void (*send_IPI_mask)(const struct cpumask *, int); | |
| + void (*send_IPI_mask_allbutself)(const struct cpumask *, int); | |
| + void (*send_IPI_allbutself)(int); | |
| + void (*send_IPI_all)(int); | |
| + void (*send_IPI_self)(int); | |
| + u64 (*icr_read)(); | |
| + void (*icr_write)(u32, u32); | |
| + int (*wakeup_secondary_cpu)(u32, long unsigned int); | |
| + int (*wakeup_secondary_cpu_64)(u32, long unsigned int); | |
| +}; | |
| + | |
| struct apm_bios_info { | |
| __u16 version; | |
| __u16 cseg; | |
| @@ -35335,6 +45193,97 @@ | |
| __u16 dseg_len; | |
| }; | |
| +struct apple_backlight_config_report { | |
| + u8 report_id; | |
| + u8 version; | |
| + u16 backlight_off; | |
| + u16 backlight_on_min; | |
| + u16 backlight_on_max; | |
| +}; | |
| + | |
| +struct apple_backlight_set_report { | |
| + u8 report_id; | |
| + u8 version; | |
| + u16 backlight; | |
| + u16 rate; | |
| +}; | |
| + | |
| +struct apple_key_translation { | |
| + u16 from; | |
| + u16 to; | |
| + u8 flags; | |
| +}; | |
| + | |
| +struct apple_non_apple_keyboard { | |
| + char *name; | |
| +}; | |
| + | |
| +struct hid_device; | |
| + | |
| +struct apple_sc_backlight; | |
| + | |
| +struct apple_sc { | |
| + struct hid_device *hdev; | |
| + long unsigned int quirks; | |
| + unsigned int fn_on; | |
| + unsigned int fn_found; | |
| + long unsigned int pressed_numlock[12]; | |
| + struct timer_list battery_timer; | |
| + struct apple_sc_backlight *backlight; | |
| +}; | |
| + | |
| +struct led_pattern; | |
| + | |
| +struct led_trigger; | |
| + | |
| +struct led_hw_trigger_type; | |
| + | |
| +struct led_classdev { | |
| + const char *name; | |
| + unsigned int brightness; | |
| + unsigned int max_brightness; | |
| + unsigned int color; | |
| + int flags; | |
| + long unsigned int work_flags; | |
| + void (*brightness_set)(struct led_classdev *, enum led_brightness); | |
| + int (*brightness_set_blocking)(struct led_classdev *, enum led_brightness); | |
| + enum led_brightness (*brightness_get)(struct led_classdev *); | |
| + int (*blink_set)(struct led_classdev *, long unsigned int *, long unsigned int *); | |
| + int (*pattern_set)(struct led_classdev *, struct led_pattern *, u32, int); | |
| + int (*pattern_clear)(struct led_classdev *); | |
| + struct device *dev; | |
| + const struct attribute_group **groups; | |
| + struct list_head node; | |
| + const char *default_trigger; | |
| + long unsigned int blink_delay_on; | |
| + long unsigned int blink_delay_off; | |
| + struct timer_list blink_timer; | |
| + int blink_brightness; | |
| + int new_blink_brightness; | |
| + void (*flash_resume)(struct led_classdev *); | |
| + struct work_struct set_brightness_work; | |
| + int delayed_set_value; | |
| + long unsigned int delayed_delay_on; | |
| + long unsigned int delayed_delay_off; | |
| + struct rw_semaphore trigger_lock; | |
| + struct led_trigger *trigger; | |
| + struct list_head trig_list; | |
| + void *trigger_data; | |
| + bool activated; | |
| + struct led_hw_trigger_type *trigger_type; | |
| + const char *hw_control_trigger; | |
| + int (*hw_control_is_supported)(struct led_classdev *, long unsigned int); | |
| + int (*hw_control_set)(struct led_classdev *, long unsigned int); | |
| + int (*hw_control_get)(struct led_classdev *, long unsigned int *); | |
| + struct device * (*hw_control_get_device)(struct led_classdev *); | |
| + struct mutex led_access; | |
| +}; | |
| + | |
| +struct apple_sc_backlight { | |
| + struct led_classdev cdev; | |
| + struct hid_device *hdev; | |
| +}; | |
| + | |
| struct workqueue_attrs; | |
| struct pool_workqueue; | |
| @@ -35347,11 +45296,17 @@ | |
| struct pool_workqueue *pwq_tbl[0]; | |
| }; | |
| +struct arc4_ctx { | |
| + u32 S[256]; | |
| + u32 x; | |
| + u32 y; | |
| +}; | |
| + | |
| struct arch_elf_state {}; | |
| struct arch_hw_breakpoint { | |
| - unsigned long address; | |
| - unsigned long mask; | |
| + long unsigned int address; | |
| + long unsigned int mask; | |
| u8 len; | |
| u8 type; | |
| }; | |
| @@ -35376,11 +45331,6 @@ | |
| struct lbr_entry entries[0]; | |
| }; | |
| -struct arch_mbm_state { | |
| - u64 chunks; | |
| - u64 prev_msr; | |
| -}; | |
| - | |
| struct arch_optimized_insn { | |
| kprobe_opcode_t copied_insn[4]; | |
| kprobe_opcode_t *insn; | |
| @@ -35443,7 +45393,7 @@ | |
| }; | |
| struct arch_uprobe_task { | |
| - unsigned long saved_scratch_register; | |
| + long unsigned int saved_scratch_register; | |
| unsigned int saved_trap_nr; | |
| unsigned int saved_tf; | |
| }; | |
| @@ -35451,7 +45401,6 @@ | |
| struct arch_vdso_data {}; | |
| struct arg_dev_net_ip { | |
| - struct net_device *dev; | |
| struct net *net; | |
| struct in6_addr *addr; | |
| }; | |
| @@ -35460,20 +45409,66 @@ | |
| const struct net_device *dev; | |
| union { | |
| unsigned char nh_flags; | |
| - unsigned long event; | |
| + long unsigned int event; | |
| }; | |
| }; | |
| -struct ark3116_private { | |
| - int irda; | |
| - struct mutex hw_lock; | |
| - int quot; | |
| - __u32 lcr; | |
| - __u32 hcr; | |
| - __u32 mcr; | |
| - spinlock_t status_lock; | |
| - __u32 msr; | |
| - __u32 lsr; | |
| +struct args_askumount { | |
| + __u32 may_umount; | |
| +}; | |
| + | |
| +struct args_expire { | |
| + __u32 how; | |
| +}; | |
| + | |
| +struct args_fail { | |
| + __u32 token; | |
| + __s32 status; | |
| +}; | |
| + | |
| +struct args_in { | |
| + __u32 type; | |
| +}; | |
| + | |
| +struct args_out { | |
| + __u32 devid; | |
| + __u32 magic; | |
| +}; | |
| + | |
| +struct args_ismountpoint { | |
| + union { | |
| + struct args_in in; | |
| + struct args_out out; | |
| + }; | |
| +}; | |
| + | |
| +struct args_openmount { | |
| + __u32 devid; | |
| +}; | |
| + | |
| +struct args_protosubver { | |
| + __u32 sub_version; | |
| +}; | |
| + | |
| +struct args_protover { | |
| + __u32 version; | |
| +}; | |
| + | |
| +struct args_ready { | |
| + __u32 token; | |
| +}; | |
| + | |
| +struct args_requester { | |
| + __u32 uid; | |
| + __u32 gid; | |
| +}; | |
| + | |
| +struct args_setpipefd { | |
| + __s32 pipefd; | |
| +}; | |
| + | |
| +struct args_timeout { | |
| + __u64 timeout; | |
| }; | |
| struct arphdr { | |
| @@ -35512,11 +45507,475 @@ | |
| struct array_buffer { | |
| struct trace_array *tr; | |
| struct trace_buffer *buffer; | |
| - struct trace_array_cpu __attribute__((btf_type_tag("percpu"))) *data; | |
| + struct trace_array_cpu *data; | |
| u64 time_start; | |
| int cpu; | |
| }; | |
| +struct asd_dma_tok { | |
| + void *vaddr; | |
| + dma_addr_t dma_handle; | |
| + size_t size; | |
| +}; | |
| + | |
| +struct asd_ha_struct; | |
| + | |
| +struct scb___3; | |
| + | |
| +struct done_list_struct; | |
| + | |
| +struct asd_ascb { | |
| + struct list_head list; | |
| + struct asd_ha_struct *ha; | |
| + struct scb___3 *scb; | |
| + struct asd_dma_tok dma_scb; | |
| + struct asd_dma_tok *sg_arr; | |
| + void (*tasklet_complete)(struct asd_ascb *, struct done_list_struct *); | |
| + u8 uldd_timer: 1; | |
| + struct timer_list timer; | |
| + struct completion *completion; | |
| + u8 tag_valid: 1; | |
| + __be16 tag; | |
| + int edb_index; | |
| + int tc_index; | |
| + void *uldd_task; | |
| +}; | |
| + | |
| +struct asd_bios_chim_struct { | |
| + char sig[4]; | |
| + u8 major; | |
| + u8 minor; | |
| + u8 bios_major; | |
| + u8 bios_minor; | |
| + __le32 bios_build; | |
| + u8 flags; | |
| + u8 pci_slot; | |
| + __le16 ue_num; | |
| + __le16 ue_size; | |
| + u8 _r[14]; | |
| +}; | |
| + | |
| +struct asd_ctrla_phy_entry { | |
| + u8 sas_addr[8]; | |
| + u8 sas_link_rates; | |
| + u8 flags; | |
| + u8 sata_link_rates; | |
| + u8 _r[5]; | |
| +}; | |
| + | |
| +struct asd_ctrla_phy_settings { | |
| + u8 id0; | |
| + u8 _r; | |
| + u16 next; | |
| + u8 num_phys; | |
| + u8 _r2[3]; | |
| + struct asd_ctrla_phy_entry phy_ent[8]; | |
| +}; | |
| + | |
| +struct asd_flash_de { | |
| + __le32 type; | |
| + __le32 offs; | |
| + __le32 pad_size; | |
| + __le32 image_size; | |
| + __le32 chksum; | |
| + u8 _r[12]; | |
| + u8 version[32]; | |
| +}; | |
| + | |
| +struct asd_flash_dir { | |
| + u8 cookie[32]; | |
| + __le32 rev; | |
| + __le32 chksum; | |
| + __le32 chksum_antidote; | |
| + __le32 bld; | |
| + u8 bld_id[32]; | |
| + u8 ver_data[32]; | |
| + __le32 ae_mask; | |
| + __le32 v_mask; | |
| + __le32 oc_mask; | |
| + u8 _r[20]; | |
| + struct asd_flash_de dir_entry[32]; | |
| +}; | |
| + | |
| +struct asd_ha_addrspace { | |
| + void *addr; | |
| + long unsigned int start; | |
| + long unsigned int len; | |
| + long unsigned int flags; | |
| + u32 swa_base; | |
| + u32 swb_base; | |
| + u32 swc_base; | |
| +}; | |
| + | |
| +struct asd_sas_phy; | |
| + | |
| +struct asd_sas_port; | |
| + | |
| +struct sas_ha_struct { | |
| + struct list_head defer_q; | |
| + struct mutex drain_mutex; | |
| + long unsigned int state; | |
| + spinlock_t lock; | |
| + int eh_active; | |
| + wait_queue_head_t eh_wait_q; | |
| + struct list_head eh_dev_q; | |
| + struct mutex disco_mutex; | |
| + struct Scsi_Host *shost; | |
| + char *sas_ha_name; | |
| + struct device *dev; | |
| + struct workqueue_struct *event_q; | |
| + struct workqueue_struct *disco_q; | |
| + u8 *sas_addr; | |
| + u8 hashed_sas_addr[3]; | |
| + spinlock_t phy_port_lock; | |
| + struct asd_sas_phy **sas_phy; | |
| + struct asd_sas_port **sas_port; | |
| + int num_phys; | |
| + int strict_wide_ports; | |
| + void *lldd_ha; | |
| + struct list_head eh_done_q; | |
| + struct list_head eh_ata_q; | |
| + int event_thres; | |
| +}; | |
| + | |
| +struct bios_struct { | |
| + int present; | |
| + u8 maj; | |
| + u8 min; | |
| + u32 bld; | |
| +}; | |
| + | |
| +struct unit_element_struct { | |
| + u16 num; | |
| + u16 size; | |
| + void *area; | |
| +}; | |
| + | |
| +struct flash_struct { | |
| + u32 bar; | |
| + int present; | |
| + int wide; | |
| + u8 manuf; | |
| + u8 dev_id; | |
| + u8 sec_prot; | |
| + u8 method; | |
| + u32 dir_offs; | |
| +}; | |
| + | |
| +struct asd_phy_desc { | |
| + u8 sas_addr[8]; | |
| + u8 max_sas_lrate; | |
| + u8 min_sas_lrate; | |
| + u8 max_sata_lrate; | |
| + u8 min_sata_lrate; | |
| + u8 flags; | |
| + u8 phy_control_0; | |
| + u8 phy_control_1; | |
| + u8 phy_control_2; | |
| + u8 phy_control_3; | |
| +}; | |
| + | |
| +struct hw_profile { | |
| + struct bios_struct bios; | |
| + struct unit_element_struct ue; | |
| + struct flash_struct flash; | |
| + u8 sas_addr[8]; | |
| + char pcba_sn[13]; | |
| + u8 enabled_phys; | |
| + struct asd_phy_desc phy_desc[8]; | |
| + u32 max_scbs; | |
| + struct asd_dma_tok *scb_ext; | |
| + u32 max_ddbs; | |
| + struct asd_dma_tok *ddb_ext; | |
| + spinlock_t ddb_lock; | |
| + void *ddb_bitmap; | |
| + int num_phys; | |
| + int max_phys; | |
| + unsigned int addr_range; | |
| + unsigned int port_name_base; | |
| + unsigned int dev_name_base; | |
| + unsigned int sata_name_base; | |
| +}; | |
| + | |
| +struct sas_phy; | |
| + | |
| +struct asd_sas_phy { | |
| + atomic_t event_nr; | |
| + int in_shutdown; | |
| + int error; | |
| + int suspended; | |
| + struct sas_phy *phy; | |
| + int enabled; | |
| + int id; | |
| + enum sas_protocol iproto; | |
| + enum sas_protocol tproto; | |
| + enum sas_phy_role role; | |
| + enum sas_oob_mode oob_mode; | |
| + enum sas_linkrate linkrate; | |
| + u8 *sas_addr; | |
| + u8 attached_sas_addr[8]; | |
| + spinlock_t frame_rcvd_lock; | |
| + u8 *frame_rcvd; | |
| + int frame_rcvd_size; | |
| + spinlock_t sas_prim_lock; | |
| + u32 sas_prim; | |
| + struct list_head port_phy_el; | |
| + struct asd_sas_port *port; | |
| + struct sas_ha_struct *ha; | |
| + void *lldd_phy; | |
| +}; | |
| + | |
| +struct sas_identify_frame; | |
| + | |
| +struct asd_port; | |
| + | |
| +struct asd_phy { | |
| + struct asd_sas_phy sas_phy; | |
| + struct asd_phy_desc *phy_desc; | |
| + struct sas_identify_frame *identify_frame; | |
| + struct asd_dma_tok *id_frm_tok; | |
| + struct asd_port *asd_port; | |
| + u8 frame_rcvd[1068]; | |
| +}; | |
| + | |
| +struct asd_port { | |
| + u8 sas_addr[8]; | |
| + u8 attached_sas_addr[8]; | |
| + u32 phy_mask; | |
| + int num_phys; | |
| +}; | |
| + | |
| +struct sas_work { | |
| + struct list_head drain_node; | |
| + struct work_struct work; | |
| +}; | |
| + | |
| +struct sas_discovery_event { | |
| + struct sas_work work; | |
| + struct asd_sas_port *port; | |
| +}; | |
| + | |
| +struct sas_discovery { | |
| + struct sas_discovery_event disc_work[4]; | |
| + long unsigned int pending; | |
| + u8 fanout_sas_addr[8]; | |
| + u8 eeds_a[8]; | |
| + u8 eeds_b[8]; | |
| + int max_level; | |
| +}; | |
| + | |
| +struct domain_device; | |
| + | |
| +struct sas_port; | |
| + | |
| +struct asd_sas_port { | |
| + struct sas_discovery disc; | |
| + struct domain_device *port_dev; | |
| + spinlock_t dev_list_lock; | |
| + struct list_head dev_list; | |
| + struct list_head disco_list; | |
| + struct list_head destroy_list; | |
| + struct list_head sas_port_del_list; | |
| + enum sas_linkrate linkrate; | |
| + struct sas_work work; | |
| + int suspended; | |
| + int id; | |
| + u8 sas_addr[8]; | |
| + u8 attached_sas_addr[8]; | |
| + enum sas_protocol iproto; | |
| + enum sas_protocol tproto; | |
| + enum sas_oob_mode oob_mode; | |
| + spinlock_t phy_list_lock; | |
| + struct list_head phy_list; | |
| + int num_phys; | |
| + u32 phy_mask; | |
| + struct sas_ha_struct *ha; | |
| + struct sas_port *port; | |
| + void *lldd_port; | |
| +}; | |
| + | |
| +struct tasklet_struct { | |
| + struct tasklet_struct *next; | |
| + long unsigned int state; | |
| + atomic_t count; | |
| + bool use_callback; | |
| + union { | |
| + void (*func)(long unsigned int); | |
| + void (*callback)(struct tasklet_struct *); | |
| + }; | |
| + long unsigned int data; | |
| +}; | |
| + | |
| +struct asd_seq_data { | |
| + spinlock_t pend_q_lock; | |
| + u16 scbpro; | |
| + int pending; | |
| + struct list_head pend_q; | |
| + int can_queue; | |
| + struct asd_dma_tok next_scb; | |
| + spinlock_t tc_index_lock; | |
| + void **tc_index_array; | |
| + void *tc_index_bitmap; | |
| + int tc_index_bitmap_bits; | |
| + struct tasklet_struct dl_tasklet; | |
| + struct done_list_struct *dl; | |
| + struct asd_dma_tok *actual_dl; | |
| + int dl_toggle; | |
| + int dl_next; | |
| + int num_edbs; | |
| + struct asd_dma_tok **edb_arr; | |
| + int num_escbs; | |
| + struct asd_ascb **escb_arr; | |
| +}; | |
| + | |
| +struct dma_pool; | |
| + | |
| +struct firmware; | |
| + | |
| +struct asd_ha_struct { | |
| + struct pci_dev *pcidev; | |
| + const char *name; | |
| + struct sas_ha_struct sas_ha; | |
| + u8 revision_id; | |
| + int iospace; | |
| + spinlock_t iolock; | |
| + struct asd_ha_addrspace io_handle[2]; | |
| + struct hw_profile hw_prof; | |
| + struct asd_phy phys[8]; | |
| + spinlock_t asd_ports_lock; | |
| + struct asd_port asd_ports[8]; | |
| + struct asd_sas_port ports[8]; | |
| + struct dma_pool *scb_pool; | |
| + struct asd_seq_data seq; | |
| + u32 bios_status; | |
| + const struct firmware *bios_image; | |
| +}; | |
| + | |
| +struct asd_ll_el { | |
| + u8 id0; | |
| + u8 id1; | |
| + __le16 next; | |
| + u8 something_here[0]; | |
| +}; | |
| + | |
| +struct asd_manuf_phy_desc { | |
| + u8 state; | |
| + u8 phy_id; | |
| + u16 _r; | |
| + u8 phy_control_0; | |
| + u8 phy_control_1; | |
| + u8 phy_control_2; | |
| + u8 phy_control_3; | |
| +}; | |
| + | |
| +struct asd_manuf_phy_param { | |
| + char sig[2]; | |
| + u16 next; | |
| + u8 maj; | |
| + u8 min; | |
| + u8 num_phy_desc; | |
| + u8 phy_desc_size; | |
| + u8 _r[3]; | |
| + u8 usage_model_id; | |
| + u32 _r2; | |
| + struct asd_manuf_phy_desc phy_desc[8]; | |
| +}; | |
| + | |
| +struct asd_manuf_sec { | |
| + char sig[2]; | |
| + u16 offs_next; | |
| + u8 maj; | |
| + u8 min; | |
| + u16 chksum; | |
| + u16 size; | |
| + u8 _r[6]; | |
| + u8 sas_addr[8]; | |
| + u8 pcba_sn[12]; | |
| + u8 linked_list[0]; | |
| +}; | |
| + | |
| +struct asd_ms_sb_desc { | |
| + u8 type; | |
| + u8 node_desc_index; | |
| + u8 conn_desc_index; | |
| + u8 _recvd[0]; | |
| +}; | |
| + | |
| +struct asd_ms_conn_desc { | |
| + u8 type; | |
| + u8 location; | |
| + u8 num_sideband_desc; | |
| + u8 size_sideband_desc; | |
| + u32 _resvd; | |
| + u8 name[16]; | |
| + struct asd_ms_sb_desc sb_desc[0]; | |
| +}; | |
| + | |
| +struct asd_nd_phy_desc { | |
| + u8 vp_attch_type; | |
| + u8 attch_specific[0]; | |
| +}; | |
| + | |
| +struct asd_ms_node_desc { | |
| + u8 type; | |
| + u8 num_phy_desc; | |
| + u8 size_phy_desc; | |
| + u8 _resvd; | |
| + u8 name[16]; | |
| + struct asd_nd_phy_desc phy_desc[0]; | |
| +}; | |
| + | |
| +struct asd_ms_conn_map { | |
| + char sig[2]; | |
| + __le16 next; | |
| + u8 maj; | |
| + u8 min; | |
| + __le16 cm_size; | |
| + u8 num_conn; | |
| + u8 conn_size; | |
| + u8 num_nodes; | |
| + u8 usage_model_id; | |
| + u32 _resvd; | |
| + union { | |
| + struct { | |
| + struct {} __empty_conn_desc; | |
| + struct asd_ms_conn_desc conn_desc[0]; | |
| + }; | |
| + struct { | |
| + struct {} __empty_node_desc; | |
| + struct asd_ms_node_desc node_desc[0]; | |
| + }; | |
| + }; | |
| +}; | |
| + | |
| +struct asd_ocm_dir_ent { | |
| + u8 type; | |
| + u8 offs[3]; | |
| + u8 _r1; | |
| + u8 size[3]; | |
| +}; | |
| + | |
| +struct asd_ocm_dir { | |
| + char sig[2]; | |
| + u8 _r1[2]; | |
| + u8 major; | |
| + u8 minor; | |
| + u8 _r2; | |
| + u8 num_de; | |
| + struct asd_ocm_dir_ent entry[15]; | |
| +}; | |
| + | |
| +struct asd_pcidev_struct { | |
| + const char *name; | |
| + int (*setup)(struct asd_ha_struct *); | |
| +}; | |
| + | |
| +struct asd_sas_event { | |
| + struct sas_work work; | |
| + struct asd_sas_phy *phy; | |
| + int event; | |
| +}; | |
| + | |
| typedef int (*asn1_action_t)(void *, size_t, unsigned char, const void *, size_t); | |
| struct asn1_decoder { | |
| @@ -35529,7 +45988,7 @@ | |
| struct assoc_array { | |
| struct assoc_array_ptr *root; | |
| - unsigned long nr_leaves_on_tree; | |
| + long unsigned int nr_leaves_on_tree; | |
| }; | |
| struct assoc_array_node; | |
| @@ -35556,7 +46015,7 @@ | |
| struct assoc_array_ptr **set_backpointers[16]; | |
| struct assoc_array_ptr *set_backpointers_to; | |
| struct assoc_array_node *adjust_count_on; | |
| - long adjust_count_by; | |
| + long int adjust_count_by; | |
| struct { | |
| struct assoc_array_ptr **ptr; | |
| struct assoc_array_ptr *to; | |
| @@ -35572,12 +46031,12 @@ | |
| struct assoc_array_ptr *back_pointer; | |
| u8 parent_slot; | |
| struct assoc_array_ptr *slots[16]; | |
| - unsigned long nr_leaves_on_branch; | |
| + long unsigned int nr_leaves_on_branch; | |
| }; | |
| struct assoc_array_ops { | |
| - unsigned long (*get_key_chunk)(const void *, int); | |
| - unsigned long (*get_object_key_chunk)(const void *, int); | |
| + long unsigned int (*get_key_chunk)(const void *, int); | |
| + long unsigned int (*get_object_key_chunk)(const void *, int); | |
| bool (*compare_object)(const void *, const void *); | |
| int (*diff_objects)(const void *, const void *); | |
| void (*free_object)(void *); | |
| @@ -35588,7 +46047,7 @@ | |
| int parent_slot; | |
| int skip_to_level; | |
| struct assoc_array_ptr *next_node; | |
| - unsigned long index_key[0]; | |
| + long unsigned int index_key[0]; | |
| }; | |
| struct assoc_array_walk_result { | |
| @@ -35601,19 +46060,20 @@ | |
| struct assoc_array_shortcut *shortcut; | |
| int level; | |
| int sc_level; | |
| - unsigned long sc_segments; | |
| - unsigned long dissimilarity; | |
| + long unsigned int sc_segments; | |
| + long unsigned int dissimilarity; | |
| } wrong_shortcut; | |
| }; | |
| struct asym_cap_data { | |
| struct list_head link; | |
| - unsigned long capacity; | |
| - unsigned long cpus[0]; | |
| + struct callback_head rcu; | |
| + long unsigned int capacity; | |
| + long unsigned int cpus[0]; | |
| }; | |
| struct asymmetric_key_id { | |
| - unsigned short len; | |
| + short unsigned int len; | |
| unsigned char data[0]; | |
| }; | |
| @@ -35643,7 +46103,7 @@ | |
| struct asymmetric_key_subtype { | |
| struct module *owner; | |
| const char *name; | |
| - unsigned short name_len; | |
| + short unsigned int name_len; | |
| void (*describe)(const struct key *, struct seq_file *); | |
| void (*destroy)(void *, void *); | |
| int (*query)(const struct kernel_pkey_params *, struct kernel_pkey_query *); | |
| @@ -35653,7 +46113,7 @@ | |
| union sigval { | |
| int sival_int; | |
| - void __attribute__((btf_type_tag("user"))) *sival_ptr; | |
| + void *sival_ptr; | |
| }; | |
| typedef union sigval sigval_t; | |
| @@ -35671,8 +46131,8 @@ | |
| const struct cred *cred; | |
| unsigned int signr; | |
| unsigned int ifnum; | |
| - void __attribute__((btf_type_tag("user"))) *userbuffer; | |
| - void __attribute__((btf_type_tag("user"))) *userurb; | |
| + void *userbuffer; | |
| + void *userurb; | |
| sigval_t userurb_sigval; | |
| struct urb *urb; | |
| struct usb_memory *usbm; | |
| @@ -35686,16 +46146,17 @@ | |
| typedef void (*btrfs_func_t)(struct btrfs_work *); | |
| +typedef void (*btrfs_ordered_func_t)(struct btrfs_work *, bool); | |
| + | |
| struct btrfs_workqueue; | |
| struct btrfs_work { | |
| btrfs_func_t func; | |
| - btrfs_func_t ordered_func; | |
| - btrfs_func_t ordered_free; | |
| + btrfs_ordered_func_t ordered_func; | |
| struct work_struct normal_work; | |
| struct list_head ordered_list; | |
| struct btrfs_workqueue *wq; | |
| - unsigned long flags; | |
| + long unsigned int flags; | |
| }; | |
| struct btrfs_inode; | |
| @@ -35742,26 +46203,12 @@ | |
| u64 start; | |
| u64 ram_size; | |
| u64 compressed_size; | |
| - struct page **pages; | |
| - unsigned long nr_pages; | |
| + struct folio **folios; | |
| + long unsigned int nr_folios; | |
| int compress_type; | |
| struct list_head list; | |
| }; | |
| -struct async_icount { | |
| - __u32 cts; | |
| - __u32 dsr; | |
| - __u32 rng; | |
| - __u32 dcd; | |
| - __u32 tx; | |
| - __u32 rx; | |
| - __u32 frame; | |
| - __u32 parity; | |
| - __u32 overrun; | |
| - __u32 brk; | |
| - __u32 buf_overrun; | |
| -}; | |
| - | |
| struct io_poll { | |
| struct file *file; | |
| struct wait_queue_head *head; | |
| @@ -35770,19 +46217,8 @@ | |
| struct wait_queue_entry wait; | |
| }; | |
| -struct io_wq_work_node { | |
| - struct io_wq_work_node *next; | |
| -}; | |
| - | |
| -struct io_cache_entry { | |
| - struct io_wq_work_node node; | |
| -}; | |
| - | |
| struct async_poll { | |
| - union { | |
| struct io_poll poll; | |
| - struct io_cache_entry cache; | |
| - }; | |
| struct io_poll *double_poll; | |
| }; | |
| @@ -35798,11 +46234,11 @@ | |
| struct btrfs_io_stripe { | |
| struct btrfs_device *dev; | |
| - union { | |
| u64 physical; | |
| + u64 length; | |
| + bool is_scrub; | |
| struct btrfs_io_context *bioc; | |
| }; | |
| -}; | |
| struct btrfs_bio; | |
| @@ -35814,32 +46250,6 @@ | |
| struct btrfs_work work; | |
| }; | |
| -struct at24_chip_data { | |
| - u32 byte_len; | |
| - u8 flags; | |
| - u8 bank_addr_shift; | |
| - void (*read_post)(unsigned int, char *, size_t); | |
| -}; | |
| - | |
| -struct nvmem_device; | |
| - | |
| -struct regmap; | |
| - | |
| -struct at24_data { | |
| - struct mutex lock; | |
| - unsigned int write_max; | |
| - unsigned int num_addresses; | |
| - unsigned int offset_adj; | |
| - u32 byte_len; | |
| - u16 page_size; | |
| - u8 flags; | |
| - struct nvmem_device *nvmem; | |
| - struct regulator *vcc_reg; | |
| - void (*read_post)(unsigned int, char *, size_t); | |
| - u8 bank_addr_shift; | |
| - struct regmap *client_regmaps[0]; | |
| -}; | |
| - | |
| struct ata_acpi_drive { | |
| u32 pio; | |
| u32 dma; | |
| @@ -35867,7 +46277,12 @@ | |
| struct ata_blacklist_entry { | |
| const char *model_num; | |
| const char *model_rev; | |
| - unsigned long horkage; | |
| + long unsigned int horkage; | |
| +}; | |
| + | |
| +struct ata_bmdma_prd { | |
| + __le32 addr; | |
| + __le32 flags_len; | |
| }; | |
| struct ata_cpr { | |
| @@ -35899,7 +46314,7 @@ | |
| struct ata_link *link; | |
| unsigned int devno; | |
| unsigned int horkage; | |
| - unsigned long flags; | |
| + long unsigned int flags; | |
| struct scsi_device *sdev; | |
| void *private_data; | |
| union acpi_object *gtf_cache; | |
| @@ -35908,7 +46323,7 @@ | |
| u64 n_sectors; | |
| u64 n_native_sectors; | |
| unsigned int class; | |
| - unsigned long unpark_deadline; | |
| + long unsigned int unpark_deadline; | |
| u8 pio_mode; | |
| u8 dma_mode; | |
| u8 xfer_mode; | |
| @@ -35925,8 +46340,6 @@ | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| - long: 64; | |
| - long: 64; | |
| union { | |
| u16 id[256]; | |
| u32 gscr[128]; | |
| @@ -35939,6 +46352,7 @@ | |
| u32 zac_zones_optimal_nonseq; | |
| u32 zac_zones_max_open; | |
| struct ata_cpr_log *cpr_log; | |
| + u8 cdl[512]; | |
| int spdn_cnt; | |
| struct ata_ering ering; | |
| long: 64; | |
| @@ -35970,13 +46384,13 @@ | |
| struct ata_eh_context { | |
| struct ata_eh_info i; | |
| int tries[2]; | |
| - int cmd_timeout_idx[14]; | |
| + int cmd_timeout_idx[16]; | |
| unsigned int classes[2]; | |
| unsigned int did_probe_mask; | |
| unsigned int unloaded_mask; | |
| unsigned int saved_ncq_enabled; | |
| u8 saved_xfer_mode[2]; | |
| - unsigned long last_reset; | |
| + long unsigned int last_reset; | |
| }; | |
| struct ata_force_param { | |
| @@ -36006,7 +46420,7 @@ | |
| unsigned int n_tags; | |
| void *private_data; | |
| struct ata_port_operations *ops; | |
| - unsigned long flags; | |
| + long unsigned int flags; | |
| struct kref kref; | |
| struct mutex eh_mutex; | |
| struct task_struct *eh_owner; | |
| @@ -36045,6 +46459,24 @@ | |
| struct device_attribute *dev_attrs[10]; | |
| }; | |
| +struct ata_ioports { | |
| + void *cmd_addr; | |
| + void *data_addr; | |
| + void *error_addr; | |
| + void *feature_addr; | |
| + void *nsect_addr; | |
| + void *lbal_addr; | |
| + void *lbam_addr; | |
| + void *lbah_addr; | |
| + void *device_addr; | |
| + void *status_addr; | |
| + void *command_addr; | |
| + void *altstatus_addr; | |
| + void *ctl_addr; | |
| + void *bmdma_addr; | |
| + void *scr_addr; | |
| +}; | |
| + | |
| struct ata_link { | |
| struct ata_port *ap; | |
| int pmp; | |
| @@ -36061,11 +46493,8 @@ | |
| struct ata_eh_context eh_context; | |
| long: 64; | |
| long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| struct ata_device device[2]; | |
| - unsigned long last_lpm_change; | |
| + long unsigned int last_lpm_change; | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| @@ -36076,7 +46505,7 @@ | |
| }; | |
| struct ata_taskfile { | |
| - unsigned long flags; | |
| + long unsigned int flags; | |
| u8 protocol; | |
| u8 ctl; | |
| u8 hob_feature; | |
| @@ -36104,8 +46533,6 @@ | |
| typedef void (*ata_qc_cb_t)(struct ata_queued_cmd *); | |
| -struct scsi_cmnd; | |
| - | |
| struct ata_queued_cmd { | |
| struct ata_port *ap; | |
| struct ata_device *dev; | |
| @@ -36113,7 +46540,7 @@ | |
| void (*scsidone)(struct scsi_cmnd *); | |
| struct ata_taskfile tf; | |
| u8 cdb[16]; | |
| - unsigned long flags; | |
| + long unsigned int flags; | |
| unsigned int tag; | |
| unsigned int hw_tag; | |
| unsigned int n_elem; | |
| @@ -36135,20 +46562,27 @@ | |
| }; | |
| struct ata_port_stats { | |
| - unsigned long unhandled_irq; | |
| - unsigned long idle_irq; | |
| - unsigned long rw_reqbuf; | |
| + long unsigned int unhandled_irq; | |
| + long unsigned int idle_irq; | |
| + long unsigned int rw_reqbuf; | |
| }; | |
| struct ata_port { | |
| struct Scsi_Host *scsi_host; | |
| struct ata_port_operations *ops; | |
| spinlock_t *lock; | |
| - unsigned long flags; | |
| + long unsigned int flags; | |
| unsigned int pflags; | |
| unsigned int print_id; | |
| unsigned int local_port_no; | |
| unsigned int port_no; | |
| + struct ata_ioports ioaddr; | |
| + u8 ctl; | |
| + u8 last_ctl; | |
| + struct ata_link *sff_pio_task_link; | |
| + struct delayed_work sff_pio_task; | |
| + struct ata_bmdma_prd *bmdma_prd; | |
| + dma_addr_t bmdma_prd_dma; | |
| unsigned int pio_mask; | |
| unsigned int mwdma_mask; | |
| unsigned int udma_mask; | |
| @@ -36181,14 +46615,15 @@ | |
| int em_message_type; | |
| void *private_data; | |
| struct ata_acpi_gtm __acpi_init_gtm; | |
| + u8 *ncq_sense_buf; | |
| long: 64; | |
| long: 64; | |
| u8 sector_buf[512]; | |
| }; | |
| struct ata_port_info { | |
| - unsigned long flags; | |
| - unsigned long link_flags; | |
| + long unsigned int flags; | |
| + long unsigned int link_flags; | |
| unsigned int pio_mask; | |
| unsigned int mwdma_mask; | |
| unsigned int udma_mask; | |
| @@ -36196,9 +46631,9 @@ | |
| void *private_data; | |
| }; | |
| -typedef int (*ata_prereset_fn_t)(struct ata_link *, unsigned long); | |
| +typedef int (*ata_prereset_fn_t)(struct ata_link *, long unsigned int); | |
| -typedef int (*ata_reset_fn_t)(struct ata_link *, unsigned int *, unsigned long); | |
| +typedef int (*ata_reset_fn_t)(struct ata_link *, unsigned int *, long unsigned int); | |
| typedef void (*ata_postreset_fn_t)(struct ata_link *, unsigned int *); | |
| @@ -36241,13 +46676,27 @@ | |
| int (*port_start)(struct ata_port *); | |
| void (*port_stop)(struct ata_port *); | |
| void (*host_stop)(struct ata_host *); | |
| + void (*sff_dev_select)(struct ata_port *, unsigned int); | |
| + void (*sff_set_devctl)(struct ata_port *, u8); | |
| + u8 (*sff_check_status)(struct ata_port *); | |
| + u8 (*sff_check_altstatus)(struct ata_port *); | |
| + void (*sff_tf_load)(struct ata_port *, const struct ata_taskfile *); | |
| + void (*sff_tf_read)(struct ata_port *, struct ata_taskfile *); | |
| + void (*sff_exec_command)(struct ata_port *, const struct ata_taskfile *); | |
| + unsigned int (*sff_data_xfer)(struct ata_queued_cmd *, unsigned char *, unsigned int, int); | |
| + void (*sff_irq_on)(struct ata_port *); | |
| + bool (*sff_irq_check)(struct ata_port *); | |
| + void (*sff_irq_clear)(struct ata_port *); | |
| + void (*sff_drain_fifo)(struct ata_queued_cmd *); | |
| + void (*bmdma_setup)(struct ata_queued_cmd *); | |
| + void (*bmdma_start)(struct ata_queued_cmd *); | |
| + void (*bmdma_stop)(struct ata_queued_cmd *); | |
| + u8 (*bmdma_status)(struct ata_port *); | |
| ssize_t (*em_show)(struct ata_port *, char *); | |
| ssize_t (*em_store)(struct ata_port *, const char *, size_t); | |
| ssize_t (*sw_activity_show)(struct ata_device *, char *); | |
| ssize_t (*sw_activity_store)(struct ata_device *, enum sw_activity); | |
| ssize_t (*transmit_led_message)(struct ata_port *, u32, ssize_t); | |
| - void (*phy_reset)(struct ata_port *); | |
| - void (*eng_timeout)(struct ata_port *); | |
| const struct ata_port_operations *inherits; | |
| }; | |
| @@ -36262,17 +46711,22 @@ | |
| int written; | |
| }; | |
| +struct ata_task_resp { | |
| + u16 frame_len; | |
| + u8 ending_fis[24]; | |
| +}; | |
| + | |
| struct ata_timing { | |
| - unsigned short mode; | |
| - unsigned short setup; | |
| - unsigned short act8b; | |
| - unsigned short rec8b; | |
| - unsigned short cyc8b; | |
| - unsigned short active; | |
| - unsigned short recover; | |
| - unsigned short dmack_hold; | |
| - unsigned short cycle; | |
| - unsigned short udma; | |
| + short unsigned int mode; | |
| + short unsigned int setup; | |
| + short unsigned int act8b; | |
| + short unsigned int rec8b; | |
| + short unsigned int cyc8b; | |
| + short unsigned int active; | |
| + short unsigned int recover; | |
| + short unsigned int dmack_hold; | |
| + short unsigned int cycle; | |
| + short unsigned int udma; | |
| }; | |
| struct ata_xfer_ent { | |
| @@ -36281,16 +46735,24 @@ | |
| u8 base; | |
| }; | |
| +struct ps2dev; | |
| + | |
| +typedef enum ps2_disposition (*ps2_pre_receive_handler_t)(struct ps2dev *, u8, unsigned int); | |
| + | |
| +typedef void (*ps2_receive_handler_t)(struct ps2dev *, u8); | |
| + | |
| struct serio; | |
| struct ps2dev { | |
| struct serio *serio; | |
| struct mutex cmd_mutex; | |
| wait_queue_head_t wait; | |
| - unsigned long flags; | |
| + long unsigned int flags; | |
| u8 cmdbuf[8]; | |
| u8 cmdcnt; | |
| u8 nak; | |
| + ps2_pre_receive_handler_t pre_receive_handler; | |
| + ps2_receive_handler_t receive_handler; | |
| }; | |
| struct vivaldi_data { | |
| @@ -36298,16 +46760,14 @@ | |
| unsigned int num_function_row_keys; | |
| }; | |
| -struct input_dev; | |
| - | |
| struct atkbd { | |
| struct ps2dev ps2dev; | |
| struct input_dev *dev; | |
| char name[64]; | |
| char phys[32]; | |
| - unsigned short id; | |
| - unsigned short keycode[512]; | |
| - unsigned long force_release_mask[8]; | |
| + short unsigned int id; | |
| + short unsigned int keycode[512]; | |
| + long unsigned int force_release_mask[8]; | |
| unsigned char set; | |
| bool translated; | |
| bool extra; | |
| @@ -36319,13 +46779,13 @@ | |
| unsigned char emul; | |
| bool resend; | |
| bool release; | |
| - unsigned long xl_bit; | |
| + long unsigned int xl_bit; | |
| unsigned int last; | |
| - unsigned long time; | |
| - unsigned long err_count; | |
| + long unsigned int time; | |
| + long unsigned int err_count; | |
| struct delayed_work event_work; | |
| - unsigned long event_jiffies; | |
| - unsigned long event_mask; | |
| + long unsigned int event_jiffies; | |
| + long unsigned int event_mask; | |
| struct mutex mutex; | |
| struct vivaldi_data vdata; | |
| }; | |
| @@ -36334,7 +46794,7 @@ | |
| struct atomic_notifier_head { | |
| spinlock_t lock; | |
| - struct notifier_block __attribute__((btf_type_tag("rcu"))) *head; | |
| + struct notifier_block *head; | |
| }; | |
| struct attribute_group { | |
| @@ -36404,7 +46864,7 @@ | |
| struct audit_chunk { | |
| struct list_head hash; | |
| - unsigned long key; | |
| + long unsigned int key; | |
| struct fsnotify_mark *mark; | |
| struct list_head trees; | |
| int count; | |
| @@ -36415,7 +46875,7 @@ | |
| struct timespec64 { | |
| time64_t tv_sec; | |
| - long tv_nsec; | |
| + long int tv_nsec; | |
| }; | |
| struct filename; | |
| @@ -36425,7 +46885,7 @@ | |
| struct filename *name; | |
| int name_len; | |
| bool hidden; | |
| - unsigned long ino; | |
| + long unsigned int ino; | |
| dev_t dev; | |
| umode_t mode; | |
| kuid_t uid; | |
| @@ -36460,8 +46920,8 @@ | |
| }; | |
| struct audit_ntp_val { | |
| - long long oldval; | |
| - long long newval; | |
| + long long int oldval; | |
| + long long int newval; | |
| }; | |
| struct audit_ntp_data { | |
| @@ -36488,8 +46948,8 @@ | |
| int major; | |
| int uring_op; | |
| struct timespec64 ctime; | |
| - unsigned long argv[4]; | |
| - long return_code; | |
| + long unsigned int argv[4]; | |
| + long int return_code; | |
| u64 prio; | |
| int return_valid; | |
| struct audit_names preallocated_names[5]; | |
| @@ -36510,7 +46970,7 @@ | |
| kgid_t egid; | |
| kgid_t sgid; | |
| kgid_t fsgid; | |
| - unsigned long personality; | |
| + long unsigned int personality; | |
| int arch; | |
| pid_t target_pid; | |
| kuid_t target_auid; | |
| @@ -36526,7 +46986,7 @@ | |
| union { | |
| struct { | |
| int nargs; | |
| - long args[6]; | |
| + long int args[6]; | |
| } socketcall; | |
| struct { | |
| kuid_t uid; | |
| @@ -36537,7 +46997,7 @@ | |
| uid_t perm_uid; | |
| gid_t perm_gid; | |
| umode_t perm_mode; | |
| - unsigned long qbytes; | |
| + long unsigned int qbytes; | |
| } ipc; | |
| struct { | |
| mqd_t mqdes; | |
| @@ -36658,7 +47118,7 @@ | |
| struct audit_fsnotify_mark { | |
| dev_t dev; | |
| - unsigned long ino; | |
| + long unsigned int ino; | |
| char *path; | |
| struct fsnotify_mark mark; | |
| struct audit_krule *rule; | |
| @@ -36756,7 +47216,7 @@ | |
| refcount_t count; | |
| dev_t dev; | |
| char *path; | |
| - unsigned long ino; | |
| + long unsigned int ino; | |
| struct audit_parent *parent; | |
| struct list_head wlist; | |
| struct list_head rules; | |
| @@ -36790,24 +47250,203 @@ | |
| char *name; | |
| struct module *owner; | |
| int flavour; | |
| - int (*accept)(struct svc_rqst *); | |
| + enum svc_auth_status (*accept)(struct svc_rqst *); | |
| int (*release)(struct svc_rqst *); | |
| void (*domain_release)(struct auth_domain *); | |
| - int (*set_client)(struct svc_rqst *); | |
| + enum svc_auth_status (*set_client)(struct svc_rqst *); | |
| + rpc_authflavor_t (*pseudoflavor)(struct svc_rqst *); | |
| +}; | |
| + | |
| +struct crypto_spawn { | |
| + struct list_head list; | |
| + struct crypto_alg *alg; | |
| + union { | |
| + struct crypto_instance *inst; | |
| + struct crypto_spawn *next; | |
| + }; | |
| + const struct crypto_type *frontend; | |
| + u32 mask; | |
| + bool dead; | |
| + bool registered; | |
| +}; | |
| + | |
| +struct crypto_ahash_spawn { | |
| + struct crypto_spawn base; | |
| +}; | |
| + | |
| +struct crypto_skcipher_spawn { | |
| + struct crypto_spawn base; | |
| +}; | |
| + | |
| +struct authenc_esn_instance_ctx { | |
| + struct crypto_ahash_spawn auth; | |
| + struct crypto_skcipher_spawn enc; | |
| +}; | |
| + | |
| +struct authenc_esn_request_ctx { | |
| + struct scatterlist src[2]; | |
| + struct scatterlist dst[2]; | |
| + char tail[0]; | |
| +}; | |
| + | |
| +struct authenc_instance_ctx { | |
| + struct crypto_ahash_spawn auth; | |
| + struct crypto_skcipher_spawn enc; | |
| + unsigned int reqoff; | |
| +}; | |
| + | |
| +struct authenc_request_ctx { | |
| + struct scatterlist src[2]; | |
| + struct scatterlist dst[2]; | |
| + char tail[0]; | |
| }; | |
| struct auto_mode_param { | |
| int qp_type; | |
| }; | |
| -struct auto_movable_group_stats { | |
| - unsigned long movable_pages; | |
| - unsigned long req_kernel_early_pages; | |
| +struct autofs_dev_ioctl { | |
| + __u32 ver_major; | |
| + __u32 ver_minor; | |
| + __u32 size; | |
| + __s32 ioctlfd; | |
| + union { | |
| + struct args_protover protover; | |
| + struct args_protosubver protosubver; | |
| + struct args_openmount openmount; | |
| + struct args_ready ready; | |
| + struct args_fail fail; | |
| + struct args_setpipefd setpipefd; | |
| + struct args_timeout timeout; | |
| + struct args_requester requester; | |
| + struct args_expire expire; | |
| + struct args_askumount askumount; | |
| + struct args_ismountpoint ismountpoint; | |
| + }; | |
| + char path[0]; | |
| }; | |
| -struct auto_movable_stats { | |
| - unsigned long kernel_early_pages; | |
| - unsigned long movable_pages; | |
| +struct autofs_fs_context { | |
| + kuid_t uid; | |
| + kgid_t gid; | |
| + int pgrp; | |
| + bool pgrp_set; | |
| +}; | |
| + | |
| +struct autofs_sb_info; | |
| + | |
| +struct autofs_info { | |
| + struct dentry *dentry; | |
| + int flags; | |
| + struct completion expire_complete; | |
| + struct list_head active; | |
| + struct list_head expiring; | |
| + struct autofs_sb_info *sbi; | |
| + long unsigned int last_used; | |
| + int count; | |
| + kuid_t uid; | |
| + kgid_t gid; | |
| + struct callback_head rcu; | |
| +}; | |
| + | |
| +struct autofs_packet_hdr { | |
| + int proto_version; | |
| + int type; | |
| +}; | |
| + | |
| +struct autofs_packet_expire { | |
| + struct autofs_packet_hdr hdr; | |
| + int len; | |
| + char name[256]; | |
| +}; | |
| + | |
| +struct autofs_packet_expire_multi { | |
| + struct autofs_packet_hdr hdr; | |
| + autofs_wqt_t wait_queue_token; | |
| + int len; | |
| + char name[256]; | |
| +}; | |
| + | |
| +struct autofs_packet_missing { | |
| + struct autofs_packet_hdr hdr; | |
| + autofs_wqt_t wait_queue_token; | |
| + int len; | |
| + char name[256]; | |
| +}; | |
| + | |
| +struct super_block; | |
| + | |
| +struct autofs_wait_queue; | |
| + | |
| +struct autofs_sb_info { | |
| + u32 magic; | |
| + int pipefd; | |
| + struct file *pipe; | |
| + struct pid *oz_pgrp; | |
| + int version; | |
| + int sub_version; | |
| + int min_proto; | |
| + int max_proto; | |
| + unsigned int flags; | |
| + long unsigned int exp_timeout; | |
| + unsigned int type; | |
| + struct super_block *sb; | |
| + struct mutex wq_mutex; | |
| + struct mutex pipe_mutex; | |
| + spinlock_t fs_lock; | |
| + struct autofs_wait_queue *queues; | |
| + spinlock_t lookup_lock; | |
| + struct list_head active_list; | |
| + struct list_head expiring_list; | |
| + struct callback_head rcu; | |
| +}; | |
| + | |
| +struct autofs_v5_packet { | |
| + struct autofs_packet_hdr hdr; | |
| + autofs_wqt_t wait_queue_token; | |
| + __u32 dev; | |
| + __u64 ino; | |
| + __u32 uid; | |
| + __u32 gid; | |
| + __u32 pid; | |
| + __u32 tgid; | |
| + __u32 len; | |
| + char name[256]; | |
| +}; | |
| + | |
| +typedef struct autofs_v5_packet autofs_packet_expire_direct_t; | |
| + | |
| +typedef struct autofs_v5_packet autofs_packet_expire_indirect_t; | |
| + | |
| +typedef struct autofs_v5_packet autofs_packet_missing_direct_t; | |
| + | |
| +typedef struct autofs_v5_packet autofs_packet_missing_indirect_t; | |
| + | |
| +struct qstr { | |
| + union { | |
| + struct { | |
| + u32 hash; | |
| + u32 len; | |
| + }; | |
| + u64 hash_len; | |
| + }; | |
| + const unsigned char *name; | |
| +}; | |
| + | |
| +struct autofs_wait_queue { | |
| + wait_queue_head_t queue; | |
| + struct autofs_wait_queue *next; | |
| + autofs_wqt_t wait_queue_token; | |
| + struct qstr name; | |
| + u32 offset; | |
| + u32 dev; | |
| + u64 ino; | |
| + kuid_t uid; | |
| + kgid_t gid; | |
| + pid_t pid; | |
| + pid_t tgid; | |
| + int status; | |
| + unsigned int wait_ctr; | |
| }; | |
| struct auxiliary_device { | |
| @@ -36912,7 +47551,7 @@ | |
| }; | |
| struct avg_latency_bucket { | |
| - unsigned long latency; | |
| + long unsigned int latency; | |
| bool valid; | |
| }; | |
| @@ -36953,11 +47592,20 @@ | |
| struct avtab_node *next; | |
| }; | |
| +struct backing_aio { | |
| + struct kiocb iocb; | |
| + refcount_t ref; | |
| + struct kiocb *orig_iocb; | |
| + void (*end_write)(struct file *); | |
| + struct work_struct work; | |
| + long int res; | |
| +}; | |
| + | |
| struct percpu_counter { | |
| raw_spinlock_t lock; | |
| s64 count; | |
| struct list_head list; | |
| - s32 __attribute__((btf_type_tag("percpu"))) *counters; | |
| + s32 *counters; | |
| }; | |
| struct fprop_local_percpu { | |
| @@ -36969,7 +47617,7 @@ | |
| struct percpu_ref_data; | |
| struct percpu_ref { | |
| - unsigned long percpu_count_ptr; | |
| + long unsigned int percpu_count_ptr; | |
| struct percpu_ref_data *data; | |
| }; | |
| @@ -36977,8 +47625,8 @@ | |
| struct bdi_writeback { | |
| struct backing_dev_info *bdi; | |
| - unsigned long state; | |
| - unsigned long last_old_flush; | |
| + long unsigned int state; | |
| + long unsigned int last_old_flush; | |
| struct list_head b_dirty; | |
| struct list_head b_io; | |
| struct list_head b_more_io; | |
| @@ -36986,13 +47634,13 @@ | |
| spinlock_t list_lock; | |
| atomic_t writeback_inodes; | |
| struct percpu_counter stat[4]; | |
| - unsigned long bw_time_stamp; | |
| - unsigned long dirtied_stamp; | |
| - unsigned long written_stamp; | |
| - unsigned long write_bandwidth; | |
| - unsigned long avg_write_bandwidth; | |
| - unsigned long dirty_ratelimit; | |
| - unsigned long balanced_dirty_ratelimit; | |
| + long unsigned int bw_time_stamp; | |
| + long unsigned int dirtied_stamp; | |
| + long unsigned int written_stamp; | |
| + long unsigned int write_bandwidth; | |
| + long unsigned int avg_write_bandwidth; | |
| + long unsigned int dirty_ratelimit; | |
| + long unsigned int balanced_dirty_ratelimit; | |
| struct fprop_local_percpu completions; | |
| int dirty_exceeded; | |
| enum wb_reason start_all_reason; | |
| @@ -37000,7 +47648,6 @@ | |
| struct list_head work_list; | |
| struct delayed_work dwork; | |
| struct delayed_work bw_dwork; | |
| - unsigned long dirty_sleep; | |
| struct list_head bdi_node; | |
| struct percpu_ref refcnt; | |
| struct fprop_local_percpu memcg_completions; | |
| @@ -37020,14 +47667,15 @@ | |
| u64 id; | |
| struct rb_node rb_node; | |
| struct list_head bdi_list; | |
| - unsigned long ra_pages; | |
| - unsigned long io_pages; | |
| + long unsigned int ra_pages; | |
| + long unsigned int io_pages; | |
| struct kref refcnt; | |
| unsigned int capabilities; | |
| unsigned int min_ratio; | |
| unsigned int max_ratio; | |
| unsigned int max_prop_frac; | |
| atomic_long_t tot_write_bandwidth; | |
| + long unsigned int last_bdp_sleep; | |
| struct bdi_writeback wb; | |
| struct list_head wb_list; | |
| struct xarray cgwb_tree; | |
| @@ -37041,6 +47689,103 @@ | |
| struct dentry *debug_dir; | |
| }; | |
| +struct fown_struct { | |
| + rwlock_t lock; | |
| + struct pid *pid; | |
| + enum pid_type pid_type; | |
| + kuid_t uid; | |
| + kuid_t euid; | |
| + int signum; | |
| +}; | |
| + | |
| +struct file_ra_state { | |
| + long unsigned int start; | |
| + unsigned int size; | |
| + unsigned int async_size; | |
| + unsigned int ra_pages; | |
| + unsigned int mmap_miss; | |
| + loff_t prev_pos; | |
| +}; | |
| + | |
| +struct file_operations; | |
| + | |
| +struct file { | |
| + union { | |
| + struct callback_head f_task_work; | |
| + struct llist_node f_llist; | |
| + unsigned int f_iocb_flags; | |
| + }; | |
| + spinlock_t f_lock; | |
| + fmode_t f_mode; | |
| + atomic_long_t f_count; | |
| + struct mutex f_pos_lock; | |
| + loff_t f_pos; | |
| + unsigned int f_flags; | |
| + struct fown_struct f_owner; | |
| + const struct cred *f_cred; | |
| + struct file_ra_state f_ra; | |
| + struct path f_path; | |
| + struct inode *f_inode; | |
| + const struct file_operations *f_op; | |
| + u64 f_version; | |
| + void *f_security; | |
| + void *private_data; | |
| + struct hlist_head *f_ep; | |
| + struct address_space *f_mapping; | |
| + errseq_t f_wb_err; | |
| + errseq_t f_sb_err; | |
| +}; | |
| + | |
| +struct backing_file { | |
| + struct file file; | |
| + struct path user_path; | |
| +}; | |
| + | |
| +struct backing_file_ctx { | |
| + const struct cred *cred; | |
| + struct file *user_file; | |
| + void (*accessed)(struct file *); | |
| + void (*end_write)(struct file *); | |
| +}; | |
| + | |
| +struct backlight_properties { | |
| + int brightness; | |
| + int max_brightness; | |
| + int power; | |
| + enum backlight_type type; | |
| + unsigned int state; | |
| + enum backlight_scale scale; | |
| +}; | |
| + | |
| +typedef int (*notifier_fn_t)(struct notifier_block *, long unsigned int, void *); | |
| + | |
| +struct notifier_block { | |
| + notifier_fn_t notifier_call; | |
| + struct notifier_block *next; | |
| + int priority; | |
| +}; | |
| + | |
| +struct backlight_ops; | |
| + | |
| +struct backlight_device { | |
| + struct backlight_properties props; | |
| + struct mutex update_lock; | |
| + struct mutex ops_lock; | |
| + const struct backlight_ops *ops; | |
| + struct notifier_block fb_notif; | |
| + struct list_head entry; | |
| + struct device dev; | |
| + bool fb_bl_on[32]; | |
| + int use_count; | |
| +}; | |
| + | |
| +struct backlight_ops { | |
| + unsigned int options; | |
| + int (*update_status)(struct backlight_device *); | |
| + int (*get_brightness)(struct backlight_device *); | |
| + bool (*controls_device)(struct backlight_device *, struct device *); | |
| +}; | |
| + | |
| struct btrfs_lru_cache_entry { | |
| struct list_head lru_list; | |
| u64 key; | |
| @@ -37078,6 +47823,7 @@ | |
| struct seqcount_spinlock { | |
| seqcount_t seqcount; | |
| + spinlock_t *lock; | |
| }; | |
| typedef struct seqcount_spinlock seqcount_spinlock_t; | |
| @@ -37099,6 +47845,12 @@ | |
| sector_t size; | |
| }; | |
| +struct badblocks_context { | |
| + sector_t start; | |
| + sector_t len; | |
| + int ack; | |
| +}; | |
| + | |
| struct rq; | |
| struct balance_callback { | |
| @@ -37107,7 +47859,7 @@ | |
| }; | |
| struct balloon_dev_info { | |
| - unsigned long isolated_pages; | |
| + long unsigned int isolated_pages; | |
| spinlock_t pages_lock; | |
| struct list_head pages; | |
| int (*migratepage)(struct balloon_dev_info *, struct page *, struct page *, enum migrate_mode); | |
| @@ -37137,33 +47889,36 @@ | |
| __u8 dest[6]; | |
| }; | |
| -typedef struct {} local_lock_t; | |
| +typedef struct { | |
| + struct lockdep_map dep_map; | |
| + struct task_struct *owner; | |
| +} local_lock_t; | |
| struct batch_u16 { | |
| u16 entropy[48]; | |
| local_lock_t lock; | |
| - unsigned long generation; | |
| + long unsigned int generation; | |
| unsigned int position; | |
| }; | |
| struct batch_u32 { | |
| u32 entropy[24]; | |
| local_lock_t lock; | |
| - unsigned long generation; | |
| + long unsigned int generation; | |
| unsigned int position; | |
| }; | |
| struct batch_u64 { | |
| u64 entropy[12]; | |
| local_lock_t lock; | |
| - unsigned long generation; | |
| + long unsigned int generation; | |
| unsigned int position; | |
| }; | |
| struct batch_u8 { | |
| u8 entropy[96]; | |
| local_lock_t lock; | |
| - unsigned long generation; | |
| + long unsigned int generation; | |
| unsigned int position; | |
| }; | |
| @@ -37227,7 +47982,7 @@ | |
| struct disk_stats; | |
| -struct super_block; | |
| +struct blk_holder_ops; | |
| struct partition_meta_info; | |
| @@ -37236,25 +47991,28 @@ | |
| sector_t bd_nr_sectors; | |
| struct gendisk *bd_disk; | |
| struct request_queue *bd_queue; | |
| - struct disk_stats __attribute__((btf_type_tag("percpu"))) *bd_stats; | |
| - unsigned long bd_stamp; | |
| + struct disk_stats *bd_stats; | |
| + long unsigned int bd_stamp; | |
| bool bd_read_only; | |
| u8 bd_partno; | |
| bool bd_write_holder; | |
| bool bd_has_submit_bio; | |
| dev_t bd_dev; | |
| + struct inode *bd_inode; | |
| + struct address_space *bd_mapping; | |
| atomic_t bd_openers; | |
| spinlock_t bd_size_lock; | |
| - struct inode *bd_inode; | |
| - struct super_block *bd_super; | |
| void *bd_claiming; | |
| void *bd_holder; | |
| - int bd_fsfreeze_count; | |
| + const struct blk_holder_ops *bd_holder_ops; | |
| + struct mutex bd_holder_lock; | |
| int bd_holders; | |
| struct kobject *bd_holder_dir; | |
| + atomic_t bd_fsfreeze_count; | |
| struct mutex bd_fsfreeze_mutex; | |
| - struct super_block *bd_fsfreeze_sb; | |
| struct partition_meta_info *bd_meta_info; | |
| + bool bd_ro_warned; | |
| + int bd_writers; | |
| struct device bd_device; | |
| }; | |
| @@ -37262,8 +48020,6 @@ | |
| struct inode_operations; | |
| -struct file_operations; | |
| - | |
| struct file_lock_context; | |
| struct pipe_inode_info; | |
| @@ -37274,7 +48030,7 @@ | |
| struct inode { | |
| umode_t i_mode; | |
| - unsigned short i_opflags; | |
| + short unsigned int i_opflags; | |
| kuid_t i_uid; | |
| kgid_t i_gid; | |
| unsigned int i_flags; | |
| @@ -37284,25 +48040,25 @@ | |
| struct super_block *i_sb; | |
| struct address_space *i_mapping; | |
| void *i_security; | |
| - unsigned long i_ino; | |
| + long unsigned int i_ino; | |
| union { | |
| const unsigned int i_nlink; | |
| unsigned int __i_nlink; | |
| }; | |
| dev_t i_rdev; | |
| loff_t i_size; | |
| - struct timespec64 i_atime; | |
| - struct timespec64 i_mtime; | |
| - struct timespec64 i_ctime; | |
| + struct timespec64 __i_atime; | |
| + struct timespec64 __i_mtime; | |
| + struct timespec64 __i_ctime; | |
| spinlock_t i_lock; | |
| - unsigned short i_bytes; | |
| + short unsigned int i_bytes; | |
| u8 i_blkbits; | |
| - u8 i_write_hint; | |
| + enum rw_hint i_write_hint; | |
| blkcnt_t i_blocks; | |
| - unsigned long i_state; | |
| + long unsigned int i_state; | |
| struct rw_semaphore i_rwsem; | |
| - unsigned long dirtied_when; | |
| - unsigned long dirtied_time_when; | |
| + long unsigned int dirtied_when; | |
| + long unsigned int dirtied_time_when; | |
| struct hlist_node i_hash; | |
| struct list_head i_io_list; | |
| struct bdi_writeback *i_wb; | |
| @@ -37337,7 +48093,7 @@ | |
| }; | |
| __u32 i_generation; | |
| __u32 i_fsnotify_mask; | |
| - struct fsnotify_mark_connector __attribute__((btf_type_tag("rcu"))) *i_fsnotify_marks; | |
| + struct fsnotify_mark_connector *i_fsnotify_marks; | |
| struct fsverity_info *i_verity_info; | |
| void *i_private; | |
| }; | |
| @@ -37347,15 +48103,27 @@ | |
| struct inode vfs_inode; | |
| }; | |
| +struct ieee80211_meshconf_ie; | |
| + | |
| +struct cfg80211_mbssid_elems; | |
| + | |
| +struct cfg80211_rnr_elems; | |
| + | |
| +struct beacon_data { | |
| + u8 *head; | |
| + u8 *tail; | |
| + int head_len; | |
| + int tail_len; | |
| + struct ieee80211_meshconf_ie *meshconf; | |
| + u16 cntdwn_counter_offsets[2]; | |
| + u8 cntdwn_current_counter; | |
| + struct cfg80211_mbssid_elems *mbssid_ies; | |
| + struct cfg80211_rnr_elems *rnr_ies; | |
| + struct callback_head callback_head; | |
| +}; | |
| + | |
| struct bgl_lock { | |
| spinlock_t lock; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| }; | |
| struct bh_accounting { | |
| @@ -37389,6 +48157,21 @@ | |
| u32 curr_rtt; | |
| }; | |
| +struct bictcp___2 { | |
| + u32 cnt; | |
| + u32 last_max_cwnd; | |
| + u32 last_cwnd; | |
| + u32 last_time; | |
| + u32 epoch_start; | |
| + u32 delayed_ack; | |
| +}; | |
| + | |
| +struct binfmt_misc { | |
| + struct list_head entries; | |
| + rwlock_t entries_lock; | |
| + bool enabled; | |
| +}; | |
| + | |
| struct bvec_iter { | |
| sector_t bi_sector; | |
| unsigned int bi_size; | |
| @@ -37412,30 +48195,29 @@ | |
| struct blkcg_gq; | |
| -struct bio_integrity_payload; | |
| - | |
| struct bio_set; | |
| struct bio { | |
| struct bio *bi_next; | |
| struct block_device *bi_bdev; | |
| blk_opf_t bi_opf; | |
| - unsigned short bi_flags; | |
| - unsigned short bi_ioprio; | |
| + short unsigned int bi_flags; | |
| + short unsigned int bi_ioprio; | |
| + enum rw_hint bi_write_hint; | |
| blk_status_t bi_status; | |
| atomic_t __bi_remaining; | |
| struct bvec_iter bi_iter; | |
| + union { | |
| blk_qc_t bi_cookie; | |
| + unsigned int __bi_nr_segments; | |
| + }; | |
| bio_end_io_t *bi_end_io; | |
| void *bi_private; | |
| struct blkcg_gq *bi_blkg; | |
| struct bio_issue bi_issue; | |
| - u64 bi_iocost_cost; | |
| - union { | |
| - struct bio_integrity_payload *bi_integrity; | |
| - }; | |
| - unsigned short bi_vcnt; | |
| - unsigned short bi_max_vecs; | |
| + union {}; | |
| + short unsigned int bi_vcnt; | |
| + short unsigned int bi_max_vecs; | |
| atomic_t __bi_cnt; | |
| struct bio_vec *bi_io_vec; | |
| struct bio_set *bi_pool; | |
| @@ -37449,25 +48231,13 @@ | |
| unsigned int nr_irq; | |
| }; | |
| -struct bio_integrity_payload { | |
| - struct bio *bip_bio; | |
| - struct bvec_iter bip_iter; | |
| - unsigned short bip_vcnt; | |
| - unsigned short bip_max_vcnt; | |
| - unsigned short bip_flags; | |
| - struct bvec_iter bio_iter; | |
| - struct work_struct bip_work; | |
| - struct bio_vec *bip_vec; | |
| - struct bio_vec bip_inline_vecs[0]; | |
| -}; | |
| - | |
| struct bio_list { | |
| struct bio *head; | |
| struct bio *tail; | |
| }; | |
| struct iovec { | |
| - void __attribute__((btf_type_tag("user"))) *iov_base; | |
| + void *iov_base; | |
| __kernel_size_t iov_len; | |
| }; | |
| @@ -37475,14 +48245,9 @@ | |
| struct iov_iter { | |
| u8 iter_type; | |
| - bool copy_mc; | |
| bool nofault; | |
| bool data_source; | |
| - bool user_backed; | |
| - union { | |
| size_t iov_offset; | |
| - int last_offset; | |
| - }; | |
| union { | |
| struct iovec __ubuf_iovec; | |
| struct { | |
| @@ -37491,18 +48256,13 @@ | |
| const struct kvec *kvec; | |
| const struct bio_vec *bvec; | |
| struct xarray *xarray; | |
| - struct pipe_inode_info *pipe; | |
| - void __attribute__((btf_type_tag("user"))) *ubuf; | |
| + void *ubuf; | |
| }; | |
| size_t count; | |
| }; | |
| }; | |
| union { | |
| - unsigned long nr_segs; | |
| - struct { | |
| - unsigned int head; | |
| - unsigned int start_head; | |
| - }; | |
| + long unsigned int nr_segs; | |
| loff_t xarray_start; | |
| }; | |
| }; | |
| @@ -37538,16 +48298,12 @@ | |
| typedef struct mempool_s mempool_t; | |
| -struct kmem_cache; | |
| - | |
| struct bio_set { | |
| struct kmem_cache *bio_slab; | |
| unsigned int front_pad; | |
| - struct bio_alloc_cache __attribute__((btf_type_tag("percpu"))) *cache; | |
| + struct bio_alloc_cache *cache; | |
| mempool_t bio_pool; | |
| mempool_t bvec_pool; | |
| - mempool_t bio_integrity_pool; | |
| - mempool_t bvec_integrity_pool; | |
| unsigned int back_pad; | |
| spinlock_t rescue_lock; | |
| struct bio_list rescue_list; | |
| @@ -37563,7 +48319,39 @@ | |
| char name[8]; | |
| }; | |
| -typedef struct bio_vec skb_frag_t; | |
| +struct bios_diskparam { | |
| + int heads; | |
| + int sectors; | |
| + int cylinders; | |
| +}; | |
| + | |
| +struct controller_id { | |
| + u32 vendor; | |
| + u32 device; | |
| + u32 sub_vendor; | |
| + u32 sub_device; | |
| +}; | |
| + | |
| +struct image_info { | |
| + u32 ImageId; | |
| + u32 ImageOffset; | |
| + u32 ImageLength; | |
| + u32 ImageChecksum; | |
| + u32 ImageVersion; | |
| +}; | |
| + | |
| +struct bios_file_header { | |
| + u8 signature[32]; | |
| + u32 checksum; | |
| + u32 antidote; | |
| + struct controller_id contrl_id; | |
| + u32 filelen; | |
| + u32 chunk_num; | |
| + u32 total_chunks; | |
| + u32 num_images; | |
| + u32 build_num; | |
| + struct image_info image_header; | |
| +}; | |
| struct biovec_slab { | |
| int nr_vecs; | |
| @@ -37576,19 +48364,20 @@ | |
| struct bitmap_counts { | |
| spinlock_t lock; | |
| struct bitmap_page *bp; | |
| - unsigned long pages; | |
| - unsigned long missing_pages; | |
| - unsigned long chunkshift; | |
| - unsigned long chunks; | |
| + long unsigned int pages; | |
| + long unsigned int missing_pages; | |
| + long unsigned int chunkshift; | |
| + long unsigned int chunks; | |
| }; | |
| struct bitmap_storage { | |
| struct file *file; | |
| struct page *sb_page; | |
| + long unsigned int sb_index; | |
| struct page **filemap; | |
| - unsigned long *filemap_attr; | |
| - unsigned long file_pages; | |
| - unsigned long bytes; | |
| + long unsigned int *filemap_attr; | |
| + long unsigned int file_pages; | |
| + long unsigned int bytes; | |
| }; | |
| struct mddev; | |
| @@ -37599,12 +48388,12 @@ | |
| __u64 events_cleared; | |
| int need_sync; | |
| struct bitmap_storage storage; | |
| - unsigned long flags; | |
| + long unsigned int flags; | |
| int allclean; | |
| atomic_t behind_writes; | |
| - unsigned long behind_writes_used; | |
| - unsigned long daemon_lastrun; | |
| - unsigned long last_end_sync; | |
| + long unsigned int behind_writes_used; | |
| + long unsigned int daemon_lastrun; | |
| + long unsigned int last_end_sync; | |
| atomic_t pending_writes; | |
| wait_queue_head_t write_wait; | |
| wait_queue_head_t overflow_wait; | |
| @@ -37614,7 +48403,7 @@ | |
| }; | |
| struct bitmap_iterator { | |
| - unsigned long *stats_bitmap; | |
| + long unsigned int *stats_bitmap; | |
| unsigned int count; | |
| unsigned int iterator; | |
| bool advance_array; | |
| @@ -37646,6 +48435,18 @@ | |
| typedef struct bitmap_super_s bitmap_super_t; | |
| +struct bitmap_unplug_work { | |
| + struct work_struct work; | |
| + struct bitmap *bitmap; | |
| + struct completion *done; | |
| +}; | |
| + | |
| +struct bl_dev_msg { | |
| + int32_t status; | |
| + uint32_t major; | |
| + uint32_t minor; | |
| +}; | |
| + | |
| struct blacklist_entry { | |
| struct list_head next; | |
| char *buf; | |
| @@ -37674,60 +48475,30 @@ | |
| unsigned int outlen; | |
| }; | |
| -struct blk_crypto_config { | |
| - enum blk_crypto_mode_num crypto_mode; | |
| - unsigned int data_unit_size; | |
| - unsigned int dun_bytes; | |
| -}; | |
| - | |
| -struct blk_crypto_key { | |
| - struct blk_crypto_config crypto_cfg; | |
| - unsigned int data_unit_size_bits; | |
| - unsigned int size; | |
| - u8 raw[64]; | |
| -}; | |
| - | |
| -struct blk_crypto_profile; | |
| - | |
| -struct blk_crypto_ll_ops { | |
| - int (*keyslot_program)(struct blk_crypto_profile *, const struct blk_crypto_key *, unsigned int); | |
| - int (*keyslot_evict)(struct blk_crypto_profile *, const struct blk_crypto_key *, unsigned int); | |
| -}; | |
| - | |
| -struct blk_crypto_keyslot; | |
| - | |
| -struct blk_crypto_profile { | |
| - struct blk_crypto_ll_ops ll_ops; | |
| - unsigned int max_dun_bytes_supported; | |
| - unsigned int modes_supported[5]; | |
| - struct device *dev; | |
| - unsigned int num_slots; | |
| - struct rw_semaphore lock; | |
| - wait_queue_head_t idle_slots_wait_queue; | |
| - struct list_head idle_slots; | |
| - spinlock_t idle_slots_lock; | |
| - struct hlist_head *slot_hashtable; | |
| - unsigned int log_slot_ht_size; | |
| - struct blk_crypto_keyslot *slots; | |
| -}; | |
| - | |
| struct blk_expired_data { | |
| bool has_timedout_rq; | |
| - unsigned long next; | |
| - unsigned long timeout_start; | |
| + long unsigned int next; | |
| + long unsigned int timeout_start; | |
| }; | |
| struct request; | |
| struct blk_flush_queue { | |
| + spinlock_t mq_flush_lock; | |
| unsigned int flush_pending_idx: 1; | |
| unsigned int flush_running_idx: 1; | |
| blk_status_t rq_status; | |
| - unsigned long flush_pending_since; | |
| + long unsigned int flush_pending_since; | |
| struct list_head flush_queue[2]; | |
| - struct list_head flush_data_in_flight; | |
| + long unsigned int flush_data_in_flight; | |
| struct request *flush_rq; | |
| - spinlock_t mq_flush_lock; | |
| +}; | |
| + | |
| +struct blk_holder_ops { | |
| + void (*mark_dead)(struct block_device *, bool); | |
| + void (*sync)(struct block_device *); | |
| + int (*freeze)(struct block_device *); | |
| + int (*thaw)(struct block_device *); | |
| }; | |
| struct blk_independent_access_range; | |
| @@ -37756,6 +48527,7 @@ | |
| const struct blk_integrity_profile *profile; | |
| unsigned char flags; | |
| unsigned char tuple_size; | |
| + unsigned char pi_offset; | |
| unsigned char interval_exp; | |
| unsigned char tag_size; | |
| }; | |
| @@ -37765,8 +48537,9 @@ | |
| void *data_buf; | |
| sector_t seed; | |
| unsigned int data_size; | |
| - unsigned short interval; | |
| + short unsigned int interval; | |
| unsigned char tuple_size; | |
| + unsigned char pi_offset; | |
| const char *disk_name; | |
| }; | |
| @@ -37804,24 +48577,6 @@ | |
| __be64 sector_from; | |
| }; | |
| -struct rq_qos_ops; | |
| - | |
| -struct rq_qos { | |
| - const struct rq_qos_ops *ops; | |
| - struct gendisk *disk; | |
| - enum rq_qos_id id; | |
| - struct rq_qos *next; | |
| - struct dentry *debugfs_dir; | |
| -}; | |
| - | |
| -struct blk_iolatency { | |
| - struct rq_qos rqos; | |
| - struct timer_list timer; | |
| - bool enabled; | |
| - atomic_t enable_cnt; | |
| - struct work_struct enable_work; | |
| -}; | |
| - | |
| struct blk_major_name { | |
| struct blk_major_name *next; | |
| int major; | |
| @@ -37852,9 +48607,10 @@ | |
| spinlock_t lock; | |
| struct list_head rq_lists[3]; | |
| long: 64; | |
| + long: 64; | |
| }; | |
| unsigned int cpu; | |
| - unsigned short index_hw[3]; | |
| + short unsigned int index_hw[3]; | |
| struct blk_mq_hw_ctx *hctxs[3]; | |
| struct request_queue *queue; | |
| struct blk_mq_ctxs *ctxs; | |
| @@ -37864,7 +48620,7 @@ | |
| struct blk_mq_ctxs { | |
| struct kobject kobj; | |
| - struct blk_mq_ctx __attribute__((btf_type_tag("percpu"))) *queue_ctx; | |
| + struct blk_mq_ctx *queue_ctx; | |
| }; | |
| struct seq_operations; | |
| @@ -37873,7 +48629,7 @@ | |
| const char *name; | |
| umode_t mode; | |
| int (*show)(void *, struct seq_file *); | |
| - ssize_t (*write)(void *, const char __attribute__((btf_type_tag("user"))) *, size_t, loff_t *); | |
| + ssize_t (*write)(void *, const char *, size_t, loff_t *); | |
| const struct seq_operations *seq_ops; | |
| }; | |
| @@ -37885,7 +48641,7 @@ | |
| unsigned int map_nr; | |
| bool round_robin; | |
| struct sbitmap_word *map; | |
| - unsigned int __attribute__((btf_type_tag("percpu"))) *alloc_hint; | |
| + unsigned int *alloc_hint; | |
| }; | |
| typedef struct wait_queue_entry wait_queue_entry_t; | |
| @@ -37894,7 +48650,8 @@ | |
| struct { | |
| spinlock_t lock; | |
| struct list_head dispatch; | |
| - unsigned long state; | |
| + long unsigned int state; | |
| + long: 64; | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| @@ -37904,7 +48661,7 @@ | |
| cpumask_var_t cpumask; | |
| int next_cpu; | |
| int next_cpu_batch; | |
| - unsigned long flags; | |
| + long unsigned int flags; | |
| void *sched_data; | |
| struct request_queue *queue; | |
| struct blk_flush_queue *fq; | |
| @@ -37912,16 +48669,14 @@ | |
| struct sbitmap ctx_map; | |
| struct blk_mq_ctx *dispatch_from; | |
| unsigned int dispatch_busy; | |
| - unsigned short type; | |
| - unsigned short nr_ctx; | |
| + short unsigned int type; | |
| + short unsigned int nr_ctx; | |
| struct blk_mq_ctx **ctxs; | |
| spinlock_t dispatch_wait_lock; | |
| wait_queue_entry_t dispatch_wait; | |
| atomic_t wait_index; | |
| struct blk_mq_tags *tags; | |
| struct blk_mq_tags *sched_tags; | |
| - unsigned long queued; | |
| - unsigned long run; | |
| unsigned int numa_node; | |
| unsigned int queue_num; | |
| atomic_t nr_active; | |
| @@ -37933,7 +48688,6 @@ | |
| struct list_head hctx_list; | |
| long: 64; | |
| long: 64; | |
| - long: 64; | |
| }; | |
| struct blk_mq_hw_ctx_sysfs_entry { | |
| @@ -37995,7 +48749,7 @@ | |
| struct blk_mq_tags { | |
| unsigned int nr_tags; | |
| unsigned int nr_reserved_tags; | |
| - atomic_t active_queues; | |
| + unsigned int active_queues; | |
| struct sbitmap_queue bitmap_tags; | |
| struct sbitmap_queue breserved_tags; | |
| struct request **rqs; | |
| @@ -38007,11 +48761,11 @@ | |
| struct blk_plug { | |
| struct request *mq_list; | |
| struct request *cached_rq; | |
| - unsigned short nr_ios; | |
| - unsigned short rq_count; | |
| + u64 cur_ktime; | |
| + short unsigned int nr_ios; | |
| + short unsigned int rq_count; | |
| bool multiple_queues; | |
| bool has_elevator; | |
| - bool nowait; | |
| struct list_head cb_list; | |
| }; | |
| @@ -38047,7 +48801,7 @@ | |
| struct blk_stat_callback { | |
| struct list_head list; | |
| struct timer_list timer; | |
| - struct blk_rq_stat __attribute__((btf_type_tag("percpu"))) *cpu_stat; | |
| + struct blk_rq_stat *cpu_stat; | |
| int (*bucket_fn)(const struct request *); | |
| unsigned int buckets; | |
| struct blk_rq_stat *stat; | |
| @@ -38061,8 +48815,8 @@ | |
| struct blk_trace { | |
| int trace_state; | |
| struct rchan *rchan; | |
| - unsigned long __attribute__((btf_type_tag("percpu"))) *sequence; | |
| - unsigned char __attribute__((btf_type_tag("percpu"))) *msg_data; | |
| + long unsigned int *sequence; | |
| + unsigned char *msg_data; | |
| u16 act_mask; | |
| u64 start_lba; | |
| u64 end_lba; | |
| @@ -38116,16 +48870,18 @@ | |
| struct blkcg_policy_data; | |
| +struct llist_head; | |
| + | |
| struct blkcg { | |
| struct cgroup_subsys_state css; | |
| spinlock_t lock; | |
| refcount_t online_pin; | |
| struct xarray blkg_tree; | |
| - struct blkcg_gq __attribute__((btf_type_tag("rcu"))) *blkg_hint; | |
| + struct blkcg_gq *blkg_hint; | |
| struct hlist_head blkg_list; | |
| struct blkcg_policy_data *cpd[6]; | |
| struct list_head all_blkcgs_node; | |
| - struct llist_head __attribute__((btf_type_tag("percpu"))) *lhead; | |
| + struct llist_head *lhead; | |
| struct list_head cgwb_list; | |
| }; | |
| @@ -38153,7 +48909,7 @@ | |
| struct blkcg_gq *parent; | |
| struct percpu_ref refcnt; | |
| bool online; | |
| - struct blkg_iostat_set __attribute__((btf_type_tag("percpu"))) *iostat_cpu; | |
| + struct blkg_iostat_set *iostat_cpu; | |
| struct blkg_iostat_set iostat; | |
| struct blkg_policy_data *pd[6]; | |
| spinlock_t async_bio_lock; | |
| @@ -38224,6 +48980,8 @@ | |
| long: 64; | |
| long: 64; | |
| struct bio bio; | |
| + long: 64; | |
| + long: 64; | |
| }; | |
| struct blkg_conf_ctx { | |
| @@ -38248,23 +49006,16 @@ | |
| u64 cnt[5]; | |
| }; | |
| -struct blkpg_compat_ioctl_arg { | |
| - compat_int_t op; | |
| - compat_int_t flags; | |
| - compat_int_t datalen; | |
| - compat_uptr_t data; | |
| -}; | |
| - | |
| struct blkpg_ioctl_arg { | |
| int op; | |
| int flags; | |
| int datalen; | |
| - void __attribute__((btf_type_tag("user"))) *data; | |
| + void *data; | |
| }; | |
| struct blkpg_partition { | |
| - long long start; | |
| - long long length; | |
| + long long int start; | |
| + long long int length; | |
| int pno; | |
| char devname[64]; | |
| char volname[64]; | |
| @@ -38285,16 +49036,16 @@ | |
| struct block_device_operations { | |
| void (*submit_bio)(struct bio *); | |
| int (*poll_bio)(struct bio *, struct io_comp_batch *, unsigned int); | |
| - int (*open)(struct block_device *, fmode_t); | |
| - void (*release)(struct gendisk *, fmode_t); | |
| - int (*ioctl)(struct block_device *, fmode_t, unsigned int, unsigned long); | |
| - int (*compat_ioctl)(struct block_device *, fmode_t, unsigned int, unsigned long); | |
| + int (*open)(struct gendisk *, blk_mode_t); | |
| + void (*release)(struct gendisk *); | |
| + int (*ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int); | |
| + int (*compat_ioctl)(struct block_device *, blk_mode_t, unsigned int, long unsigned int); | |
| unsigned int (*check_events)(struct gendisk *, unsigned int); | |
| void (*unlock_native_capacity)(struct gendisk *); | |
| int (*getgeo)(struct block_device *, struct hd_geometry *); | |
| int (*set_read_only)(struct block_device *, bool); | |
| void (*free_disk)(struct gendisk *); | |
| - void (*swap_slot_free_notify)(struct block_device *, unsigned long); | |
| + void (*swap_slot_free_notify)(struct block_device *, long unsigned int); | |
| int (*report_zones)(struct gendisk *, sector_t, unsigned int, report_zones_cb, void *); | |
| char * (*devnode)(struct gendisk *, umode_t *); | |
| int (*get_unique_id)(struct gendisk *, u8 *, enum blk_unique_id); | |
| @@ -38309,1617 +49060,439 @@ | |
| struct blocking_notifier_head { | |
| struct rw_semaphore rwsem; | |
| - struct notifier_block __attribute__((btf_type_tag("rcu"))) *head; | |
| -}; | |
| - | |
| -struct bnxt_queue_info { | |
| - u8 queue_id; | |
| - u8 queue_profile; | |
| -}; | |
| - | |
| -struct rtnl_link_stats64 { | |
| - __u64 rx_packets; | |
| - __u64 tx_packets; | |
| - __u64 rx_bytes; | |
| - __u64 tx_bytes; | |
| - __u64 rx_errors; | |
| - __u64 tx_errors; | |
| - __u64 rx_dropped; | |
| - __u64 tx_dropped; | |
| - __u64 multicast; | |
| - __u64 collisions; | |
| - __u64 rx_length_errors; | |
| - __u64 rx_over_errors; | |
| - __u64 rx_crc_errors; | |
| - __u64 rx_frame_errors; | |
| - __u64 rx_fifo_errors; | |
| - __u64 rx_missed_errors; | |
| - __u64 tx_aborted_errors; | |
| - __u64 tx_carrier_errors; | |
| - __u64 tx_fifo_errors; | |
| - __u64 tx_heartbeat_errors; | |
| - __u64 tx_window_errors; | |
| - __u64 rx_compressed; | |
| - __u64 tx_compressed; | |
| - __u64 rx_nohandler; | |
| - __u64 rx_otherhost_dropped; | |
| -}; | |
| - | |
| -struct bnxt_stats_mem { | |
| - u64 *sw_stats; | |
| - u64 *hw_masks; | |
| - void *hw_stats; | |
| - dma_addr_t hw_stats_map; | |
| - int len; | |
| -}; | |
| - | |
| -struct bnxt_total_ring_err_stats { | |
| - u64 rx_total_l4_csum_errors; | |
| - u64 rx_total_resets; | |
| - u64 rx_total_buf_errors; | |
| - u64 rx_total_oom_discards; | |
| - u64 rx_total_netpoll_discards; | |
| - u64 rx_total_ring_discards; | |
| - u64 tx_total_resets; | |
| - u64 tx_total_ring_discards; | |
| - u64 total_missed_irqs; | |
| -}; | |
| - | |
| -struct hwrm_ver_get_output { | |
| - __le16 error_code; | |
| - __le16 req_type; | |
| - __le16 seq_id; | |
| - __le16 resp_len; | |
| - u8 hwrm_intf_maj_8b; | |
| - u8 hwrm_intf_min_8b; | |
| - u8 hwrm_intf_upd_8b; | |
| - u8 hwrm_intf_rsvd_8b; | |
| - u8 hwrm_fw_maj_8b; | |
| - u8 hwrm_fw_min_8b; | |
| - u8 hwrm_fw_bld_8b; | |
| - u8 hwrm_fw_rsvd_8b; | |
| - u8 mgmt_fw_maj_8b; | |
| - u8 mgmt_fw_min_8b; | |
| - u8 mgmt_fw_bld_8b; | |
| - u8 mgmt_fw_rsvd_8b; | |
| - u8 netctrl_fw_maj_8b; | |
| - u8 netctrl_fw_min_8b; | |
| - u8 netctrl_fw_bld_8b; | |
| - u8 netctrl_fw_rsvd_8b; | |
| - __le32 dev_caps_cfg; | |
| - u8 roce_fw_maj_8b; | |
| - u8 roce_fw_min_8b; | |
| - u8 roce_fw_bld_8b; | |
| - u8 roce_fw_rsvd_8b; | |
| - char hwrm_fw_name[16]; | |
| - char mgmt_fw_name[16]; | |
| - char netctrl_fw_name[16]; | |
| - char active_pkg_name[16]; | |
| - char roce_fw_name[16]; | |
| - __le16 chip_num; | |
| - u8 chip_rev; | |
| - u8 chip_metal; | |
| - u8 chip_bond_id; | |
| - u8 chip_platform_type; | |
| - __le16 max_req_win_len; | |
| - __le16 max_resp_len; | |
| - __le16 def_req_timeout; | |
| - u8 flags; | |
| - u8 unused_0[2]; | |
| - u8 always_1; | |
| - __le16 hwrm_intf_major; | |
| - __le16 hwrm_intf_minor; | |
| - __le16 hwrm_intf_build; | |
| - __le16 hwrm_intf_patch; | |
| - __le16 hwrm_fw_major; | |
| - __le16 hwrm_fw_minor; | |
| - __le16 hwrm_fw_build; | |
| - __le16 hwrm_fw_patch; | |
| - __le16 mgmt_fw_major; | |
| - __le16 mgmt_fw_minor; | |
| - __le16 mgmt_fw_build; | |
| - __le16 mgmt_fw_patch; | |
| - __le16 netctrl_fw_major; | |
| - __le16 netctrl_fw_minor; | |
| - __le16 netctrl_fw_build; | |
| - __le16 netctrl_fw_patch; | |
| - __le16 roce_fw_major; | |
| - __le16 roce_fw_minor; | |
| - __le16 roce_fw_build; | |
| - __le16 roce_fw_patch; | |
| - __le16 max_ext_req_len; | |
| - __le16 max_req_timeout; | |
| - u8 unused_1[3]; | |
| - u8 valid; | |
| -}; | |
| - | |
| -struct bnxt_coal_cap { | |
| - u32 cmpl_params; | |
| - u32 nq_params; | |
| - u16 num_cmpl_dma_aggr_max; | |
| - u16 num_cmpl_dma_aggr_during_int_max; | |
| - u16 cmpl_aggr_dma_tmr_max; | |
| - u16 cmpl_aggr_dma_tmr_during_int_max; | |
| - u16 int_lat_tmr_min_max; | |
| - u16 int_lat_tmr_max_max; | |
| - u16 num_cmpl_aggr_int_max; | |
| - u16 timer_units; | |
| -}; | |
| - | |
| -struct bnxt_coal { | |
| - u16 coal_ticks; | |
| - u16 coal_ticks_irq; | |
| - u16 coal_bufs; | |
| - u16 coal_bufs_irq; | |
| - u16 idle_thresh; | |
| - u8 bufs_per_record; | |
| - u8 budget; | |
| - u16 flags; | |
| -}; | |
| - | |
| -struct bnxt_hw_resc { | |
| - u16 min_rsscos_ctxs; | |
| - u16 max_rsscos_ctxs; | |
| - u16 min_cp_rings; | |
| - u16 max_cp_rings; | |
| - u16 resv_cp_rings; | |
| - u16 min_tx_rings; | |
| - u16 max_tx_rings; | |
| - u16 resv_tx_rings; | |
| - u16 max_tx_sch_inputs; | |
| - u16 min_rx_rings; | |
| - u16 max_rx_rings; | |
| - u16 resv_rx_rings; | |
| - u16 min_hw_ring_grps; | |
| - u16 max_hw_ring_grps; | |
| - u16 resv_hw_ring_grps; | |
| - u16 min_l2_ctxs; | |
| - u16 max_l2_ctxs; | |
| - u16 min_vnics; | |
| - u16 max_vnics; | |
| - u16 resv_vnics; | |
| - u16 min_stat_ctxs; | |
| - u16 max_stat_ctxs; | |
| - u16 resv_stat_ctxs; | |
| - u16 max_nqs; | |
| - u16 max_irqs; | |
| - u16 resv_irqs; | |
| -}; | |
| - | |
| -struct bnxt_vf_info; | |
| - | |
| -struct bnxt_pf_info { | |
| - u16 fw_fid; | |
| - u16 port_id; | |
| - u8 mac_addr[6]; | |
| - u32 first_vf_id; | |
| - u16 active_vfs; | |
| - u16 registered_vfs; | |
| - u16 max_vfs; | |
| - u32 max_encap_records; | |
| - u32 max_decap_records; | |
| - u32 max_tx_em_flows; | |
| - u32 max_tx_wm_flows; | |
| - u32 max_rx_em_flows; | |
| - u32 max_rx_wm_flows; | |
| - unsigned long *vf_event_bmap; | |
| - u16 hwrm_cmd_req_pages; | |
| - u8 vf_resv_strategy; | |
| - void *hwrm_cmd_req_addr[4]; | |
| - dma_addr_t hwrm_cmd_req_dma_addr[4]; | |
| - struct bnxt_vf_info *vf; | |
| -}; | |
| - | |
| -struct hwrm_port_phy_qcfg_output { | |
| - __le16 error_code; | |
| - __le16 req_type; | |
| - __le16 seq_id; | |
| - __le16 resp_len; | |
| - u8 link; | |
| - u8 active_fec_signal_mode; | |
| - __le16 link_speed; | |
| - u8 duplex_cfg; | |
| - u8 pause; | |
| - __le16 support_speeds; | |
| - __le16 force_link_speed; | |
| - u8 auto_mode; | |
| - u8 auto_pause; | |
| - __le16 auto_link_speed; | |
| - __le16 auto_link_speed_mask; | |
| - u8 wirespeed; | |
| - u8 lpbk; | |
| - u8 force_pause; | |
| - u8 module_status; | |
| - __le32 preemphasis; | |
| - u8 phy_maj; | |
| - u8 phy_min; | |
| - u8 phy_bld; | |
| - u8 phy_type; | |
| - u8 media_type; | |
| - u8 xcvr_pkg_type; | |
| - u8 eee_config_phy_addr; | |
| - u8 parallel_detect; | |
| - __le16 link_partner_adv_speeds; | |
| - u8 link_partner_adv_auto_mode; | |
| - u8 link_partner_adv_pause; | |
| - __le16 adv_eee_link_speed_mask; | |
| - __le16 link_partner_adv_eee_link_speed_mask; | |
| - __le32 xcvr_identifier_type_tx_lpi_timer; | |
| - __le16 fec_cfg; | |
| - u8 duplex_state; | |
| - u8 option_flags; | |
| - char phy_vendor_name[16]; | |
| - char phy_vendor_partnumber[16]; | |
| - __le16 support_pam4_speeds; | |
| - __le16 force_pam4_link_speed; | |
| - __le16 auto_pam4_link_speed_mask; | |
| - u8 link_partner_pam4_adv_speeds; | |
| - u8 link_down_reason; | |
| - u8 unused_0[7]; | |
| - u8 valid; | |
| -}; | |
| - | |
| -struct bnxt_link_info { | |
| - u8 phy_type; | |
| - u8 media_type; | |
| - u8 transceiver; | |
| - u8 phy_addr; | |
| - u8 phy_link_status; | |
| - u8 wire_speed; | |
| - u8 phy_state; | |
| - u8 link_state; | |
| - u8 duplex; | |
| - u8 pause; | |
| - u8 lp_pause; | |
| - u8 auto_pause_setting; | |
| - u8 force_pause_setting; | |
| - u8 duplex_setting; | |
| - u8 auto_mode; | |
| - u8 phy_ver[3]; | |
| - u16 link_speed; | |
| - u16 support_speeds; | |
| - u16 support_pam4_speeds; | |
| - u16 auto_link_speeds; | |
| - u16 auto_pam4_link_speeds; | |
| - u16 support_auto_speeds; | |
| - u16 support_pam4_auto_speeds; | |
| - u16 lp_auto_link_speeds; | |
| - u16 lp_auto_pam4_link_speeds; | |
| - u16 force_link_speed; | |
| - u16 force_pam4_link_speed; | |
| - u32 preemphasis; | |
| - u8 module_status; | |
| - u8 active_fec_sig_mode; | |
| - u16 fec_cfg; | |
| - u8 autoneg; | |
| - u8 req_signal_mode; | |
| - u8 req_duplex; | |
| - u8 req_flow_ctrl; | |
| - u16 req_link_speed; | |
| - u16 advertising; | |
| - u16 advertising_pam4; | |
| - bool force_link_chng; | |
| - bool phy_retry; | |
| - unsigned long phy_retry_expires; | |
| - struct hwrm_port_phy_qcfg_output phy_qcfg_resp; | |
| -}; | |
| - | |
| -struct ethtool_eee { | |
| - __u32 cmd; | |
| - __u32 supported; | |
| - __u32 advertised; | |
| - __u32 lp_advertised; | |
| - __u32 eee_active; | |
| - __u32 eee_enabled; | |
| - __u32 tx_lpi_enabled; | |
| - __u32 tx_lpi_timer; | |
| - __u32 reserved[2]; | |
| -}; | |
| - | |
| -struct bnxt_led_info { | |
| - u8 led_id; | |
| - u8 led_type; | |
| - u8 led_group_id; | |
| - u8 unused; | |
| - __le16 led_state_caps; | |
| - __le16 led_color_caps; | |
| -}; | |
| - | |
| -struct netdev_phys_item_id { | |
| - unsigned char id[32]; | |
| - unsigned char id_len; | |
| -}; | |
| - | |
| -struct devlink_port_phys_attrs { | |
| - u32 port_number; | |
| - u32 split_subport_number; | |
| -}; | |
| - | |
| -struct devlink_port_pci_pf_attrs { | |
| - u32 controller; | |
| - u16 pf; | |
| - u8 external: 1; | |
| -}; | |
| - | |
| -struct devlink_port_pci_vf_attrs { | |
| - u32 controller; | |
| - u16 pf; | |
| - u16 vf; | |
| - u8 external: 1; | |
| -}; | |
| - | |
| -struct devlink_port_pci_sf_attrs { | |
| - u32 controller; | |
| - u32 sf; | |
| - u16 pf; | |
| - u8 external: 1; | |
| -}; | |
| - | |
| -struct devlink_port_attrs { | |
| - u8 split: 1; | |
| - u8 splittable: 1; | |
| - u32 lanes; | |
| - enum devlink_port_flavour flavour; | |
| - struct netdev_phys_item_id switch_id; | |
| - union { | |
| - struct devlink_port_phys_attrs phys; | |
| - struct devlink_port_pci_pf_attrs pci_pf; | |
| - struct devlink_port_pci_vf_attrs pci_vf; | |
| - struct devlink_port_pci_sf_attrs pci_sf; | |
| - }; | |
| -}; | |
| - | |
| -struct devlink; | |
| - | |
| -struct ib_device; | |
| - | |
| -struct devlink_rate; | |
| - | |
| -struct devlink_linecard; | |
| - | |
| -struct devlink_port { | |
| - struct list_head list; | |
| - struct list_head region_list; | |
| - struct devlink *devlink; | |
| - unsigned int index; | |
| - spinlock_t type_lock; | |
| - enum devlink_port_type type; | |
| - enum devlink_port_type desired_type; | |
| - union { | |
| - struct { | |
| - struct net_device *netdev; | |
| - int ifindex; | |
| - char ifname[16]; | |
| - } type_eth; | |
| - struct { | |
| - struct ib_device *ibdev; | |
| - } type_ib; | |
| - }; | |
| - struct devlink_port_attrs attrs; | |
| - u8 attrs_set: 1; | |
| - u8 switch_port: 1; | |
| - u8 registered: 1; | |
| - u8 initialized: 1; | |
| - struct delayed_work type_warn_dw; | |
| - struct list_head reporter_list; | |
| - struct devlink_rate *devlink_rate; | |
| - struct devlink_linecard *linecard; | |
| -}; | |
| - | |
| -struct bnxt_aux_priv; | |
| - | |
| -struct bnxt_en_dev; | |
| - | |
| -struct bnxt_napi; | |
| - | |
| -struct bnxt_rx_ring_info; | |
| - | |
| -struct bnxt_tx_ring_info; | |
| - | |
| -struct bnxt_tpa_info; | |
| - | |
| -struct bnxt_ring_grp_info; | |
| - | |
| -struct bnxt_vnic_info; | |
| - | |
| -struct bnxt_irq; | |
| - | |
| -struct dma_pool; | |
| - | |
| -struct bnxt_fw_health; | |
| - | |
| -struct bnxt_ctx_mem_info; | |
| - | |
| -struct bnxt_test_info; | |
| - | |
| -struct bpf_prog; | |
| - | |
| -struct bnxt_ptp_cfg; | |
| - | |
| -struct bnxt_vf_rep; | |
| - | |
| -struct bnxt_tc_info; | |
| - | |
| -struct bnxt { | |
| - void *bar0; | |
| - void *bar1; | |
| - void *bar2; | |
| - u32 reg_base; | |
| - u16 chip_num; | |
| - u8 chip_rev; | |
| - char board_partno[32]; | |
| - char board_serialno[32]; | |
| - struct net_device *dev; | |
| - struct pci_dev *pdev; | |
| - atomic_t intr_sem; | |
| - u32 flags; | |
| - struct bnxt_aux_priv *aux_priv; | |
| - struct bnxt_en_dev *edev; | |
| - struct bnxt_napi **bnapi; | |
| - struct bnxt_rx_ring_info *rx_ring; | |
| - struct bnxt_tx_ring_info *tx_ring; | |
| - u16 *tx_ring_map; | |
| - struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int, struct sk_buff *); | |
| - struct sk_buff * (*rx_skb_func)(struct bnxt *, struct bnxt_rx_ring_info *, u16, void *, u8 *, dma_addr_t, unsigned int); | |
| - u16 max_tpa_v2; | |
| - u16 max_tpa; | |
| - u32 rx_buf_size; | |
| - u32 rx_buf_use_size; | |
| - u16 rx_offset; | |
| - u16 rx_dma_offset; | |
| - enum dma_data_direction rx_dir; | |
| - u32 rx_ring_size; | |
| - u32 rx_agg_ring_size; | |
| - u32 rx_copy_thresh; | |
| - u32 rx_ring_mask; | |
| - u32 rx_agg_ring_mask; | |
| - int rx_nr_pages; | |
| - int rx_agg_nr_pages; | |
| - int rx_nr_rings; | |
| - int rsscos_nr_ctxs; | |
| - u32 tx_ring_size; | |
| - u32 tx_ring_mask; | |
| - int tx_nr_pages; | |
| - int tx_nr_rings; | |
| - int tx_nr_rings_per_tc; | |
| - int tx_nr_rings_xdp; | |
| - int tx_wake_thresh; | |
| - int tx_push_thresh; | |
| - int tx_push_size; | |
| - u32 cp_ring_size; | |
| - u32 cp_ring_mask; | |
| - u32 cp_bit; | |
| - int cp_nr_pages; | |
| - int cp_nr_rings; | |
| - struct bnxt_ring_grp_info *grp_info; | |
| - struct bnxt_vnic_info *vnic_info; | |
| - int nr_vnics; | |
| - u16 *rss_indir_tbl; | |
| - u16 rss_indir_tbl_entries; | |
| - u32 rss_hash_cfg; | |
| - u32 rss_hash_delta; | |
| - u16 max_mtu; | |
| - u8 max_tc; | |
| - u8 max_lltc; | |
| - struct bnxt_queue_info q_info[8]; | |
| - u8 tc_to_qidx[8]; | |
| - u8 q_ids[8]; | |
| - u8 max_q; | |
| - unsigned int current_interval; | |
| - struct timer_list timer; | |
| - unsigned long state; | |
| - struct bnxt_irq *irq_tbl; | |
| - int total_irqs; | |
| - u8 mac_addr[6]; | |
| - u32 msg_enable; | |
| - u64 fw_cap; | |
| - u32 fw_dbg_cap; | |
| - u32 hwrm_spec_code; | |
| - u16 hwrm_cmd_seq; | |
| - u16 hwrm_cmd_kong_seq; | |
| - struct dma_pool *hwrm_dma_pool; | |
| - struct hlist_head hwrm_pending_list; | |
| - struct rtnl_link_stats64 net_stats_prev; | |
| - struct bnxt_stats_mem port_stats; | |
| - struct bnxt_stats_mem rx_port_stats_ext; | |
| - struct bnxt_stats_mem tx_port_stats_ext; | |
| - u16 fw_rx_stats_ext_size; | |
| - u16 fw_tx_stats_ext_size; | |
| - u16 hw_ring_stats_size; | |
| - u8 pri2cos_idx[8]; | |
| - u8 pri2cos_valid; | |
| - struct bnxt_total_ring_err_stats ring_err_stats_prev; | |
| - u16 hwrm_max_req_len; | |
| - u16 hwrm_max_ext_req_len; | |
| - unsigned int hwrm_cmd_timeout; | |
| - unsigned int hwrm_cmd_max_timeout; | |
| - struct mutex hwrm_cmd_lock; | |
| - struct hwrm_ver_get_output ver_resp; | |
| - char fw_ver_str[32]; | |
| - char hwrm_ver_supp[32]; | |
| - char nvm_cfg_ver[32]; | |
| - u64 fw_ver_code; | |
| - u16 vxlan_fw_dst_port_id; | |
| - u16 nge_fw_dst_port_id; | |
| - __be16 vxlan_port; | |
| - __be16 nge_port; | |
| - u8 port_partition_type; | |
| - u8 port_count; | |
| - u16 br_mode; | |
| - struct bnxt_coal_cap coal_cap; | |
| - struct bnxt_coal rx_coal; | |
| - struct bnxt_coal tx_coal; | |
| - u32 stats_coal_ticks; | |
| - struct work_struct sp_task; | |
| - unsigned long sp_event; | |
| - struct delayed_work fw_reset_task; | |
| - int fw_reset_state; | |
| - u16 fw_reset_min_dsecs; | |
| - u16 fw_reset_max_dsecs; | |
| - unsigned long fw_reset_timestamp; | |
| - struct bnxt_fw_health *fw_health; | |
| - struct bnxt_hw_resc hw_resc; | |
| - struct bnxt_pf_info pf; | |
| - struct bnxt_ctx_mem_info *ctx; | |
| - int db_size; | |
| - struct hlist_head ntp_fltr_hash_tbl[512]; | |
| - spinlock_t ntp_fltr_lock; | |
| - unsigned long *ntp_fltr_bmap; | |
| - int ntp_fltr_count; | |
| - struct mutex link_lock; | |
| - struct bnxt_link_info link_info; | |
| - struct ethtool_eee eee; | |
| - u32 lpi_tmr_lo; | |
| - u32 lpi_tmr_hi; | |
| - u32 phy_flags; | |
| - u8 num_tests; | |
| - struct bnxt_test_info *test_info; | |
| - u8 wol_filter_id; | |
| - u8 wol; | |
| - u8 num_leds; | |
| - struct bnxt_led_info leds[4]; | |
| - u16 dump_flag; | |
| - struct bpf_prog *xdp_prog; | |
| - struct bnxt_ptp_cfg *ptp_cfg; | |
| - u8 ptp_all_rx_tstamp; | |
| - struct devlink *dl; | |
| - struct devlink_port dl_port; | |
| - enum devlink_eswitch_mode eswitch_mode; | |
| - struct bnxt_vf_rep **vf_reps; | |
| - u16 *cfa_code_map; | |
| - u8 dsn[8]; | |
| - struct bnxt_tc_info *tc_info; | |
| - struct list_head tc_indr_block_list; | |
| - struct dentry *debugfs_pdev; | |
| - struct device *hwmon_dev; | |
| - u8 warn_thresh_temp; | |
| - u8 crit_thresh_temp; | |
| - u8 fatal_thresh_temp; | |
| - u8 shutdown_thresh_temp; | |
| - u32 thermal_threshold_type; | |
| - enum board_idx board_idx; | |
| -}; | |
| - | |
| -struct bnxt_aux_priv { | |
| - struct auxiliary_device aux_dev; | |
| - struct bnxt_en_dev *edev; | |
| - int id; | |
| -}; | |
| - | |
| -struct bnxt_cmn_sw_stats { | |
| - u64 missed_irqs; | |
| -}; | |
| - | |
| -struct bnxt_coredump { | |
| - void *data; | |
| - int data_size; | |
| - u16 total_segs; | |
| -}; | |
| - | |
| -struct bnxt_coredump_record { | |
| - __u8 signature[4]; | |
| - __le32 flags; | |
| - __u8 low_version; | |
| - __u8 high_version; | |
| - __u8 asic_state; | |
| - __u8 rsvd0[5]; | |
| - char system_name[32]; | |
| - __le16 year; | |
| - __le16 month; | |
| - __le16 day; | |
| - __le16 hour; | |
| - __le16 minute; | |
| - __le16 second; | |
| - __le16 utc_bias; | |
| - __le16 rsvd1; | |
| - char commandline[256]; | |
| - __le32 total_segments; | |
| - __le32 os_ver_major; | |
| - __le32 os_ver_minor; | |
| - __le32 rsvd2; | |
| - char os_name[32]; | |
| - __le16 end_year; | |
| - __le16 end_month; | |
| - __le16 end_day; | |
| - __le16 end_hour; | |
| - __le16 end_minute; | |
| - __le16 end_second; | |
| - __le16 end_utc_bias; | |
| - __le32 asic_id1; | |
| - __le32 asic_id2; | |
| - __le32 coredump_status; | |
| - __u8 ioctl_low_version; | |
| - __u8 ioctl_high_version; | |
| - __le16 rsvd3[313]; | |
| -}; | |
| - | |
| -struct bnxt_coredump_segment_hdr { | |
| - __u8 signature[4]; | |
| - __le32 component_id; | |
| - __le32 segment_id; | |
| - __le32 flags; | |
| - __u8 low_version; | |
| - __u8 high_version; | |
| - __le16 function_id; | |
| - __le32 offset; | |
| - __le32 length; | |
| - __le32 status; | |
| - __le32 duration; | |
| - __le32 data_offset; | |
| - __le32 instance; | |
| - __le32 rsvd[5]; | |
| -}; | |
| - | |
| -struct bnxt_db_info { | |
| - void *doorbell; | |
| - union { | |
| - u64 db_key64; | |
| - u32 db_key32; | |
| - }; | |
| -}; | |
| - | |
| -struct dim_stats { | |
| - int ppms; | |
| - int bpms; | |
| - int epms; | |
| - int cpms; | |
| - int cpe_ratio; | |
| -}; | |
| - | |
| -struct dim_sample { | |
| - ktime_t time; | |
| - u32 pkt_ctr; | |
| - u32 byte_ctr; | |
| - u16 event_ctr; | |
| - u32 comp_ctr; | |
| -}; | |
| - | |
| -struct dim { | |
| - u8 state; | |
| - struct dim_stats prev_stats; | |
| - struct dim_sample start_sample; | |
| - struct dim_sample measuring_sample; | |
| - struct work_struct work; | |
| - void *priv; | |
| - u8 profile_ix; | |
| - u8 mode; | |
| - u8 tune_state; | |
| - u8 steps_right; | |
| - u8 steps_left; | |
| - u8 tired; | |
| -}; | |
| - | |
| -struct bnxt_rx_sw_stats { | |
| - u64 rx_l4_csum_errors; | |
| - u64 rx_resets; | |
| - u64 rx_buf_errors; | |
| - u64 rx_oom_discards; | |
| - u64 rx_netpoll_discards; | |
| -}; | |
| - | |
| -struct bnxt_tx_sw_stats { | |
| - u64 tx_resets; | |
| -}; | |
| - | |
| -struct bnxt_sw_stats { | |
| - struct bnxt_rx_sw_stats rx; | |
| - struct bnxt_tx_sw_stats tx; | |
| - struct bnxt_cmn_sw_stats cmn; | |
| -}; | |
| - | |
| -struct bnxt_mem_init; | |
| - | |
| -struct bnxt_ring_mem_info { | |
| - int nr_pages; | |
| - int page_size; | |
| - u16 flags; | |
| - u16 depth; | |
| - struct bnxt_mem_init *mem_init; | |
| - void **pg_arr; | |
| - dma_addr_t *dma_arr; | |
| - __le64 *pg_tbl; | |
| - dma_addr_t pg_tbl_map; | |
| - int vmem_size; | |
| - void **vmem; | |
| -}; | |
| - | |
| -struct bnxt_ring_struct { | |
| - struct bnxt_ring_mem_info ring_mem; | |
| - u16 fw_ring_id; | |
| - union { | |
| - u16 grp_idx; | |
| - u16 map_idx; | |
| - }; | |
| - u32 handle; | |
| - u8 queue_id; | |
| -}; | |
| - | |
| -struct tx_cmp; | |
| - | |
| -struct nqe_cn; | |
| - | |
| -struct bnxt_cp_ring_info { | |
| - struct bnxt_napi *bnapi; | |
| - u32 cp_raw_cons; | |
| - struct bnxt_db_info cp_db; | |
| - u8 had_work_done: 1; | |
| - u8 has_more_work: 1; | |
| - u32 last_cp_raw_cons; | |
| - struct bnxt_coal rx_ring_coal; | |
| - u64 rx_packets; | |
| - u64 rx_bytes; | |
| - u64 event_ctr; | |
| - struct dim dim; | |
| - union { | |
| - struct tx_cmp **cp_desc_ring; | |
| - struct nqe_cn **nq_desc_ring; | |
| - }; | |
| - dma_addr_t *cp_desc_mapping; | |
| - struct bnxt_stats_mem stats; | |
| - u32 hw_stats_ctx_id; | |
| - struct bnxt_sw_stats sw_stats; | |
| - struct bnxt_ring_struct cp_ring_struct; | |
| - struct bnxt_cp_ring_info *cp_ring_arr[2]; | |
| -}; | |
| - | |
| -struct bnxt_ctx_pg_info { | |
| - u32 entries; | |
| - u32 nr_pages; | |
| - void *ctx_pg_arr[512]; | |
| - dma_addr_t ctx_dma_arr[512]; | |
| - struct bnxt_ring_mem_info ring_mem; | |
| - struct bnxt_ctx_pg_info **ctx_pg_tbl; | |
| -}; | |
| - | |
| -struct bnxt_mem_init { | |
| - u8 init_val; | |
| - u16 offset; | |
| - u16 size; | |
| -}; | |
| - | |
| -struct bnxt_ctx_mem_info { | |
| - u32 qp_max_entries; | |
| - u16 qp_min_qp1_entries; | |
| - u16 qp_max_l2_entries; | |
| - u16 qp_entry_size; | |
| - u16 srq_max_l2_entries; | |
| - u32 srq_max_entries; | |
| - u16 srq_entry_size; | |
| - u16 cq_max_l2_entries; | |
| - u32 cq_max_entries; | |
| - u16 cq_entry_size; | |
| - u16 vnic_max_vnic_entries; | |
| - u16 vnic_max_ring_table_entries; | |
| - u16 vnic_entry_size; | |
| - u32 stat_max_entries; | |
| - u16 stat_entry_size; | |
| - u16 tqm_entry_size; | |
| - u32 tqm_min_entries_per_ring; | |
| - u32 tqm_max_entries_per_ring; | |
| - u32 mrav_max_entries; | |
| - u16 mrav_entry_size; | |
| - u16 tim_entry_size; | |
| - u32 tim_max_entries; | |
| - u16 mrav_num_entries_units; | |
| - u8 tqm_entries_multiple; | |
| - u8 tqm_fp_rings_count; | |
| - u32 flags; | |
| - struct bnxt_ctx_pg_info qp_mem; | |
| - struct bnxt_ctx_pg_info srq_mem; | |
| - struct bnxt_ctx_pg_info cq_mem; | |
| - struct bnxt_ctx_pg_info vnic_mem; | |
| - struct bnxt_ctx_pg_info stat_mem; | |
| - struct bnxt_ctx_pg_info mrav_mem; | |
| - struct bnxt_ctx_pg_info tim_mem; | |
| - struct bnxt_ctx_pg_info *tqm_mem[9]; | |
| - struct bnxt_mem_init mem_init[6]; | |
| -}; | |
| - | |
| -struct bnxt_dl { | |
| - struct bnxt *bp; | |
| - bool remote_reset; | |
| -}; | |
| - | |
| -struct bnxt_dl_nvm_param { | |
| - u16 id; | |
| - u16 offset; | |
| - u16 dir_type; | |
| - u16 nvm_num_bits; | |
| - u8 dl_num_bytes; | |
| + struct notifier_block *head; | |
| }; | |
| -struct bnxt_msix_entry { | |
| - u32 vector; | |
| - u32 ring_idx; | |
| - u32 db_offset; | |
| +struct fpoint_info { | |
| + u32 base_addr; | |
| + bool present; | |
| + unsigned char irq_ch; | |
| + unsigned char scsi_id; | |
| + unsigned char scsi_lun; | |
| + u16 fw_rev; | |
| + u16 sync_ok; | |
| + u16 fast_ok; | |
| + u16 ultra_ok; | |
| + u16 discon_ok; | |
| + u16 wide_ok; | |
| + bool parity: 1; | |
| + bool wide: 1; | |
| + bool softreset: 1; | |
| + bool ext_trans_enable: 1; | |
| + bool low_term: 1; | |
| + bool high_term: 1; | |
| + bool report_underrun: 1; | |
| + bool scam_enabled: 1; | |
| + bool scam_lev2: 1; | |
| + unsigned char family; | |
| + unsigned char bus_type; | |
| + unsigned char model[3]; | |
| + unsigned char relative_cardnum; | |
| + unsigned char rsvd[4]; | |
| + u32 os_rsvd; | |
| + unsigned char translation_info[4]; | |
| + u32 rsvd2[5]; | |
| + u32 sec_range; | |
| }; | |
| -struct bnxt_ulp; | |
| - | |
| -struct bnxt_en_dev { | |
| - struct net_device *net; | |
| - struct pci_dev *pdev; | |
| - struct bnxt_msix_entry msix_entries[9]; | |
| - u32 flags; | |
| - struct bnxt_ulp *ulp_tbl; | |
| - int l2_db_size; | |
| - int l2_db_size_nc; | |
| - u16 chip_num; | |
| - u16 hw_ring_stats_size; | |
| - u16 pf_port_id; | |
| - unsigned long en_state; | |
| +struct blogic_tgt_flags { | |
| + bool tgt_exists: 1; | |
| + bool tagq_ok: 1; | |
| + bool wide_ok: 1; | |
| + bool tagq_active: 1; | |
| + bool wide_active: 1; | |
| + bool cmd_good: 1; | |
| + bool tgt_info_in: 1; | |
| }; | |
| -struct bnxt_fw_header { | |
| - __le32 signature; | |
| - u8 flags; | |
| - u8 code_type; | |
| - u8 device; | |
| - u8 media; | |
| - u8 version[16]; | |
| - u8 build; | |
| - u8 revision; | |
| - u8 minor_ver; | |
| - u8 major_ver; | |
| +struct blogic_byte_count { | |
| + unsigned int units; | |
| + unsigned int billions; | |
| }; | |
| -struct devlink_health_reporter; | |
| - | |
| -struct bnxt_fw_health { | |
| - u32 flags; | |
| - u32 polling_dsecs; | |
| - u32 master_func_wait_dsecs; | |
| - u32 normal_func_wait_dsecs; | |
| - u32 post_reset_wait_dsecs; | |
| - u32 post_reset_max_wait_dsecs; | |
| - u32 regs[4]; | |
| - u32 mapped_regs[4]; | |
| - u32 fw_reset_inprog_reg_mask; | |
| - u32 last_fw_heartbeat; | |
| - u32 last_fw_reset_cnt; | |
| - u8 enabled: 1; | |
| - u8 primary: 1; | |
| - u8 status_reliable: 1; | |
| - u8 resets_reliable: 1; | |
| - u8 tmr_multiplier; | |
| - u8 tmr_counter; | |
| - u8 fw_reset_seq_cnt; | |
| - u32 fw_reset_seq_regs[16]; | |
| - u32 fw_reset_seq_vals[16]; | |
| - u32 fw_reset_seq_delay_msec[16]; | |
| - u32 echo_req_data1; | |
| - u32 echo_req_data2; | |
| - struct devlink_health_reporter *fw_reporter; | |
| - struct mutex lock; | |
| - enum bnxt_health_severity severity; | |
| - enum bnxt_health_remedy remedy; | |
| - u32 arrests; | |
| - u32 discoveries; | |
| - u32 survivals; | |
| - u32 fatalities; | |
| - u32 diagnoses; | |
| +struct blogic_tgt_stats { | |
| + unsigned int cmds_tried; | |
| + unsigned int cmds_complete; | |
| + unsigned int read_cmds; | |
| + unsigned int write_cmds; | |
| + struct blogic_byte_count bytesread; | |
| + struct blogic_byte_count byteswritten; | |
| + unsigned int read_sz_buckets[10]; | |
| + unsigned int write_sz_buckets[10]; | |
| + short unsigned int aborts_request; | |
| + short unsigned int aborts_tried; | |
| + short unsigned int aborts_done; | |
| + short unsigned int bdr_request; | |
| + short unsigned int bdr_tried; | |
| + short unsigned int bdr_done; | |
| + short unsigned int adapter_reset_req; | |
| + short unsigned int adapter_reset_attempt; | |
| + short unsigned int adapter_reset_done; | |
| }; | |
| -struct bnxt_fw_msg { | |
| - void *msg; | |
| - int msg_len; | |
| - void *resp; | |
| - int resp_max_len; | |
| - int timeout; | |
| -}; | |
| +struct blogic_drvr_options; | |
| -struct output; | |
| +struct blogic_ccb; | |
| -struct input; | |
| +struct blogic_outbox; | |
| -struct bnxt_hwrm_ctx { | |
| - u64 sentinel; | |
| - dma_addr_t dma_handle; | |
| - struct output *resp; | |
| - struct input *req; | |
| - dma_addr_t slice_handle; | |
| - void *slice_addr; | |
| - u32 slice_size; | |
| - u32 req_len; | |
| - enum bnxt_hwrm_ctx_flags flags; | |
| - unsigned int timeout; | |
| - u32 allocated; | |
| - gfp_t gfp; | |
| -}; | |
| +struct blogic_inbox; | |
| -struct bnxt_hwrm_dbg_dma_info { | |
| - void *dest_buf; | |
| - int dest_buf_size; | |
| - u16 dma_len; | |
| - u16 seq_off; | |
| - u16 data_len_off; | |
| - u16 segs; | |
| - u32 seg_start; | |
| - u32 buf_len; | |
| +struct blogic_adapter { | |
| + struct Scsi_Host *scsi_host; | |
| + struct pci_dev *pci_device; | |
| + enum blogic_adapter_type adapter_type; | |
| + enum blogic_adapter_bus_type adapter_bus_type; | |
| + long unsigned int io_addr; | |
| + long unsigned int pci_addr; | |
| + short unsigned int addr_count; | |
| + unsigned char host_no; | |
| + unsigned char model[9]; | |
| + unsigned char fw_ver[6]; | |
| + unsigned char full_model[18]; | |
| + unsigned char bus; | |
| + unsigned char dev; | |
| + unsigned char irq_ch; | |
| + unsigned char scsi_id; | |
| + bool irq_acquired: 1; | |
| + bool ext_trans_enable: 1; | |
| + bool parity: 1; | |
| + bool reset_enabled: 1; | |
| + bool level_int: 1; | |
| + bool wide: 1; | |
| + bool differential: 1; | |
| + bool scam: 1; | |
| + bool ultra: 1; | |
| + bool ext_lun: 1; | |
| + bool terminfo_valid: 1; | |
| + bool low_term: 1; | |
| + bool high_term: 1; | |
| + bool strict_rr: 1; | |
| + bool scam_enabled: 1; | |
| + bool scam_lev2: 1; | |
| + bool adapter_initd: 1; | |
| + bool adapter_extreset: 1; | |
| + bool adapter_intern_err: 1; | |
| + bool processing_ccbs; | |
| + volatile bool adapter_cmd_complete; | |
| + short unsigned int adapter_sglimit; | |
| + short unsigned int drvr_sglimit; | |
| + short unsigned int maxdev; | |
| + short unsigned int maxlun; | |
| + short unsigned int mbox_count; | |
| + short unsigned int initccbs; | |
| + short unsigned int inc_ccbs; | |
| + short unsigned int alloc_ccbs; | |
| + short unsigned int drvr_qdepth; | |
| + short unsigned int adapter_qdepth; | |
| + short unsigned int untag_qdepth; | |
| + short unsigned int common_qdepth; | |
| + short unsigned int bus_settle_time; | |
| + short unsigned int sync_ok; | |
| + short unsigned int fast_ok; | |
| + short unsigned int ultra_ok; | |
| + short unsigned int wide_ok; | |
| + short unsigned int discon_ok; | |
| + short unsigned int tagq_ok; | |
| + short unsigned int ext_resets; | |
| + short unsigned int adapter_intern_errors; | |
| + short unsigned int tgt_count; | |
| + short unsigned int msgbuflen; | |
| + u32 bios_addr; | |
| + struct blogic_drvr_options *drvr_opts; | |
| + struct fpoint_info fpinfo; | |
| + void *cardhandle; | |
| + struct list_head host_list; | |
| + struct blogic_ccb *all_ccbs; | |
| + struct blogic_ccb *free_ccbs; | |
| + struct blogic_ccb *firstccb; | |
| + struct blogic_ccb *lastccb; | |
| + struct blogic_ccb *bdr_pend[16]; | |
| + struct blogic_tgt_flags tgt_flags[16]; | |
| + unsigned char qdepth[16]; | |
| + unsigned char sync_period[16]; | |
| + unsigned char sync_offset[16]; | |
| + unsigned char active_cmds[16]; | |
| + unsigned int cmds_since_rst[16]; | |
| + long unsigned int last_seqpoint[16]; | |
| + long unsigned int last_resettried[16]; | |
| + long unsigned int last_resetdone[16]; | |
| + struct blogic_outbox *first_outbox; | |
| + struct blogic_outbox *last_outbox; | |
| + struct blogic_outbox *next_outbox; | |
| + struct blogic_inbox *first_inbox; | |
| + struct blogic_inbox *last_inbox; | |
| + struct blogic_inbox *next_inbox; | |
| + struct blogic_tgt_stats tgt_stats[16]; | |
| + unsigned char *mbox_space; | |
| + dma_addr_t mbox_space_handle; | |
| + unsigned int mbox_sz; | |
| + long unsigned int ccb_offset; | |
| + char msgbuf[9700]; | |
| }; | |
| -struct bnxt_hwrm_wait_token { | |
| - struct callback_head rcu; | |
| - struct hlist_node node; | |
| - enum bnxt_hwrm_wait_state state; | |
| - enum bnxt_hwrm_chnl dst; | |
| - u16 seq_id; | |
| +struct blogic_adapter_info { | |
| + enum blogic_isa_ioport isa_port; | |
| + unsigned char irq_ch; | |
| + bool low_term: 1; | |
| + bool high_term: 1; | |
| + char: 2; | |
| + bool JP1: 1; | |
| + bool JP2: 1; | |
| + bool JP3: 1; | |
| + bool genericinfo_valid: 1; | |
| + int: 0; | |
| }; | |
| -struct bnxt_irq { | |
| - irq_handler_t handler; | |
| - unsigned int vector; | |
| - u8 requested: 1; | |
| - u8 have_cpumask: 1; | |
| - char name[18]; | |
| - cpumask_var_t cpu_mask; | |
| -}; | |
| +struct blogic_autoscsi { | |
| + unsigned char factory_sig[2]; | |
| + unsigned char info_bytes; | |
| + unsigned char adapter_type[6]; | |
| + short: 0; | |
| + bool floppy: 1; | |
| + bool floppy_sec: 1; | |
| + bool level_int: 1; | |
| + char: 2; | |
| + unsigned char systemram_bios: 3; | |
| + unsigned char dma_ch: 7; | |
| + bool dma_autoconf: 1; | |
| + unsigned char irq_ch: 7; | |
| + bool irq_autoconf: 1; | |
| + unsigned char dma_tx_rate; | |
| + unsigned char scsi_id; | |
| + bool low_term: 1; | |
| + bool parity: 1; | |
| + bool high_term: 1; | |
| + bool noisy_cable: 1; | |
| + bool fast_sync_neg: 1; | |
| + bool reset_enabled: 1; | |
| + char: 1; | |
| + bool active_negation: 1; | |
| + unsigned char bus_on_delay; | |
| + unsigned char bus_off_delay; | |
| + bool bios_enabled: 1; | |
| + bool int19_redir_enabled: 1; | |
| + bool ext_trans_enable: 1; | |
| + bool removable_as_fixed: 1; | |
| + char: 1; | |
| + bool morethan2_drives: 1; | |
| + bool bios_int: 1; | |
| + bool floptical: 1; | |
| + short unsigned int dev_enabled; | |
| + short unsigned int wide_ok; | |
| + short unsigned int fast_ok; | |
| + short unsigned int sync_ok; | |
| + short unsigned int discon_ok; | |
| + short unsigned int send_start_unit; | |
| + short unsigned int ignore_bios_scan; | |
| + unsigned char pci_int_pin: 2; | |
| + unsigned char adapter_ioport: 2; | |
| + bool strict_rr_enabled: 1; | |
| + bool vesabus_33mhzplus: 1; | |
| + bool vesa_burst_write: 1; | |
| + bool vesa_burst_read: 1; | |
| + short unsigned int ultra_ok; | |
| + long: 0; | |
| + char: 8; | |
| + unsigned char autoscsi_maxlun; | |
| + char: 1; | |
| + bool scam_dominant: 1; | |
| + bool scam_enabled: 1; | |
| + bool scam_lev2: 1; | |
| + char: 4; | |
| + bool int13_exten: 1; | |
| + char: 1; | |
| + bool cd_boot: 1; | |
| + int: 5; | |
| + unsigned char boot_id: 4; | |
| + unsigned char boot_ch: 4; | |
| + unsigned char force_scan_order: 1; | |
| + short unsigned int nontagged_to_alt_ok; | |
| + short unsigned int reneg_sync_on_check; | |
| + unsigned char rsvd[10]; | |
| + unsigned char manuf_diag[2]; | |
| + short unsigned int cksum; | |
| +} __attribute__((packed)); | |
| -struct bnxt_led_cfg { | |
| - u8 led_id; | |
| - u8 led_state; | |
| - u8 led_color; | |
| - u8 unused; | |
| - __le16 led_blink_on; | |
| - __le16 led_blink_off; | |
| - u8 led_group_id; | |
| - u8 rsvd; | |
| +struct blogic_autoscsi_byte45 { | |
| + unsigned char force_scan_order: 1; | |
| }; | |
| -struct gro_list { | |
| - struct list_head list; | |
| - int count; | |
| +struct blogic_bios_drvmap { | |
| + unsigned char tgt_idbit3: 1; | |
| + char: 2; | |
| + enum blogic_bios_diskgeometry diskgeom: 2; | |
| + unsigned char tgt_id: 3; | |
| }; | |
| -struct napi_struct { | |
| - struct list_head poll_list; | |
| - unsigned long state; | |
| - int weight; | |
| - int defer_hard_irqs_count; | |
| - unsigned long gro_bitmask; | |
| - int (*poll)(struct napi_struct *, int); | |
| - int poll_owner; | |
| - int list_owner; | |
| - struct net_device *dev; | |
| - struct gro_list gro_hash[8]; | |
| - struct sk_buff *skb; | |
| - struct list_head rx_list; | |
| - int rx_count; | |
| - unsigned int napi_id; | |
| - struct hrtimer timer; | |
| - struct task_struct *thread; | |
| - struct list_head dev_list; | |
| - struct hlist_node napi_hash_node; | |
| - int irq; | |
| +struct blogic_board_id { | |
| + unsigned char type; | |
| + unsigned char custom_features; | |
| + unsigned char fw_ver_digit1; | |
| + unsigned char fw_ver_digit2; | |
| }; | |
| -struct bnxt_napi { | |
| - struct napi_struct napi; | |
| - struct bnxt *bp; | |
| - int index; | |
| - struct bnxt_cp_ring_info cp_ring; | |
| - struct bnxt_rx_ring_info *rx_ring; | |
| - struct bnxt_tx_ring_info *tx_ring; | |
| - void (*tx_int)(struct bnxt *, struct bnxt_napi *, int); | |
| - int tx_pkts; | |
| - u8 events; | |
| - u8 tx_fault: 1; | |
| - u32 flags; | |
| - bool in_reset; | |
| +struct blogic_sg_seg { | |
| + u32 segbytes; | |
| + u32 segdata; | |
| }; | |
| -struct flow_dissector_key_control { | |
| - u16 thoff; | |
| - u16 addr_type; | |
| - u32 flags; | |
| +struct blogic_ccb { | |
| + enum blogic_ccb_opcode opcode; | |
| + char: 3; | |
| + enum blogic_datadir datadir: 2; | |
| + bool tag_enable: 1; | |
| + enum blogic_queuetag queuetag: 2; | |
| + unsigned char cdblen; | |
| + unsigned char sense_datalen; | |
| + u32 datalen; | |
| + u32 data; | |
| + short: 16; | |
| + enum blogic_adapter_status adapter_status; | |
| + enum blogic_tgt_status tgt_status; | |
| + unsigned char tgt_id; | |
| + unsigned char lun: 5; | |
| + bool legacytag_enable: 1; | |
| + enum blogic_queuetag legacy_tag: 2; | |
| + unsigned char cdb[12]; | |
| + u32 rsvd_int; | |
| + u32 sensedata; | |
| + void (*callback)(struct blogic_ccb *); | |
| + u32 base_addr; | |
| + enum blogic_cmplt_code comp_code; | |
| + dma_addr_t allocgrp_head; | |
| + unsigned int allocgrp_size; | |
| + u32 dma_handle; | |
| + enum blogic_ccb_status status; | |
| + long unsigned int serial; | |
| + struct scsi_cmnd *command; | |
| + struct blogic_adapter *adapter; | |
| + struct blogic_ccb *next; | |
| + struct blogic_ccb *next_all; | |
| + struct blogic_sg_seg sglist[128]; | |
| }; | |
| -struct flow_dissector_key_basic { | |
| - __be16 n_proto; | |
| - u8 ip_proto; | |
| - u8 padding; | |
| +struct blogic_config { | |
| + char: 5; | |
| + bool dma_ch5: 1; | |
| + bool dma_ch6: 1; | |
| + bool dma_ch7: 1; | |
| + bool irq_ch9: 1; | |
| + bool irq_ch10: 1; | |
| + bool irq_ch11: 1; | |
| + bool irq_ch12: 1; | |
| + char: 1; | |
| + bool irq_ch14: 1; | |
| + bool irq_ch15: 1; | |
| + short: 1; | |
| + unsigned char id: 4; | |
| }; | |
| -struct flow_dissector_key_tags { | |
| - u32 flow_label; | |
| +struct blogic_drvr_options { | |
| + short unsigned int tagq_ok; | |
| + short unsigned int tagq_ok_mask; | |
| + short unsigned int bus_settle_time; | |
| + short unsigned int stop_tgt_inquiry; | |
| + unsigned char common_qdepth; | |
| + unsigned char qdepth[16]; | |
| }; | |
| -struct flow_dissector_key_vlan { | |
| - union { | |
| +struct blogic_ext_setup { | |
| + unsigned char bus_type; | |
| + unsigned char bios_addr; | |
| + short unsigned int sg_limit; | |
| + unsigned char mbox_count; | |
| + u32 base_mbox_addr; | |
| struct { | |
| - u16 vlan_id: 12; | |
| - u16 vlan_dei: 1; | |
| - u16 vlan_priority: 3; | |
| - }; | |
| - __be16 vlan_tci; | |
| - }; | |
| - __be16 vlan_tpid; | |
| - __be16 vlan_eth_type; | |
| - u16 padding; | |
| -}; | |
| + char: 2; | |
| + bool fast_on_eisa: 1; | |
| + char: 3; | |
| + bool level_int: 1; | |
| + } misc; | |
| + unsigned char fw_rev[3]; | |
| + bool wide: 1; | |
| + bool differential: 1; | |
| + bool scam: 1; | |
| + bool ultra: 1; | |
| + bool smart_term: 1; | |
| +} __attribute__((packed)); | |
| -struct flow_dissector_key_keyid { | |
| - __be32 keyid; | |
| -}; | |
| +struct blogic_extmbox_req { | |
| + unsigned char mbox_count; | |
| + u32 base_mbox_addr; | |
| +} __attribute__((packed)); | |
| -struct flow_dissector_key_ports { | |
| - union { | |
| - __be32 ports; | |
| - struct { | |
| - __be16 src; | |
| - __be16 dst; | |
| - }; | |
| - }; | |
| +struct blogic_fetch_localram { | |
| + unsigned char offset; | |
| + unsigned char count; | |
| }; | |
| -struct flow_dissector_key_icmp { | |
| - struct { | |
| - u8 type; | |
| - u8 code; | |
| - }; | |
| - u16 id; | |
| +struct blogic_global_options { | |
| + bool trace_probe: 1; | |
| + bool trace_hw_reset: 1; | |
| + bool trace_config: 1; | |
| + bool trace_err: 1; | |
| }; | |
| -struct flow_dissector_key_ipv4_addrs { | |
| - __be32 src; | |
| - __be32 dst; | |
| +struct blogic_inbox { | |
| + u32 ccb; | |
| + enum blogic_adapter_status adapter_status; | |
| + enum blogic_tgt_status tgt_status; | |
| + char: 8; | |
| + enum blogic_cmplt_code comp_code; | |
| }; | |
| -struct flow_dissector_key_ipv6_addrs { | |
| - struct in6_addr src; | |
| - struct in6_addr dst; | |
| +struct blogic_outbox { | |
| + u32 ccb; | |
| + int: 24; | |
| + enum blogic_action action; | |
| }; | |
| -struct flow_dissector_key_tipc { | |
| - __be32 key; | |
| +struct blogic_probe_options { | |
| + bool noprobe: 1; | |
| + bool noprobe_pci: 1; | |
| + bool nosort_pci: 1; | |
| + bool multimaster_first: 1; | |
| + bool flashpoint_first: 1; | |
| }; | |
| -struct flow_dissector_key_addrs { | |
| - union { | |
| - struct flow_dissector_key_ipv4_addrs v4addrs; | |
| - struct flow_dissector_key_ipv6_addrs v6addrs; | |
| - struct flow_dissector_key_tipc tipckey; | |
| - }; | |
| +struct blogic_probeinfo { | |
| + enum blogic_adapter_type adapter_type; | |
| + enum blogic_adapter_bus_type adapter_bus_type; | |
| + long unsigned int io_addr; | |
| + long unsigned int pci_addr; | |
| + struct pci_dev *pci_device; | |
| + unsigned char bus; | |
| + unsigned char dev; | |
| + unsigned char irq_ch; | |
| }; | |
| -struct flow_keys { | |
| - struct flow_dissector_key_control control; | |
| - struct flow_dissector_key_basic basic; | |
| - struct flow_dissector_key_tags tags; | |
| - struct flow_dissector_key_vlan vlan; | |
| - struct flow_dissector_key_vlan cvlan; | |
| - struct flow_dissector_key_keyid keyid; | |
| - struct flow_dissector_key_ports ports; | |
| - struct flow_dissector_key_icmp icmp; | |
| - struct flow_dissector_key_addrs addrs; | |
| - long: 0; | |
| +struct blogic_syncval { | |
| + unsigned char offset: 4; | |
| + unsigned char tx_period: 3; | |
| + bool sync: 1; | |
| }; | |
| -struct bnxt_ntuple_filter { | |
| - struct hlist_node hash; | |
| - u8 dst_mac_addr[6]; | |
| - u8 src_mac_addr[6]; | |
| +struct blogic_setup_info { | |
| + bool sync: 1; | |
| + bool parity: 1; | |
| + unsigned char tx_rate; | |
| + unsigned char preempt_time; | |
| + unsigned char timeoff_bus; | |
| + unsigned char mbox_count; | |
| + unsigned char mbox_addr[3]; | |
| + struct blogic_syncval sync0to7[8]; | |
| + unsigned char disconnect_ok0to7; | |
| + unsigned char sig; | |
| + unsigned char char_d; | |
| + unsigned char bus_type; | |
| + unsigned char wide_tx_ok0to7; | |
| + unsigned char wide_tx_active0to7; | |
| + struct blogic_syncval sync8to15[8]; | |
| + unsigned char disconnect_ok8to15; | |
| long: 0; | |
| - struct flow_keys fkeys; | |
| - __le64 filter_id; | |
| - u16 sw_id; | |
| - u8 l2_fltr_idx; | |
| - u16 rxq; | |
| - u32 flow_id; | |
| - unsigned long state; | |
| -}; | |
| - | |
| -struct pps_pin { | |
| - u8 event; | |
| - u8 usage; | |
| - u8 state; | |
| -}; | |
| - | |
| -struct bnxt_pps { | |
| - u8 num_pins; | |
| - struct pps_pin pins[4]; | |
| -}; | |
| - | |
| -struct ptp_pin_desc; | |
| - | |
| -struct ptp_system_timestamp; | |
| - | |
| -struct system_device_crosststamp; | |
| - | |
| -struct ptp_clock_request; | |
| - | |
| -struct ptp_clock_info { | |
| - struct module *owner; | |
| - char name[32]; | |
| - s32 max_adj; | |
| - int n_alarm; | |
| - int n_ext_ts; | |
| - int n_per_out; | |
| - int n_pins; | |
| - int pps; | |
| - struct ptp_pin_desc *pin_config; | |
| - int (*adjfine)(struct ptp_clock_info *, long); | |
| - int (*adjphase)(struct ptp_clock_info *, s32); | |
| - int (*adjtime)(struct ptp_clock_info *, s64); | |
| - int (*gettime64)(struct ptp_clock_info *, struct timespec64 *); | |
| - int (*gettimex64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *); | |
| - int (*getcrosststamp)(struct ptp_clock_info *, struct system_device_crosststamp *); | |
| - int (*settime64)(struct ptp_clock_info *, const struct timespec64 *); | |
| - int (*getcycles64)(struct ptp_clock_info *, struct timespec64 *); | |
| - int (*getcyclesx64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *); | |
| - int (*getcrosscycles)(struct ptp_clock_info *, struct system_device_crosststamp *); | |
| - int (*enable)(struct ptp_clock_info *, struct ptp_clock_request *, int); | |
| - int (*verify)(struct ptp_clock_info *, unsigned int, enum ptp_pin_function, unsigned int); | |
| - long (*do_aux_work)(struct ptp_clock_info *); | |
| -}; | |
| - | |
| -struct cyclecounter { | |
| - u64 (*read)(const struct cyclecounter *); | |
| - u64 mask; | |
| - u32 mult; | |
| - u32 shift; | |
| -}; | |
| - | |
| -struct timecounter { | |
| - const struct cyclecounter *cc; | |
| - u64 cycle_last; | |
| - u64 nsec; | |
| - u64 mask; | |
| - u64 frac; | |
| -}; | |
| - | |
| -struct ptp_clock; | |
| - | |
| -struct bnxt_ptp_cfg { | |
| - struct ptp_clock_info ptp_info; | |
| - struct ptp_clock *ptp_clock; | |
| - struct cyclecounter cc; | |
| - struct timecounter tc; | |
| - struct bnxt_pps pps_info; | |
| - spinlock_t ptp_lock; | |
| - struct sk_buff *tx_skb; | |
| - u64 current_time; | |
| - u64 old_time; | |
| - unsigned long next_period; | |
| - unsigned long next_overflow_check; | |
| - u32 cmult; | |
| - u16 tx_seqid; | |
| - u16 tx_hdr_off; | |
| - struct bnxt *bp; | |
| - atomic_t tx_avail; | |
| - u16 rxctl; | |
| - u8 tx_tstamp_en: 1; | |
| - u8 txts_pending: 1; | |
| - int rx_filter; | |
| - u32 tstamp_filters; | |
| - u32 refclk_regs[2]; | |
| - u32 refclk_mapped_regs[2]; | |
| - u32 txts_tmo; | |
| - unsigned long abs_txts_tmo; | |
| -}; | |
| - | |
| -struct bnxt_ring_grp_info { | |
| - u16 fw_stats_ctx; | |
| - u16 fw_grp_id; | |
| - u16 rx_fw_ring_id; | |
| - u16 agg_fw_ring_id; | |
| - u16 cp_fw_ring_id; | |
| -}; | |
| - | |
| -struct xdp_mem_info { | |
| - u32 type; | |
| - u32 id; | |
| -}; | |
| - | |
| -struct xdp_rxq_info { | |
| - struct net_device *dev; | |
| - u32 queue_index; | |
| - u32 reg_state; | |
| - struct xdp_mem_info mem; | |
| - unsigned int napi_id; | |
| - u32 frag_size; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| -}; | |
| - | |
| -struct rx_bd; | |
| - | |
| -struct bnxt_sw_rx_bd; | |
| - | |
| -struct bnxt_sw_rx_agg_bd; | |
| - | |
| -struct bnxt_tpa_idx_map; | |
| - | |
| -struct page_pool; | |
| - | |
| -struct bnxt_rx_ring_info { | |
| - struct bnxt_napi *bnapi; | |
| - u16 rx_prod; | |
| - u16 rx_agg_prod; | |
| - u16 rx_sw_agg_prod; | |
| - u16 rx_next_cons; | |
| - struct bnxt_db_info rx_db; | |
| - struct bnxt_db_info rx_agg_db; | |
| - struct bpf_prog *xdp_prog; | |
| - struct rx_bd *rx_desc_ring[32]; | |
| - struct bnxt_sw_rx_bd *rx_buf_ring; | |
| - struct rx_bd *rx_agg_desc_ring[32]; | |
| - struct bnxt_sw_rx_agg_bd *rx_agg_ring; | |
| - unsigned long *rx_agg_bmap; | |
| - u16 rx_agg_bmap_size; | |
| - dma_addr_t rx_desc_mapping[32]; | |
| - dma_addr_t rx_agg_desc_mapping[32]; | |
| - struct bnxt_tpa_info *rx_tpa; | |
| - struct bnxt_tpa_idx_map *rx_tpa_idx_map; | |
| - struct bnxt_ring_struct rx_ring_struct; | |
| - struct bnxt_ring_struct rx_agg_ring_struct; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - struct xdp_rxq_info xdp_rxq; | |
| - struct page_pool *page_pool; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| -}; | |
| - | |
| -struct bnxt_sw_rx_agg_bd { | |
| - struct page *page; | |
| - unsigned int offset; | |
| - dma_addr_t mapping; | |
| -}; | |
| - | |
| -struct bnxt_sw_rx_bd { | |
| - void *data; | |
| - u8 *data_ptr; | |
| - dma_addr_t mapping; | |
| -}; | |
| - | |
| -struct xdp_frame; | |
| - | |
| -struct bnxt_sw_tx_bd { | |
| - union { | |
| - struct sk_buff *skb; | |
| - struct xdp_frame *xdpf; | |
| - }; | |
| - dma_addr_t mapping; | |
| - __u32 len; | |
| - struct page *page; | |
| - u8 is_gso; | |
| - u8 is_push; | |
| - u8 action; | |
| - unsigned short nr_frags; | |
| - u16 rx_prod; | |
| -}; | |
| - | |
| -struct bnxt_tc_flow_stats { | |
| - u64 packets; | |
| - u64 bytes; | |
| -}; | |
| - | |
| -typedef u32 (*rht_hashfn_t)(const void *, u32, u32); | |
| - | |
| -typedef u32 (*rht_obj_hashfn_t)(const void *, u32, u32); | |
| - | |
| -struct rhashtable_compare_arg; | |
| - | |
| -typedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *, const void *); | |
| - | |
| -struct rhashtable_params { | |
| - u16 nelem_hint; | |
| - u16 key_len; | |
| - u16 key_offset; | |
| - u16 head_offset; | |
| - unsigned int max_size; | |
| - u16 min_size; | |
| - bool automatic_shrinking; | |
| - rht_hashfn_t hashfn; | |
| - rht_obj_hashfn_t obj_hashfn; | |
| - rht_obj_cmpfn_t obj_cmpfn; | |
| -}; | |
| - | |
| -struct bucket_table; | |
| - | |
| -struct rhashtable { | |
| - struct bucket_table __attribute__((btf_type_tag("rcu"))) *tbl; | |
| - unsigned int key_len; | |
| - unsigned int max_elems; | |
| - struct rhashtable_params p; | |
| - bool rhlist; | |
| - struct work_struct run_work; | |
| - struct mutex mutex; | |
| - spinlock_t lock; | |
| - atomic_t nelems; | |
| -}; | |
| - | |
| -struct rhashtable_walker { | |
| - struct list_head list; | |
| - struct bucket_table *tbl; | |
| -}; | |
| - | |
| -struct rhash_head; | |
| - | |
| -struct rhlist_head; | |
| - | |
| -struct rhashtable_iter { | |
| - struct rhashtable *ht; | |
| - struct rhash_head *p; | |
| - struct rhlist_head *list; | |
| - struct rhashtable_walker walker; | |
| - unsigned int slot; | |
| - unsigned int skip; | |
| - bool end_of_table; | |
| -}; | |
| - | |
| -struct bnxt_tc_stats_batch { | |
| - void *flow_node; | |
| - struct bnxt_tc_flow_stats hw_stats; | |
| -}; | |
| - | |
| -struct bnxt_tc_info { | |
| - bool enabled; | |
| - struct rhashtable flow_table; | |
| - struct rhashtable_params flow_ht_params; | |
| - struct rhashtable l2_table; | |
| - struct rhashtable_params l2_ht_params; | |
| - struct rhashtable decap_l2_table; | |
| - struct rhashtable_params decap_l2_ht_params; | |
| - struct rhashtable decap_table; | |
| - struct rhashtable_params decap_ht_params; | |
| - struct rhashtable encap_table; | |
| - struct rhashtable_params encap_ht_params; | |
| - struct mutex lock; | |
| - struct rhashtable_iter iter; | |
| - struct bnxt_tc_stats_batch stats_batch[10]; | |
| - u64 bytes_mask; | |
| - u64 packets_mask; | |
| -}; | |
| - | |
| -struct bnxt_test_info { | |
| - u8 offline_mask; | |
| - u16 timeout; | |
| - char string[256]; | |
| -}; | |
| - | |
| -struct bnxt_tpa_idx_map { | |
| - u16 agg_id_tbl[1024]; | |
| - unsigned long agg_idx_bmap[4]; | |
| -}; | |
| - | |
| -struct rx_agg_cmp; | |
| - | |
| -struct bnxt_tpa_info { | |
| - void *data; | |
| - u8 *data_ptr; | |
| - dma_addr_t mapping; | |
| - u16 len; | |
| - unsigned short gso_type; | |
| - u32 flags2; | |
| - u32 metadata; | |
| - enum pkt_hash_types hash_type; | |
| - u32 rss_hash; | |
| - u32 hdr_info; | |
| - u16 cfa_code; | |
| - u8 agg_count; | |
| - struct rx_agg_cmp *agg_arr; | |
| -}; | |
| - | |
| -struct tx_bd; | |
| - | |
| -struct tx_push_buffer; | |
| - | |
| -struct bnxt_tx_ring_info { | |
| - struct bnxt_napi *bnapi; | |
| - u16 tx_prod; | |
| - u16 tx_cons; | |
| - u16 txq_index; | |
| - u8 kick_pending; | |
| - struct bnxt_db_info tx_db; | |
| - struct tx_bd *tx_desc_ring[8]; | |
| - struct bnxt_sw_tx_bd *tx_buf_ring; | |
| - dma_addr_t tx_desc_mapping[8]; | |
| - struct tx_push_buffer *tx_push; | |
| - dma_addr_t tx_push_mapping; | |
| - __le64 data_mapping; | |
| - u32 dev_state; | |
| - struct bnxt_ring_struct tx_ring_struct; | |
| - spinlock_t xdp_tx_lock; | |
| -}; | |
| - | |
| -struct bnxt_ucode_trailer { | |
| - u8 rsa_sig[256]; | |
| - __le16 flags; | |
| - u8 version_format; | |
| - u8 version_length; | |
| - u8 version[16]; | |
| - __le16 dir_type; | |
| - __le16 trailer_length; | |
| - __le32 sig; | |
| - __le32 chksum; | |
| -}; | |
| - | |
| -struct bnxt_ulp_ops; | |
| - | |
| -struct bnxt_ulp { | |
| - void *handle; | |
| - struct bnxt_ulp_ops __attribute__((btf_type_tag("rcu"))) *ulp_ops; | |
| - unsigned long *async_events_bmap; | |
| - u16 max_async_event_id; | |
| - u16 msix_requested; | |
| - u16 msix_base; | |
| - atomic_t ref_count; | |
| -}; | |
| - | |
| -struct bnxt_ulp_ops { | |
| - void (*ulp_irq_stop)(void *); | |
| - void (*ulp_irq_restart)(void *, struct bnxt_msix_entry *); | |
| -}; | |
| - | |
| -struct bnxt_vf_rep_stats { | |
| - u64 packets; | |
| - u64 bytes; | |
| - u64 dropped; | |
| -}; | |
| - | |
| -struct metadata_dst; | |
| - | |
| -struct bnxt_vf_rep { | |
| - struct bnxt *bp; | |
| - struct net_device *dev; | |
| - struct metadata_dst *dst; | |
| - u16 vf_idx; | |
| - u16 tx_cfa_action; | |
| - u16 rx_cfa_code; | |
| - struct bnxt_vf_rep_stats rx_stats; | |
| - struct bnxt_vf_rep_stats tx_stats; | |
| -}; | |
| - | |
| -struct bnxt_vnic_info { | |
| - u16 fw_vnic_id; | |
| - u16 fw_rss_cos_lb_ctx[8]; | |
| - u16 fw_l2_ctx_id; | |
| - __le64 fw_l2_filter_id[4]; | |
| - u16 uc_filter_count; | |
| - u8 *uc_list; | |
| - u16 *fw_grp_ids; | |
| - dma_addr_t rss_table_dma_addr; | |
| - __le16 *rss_table; | |
| - dma_addr_t rss_hash_key_dma_addr; | |
| - u64 *rss_hash_key; | |
| - int rss_table_size; | |
| - u32 rx_mask; | |
| - u8 *mc_list; | |
| - int mc_list_size; | |
| - int mc_list_count; | |
| - dma_addr_t mc_list_mapping; | |
| - u32 flags; | |
| -}; | |
| - | |
| -struct software_node; | |
| - | |
| -struct spi_board_info { | |
| - char modalias[32]; | |
| - const void *platform_data; | |
| - const struct software_node *swnode; | |
| - void *controller_data; | |
| - int irq; | |
| - u32 max_speed_hz; | |
| - u16 bus_num; | |
| - u16 chip_select; | |
| - u32 mode; | |
| -}; | |
| - | |
| -struct boardinfo { | |
| - struct list_head list; | |
| - struct spi_board_info board_info; | |
| -}; | |
| - | |
| -struct reciprocal_value { | |
| - u32 m; | |
| - u8 sh1; | |
| - u8 sh2; | |
| -}; | |
| - | |
| -struct bond_params { | |
| - int mode; | |
| - int xmit_policy; | |
| - int miimon; | |
| - u8 num_peer_notif; | |
| - u8 missed_max; | |
| - int arp_interval; | |
| - int arp_validate; | |
| - int arp_all_targets; | |
| - int use_carrier; | |
| - int fail_over_mac; | |
| - int updelay; | |
| - int downdelay; | |
| - int peer_notif_delay; | |
| - int lacp_active; | |
| - int lacp_fast; | |
| - unsigned int min_links; | |
| - int ad_select; | |
| - char primary[16]; | |
| - int primary_reselect; | |
| - __be32 arp_targets[16]; | |
| - int tx_queues; | |
| - int all_slaves_active; | |
| - int resend_igmp; | |
| - int lp_interval; | |
| - int packets_per_slave; | |
| - int tlb_dynamic_lb; | |
| - struct reciprocal_value reciprocal_packets_per_slave; | |
| - u16 ad_actor_sys_prio; | |
| - u16 ad_user_port_key; | |
| - struct in6_addr ns_targets[16]; | |
| - u8 ad_actor_system[8]; | |
| -}; | |
| - | |
| -struct bond_up_slave { | |
| - unsigned int count; | |
| - struct callback_head rcu; | |
| - struct slave *arr[0]; | |
| -}; | |
| - | |
| -struct bonding { | |
| - struct net_device *dev; | |
| - struct slave __attribute__((btf_type_tag("rcu"))) *curr_active_slave; | |
| - struct slave __attribute__((btf_type_tag("rcu"))) *current_arp_slave; | |
| - struct slave __attribute__((btf_type_tag("rcu"))) *primary_slave; | |
| - struct bond_up_slave __attribute__((btf_type_tag("rcu"))) *usable_slaves; | |
| - struct bond_up_slave __attribute__((btf_type_tag("rcu"))) *all_slaves; | |
| - bool force_primary; | |
| - bool notifier_ctx; | |
| - s32 slave_cnt; | |
| - int (*recv_probe)(const struct sk_buff *, struct bonding *, struct slave *); | |
| - spinlock_t mode_lock; | |
| - spinlock_t stats_lock; | |
| - u32 send_peer_notif; | |
| - u8 igmp_retrans; | |
| - struct proc_dir_entry *proc_entry; | |
| - char proc_file_name[16]; | |
| - struct list_head bond_list; | |
| - u32 __attribute__((btf_type_tag("percpu"))) *rr_tx_counter; | |
| - struct ad_bond_info ad_info; | |
| - struct alb_bond_info alb_info; | |
| - struct bond_params params; | |
| - struct workqueue_struct *wq; | |
| - struct delayed_work mii_work; | |
| - struct delayed_work arp_work; | |
| - struct delayed_work alb_work; | |
| - struct delayed_work ad_work; | |
| - struct delayed_work mcast_work; | |
| - struct delayed_work slave_arr_work; | |
| - struct dentry *debug_dir; | |
| - struct rtnl_link_stats64 bond_stats; | |
| - struct bpf_prog *xdp_prog; | |
| + unsigned char wide_tx_ok8to15; | |
| + unsigned char wide_tx_active8to15; | |
| }; | |
| struct boot_e820_entry { | |
| @@ -40250,15 +49823,13 @@ | |
| struct btf *btf; | |
| struct obj_cgroup *objcg; | |
| char name[16]; | |
| - long: 64; | |
| - long: 64; | |
| + struct mutex freeze_mutex; | |
| atomic64_t refcnt; | |
| atomic64_t usercnt; | |
| union { | |
| struct work_struct work; | |
| struct callback_head rcu; | |
| }; | |
| - struct mutex freeze_mutex; | |
| atomic64_t writecnt; | |
| struct { | |
| spinlock_t lock; | |
| @@ -40271,8 +49842,30 @@ | |
| bool free_after_mult_rcu_gp; | |
| bool free_after_rcu_gp; | |
| atomic64_t sleepable_refcnt; | |
| - s64 __attribute__((btf_type_tag("percpu"))) *elem_count; | |
| - long: 64; | |
| + s64 *elem_count; | |
| +}; | |
| + | |
| +typedef struct lockdep_map *lockdep_map_p; | |
| + | |
| +struct maple_tree { | |
| + union { | |
| + spinlock_t ma_lock; | |
| + lockdep_map_p ma_external_lock; | |
| + }; | |
| + unsigned int ma_flags; | |
| + void *ma_root; | |
| +}; | |
| + | |
| +struct vm_struct; | |
| + | |
| +struct bpf_arena { | |
| + struct bpf_map map; | |
| + u64 user_vm_start; | |
| + u64 user_vm_end; | |
| + struct vm_struct *kern_vm; | |
| + struct maple_tree mt; | |
| + struct list_head vma_list; | |
| + struct mutex lock; | |
| }; | |
| struct bpf_array_aux; | |
| @@ -40293,15 +49886,9 @@ | |
| }; | |
| struct { | |
| struct {} __empty_pptrs; | |
| - void __attribute__((btf_type_tag("percpu"))) *pptrs[0]; | |
| + void *pptrs[0]; | |
| }; | |
| }; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| }; | |
| struct bpf_array_aux { | |
| @@ -40311,6 +49898,34 @@ | |
| struct work_struct work; | |
| }; | |
| +struct bpf_prog; | |
| + | |
| +struct bpf_async_cb { | |
| + struct bpf_map *map; | |
| + struct bpf_prog *prog; | |
| + void *callback_fn; | |
| + void *value; | |
| + struct callback_head rcu; | |
| + u64 flags; | |
| +}; | |
| + | |
| +struct bpf_spin_lock { | |
| + __u32 val; | |
| +}; | |
| + | |
| +struct bpf_hrtimer; | |
| + | |
| +struct bpf_work; | |
| + | |
| +struct bpf_async_kern { | |
| + union { | |
| + struct bpf_async_cb *cb; | |
| + struct bpf_hrtimer *timer; | |
| + struct bpf_work *work; | |
| + }; | |
| + struct bpf_spin_lock lock; | |
| +}; | |
| + | |
| struct btf_func_model { | |
| u8 ret_size; | |
| u8 ret_flags; | |
| @@ -40323,7 +49938,7 @@ | |
| struct bpf_attach_target_info { | |
| struct btf_func_model fmodel; | |
| - long tgt_addr; | |
| + long int tgt_addr; | |
| struct module *tgt_mod; | |
| const char *tgt_name; | |
| const struct btf_type *tgt_type; | |
| @@ -40340,13 +49955,7 @@ | |
| u32 bitset_mask; | |
| u32 hash_seed; | |
| u32 nr_hash_funcs; | |
| - unsigned long bitset[0]; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| + long unsigned int bitset[0]; | |
| }; | |
| struct bpf_bprintf_buffers { | |
| @@ -40428,8 +50037,11 @@ | |
| enum bpf_link_type type; | |
| const struct bpf_link_ops *ops; | |
| struct bpf_prog *prog; | |
| + union { | |
| + struct callback_head rcu; | |
| struct work_struct work; | |
| }; | |
| +}; | |
| struct bpf_cgroup_link { | |
| struct bpf_link link; | |
| @@ -40449,7 +50061,7 @@ | |
| struct bpf_cgroup_storage { | |
| union { | |
| struct bpf_storage_buffer *buf; | |
| - void __attribute__((btf_type_tag("percpu"))) *percpu_buf; | |
| + void *percpu_buf; | |
| }; | |
| struct bpf_cgroup_storage_map *map; | |
| struct bpf_cgroup_storage_key key; | |
| @@ -40464,10 +50076,6 @@ | |
| spinlock_t lock; | |
| struct rb_root root; | |
| struct list_head list; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| }; | |
| struct bpf_lru_list { | |
| @@ -40475,20 +50083,13 @@ | |
| unsigned int counts[2]; | |
| struct list_head *next_inactive_rotation; | |
| raw_spinlock_t lock; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| }; | |
| struct bpf_lru_locallist; | |
| struct bpf_common_lru { | |
| struct bpf_lru_list lru_list; | |
| - struct bpf_lru_locallist __attribute__((btf_type_tag("percpu"))) *local_list; | |
| + struct bpf_lru_locallist *local_list; | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| @@ -40555,14 +50156,7 @@ | |
| struct bpf_cpu_map { | |
| struct bpf_map map; | |
| - struct bpf_cpu_map_entry __attribute__((btf_type_tag("rcu"))) **cpu_map; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| + struct bpf_cpu_map_entry **cpu_map; | |
| }; | |
| struct bpf_cpumap_val { | |
| @@ -40580,7 +50174,7 @@ | |
| struct bpf_cpu_map_entry { | |
| u32 cpu; | |
| int map_id; | |
| - struct xdp_bulk_queue __attribute__((btf_type_tag("percpu"))) *bulkq; | |
| + struct xdp_bulk_queue *bulkq; | |
| struct ptr_ring *queue; | |
| struct task_struct *kthread; | |
| struct bpf_cpumap_val value; | |
| @@ -40594,9 +50188,57 @@ | |
| refcount_t usage; | |
| }; | |
| +struct bpf_crypto_type; | |
| + | |
| +struct bpf_crypto_ctx { | |
| + const struct bpf_crypto_type *type; | |
| + void *tfm; | |
| + u32 siv_len; | |
| + struct callback_head rcu; | |
| + refcount_t usage; | |
| +}; | |
| + | |
| +struct bpf_crypto_params { | |
| + char type[14]; | |
| + u8 reserved[2]; | |
| + char algo[128]; | |
| + u8 key[256]; | |
| + u32 key_len; | |
| + u32 authsize; | |
| +}; | |
| + | |
| +struct bpf_crypto_type { | |
| + void * (*alloc_tfm)(const char *); | |
| + void (*free_tfm)(void *); | |
| + int (*has_algo)(const char *); | |
| + int (*setkey)(void *, const u8 *, unsigned int); | |
| + int (*setauthsize)(void *, unsigned int); | |
| + int (*encrypt)(void *, const u8 *, u8 *, unsigned int, u8 *); | |
| + int (*decrypt)(void *, const u8 *, u8 *, unsigned int, u8 *); | |
| + unsigned int (*ivsize)(void *); | |
| + unsigned int (*statesize)(void *); | |
| + u32 (*get_flags)(void *); | |
| + struct module *owner; | |
| + char name[14]; | |
| +}; | |
| + | |
| +struct bpf_crypto_type_list { | |
| + const struct bpf_crypto_type *type; | |
| + struct list_head list; | |
| +}; | |
| + | |
| +struct bpf_ct_opts { | |
| + s32 netns_id; | |
| + s32 error; | |
| + u8 l4proto; | |
| + u8 dir; | |
| + u8 reserved[2]; | |
| +}; | |
| + | |
| struct bpf_ctx_arg_aux { | |
| u32 offset; | |
| enum bpf_reg_type reg_type; | |
| + struct btf *btf; | |
| u32 btf_id; | |
| }; | |
| @@ -40609,17 +50251,14 @@ | |
| struct sk_buff *prev; | |
| union { | |
| struct net_device *dev; | |
| - unsigned long dev_scratch; | |
| + long unsigned int dev_scratch; | |
| }; | |
| }; | |
| struct rb_node rbnode; | |
| struct list_head list; | |
| struct llist_node ll_node; | |
| }; | |
| - union { | |
| struct sock *sk; | |
| - int ip_defrag_offset; | |
| - }; | |
| union { | |
| ktime_t tstamp; | |
| u64 skb_mstamp_ns; | |
| @@ -40627,13 +50266,13 @@ | |
| char cb[48]; | |
| union { | |
| struct { | |
| - unsigned long _skb_refdst; | |
| + long unsigned int _skb_refdst; | |
| void (*destructor)(struct sk_buff *); | |
| }; | |
| struct list_head tcp_tsorted_anchor; | |
| - unsigned long _sk_redir; | |
| + long unsigned int _sk_redir; | |
| }; | |
| - unsigned long _nfct; | |
| + long unsigned int _nfct; | |
| unsigned int len; | |
| unsigned int data_len; | |
| __u16 mac_len; | |
| @@ -40666,16 +50305,19 @@ | |
| __u8 inner_protocol_type: 1; | |
| __u8 l4_hash: 1; | |
| __u8 sw_hash: 1; | |
| + __u8 wifi_acked_valid: 1; | |
| + __u8 wifi_acked: 1; | |
| __u8 no_fcs: 1; | |
| __u8 encapsulation: 1; | |
| __u8 encap_hdr_csum: 1; | |
| __u8 csum_valid: 1; | |
| __u8 ndisc_nodetype: 2; | |
| - __u8 nf_trace: 1; | |
| - __u8 offload_fwd_mark: 1; | |
| - __u8 offload_l3_fwd_mark: 1; | |
| + __u8 ipvs_property: 1; | |
| __u8 redirected: 1; | |
| + __u8 from_ingress: 1; | |
| + __u8 nf_skip_egress: 1; | |
| __u8 slow_gro: 1; | |
| + __u8 csum_not_inet: 1; | |
| __u16 tc_index; | |
| u16 alloc_cpu; | |
| union { | |
| @@ -40733,16 +50375,19 @@ | |
| __u8 inner_protocol_type: 1; | |
| __u8 l4_hash: 1; | |
| __u8 sw_hash: 1; | |
| + __u8 wifi_acked_valid: 1; | |
| + __u8 wifi_acked: 1; | |
| __u8 no_fcs: 1; | |
| __u8 encapsulation: 1; | |
| __u8 encap_hdr_csum: 1; | |
| __u8 csum_valid: 1; | |
| __u8 ndisc_nodetype: 2; | |
| - __u8 nf_trace: 1; | |
| - __u8 offload_fwd_mark: 1; | |
| - __u8 offload_l3_fwd_mark: 1; | |
| + __u8 ipvs_property: 1; | |
| __u8 redirected: 1; | |
| + __u8 from_ingress: 1; | |
| + __u8 nf_skip_egress: 1; | |
| __u8 slow_gro: 1; | |
| + __u8 csum_not_inet: 1; | |
| __u16 tc_index; | |
| u16 alloc_cpu; | |
| union { | |
| @@ -40802,6 +50447,8 @@ | |
| __u32 egress_ifindex; | |
| }; | |
| +struct xdp_rxq_info; | |
| + | |
| struct xdp_txq_info; | |
| struct xdp_buff { | |
| @@ -40951,7 +50598,7 @@ | |
| u32 end; | |
| u32 size; | |
| u32 copybreak; | |
| - unsigned long copy[1]; | |
| + long unsigned int copy[1]; | |
| struct scatterlist data[19]; | |
| }; | |
| @@ -40975,28 +50622,59 @@ | |
| const void *data_end; | |
| }; | |
| +struct fred_cs { | |
| + u64 cs: 16; | |
| + u64 sl: 2; | |
| + u64 wfe: 1; | |
| +}; | |
| + | |
| +struct fred_ss { | |
| + u64 ss: 16; | |
| + u64 sti: 1; | |
| + u64 swevent: 1; | |
| + u64 nmi: 1; | |
| + int: 13; | |
| + u64 vector: 8; | |
| + short: 8; | |
| + u64 type: 4; | |
| + char: 4; | |
| + u64 enclave: 1; | |
| + u64 lm: 1; | |
| + u64 nested: 1; | |
| + char: 1; | |
| + u64 insnlen: 4; | |
| +}; | |
| + | |
| struct pt_regs { | |
| - unsigned long r15; | |
| - unsigned long r14; | |
| - unsigned long r13; | |
| - unsigned long r12; | |
| - unsigned long bp; | |
| - unsigned long bx; | |
| - unsigned long r11; | |
| - unsigned long r10; | |
| - unsigned long r9; | |
| - unsigned long r8; | |
| - unsigned long ax; | |
| - unsigned long cx; | |
| - unsigned long dx; | |
| - unsigned long si; | |
| - unsigned long di; | |
| - unsigned long orig_ax; | |
| - unsigned long ip; | |
| - unsigned long cs; | |
| - unsigned long flags; | |
| - unsigned long sp; | |
| - unsigned long ss; | |
| + long unsigned int r15; | |
| + long unsigned int r14; | |
| + long unsigned int r13; | |
| + long unsigned int r12; | |
| + long unsigned int bp; | |
| + long unsigned int bx; | |
| + long unsigned int r11; | |
| + long unsigned int r10; | |
| + long unsigned int r9; | |
| + long unsigned int r8; | |
| + long unsigned int ax; | |
| + long unsigned int cx; | |
| + long unsigned int dx; | |
| + long unsigned int si; | |
| + long unsigned int di; | |
| + long unsigned int orig_ax; | |
| + long unsigned int ip; | |
| + union { | |
| + u16 cs; | |
| + u64 csx; | |
| + struct fred_cs fred_cs; | |
| + }; | |
| + long unsigned int flags; | |
| + long unsigned int sp; | |
| + union { | |
| + u16 ss; | |
| + u64 ssx; | |
| + struct fred_ss fred_ss; | |
| + }; | |
| }; | |
| typedef struct pt_regs bpf_user_pt_regs_t; | |
| @@ -41191,6 +50869,8 @@ | |
| struct bpf_sysctl_kern BPF_PROG_TYPE_CGROUP_SYSCTL_kern; | |
| struct bpf_sockopt BPF_PROG_TYPE_CGROUP_SOCKOPT_prog; | |
| struct bpf_sockopt_kern BPF_PROG_TYPE_CGROUP_SOCKOPT_kern; | |
| + __u32 BPF_PROG_TYPE_LIRC_MODE2_prog; | |
| + u32 BPF_PROG_TYPE_LIRC_MODE2_kern; | |
| struct sk_reuseport_md BPF_PROG_TYPE_SK_REUSEPORT_prog; | |
| struct sk_reuseport_kern BPF_PROG_TYPE_SK_REUSEPORT_kern; | |
| struct bpf_sk_lookup BPF_PROG_TYPE_SK_LOOKUP_prog; | |
| @@ -41225,8 +50905,8 @@ | |
| }; | |
| struct bpf_ksym { | |
| - unsigned long start; | |
| - unsigned long end; | |
| + long unsigned int start; | |
| + long unsigned int end; | |
| char name[512]; | |
| struct list_head lnode; | |
| struct latch_tree_node tnode; | |
| @@ -41252,14 +50932,12 @@ | |
| struct bpf_dtab { | |
| struct bpf_map map; | |
| - struct bpf_dtab_netdev __attribute__((btf_type_tag("rcu"))) **netdev_map; | |
| + struct bpf_dtab_netdev **netdev_map; | |
| struct list_head list; | |
| struct hlist_head *dev_index_head; | |
| spinlock_t index_lock; | |
| unsigned int items; | |
| u32 n_buckets; | |
| - long: 64; | |
| - long: 64; | |
| }; | |
| struct bpf_dtab_netdev { | |
| @@ -41275,7 +50953,7 @@ | |
| struct bpf_dummy_ops { | |
| int (*test_1)(struct bpf_dummy_ops_state *); | |
| - int (*test_2)(struct bpf_dummy_ops_state *, int, unsigned short, char, unsigned long); | |
| + int (*test_2)(struct bpf_dummy_ops_state *, int, short unsigned int, char, long unsigned int); | |
| int (*test_sleepable)(struct bpf_dummy_ops_state *); | |
| }; | |
| @@ -41357,9 +51035,16 @@ | |
| }; | |
| __u32 tbid; | |
| }; | |
| + union { | |
| + struct { | |
| + __u32 mark; | |
| + }; | |
| + struct { | |
| __u8 smac[6]; | |
| __u8 dmac[6]; | |
| }; | |
| + }; | |
| +}; | |
| struct bpf_flow_keys { | |
| __u16 nhoff; | |
| @@ -41386,6 +51071,11 @@ | |
| __be32 flow_label; | |
| }; | |
| +struct bpf_fou_encap { | |
| + __be16 sport; | |
| + __be16 dport; | |
| +}; | |
| + | |
| struct bpf_func_info { | |
| __u32 insn_off; | |
| __u32 type_id; | |
| @@ -41469,8 +51159,8 @@ | |
| int depth: 30; | |
| } iter; | |
| struct { | |
| - unsigned long raw1; | |
| - unsigned long raw2; | |
| + long unsigned int raw1; | |
| + long unsigned int raw2; | |
| } raw; | |
| u32 subprogno; | |
| }; | |
| @@ -41519,11 +51209,8 @@ | |
| }; | |
| struct bpf_hrtimer { | |
| + struct bpf_async_cb cb; | |
| struct hrtimer timer; | |
| - struct bpf_map *map; | |
| - struct bpf_prog *prog; | |
| - void __attribute__((btf_type_tag("rcu"))) *callback_fn; | |
| - void *value; | |
| }; | |
| struct bpf_mem_caches; | |
| @@ -41531,8 +51218,8 @@ | |
| struct bpf_mem_cache; | |
| struct bpf_mem_alloc { | |
| - struct bpf_mem_caches __attribute__((btf_type_tag("percpu"))) *caches; | |
| - struct bpf_mem_cache __attribute__((btf_type_tag("percpu"))) *cache; | |
| + struct bpf_mem_caches *caches; | |
| + struct bpf_mem_cache *cache; | |
| struct obj_cgroup *objcg; | |
| bool percpu; | |
| struct work_struct work; | |
| @@ -41546,7 +51233,7 @@ | |
| }; | |
| struct pcpu_freelist { | |
| - struct pcpu_freelist_head __attribute__((btf_type_tag("percpu"))) *freelist; | |
| + struct pcpu_freelist_head *freelist; | |
| struct pcpu_freelist_head extralist; | |
| }; | |
| @@ -41557,7 +51244,7 @@ | |
| struct bpf_lru { | |
| union { | |
| struct bpf_common_lru common_lru; | |
| - struct bpf_lru_list __attribute__((btf_type_tag("percpu"))) *percpu_lru; | |
| + struct bpf_lru_list *percpu_lru; | |
| }; | |
| del_from_htab_func del_from_htab; | |
| void *del_arg; | |
| @@ -41570,8 +51257,6 @@ | |
| long: 64; | |
| }; | |
| -struct lock_class_key {}; | |
| - | |
| struct bucket; | |
| struct htab_elem; | |
| @@ -41586,13 +51271,11 @@ | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| - long: 64; | |
| - long: 64; | |
| union { | |
| struct pcpu_freelist freelist; | |
| struct bpf_lru lru; | |
| }; | |
| - struct htab_elem * __attribute__((btf_type_tag("percpu"))) *extra_elems; | |
| + struct htab_elem **extra_elems; | |
| struct percpu_counter pcount; | |
| atomic_t count; | |
| bool use_percpu_counter; | |
| @@ -41600,8 +51283,7 @@ | |
| u32 elem_size; | |
| u32 hashrnd; | |
| struct lock_class_key lockdep_key; | |
| - int __attribute__((btf_type_tag("percpu"))) *map_locked[8]; | |
| - long: 64; | |
| + int *map_locked[8]; | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| @@ -41645,6 +51327,12 @@ | |
| struct bpf_verifier_log *log; | |
| }; | |
| +struct bpf_map_ptr_state { | |
| + struct bpf_map *map_ptr; | |
| + bool poison; | |
| + bool unpriv; | |
| +}; | |
| + | |
| struct bpf_loop_inline_state { | |
| unsigned int initialized: 1; | |
| unsigned int fit_for_inline: 1; | |
| @@ -41656,7 +51344,7 @@ | |
| struct bpf_insn_aux_data { | |
| union { | |
| enum bpf_reg_type ptr_type; | |
| - unsigned long map_ptr_state; | |
| + struct bpf_map_ptr_state map_ptr_state; | |
| s32 call_imm; | |
| u32 alu_limit; | |
| struct { | |
| @@ -41685,6 +51373,7 @@ | |
| u32 seen; | |
| bool sanitize_stack_spill; | |
| bool zext_dst; | |
| + bool needs_zext; | |
| bool storage_get_func_atomic; | |
| bool is_iter_next; | |
| bool call_with_percpu_alloc_ptr; | |
| @@ -42065,16 +51754,14 @@ | |
| u32 tid; | |
| }; | |
| -struct mm_struct; | |
| - | |
| struct bpf_iter_seq_task_vma_info { | |
| struct bpf_iter_seq_task_common common; | |
| struct task_struct *task; | |
| struct mm_struct *mm; | |
| struct vm_area_struct *vma; | |
| u32 tid; | |
| - unsigned long prev_vm_start; | |
| - unsigned long prev_vm_end; | |
| + long unsigned int prev_vm_start; | |
| + long unsigned int prev_vm_end; | |
| }; | |
| struct bpf_iter_target_info { | |
| @@ -42105,21 +51792,21 @@ | |
| struct maple_enode; | |
| -struct maple_tree; | |
| - | |
| struct maple_alloc; | |
| struct ma_state { | |
| struct maple_tree *tree; | |
| - unsigned long index; | |
| - unsigned long last; | |
| + long unsigned int index; | |
| + long unsigned int last; | |
| struct maple_enode *node; | |
| - unsigned long min; | |
| - unsigned long max; | |
| + long unsigned int min; | |
| + long unsigned int max; | |
| struct maple_alloc *alloc; | |
| + enum maple_status status; | |
| unsigned char depth; | |
| unsigned char offset; | |
| unsigned char mas_flags; | |
| + unsigned char end; | |
| }; | |
| struct vma_iterator { | |
| @@ -42208,6 +51895,10 @@ | |
| u8 spi; | |
| u8 frameno; | |
| } iter; | |
| + struct { | |
| + struct bpf_map *ptr; | |
| + int uid; | |
| + } map; | |
| u64 mem_size; | |
| }; | |
| @@ -42216,7 +51907,7 @@ | |
| u32 func_id; | |
| s32 imm; | |
| u16 offset; | |
| - unsigned long addr; | |
| + long unsigned int addr; | |
| }; | |
| struct bpf_kfunc_desc_tab { | |
| @@ -42228,13 +51919,13 @@ | |
| struct ftrace_regs; | |
| -typedef void (*ftrace_func_t)(unsigned long, unsigned long, struct ftrace_ops *, struct ftrace_regs *); | |
| +typedef void (*ftrace_func_t)(long unsigned int, long unsigned int, struct ftrace_ops *, struct ftrace_regs *); | |
| struct ftrace_hash; | |
| struct ftrace_ops_hash { | |
| - struct ftrace_hash __attribute__((btf_type_tag("rcu"))) *notrace_hash; | |
| - struct ftrace_hash __attribute__((btf_type_tag("rcu"))) *filter_hash; | |
| + struct ftrace_hash *notrace_hash; | |
| + struct ftrace_hash *filter_hash; | |
| struct mutex regex_lock; | |
| }; | |
| @@ -42242,37 +51933,37 @@ | |
| struct ftrace_ops { | |
| ftrace_func_t func; | |
| - struct ftrace_ops __attribute__((btf_type_tag("rcu"))) *next; | |
| - unsigned long flags; | |
| + struct ftrace_ops *next; | |
| + long unsigned int flags; | |
| void *private; | |
| ftrace_func_t saved_func; | |
| struct ftrace_ops_hash local_hash; | |
| struct ftrace_ops_hash *func_hash; | |
| struct ftrace_ops_hash old_hash; | |
| - unsigned long trampoline; | |
| - unsigned long trampoline_size; | |
| + long unsigned int trampoline; | |
| + long unsigned int trampoline_size; | |
| struct list_head list; | |
| ftrace_ops_func_t ops_func; | |
| - unsigned long direct_call; | |
| + long unsigned int direct_call; | |
| }; | |
| struct rethook; | |
| struct fprobe { | |
| struct ftrace_ops ops; | |
| - unsigned long nmissed; | |
| + long unsigned int nmissed; | |
| unsigned int flags; | |
| struct rethook *rethook; | |
| size_t entry_data_size; | |
| int nr_maxactive; | |
| - int (*entry_handler)(struct fprobe *, unsigned long, struct pt_regs *, void *); | |
| - void (*exit_handler)(struct fprobe *, unsigned long, struct pt_regs *, void *); | |
| + int (*entry_handler)(struct fprobe *, long unsigned int, long unsigned int, struct pt_regs *, void *); | |
| + void (*exit_handler)(struct fprobe *, long unsigned int, long unsigned int, struct pt_regs *, void *); | |
| }; | |
| struct bpf_kprobe_multi_link { | |
| struct bpf_link link; | |
| struct fprobe fp; | |
| - unsigned long *addrs; | |
| + long unsigned int *addrs; | |
| u64 *cookies; | |
| u32 cnt; | |
| u32 mods_cnt; | |
| @@ -42280,10 +51971,16 @@ | |
| u32 flags; | |
| }; | |
| -struct bpf_kprobe_multi_run_ctx { | |
| +struct bpf_session_run_ctx { | |
| struct bpf_run_ctx run_ctx; | |
| + bool is_return; | |
| + void *data; | |
| +}; | |
| + | |
| +struct bpf_kprobe_multi_run_ctx { | |
| + struct bpf_session_run_ctx session_ctx; | |
| struct bpf_kprobe_multi_link *link; | |
| - unsigned long entry_ip; | |
| + long unsigned int entry_ip; | |
| }; | |
| struct bpf_line_info { | |
| @@ -42351,6 +52048,7 @@ | |
| __u32 count; | |
| __u32 flags; | |
| __u64 missed; | |
| + __u64 cookies; | |
| } kprobe_multi; | |
| struct { | |
| __u64 path; | |
| @@ -42369,6 +52067,7 @@ | |
| __u64 file_name; | |
| __u32 name_len; | |
| __u32 offset; | |
| + __u64 cookie; | |
| } uprobe; | |
| struct { | |
| __u64 func_name; | |
| @@ -42376,14 +52075,17 @@ | |
| __u32 offset; | |
| __u64 addr; | |
| __u64 missed; | |
| + __u64 cookie; | |
| } kprobe; | |
| struct { | |
| __u64 tp_name; | |
| __u32 name_len; | |
| + __u64 cookie; | |
| } tracepoint; | |
| struct { | |
| __u64 config; | |
| __u32 type; | |
| + __u64 cookie; | |
| } event; | |
| }; | |
| } perf_event; | |
| @@ -42395,12 +52097,17 @@ | |
| __u32 ifindex; | |
| __u32 attach_type; | |
| } netkit; | |
| + struct { | |
| + __u32 map_id; | |
| + __u32 attach_type; | |
| + } sockmap; | |
| }; | |
| }; | |
| struct bpf_link_ops { | |
| void (*release)(struct bpf_link *); | |
| void (*dealloc)(struct bpf_link *); | |
| + void (*dealloc_deferred)(struct bpf_link *); | |
| int (*detach)(struct bpf_link *); | |
| int (*update_prog)(struct bpf_link *, struct bpf_prog *, struct bpf_prog *); | |
| void (*show_fdinfo)(const struct bpf_link *, struct seq_file *); | |
| @@ -42428,13 +52135,32 @@ | |
| void *owner; | |
| }; | |
| +struct bpf_loader_ctx; | |
| + | |
| +struct bpf_load_and_run_opts { | |
| + struct bpf_loader_ctx *ctx; | |
| + const void *data; | |
| + const void *insns; | |
| + __u32 data_sz; | |
| + __u32 insns_sz; | |
| + const char *errstr; | |
| +}; | |
| + | |
| +struct bpf_loader_ctx { | |
| + __u32 sz; | |
| + __u32 flags; | |
| + __u32 log_level; | |
| + __u32 log_size; | |
| + __u64 log_buf; | |
| +}; | |
| + | |
| struct bpf_local_storage_data; | |
| struct bpf_local_storage_map; | |
| struct bpf_local_storage { | |
| - struct bpf_local_storage_data __attribute__((btf_type_tag("rcu"))) *cache[16]; | |
| - struct bpf_local_storage_map __attribute__((btf_type_tag("rcu"))) *smap; | |
| + struct bpf_local_storage_data *cache[16]; | |
| + struct bpf_local_storage_map *smap; | |
| struct hlist_head list; | |
| void *owner; | |
| struct callback_head rcu; | |
| @@ -42447,14 +52173,14 @@ | |
| }; | |
| struct bpf_local_storage_data { | |
| - struct bpf_local_storage_map __attribute__((btf_type_tag("rcu"))) *smap; | |
| + struct bpf_local_storage_map *smap; | |
| u8 data[0]; | |
| }; | |
| struct bpf_local_storage_elem { | |
| struct hlist_node map_node; | |
| struct hlist_node snode; | |
| - struct bpf_local_storage __attribute__((btf_type_tag("rcu"))) *local_storage; | |
| + struct bpf_local_storage *local_storage; | |
| struct callback_head rcu; | |
| long: 64; | |
| struct bpf_local_storage_data sdata; | |
| @@ -42478,11 +52204,6 @@ | |
| struct bpf_mem_alloc selem_ma; | |
| struct bpf_mem_alloc storage_ma; | |
| bool bpf_ma; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| }; | |
| struct bpf_local_storage_map_bucket { | |
| @@ -42490,8 +52211,15 @@ | |
| raw_spinlock_t lock; | |
| }; | |
| -struct bpf_lpm_trie_key { | |
| +struct bpf_lpm_trie_key_hdr { | |
| + __u32 prefixlen; | |
| +}; | |
| + | |
| +struct bpf_lpm_trie_key_u8 { | |
| + union { | |
| + struct bpf_lpm_trie_key_hdr hdr; | |
| __u32 prefixlen; | |
| + }; | |
| __u8 data[0]; | |
| }; | |
| @@ -42520,6 +52248,12 @@ | |
| int family; | |
| }; | |
| +struct bpf_map_desc { | |
| + int map_fd; | |
| + __u32 max_entries; | |
| + __u64 initial_value; | |
| +}; | |
| + | |
| struct bpf_offloaded_map; | |
| struct bpf_map_dev_ops { | |
| @@ -42544,6 +52278,7 @@ | |
| __u32 btf_id; | |
| __u32 btf_key_type_id; | |
| __u32 btf_value_type_id; | |
| + __u32 btf_vmlinux_id; | |
| __u64 map_extra; | |
| }; | |
| @@ -42561,17 +52296,17 @@ | |
| int (*map_get_next_key)(struct bpf_map *, void *, void *); | |
| void (*map_release_uref)(struct bpf_map *); | |
| void * (*map_lookup_elem_sys_only)(struct bpf_map *, void *); | |
| - int (*map_lookup_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr __attribute__((btf_type_tag("user"))) *); | |
| + int (*map_lookup_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *); | |
| int (*map_lookup_and_delete_elem)(struct bpf_map *, void *, void *, u64); | |
| - int (*map_lookup_and_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr __attribute__((btf_type_tag("user"))) *); | |
| - int (*map_update_batch)(struct bpf_map *, struct file *, const union bpf_attr *, union bpf_attr __attribute__((btf_type_tag("user"))) *); | |
| - int (*map_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr __attribute__((btf_type_tag("user"))) *); | |
| + int (*map_lookup_and_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *); | |
| + int (*map_update_batch)(struct bpf_map *, struct file *, const union bpf_attr *, union bpf_attr *); | |
| + int (*map_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *); | |
| void * (*map_lookup_elem)(struct bpf_map *, void *); | |
| - long (*map_update_elem)(struct bpf_map *, void *, void *, u64); | |
| - long (*map_delete_elem)(struct bpf_map *, void *); | |
| - long (*map_push_elem)(struct bpf_map *, void *, u64); | |
| - long (*map_pop_elem)(struct bpf_map *, void *); | |
| - long (*map_peek_elem)(struct bpf_map *, void *); | |
| + long int (*map_update_elem)(struct bpf_map *, void *, void *, u64); | |
| + long int (*map_delete_elem)(struct bpf_map *, void *); | |
| + long int (*map_push_elem)(struct bpf_map *, void *, u64); | |
| + long int (*map_pop_elem)(struct bpf_map *, void *); | |
| + long int (*map_peek_elem)(struct bpf_map *, void *); | |
| void * (*map_lookup_percpu_elem)(struct bpf_map *, void *, u32); | |
| void * (*map_fd_get_ptr)(struct bpf_map *, struct file *, int); | |
| void (*map_fd_put_ptr)(struct bpf_map *, void *, bool); | |
| @@ -42586,20 +52321,25 @@ | |
| int (*map_direct_value_meta)(const struct bpf_map *, u64, u32 *); | |
| int (*map_mmap)(struct bpf_map *, struct vm_area_struct *); | |
| __poll_t (*map_poll)(struct bpf_map *, struct file *, struct poll_table_struct *); | |
| + long unsigned int (*map_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int); | |
| int (*map_local_storage_charge)(struct bpf_local_storage_map *, void *, u32); | |
| void (*map_local_storage_uncharge)(struct bpf_local_storage_map *, void *, u32); | |
| - struct bpf_local_storage __attribute__((btf_type_tag("rcu"))) ** (*map_owner_storage_ptr)(void *); | |
| - long (*map_redirect)(struct bpf_map *, u64, u64); | |
| + struct bpf_local_storage ** (*map_owner_storage_ptr)(void *); | |
| + long int (*map_redirect)(struct bpf_map *, u64, u64); | |
| bool (*map_meta_equal)(const struct bpf_map *, const struct bpf_map *); | |
| int (*map_set_for_each_callback_args)(struct bpf_verifier_env *, struct bpf_func_state *, struct bpf_func_state *); | |
| - long (*map_for_each_callback)(struct bpf_map *, bpf_callback_t, void *, u64); | |
| + long int (*map_for_each_callback)(struct bpf_map *, bpf_callback_t, void *, u64); | |
| u64 (*map_mem_usage)(const struct bpf_map *); | |
| int *map_btf_id; | |
| const struct bpf_iter_seq_info *iter_seq_info; | |
| }; | |
| +struct llist_head { | |
| + struct llist_node *first; | |
| +}; | |
| + | |
| struct rcuwait { | |
| - struct task_struct __attribute__((btf_type_tag("rcu"))) *task; | |
| + struct task_struct *task; | |
| }; | |
| struct irq_work { | |
| @@ -42724,7 +52464,7 @@ | |
| }; | |
| struct rhash_head { | |
| - struct rhash_head __attribute__((btf_type_tag("rcu"))) *next; | |
| + struct rhash_head *next; | |
| }; | |
| struct bpf_offload_netdev { | |
| @@ -42742,9 +52482,6 @@ | |
| const struct bpf_map_dev_ops *dev_ops; | |
| void *dev_priv; | |
| struct list_head offloads; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| }; | |
| struct bpf_perf_event_value { | |
| @@ -42800,13 +52537,14 @@ | |
| u16 call_get_stack: 1; | |
| u16 call_get_func_ip: 1; | |
| u16 tstamp_type_access: 1; | |
| + u16 sleepable: 1; | |
| enum bpf_prog_type type; | |
| enum bpf_attach_type expected_attach_type; | |
| u32 len; | |
| u32 jited_len; | |
| u8 tag[8]; | |
| - struct bpf_prog_stats __attribute__((btf_type_tag("percpu"))) *stats; | |
| - int __attribute__((btf_type_tag("percpu"))) *active; | |
| + struct bpf_prog_stats *stats; | |
| + int *active; | |
| unsigned int (*bpf_func)(const void *, const struct bpf_insn *); | |
| struct bpf_prog_aux *aux; | |
| struct sock_fprog_kern *orig_prog; | |
| @@ -42865,11 +52603,11 @@ | |
| bool attach_btf_trace; | |
| bool attach_tracing_prog; | |
| bool func_proto_unreliable; | |
| - bool sleepable; | |
| bool tail_call_reachable; | |
| bool xdp_has_frags; | |
| bool exception_cb; | |
| bool exception_boundary; | |
| + struct bpf_arena *arena; | |
| const struct btf_type *attach_func_proto; | |
| const char *attach_func_name; | |
| struct bpf_prog **func; | |
| @@ -42911,6 +52649,10 @@ | |
| }; | |
| }; | |
| +struct bpf_prog_desc { | |
| + int prog_fd; | |
| +}; | |
| + | |
| struct bpf_prog_dummy { | |
| struct bpf_prog prog; | |
| }; | |
| @@ -42992,13 +52734,13 @@ | |
| }; | |
| struct bpf_prog_ops { | |
| - int (*test_run)(struct bpf_prog *, const union bpf_attr *, union bpf_attr __attribute__((btf_type_tag("user"))) *); | |
| + int (*test_run)(struct bpf_prog *, const union bpf_attr *, union bpf_attr *); | |
| }; | |
| struct bpf_prog_pack { | |
| struct list_head list; | |
| void *ptr; | |
| - unsigned long bitmap[0]; | |
| + long unsigned int bitmap[0]; | |
| }; | |
| struct bpf_prog_stats { | |
| @@ -43015,17 +52757,10 @@ | |
| u32 head; | |
| u32 tail; | |
| u32 size; | |
| + long: 0; | |
| char elements[0]; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| }; | |
| -struct tracepoint; | |
| - | |
| struct bpf_raw_event_map { | |
| struct tracepoint *tp; | |
| void *bpf_func; | |
| @@ -43037,6 +52772,7 @@ | |
| struct bpf_raw_tp_link { | |
| struct bpf_link link; | |
| struct bpf_raw_event_map *btp; | |
| + u64 cookie; | |
| }; | |
| struct bpf_raw_tp_regs { | |
| @@ -43108,14 +52844,8 @@ | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| - spinlock_t spinlock; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| long: 64; | |
| + spinlock_t spinlock; | |
| atomic_t busy; | |
| long: 64; | |
| long: 64; | |
| @@ -43596,15 +53326,7 @@ | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - unsigned long consumer_pos; | |
| + long unsigned int consumer_pos; | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| @@ -44116,7 +53838,7 @@ | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| - unsigned long producer_pos; | |
| + long unsigned int producer_pos; | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| @@ -44639,13 +54361,6 @@ | |
| struct bpf_ringbuf_map { | |
| struct bpf_map map; | |
| struct bpf_ringbuf *rb; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| }; | |
| struct bpf_sanitize_info { | |
| @@ -44680,6 +54395,10 @@ | |
| struct bpf_prog *stream_parser; | |
| struct bpf_prog *stream_verdict; | |
| struct bpf_prog *skb_verdict; | |
| + struct bpf_link *msg_parser_link; | |
| + struct bpf_link *stream_parser_link; | |
| + struct bpf_link *stream_verdict_link; | |
| + struct bpf_link *skb_verdict_link; | |
| }; | |
| struct bpf_shtab_bucket; | |
| @@ -44691,7 +54410,6 @@ | |
| u32 elem_size; | |
| struct sk_psock_progs progs; | |
| atomic_t count; | |
| - long: 64; | |
| }; | |
| struct bpf_shtab_bucket { | |
| @@ -44748,17 +54466,11 @@ | |
| u8 data[32]; | |
| }; | |
| -struct bpf_spin_lock { | |
| - __u32 val; | |
| -}; | |
| - | |
| struct bpf_stab { | |
| struct bpf_map map; | |
| struct sock **sks; | |
| struct sk_psock_progs progs; | |
| spinlock_t lock; | |
| - long: 64; | |
| - long: 64; | |
| }; | |
| struct bpf_stack_build_id { | |
| @@ -44778,9 +54490,6 @@ | |
| struct pcpu_freelist freelist; | |
| u32 n_buckets; | |
| struct stack_map_bucket *buckets[0]; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| }; | |
| struct bpf_stack_state { | |
| @@ -44789,7 +54498,7 @@ | |
| }; | |
| struct bpf_storage_blob { | |
| - struct bpf_local_storage __attribute__((btf_type_tag("rcu"))) *storage; | |
| + struct bpf_local_storage *storage; | |
| }; | |
| struct bpf_storage_buffer { | |
| @@ -44810,18 +54519,24 @@ | |
| void (*unreg)(void *); | |
| int (*update)(void *, void *); | |
| int (*validate)(void *); | |
| - const struct btf_type *type; | |
| - const struct btf_type *value_type; | |
| + void *cfi_stubs; | |
| + struct module *owner; | |
| const char *name; | |
| struct btf_func_model func_models[64]; | |
| - u32 type_id; | |
| - u32 value_id; | |
| - void *cfi_stubs; | |
| }; | |
| -struct bpf_struct_ops_bpf_dummy_ops { | |
| +struct bpf_struct_ops_arg_info { | |
| + struct bpf_ctx_arg_aux *info; | |
| + u32 cnt; | |
| +}; | |
| + | |
| +struct bpf_struct_ops_common_value { | |
| refcount_t refcnt; | |
| enum bpf_struct_ops_state state; | |
| +}; | |
| + | |
| +struct bpf_struct_ops_bpf_dummy_ops { | |
| + struct bpf_struct_ops_common_value common; | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| @@ -44837,14 +54552,22 @@ | |
| long: 64; | |
| }; | |
| +struct bpf_struct_ops_desc { | |
| + struct bpf_struct_ops *st_ops; | |
| + const struct btf_type *type; | |
| + const struct btf_type *value_type; | |
| + u32 type_id; | |
| + u32 value_id; | |
| + struct bpf_struct_ops_arg_info *arg_info; | |
| +}; | |
| + | |
| struct bpf_struct_ops_link { | |
| struct bpf_link link; | |
| - struct bpf_map __attribute__((btf_type_tag("rcu"))) *map; | |
| + struct bpf_map *map; | |
| }; | |
| struct bpf_struct_ops_value { | |
| - refcount_t refcnt; | |
| - enum bpf_struct_ops_state state; | |
| + struct bpf_struct_ops_common_value common; | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| @@ -44858,10 +54581,13 @@ | |
| struct bpf_struct_ops_map { | |
| struct bpf_map map; | |
| struct callback_head rcu; | |
| - const struct bpf_struct_ops *st_ops; | |
| + const struct bpf_struct_ops_desc *st_ops_desc; | |
| struct mutex lock; | |
| struct bpf_link **links; | |
| - void *image; | |
| + u32 links_cnt; | |
| + u32 image_pages_cnt; | |
| + void *image_pages[8]; | |
| + struct btf *btf; | |
| struct bpf_struct_ops_value *uvalue; | |
| long: 64; | |
| long: 64; | |
| @@ -44869,66 +54595,8 @@ | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| - struct bpf_struct_ops_value kvalue; | |
| -}; | |
| - | |
| -struct scx_cpu_acquire_args; | |
| - | |
| -struct scx_cpu_release_args; | |
| - | |
| -struct scx_enable_args; | |
| - | |
| -struct scx_cgroup_init_args; | |
| - | |
| -struct scx_exit_info; | |
| - | |
| -struct sched_ext_ops { | |
| - s32 (*select_cpu)(struct task_struct *, s32, u64); | |
| - void (*enqueue)(struct task_struct *, u64); | |
| - void (*dequeue)(struct task_struct *, u64); | |
| - void (*dispatch)(s32, struct task_struct *); | |
| - void (*runnable)(struct task_struct *, u64); | |
| - void (*running)(struct task_struct *); | |
| - void (*stopping)(struct task_struct *, bool); | |
| - void (*quiescent)(struct task_struct *, u64); | |
| - bool (*yield)(struct task_struct *, struct task_struct *); | |
| - bool (*core_sched_before)(struct task_struct *, struct task_struct *); | |
| - void (*set_weight)(struct task_struct *, u32); | |
| - void (*set_cpumask)(struct task_struct *, struct cpumask *); | |
| - void (*update_idle)(s32, bool); | |
| - void (*cpu_acquire)(s32, struct scx_cpu_acquire_args *); | |
| - void (*cpu_release)(s32, struct scx_cpu_release_args *); | |
| - void (*cpu_online)(s32); | |
| - void (*cpu_offline)(s32); | |
| - s32 (*prep_enable)(struct task_struct *, struct scx_enable_args *); | |
| - void (*enable)(struct task_struct *, struct scx_enable_args *); | |
| - void (*cancel_enable)(struct task_struct *, struct scx_enable_args *); | |
| - void (*disable)(struct task_struct *); | |
| - s32 (*cgroup_init)(struct cgroup *, struct scx_cgroup_init_args *); | |
| - void (*cgroup_exit)(struct cgroup *); | |
| - s32 (*cgroup_prep_move)(struct task_struct *, struct cgroup *, struct cgroup *); | |
| - void (*cgroup_move)(struct task_struct *, struct cgroup *, struct cgroup *); | |
| - void (*cgroup_cancel_move)(struct task_struct *, struct cgroup *, struct cgroup *); | |
| - void (*cgroup_set_weight)(struct cgroup *, u32); | |
| - s32 (*init)(); | |
| - void (*exit)(struct scx_exit_info *); | |
| - u32 dispatch_max_batch; | |
| - u64 flags; | |
| - u32 timeout_ms; | |
| - char name[128]; | |
| -}; | |
| - | |
| -struct bpf_struct_ops_sched_ext_ops { | |
| - refcount_t refcnt; | |
| - enum bpf_struct_ops_state state; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - long: 64; | |
| - struct sched_ext_ops data; | |
| + struct bpf_struct_ops_value kvalue; | |
| }; | |
| struct rate_sample; | |
| @@ -44943,7 +54611,7 @@ | |
| void (*in_ack_event)(struct sock *, u32); | |
| void (*pkts_acked)(struct sock *, const struct ack_sample *); | |
| u32 (*min_tso_segs)(struct sock *); | |
| - void (*cong_control)(struct sock *, const struct rate_sample *); | |
| + void (*cong_control)(struct sock *, u32, int, const struct rate_sample *); | |
| u32 (*undo_cwnd)(struct sock *); | |
| u32 (*sndbuf_expand)(struct sock *); | |
| size_t (*get_info)(struct sock *, u32, int *, union tcp_cc_info *); | |
| @@ -44962,8 +54630,7 @@ | |
| }; | |
| struct bpf_struct_ops_tcp_congestion_ops { | |
| - refcount_t refcnt; | |
| - enum bpf_struct_ops_state state; | |
| + struct bpf_struct_ops_common_value common; | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| @@ -44986,6 +54653,7 @@ | |
| u32 start; | |
| u32 linfo_idx; | |
| u16 stack_depth; | |
| + u16 stack_extra; | |
| bool has_tail_call: 1; | |
| bool tail_call_reachable: 1; | |
| bool has_ld_abs: 1; | |
| @@ -45017,6 +54685,20 @@ | |
| bool st_bucket_done; | |
| }; | |
| +struct bpf_tcp_req_attrs { | |
| + u32 rcv_tsval; | |
| + u32 rcv_tsecr; | |
| + u16 mss; | |
| + u8 rcv_wscale; | |
| + u8 snd_wscale; | |
| + u8 ecn_ok; | |
| + u8 wscale_ok; | |
| + u8 sack_ok; | |
| + u8 tstamp_ok; | |
| + u8 usec_ts_ok; | |
| + u8 reserved[3]; | |
| +}; | |
| + | |
| struct bpf_tcp_sock { | |
| __u32 snd_cwnd; | |
| __u32 srtt_us; | |
| @@ -45067,11 +54749,6 @@ | |
| __u64 __opaque[2]; | |
| }; | |
| -struct bpf_timer_kern { | |
| - struct bpf_hrtimer *timer; | |
| - struct bpf_spin_lock lock; | |
| -}; | |
| - | |
| struct user_namespace; | |
| struct bpf_token { | |
| @@ -45152,6 +54829,7 @@ | |
| struct perf_callchain_entry *callchain; | |
| struct perf_raw_record *raw; | |
| struct perf_branch_stack *br_stack; | |
| + u64 *br_stack_cntr; | |
| union perf_sample_weight weight; | |
| union perf_mem_data_src data_src; | |
| u64 txn; | |
| @@ -45169,7 +54847,6 @@ | |
| long: 64; | |
| long: 64; | |
| long: 64; | |
| - long: 64; | |
| }; | |
| struct bpf_trace_sample_data { | |
| @@ -45223,7 +54900,6 @@ | |
| struct hlist_head progs_hlist[3]; | |
| int progs_cnt[3]; | |
| struct bpf_tramp_image *cur_image; | |
| - struct module *mod; | |
| }; | |
| struct bpf_tunnel_key { | |
| @@ -45276,7 +54952,7 @@ | |
| struct uprobe_consumer { | |
| int (*handler)(struct uprobe_consumer *, struct pt_regs *); | |
| - int (*ret_handler)(struct uprobe_consumer *, unsigned long, struct pt_regs *); | |
| + int (*ret_handler)(struct uprobe_consumer *, long unsigned int, struct pt_regs *); | |
| bool (*filter)(struct uprobe_consumer *, enum uprobe_filter_ctx, struct mm_struct *); | |
| struct uprobe_consumer *next; | |
| }; | |
| @@ -45286,7 +54962,7 @@ | |
| struct bpf_uprobe { | |
| struct bpf_uprobe_multi_link *link; | |
| loff_t offset; | |
| - unsigned long ref_ctr_offset; | |
| + long unsigned int ref_ctr_offset; | |
| u64 cookie; | |
| struct uprobe_consumer consumer; | |
| }; | |
| @@ -45302,7 +54978,7 @@ | |
| struct bpf_uprobe_multi_run_ctx { | |
| struct bpf_run_ctx run_ctx; | |
| - unsigned long entry_ip; | |
| + long unsigned int entry_ip; | |
| struct bpf_uprobe *uprobe; | |
| }; | |
| @@ -45314,7 +54990,7 @@ | |
| struct bpf_verifier_log { | |
| u64 start_pos; | |
| u64 end_pos; | |
| - char __attribute__((btf_type_tag("user"))) *ubuf; | |
| + char *ubuf; | |
| u32 level; | |
| u32 len_total; | |
| u32 len_max; | |
| @@ -45334,6 +55010,7 @@ | |
| u32 prev_insn_idx; | |
| struct bpf_prog *prog; | |
| const struct bpf_verifier_ops *ops; | |
| + struct module *attach_btf_mod; | |
| struct bpf_verifier_stack_elem *head; | |
| int stack_size; | |
| bool strict_alignment; | |
| @@ -45409,7 +55086,9 @@ | |
| struct bpf_active_lock active_lock; | |
| bool speculative; | |
| bool active_rcu_lock; | |
| + u32 active_preempt_lock; | |
| bool used_as_loop_entry; | |
| + bool in_sleepable; | |
| u32 first_insn_idx; | |
| u32 last_insn_idx; | |
| struct bpf_verifier_state *loop_entry; | |
| @@ -45417,6 +55096,7 @@ | |
| u32 jmp_history_cnt; | |
| u32 dfs_depth; | |
| u32 callback_unroll_depth; | |
| + u32 may_goto_depth; | |
| }; | |
| struct bpf_verifier_stack_elem { | |
| @@ -45434,6 +55114,16 @@ | |
| int hit_cnt; | |
| }; | |
| +struct bpf_work { | |
| + struct bpf_async_cb cb; | |
| + struct work_struct work; | |
| + struct work_struct delete_work; | |
| +}; | |
| + | |
| +struct bpf_wq { | |
| + __u64 __opaque[2]; | |
| +}; | |
| + | |
| struct bpf_xdp_link; | |
| struct bpf_xdp_entity { | |
| @@ -45447,6 +55137,15 @@ | |
| int flags; | |
| }; | |
| +struct bpf_xdp_sock { | |
| + __u32 queue_id; | |
| +}; | |
| + | |
| +struct bpf_xfrm_info { | |
| + u32 if_id; | |
| + int link; | |
| +}; | |
| + | |
| struct bpf_xfrm_state { | |
| __u32 reqid; | |
| __u32 spi; | |
| @@ -45483,7 +55182,7 @@ | |
| }; | |
| struct trace_entry { | |
| - unsigned short type; | |
| + short unsigned int type; | |
| unsigned char flags; | |
| unsigned char preempt_count; | |
| int pid; | |
| @@ -45491,17 +55190,50 @@ | |
| struct bprint_entry { | |
| struct trace_entry ent; | |
| - unsigned long ip; | |
| + long unsigned int ip; | |
| const char *fmt; | |
| u32 buf[0]; | |
| }; | |
| struct bputs_entry { | |
| struct trace_entry ent; | |
| - unsigned long ip; | |
| + long unsigned int ip; | |
| const char *str; | |
| }; | |
| +struct br_boolopt_multi { | |
| + __u32 optval; | |
| + __u32 optmask; | |
| +}; | |
| + | |
| +struct bridge_id { | |
| + unsigned char prio[2]; | |
| + unsigned char addr[6]; | |
| +}; | |
| + | |
| +typedef struct bridge_id bridge_id; | |
| + | |
| +struct br_config_bpdu { | |
| + unsigned int topology_change: 1; | |
| + unsigned int topology_change_ack: 1; | |
| + bridge_id root; | |
| + int root_path_cost; | |
| + bridge_id bridge_id; | |
| + port_id port_id; | |
| + int message_age; | |
| + int max_age; | |
| + int hello_time; | |
| + int forward_delay; | |
| +}; | |
| + | |
| +struct net_bridge_port; | |
| + | |
| +struct br_frame_type { | |
| + __be16 type; | |
| + int (*frame_handler)(struct net_bridge_port *, struct sk_buff *); | |
| + struct hlist_node list; | |
| +}; | |
| + | |
| struct br_input_skb_cb { | |
| struct net_device *brd |
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