STM8L051 ADC Read

myadc.fs

#require lib/]B!
#require lib/]C!

NVM

\res MCU: STM8L051
\res export PA_ODR PA_DDR PB_ODR PB_DDR PC_ODR PC_DDR PD_ODR PD_DDR
\res export PA_CR1 PB_CR1 PC_CR1 PD_CR1 PA_CR2 PB_CR2 PC_CR2 PD_CR2
\res export CLK_PCKENR2
\res export ADC1_CR1 ADC1_CR2 ADC1_SR ADC1_DRH ADC1_DRL
\res export ADC1_SQR1 ADC1_SQR2 ADC1_SQR3 ADC1_SQR4

$04 CONSTANT ADC_CR1_CONT
$60 CONSTANT ADC_CR1_RES
$02 CONSTANT ADC_CR1_START
$01 CONSTANT ADC_CR1_ADON

$00 CONSTANT ADC_Conv_Single
\ $04 CONSTANT ADC_Conv_Cont
$00 CONSTANT ADC_Res_12Bit

$80 CONSTANT ADC_CR2_PRESC
$00 CONSTANT ADC_PRESC_1
$80 CONSTANT ADC_PRESC_2
$00 CONSTANT ADC_Res_12Bit

$00 CONSTANT ADC_GRP_SLO_CH
$07 CONSTANT ADC_384_Cycles
$07 CONSTANT ADC_CR2_SMPT1

$0310 CONSTANT ADC_Channel_4
$0104 CONSTANT ADC_Channel_18
$0140 CONSTANT ADC_Channel_22
$01 CONSTANT ADC_FLAG_EOC

: PINS
    [ 0 PC_DDR 4 ]B!
    [ 0 PC_CR1 4 ]B!
    [ 0 PC_CR2 4 ]B!
;

: CLKCFG
    \ Function
    \ CLK_PeripheralClockConfig(CLK_Peripheral_ADC1, ENABLE);

    [ 1 CLK_PCKENR2 2 ]B! \ Perif CLK Config ADC

    \ CLK_PCKENR2 c@ . 128 ok
    \ CLKCFG ok
    \ CLK_PCKENR2 c@ . 132 ok
    \ it works

;

: ADCINIT
    \ Function
    \ ADC_Init(ADC1, ADC_ConversionMode_Single, ADC_Resolution_12Bit, ADC_Prescaler_1);

    \ ADCx->CR1 &= (uint8_t)~(ADC_CR1_CONT | ADC_CR1_RES);
    [ ADC_CR1_CONT ADC_CR1_RES OR NOT ADC1_CR1 @ AND ADC1_CR1 ]C!  \ clear CR1 Register

    \ ADCx->CR2 &= (uint8_t)~(ADC_CR2_PRESC);
    [ ADC_CR2_PRESC NOT ADC1_CR2 @ AND ADC1_CR2 ]C!  \  

    \ ADC1_CR2 |= ADC_PRESC_2
    [ ADC_PRESC_2 ADC1_CR2 @ OR ADC1_CR2 ]C!  \ Set ADC_Prescalar_1
;

: STCFG
    \ Function
    \ ADC_SamplingTimeConfig(ADC1, ADC_Group_SlowChannels, ADC_SamplingTime_384Cycles);

    \ ADC1_CR2 &= ~ADC_CR2_SMPT1;
    [ ADC_CR2_SMPT1 NOT ADC1_CR2 @ AND ADC1_CR2 ]C!  \ 

    \ ADC1_CR2 |= ADC_384_Cycles;
    [ ADC_384_Cycles ADC1_CR2 @ OR ADC1_CR2 ]C!  \ 
;

: ADCEN
    \ Function
    \ ADC_Cmd(ADC1, ENABLE);

    \ ADC1_CR1 |= ADC_CR1_ADON;
    [ ADC_CR1_ADON ADC1_CR1 @ OR ADC1_CR1 ]C! \ ADC Enable
;

: ADCCH
    \ Function
    \ ADC_ChannelCmd(ADC1, Channel, ENABLE);
    \ regindex = (uint8_t)((uint16_t)ADC_Channels >> 8);
    \ /* Enable the selected ADC channel(s). */
    \ ADCx->SQR[regindex] |= (uint8_t)(ADC_Channels);
    \ ADC1_SQR[reg] |= ADC_Channel_4

    [ ADC_Channel_4 ADC1_SQR1 @ OR ADC1_SQR1 ]C! \ ADC Enable Channel 
;
 
: STARTCONV
    \ Function
    \ ADC_SoftwareStartConv(ADC1);
    \ ADC1_CR1 |= ADC_CR1_START
    [ ADC_CR1_START ADC1_CR1 @ OR ADC1_CR1 ]C!
;

: WAITCONV
    \ Function
    \ while(ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC) == RESET) {
    \ }
    begin ADC1_SR @ ADC_FLAG_EOC AND 0 = until
;

: ADCGETVAL
    \ Function
    \ ADC_value = ADC_GetConversionValue(ADC1);
    \ tmpreg = (uint16_t)(ADCx->DRH);
    \ tmpreg = (uint16_t)((uint16_t)((uint16_t)tmpreg << 8) | ADCx->DRL);
    \ return (DRH << 8) | DRL
    \ return (read 0x5404 DRH << 8) | read 0x5405 //DRL

    ADC1_DRH @ 2* ADC1_DRL @ AND \ it is on the stack
;

: ADCDISABLE
    \ Function
    \ ADC_Cmd(ADC1, DISABLE);
    \ ADC1_CR1 &= ~ADC_CR1_ADON;
    [ ADC_CR1_ADON NOT ADC1_CR1 AND ADC1_CR1 ]C!

    \ return(ADC_value);
    \ just put/leave it on the stack
;

: ADCRD
    CLKCFG 
    ADCINIT 
    STCFG 
    ADCEN 
    ADCCH 
    STARTCONV 
    WAITCONV 
    ADCGETVAL 
    ADCDISABLE 
;

PINS

RAM

I have a working ADC read that was written in C, and compiled with SDCC for the L051. This is my first attempt to "translate" it to forth.