gistfile1.vhdl

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY UART_TEST IS
END UART_TEST;
 
ARCHITECTURE behavior OF UART_TEST IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT UARTM
    PORT(
         inRST : IN  std_logic;
         iCLK : IN  std_logic;
         RXD : IN  std_logic;
         DATAout : OUT  std_logic_vector(7 downto 0);
         test_tick : OUT  std_logic;
         test_big_tick : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal inRST : std_logic := '0';
   signal iCLK : std_logic := '0';
   signal RXD : std_logic := '1';

 	--Outputs
   signal DATAout : std_logic_vector(7 downto 0);
   signal test_tick : std_logic;
   signal test_big_tick : std_logic;

   -- Clock period definitions
   constant iCLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: UARTM PORT MAP (
          inRST => inRST,
          iCLK => iCLK,
          RXD => RXD,
          DATAout => DATAout,
          test_tick => test_tick,
          test_big_tick => test_big_tick
        );

   -- Clock process definitions
   iCLK_process :process
   begin
		iCLK <= '0';
		wait for iCLK_period/2;
		iCLK <= '1';
		wait for iCLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		


      inRST <= '1';
		RXD <= '1';
		
		wait for iCLK_period*10;
   
		RXD <= '0';
		
		wait for iCLK_period*1392;
		
		RXD <= '1';
		
		wait for iCLK_period*1392;
		
		RXD <= '1';
		
		wait for iCLK_period*1392;
		
		RXD <= '0';
		
		wait for iCLK_period*1392;
		
		RXD <= '1';
		
		wait for iCLK_period*1392;
		
		RXD <= '0';
		
		wait for iCLK_period*1392;
		
		RXD <= '1';
		
		wait for iCLK_period*1392;
		
		RXD <= '0';
		
		wait for iCLK_period*1392;
		
		RXD <= '1';
		
		wait for iCLK_period*1392;
		
		RXD <= '1';

      wait;
   end process;

END;