Created
June 19, 2013 09:17
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Beginnings of a DCPU-16 emulator (using the v1.7 spec)
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#include "DCPU.h" | |
DCPU::DCPU() | |
{ | |
resetRam(); | |
} | |
void DCPU::executeInstruction(const DCPU_WORD instruction) | |
{ | |
DCPU_WORD a = (instruction >> 10) & 0x3F; | |
DCPU_WORD b = (instruction >> 5) & 0x1F; | |
DCPU_WORD opcode = instruction & 0x1F; | |
switch(opcode) | |
{ | |
case 0x00: | |
// Special instruction. | |
executeSpecialInstruction(b, a); | |
break; | |
case 0x01: | |
// SET b, a | |
// todo | |
break; | |
case 0x02: | |
// ADD b, a | |
// todo | |
break; | |
case 0x03: | |
// SUB b, a | |
// todo | |
break; | |
case 0x04: | |
// MUL b, a | |
// todo | |
break; | |
case 0x05: | |
// MLI b, a | |
// todo | |
break; | |
case 0x06: | |
// DIV b, a | |
// todo | |
break; | |
case 0x07: | |
// DVI b, a | |
// todo | |
break; | |
case 0x08: | |
// MOD b, a | |
// todo | |
break; | |
case 0x09: | |
// MDI b, a | |
// todo | |
break; | |
case 0x0A: | |
// AND b, a | |
// todo | |
break; | |
case 0x0B: | |
// BOR b, a | |
// todo | |
break; | |
case 0x0C: | |
// XOR b, a | |
// todo | |
break; | |
case 0x0D: | |
// SHR b, a | |
// todo | |
break; | |
case 0x0E: | |
// ASR b, a | |
// todo | |
break; | |
case 0x0F: | |
// SHL b, a | |
// todo | |
break; | |
case 0x10: | |
// IFB b, a | |
// todo | |
break; | |
case 0x11: | |
// IFC b, a | |
// todo | |
break; | |
case 0x12: | |
// IFE b, a | |
// todo | |
break; | |
case 0x13: | |
// IFN b, a | |
// todo | |
break; | |
case 0x14: | |
// IFG b, a | |
// todo | |
break; | |
case 0x15: | |
// IFA b, a | |
// todo | |
break; | |
case 0x16: | |
// IFL b, a | |
// todo | |
break; | |
case 0x17: | |
// IFU b, a | |
// todo | |
break; | |
case 0x18: | |
// No operation specified yet | |
break; | |
case 0x19: | |
// No operation specified yet | |
break; | |
case 0x1A: | |
// ADX b, a | |
// todo | |
break; | |
case 0x1B: | |
// SBX b, a | |
// todo | |
break; | |
case 0x1C: | |
// No operation specified yet | |
break; | |
case 0x1D: | |
// No operation specified yet | |
break; | |
case 0x1E: | |
// STI b, a | |
// todo | |
break; | |
case 0x1F: | |
// STD b, a | |
// todo | |
break; | |
default: | |
// Opcode not recognized | |
// This *should never happen*. | |
break; | |
} | |
} | |
void DCPU::executeSpecialInstruction(const DCPU_WORD opcode, const DCPU_WORD a) | |
{ | |
switch(opcode) | |
{ | |
case 0x00: | |
// N/A. Reserved for future expansion | |
break; | |
case 0x01: | |
// JSR a | |
// todo | |
break; | |
case 0x02: | |
// No operation specified yet | |
break; | |
case 0x03: | |
// No operation specified yet | |
break; | |
case 0x04: | |
// No operation specified yet | |
break; | |
case 0x05: | |
// No operation specified yet | |
break; | |
case 0x06: | |
// No operation specified yet | |
break; | |
case 0x07: | |
// No operation specified yet | |
break; | |
case 0x08: | |
// INT a | |
// todo | |
break; | |
case 0x09: | |
// IAG a | |
// todo | |
break; | |
case 0x0A: | |
// IAS a | |
// todo | |
break; | |
case 0x0B: | |
// RFI a | |
// todo | |
break; | |
case 0x0C: | |
// IAQ a | |
// todo | |
break; | |
case 0x0D: | |
// No operation specified yet | |
break; | |
case 0x0E: | |
// No operation specified yet | |
break; | |
case 0x0F: | |
// No operation specified yet | |
break; | |
case 0x10: | |
// HWN a | |
// todo | |
break; | |
case 0x11: | |
// HWQ a | |
// todo | |
break; | |
case 0x12: | |
// HWI a | |
// todo | |
break; | |
case 0x13: | |
// No operation specified yet | |
break; | |
case 0x14: | |
// No operation specified yet | |
break; | |
case 0x15: | |
// No operation specified yet | |
break; | |
case 0x16: | |
// No operation specified yet | |
break; | |
case 0x17: | |
// No operation specified yet | |
break; | |
case 0x18: | |
// No operation specified yet | |
break; | |
case 0x19: | |
// No operation specified yet | |
break; | |
case 0x1A: | |
// No operation specified yet | |
break; | |
case 0x1B: | |
// No operation specified yet | |
break; | |
case 0x1C: | |
// No operation specified yet | |
break; | |
case 0x1D: | |
// No operation specified yet | |
break; | |
case 0x1E: | |
// No operation specified yet | |
break; | |
case 0x1F: | |
// No operation specified yet | |
break; | |
default: | |
// Opcode not recognized | |
// This *should never happen*. | |
break; | |
} | |
} | |
void DCPU::resetRam() | |
{ | |
for(unsigned int i = 0; i < RAM_SIZE; i++) | |
{ | |
RAM[i] = 0; | |
} | |
} |
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#ifndef DCPU_H | |
#define DCPU_H | |
#include <cstdint> | |
#define DCPU_WORD uint16_t | |
#define RAM_SIZE 0x10000 | |
class DCPU | |
{ | |
public: | |
DCPU(); | |
void executeInstruction(const DCPU_WORD); | |
private: | |
void executeSpecialInstruction(const DCPU_WORD, const DCPU_WORD); | |
void resetRam(); | |
// Registers | |
DCPU_WORD A, B, C, X, Y, Z, I, J; | |
// Program counter | |
DCPU_WORD PC; | |
// Stack pointer | |
DCPU_WORD SP; | |
// Extra/excess | |
DCPU_WORD EX; | |
// Interrupt address | |
DCPU_WORD IA; | |
// RAM | |
DCPU_WORD RAM[RAM_SIZE]; | |
}; | |
#endif // DCPU_H |
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