Skip to content

Instantly share code, notes, and snippets.

Created February 12, 2018 18:24
Show Gist options
  • Star 0 You must be signed in to star a gist
  • Fork 0 You must be signed in to fork a gist
  • Save anonymous/5a93ebb78081bab455b8e64f292a9581 to your computer and use it in GitHub Desktop.
Save anonymous/5a93ebb78081bab455b8e64f292a9581 to your computer and use it in GitHub Desktop.
# ./tinymembench
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 2880.4 MB/s
C copy backwards (32 byte blocks) : 2871.2 MB/s
C copy backwards (64 byte blocks) : 2867.6 MB/s
C copy : 2799.9 MB/s
C copy prefetched (32 bytes step) : 2816.8 MB/s
C copy prefetched (64 bytes step) : 2815.9 MB/s
C 2-pass copy : 2552.6 MB/s
C 2-pass copy prefetched (32 bytes step) : 2591.4 MB/s
C 2-pass copy prefetched (64 bytes step) : 2593.1 MB/s
C fill : 4866.9 MB/s (0.4%)
C fill (shuffle within 16 byte blocks) : 4869.5 MB/s
C fill (shuffle within 32 byte blocks) : 4868.1 MB/s (0.2%)
C fill (shuffle within 64 byte blocks) : 4854.0 MB/s
---
standard memcpy : 2866.8 MB/s
standard memset : 4856.0 MB/s (0.3%)
---
NEON LDP/STP copy : 2868.2 MB/s
NEON LDP/STP copy pldl2strm (32 bytes step) : 2888.3 MB/s
NEON LDP/STP copy pldl2strm (64 bytes step) : 2891.7 MB/s
NEON LDP/STP copy pldl1keep (32 bytes step) : 2802.7 MB/s
NEON LDP/STP copy pldl1keep (64 bytes step) : 2799.6 MB/s
NEON LD1/ST1 copy : 2867.2 MB/s
NEON STP fill : 4855.1 MB/s (0.3%)
NEON STNP fill : 4822.2 MB/s
ARM LDP/STP copy : 2872.2 MB/s
ARM STP fill : 4855.6 MB/s (0.3%)
ARM STNP fill : 4821.5 MB/s
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 647.8 MB/s
NEON LDP/STP 2-pass copy (from framebuffer) : 580.0 MB/s
NEON LD1/ST1 copy (from framebuffer) : 683.9 MB/s
NEON LD1/ST1 2-pass copy (from framebuffer) : 623.9 MB/s
ARM LDP/STP copy (from framebuffer) : 470.3 MB/s
ARM LDP/STP 2-pass copy (from framebuffer) : 454.8 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.5 ns / 7.2 ns
131072 : 6.9 ns / 9.7 ns
262144 : 9.9 ns / 12.8 ns
524288 : 11.4 ns / 14.7 ns
1048576 : 17.3 ns / 24.8 ns
2097152 : 108.9 ns / 164.8 ns
4194304 : 152.9 ns / 205.0 ns
8388608 : 180.5 ns / 225.6 ns
16777216 : 194.1 ns / 233.6 ns
33554432 : 201.1 ns / 238.3 ns
67108864 : 211.7 ns / 251.5 ns
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment