gistfile1.diff

diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index b1a07a8..b253516 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -74,9 +74,9 @@ static int get_physical_address(LM32CPU *cpu,
     return 0;
 
 tlb_miss:
-    return 1;
+    return (dtlb) ? EXCP_DTLB_MISS : EXCP_ITLB_MISS;
 tlb_fault:
-    return 2;
+    return EXCP_DTLB_FAULT;
 }
 
 void mmu_fill_tbl(CPULM32State *env, tlb_t *tlb, uint32_t tlbpaddr)
@@ -105,22 +105,18 @@ void mmu_invalidate_tlb(CPULM32State *env, tlb_t *tlb)
     tlb_flush_page(env, tlb[idx].vaddr);
 }
 
-static void raise_mmu_exception(CPULM32State *env, target_ulong address, int rw)
+static void raise_mmu_exception(CPULM32State *env, target_ulong address,
+        int excp)
 {
     /* already preset TLBVADDR and set TLBBADVADDR to miss address */
     env->tlbvaddr = address & TARGET_PAGE_MASK;
     env->tlbbadvaddr = address;
+    env->exception_index = excp;
 
-    if (rw == 0) {
+    if (excp == EXCP_DTLB_MISS || excp == EXCP_DTLB_FAULT) {
         /* preset lower bit, indicating that DTLB is selected on next write
          * to TLBPADDR */
         env->tlbvaddr |= 1;
-        env->exception_index = EXCP_DTLB_MISS;
-    } else if (rw == 1) {
-        env->tlbvaddr |= 1;
-        env->exception_index = EXCP_DTLB_FAULT;
-    } else {
-        env->exception_index = EXCP_ITLB_MISS;
     }
 }
 
@@ -144,7 +140,7 @@ int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
                 TARGET_PAGE_SIZE);
         ret = 0;
     } else {
-        raise_mmu_exception(env, address, rw);
+        raise_mmu_exception(env, address, ret);
         ret = 1;
     }