memcmp.v

module memcmp (
	input clk,
	input [3:0] wstrb,
	input [15:0] waddr,
	input [15:0] raddr,
	input [31:0] wdata,
	output [31:0] rdata1,
	output [31:0] rdata2
);
	memory1 mem1 (
		.clk  (clk   ),
		.wstrb(wstrb ),
		.waddr(waddr ),
		.raddr(raddr ),
		.wdata(wdata ),
		.rdata(rdata1)
	);

	memory2 mem2 (
		.clk  (clk   ),
		.wstrb(wstrb ),
		.waddr(waddr ),
		.raddr(raddr ),
		.wdata(wdata ),
		.rdata(rdata2)
	);
endmodule

module memory1 (
	input clk,
	input [3:0] wstrb,
	input [15:0] waddr,
	input [15:0] raddr,
	input [31:0] wdata,
	output [31:0] rdata
);
	reg [31:0] mem [0:2**16-1];
	reg [15:0] buffered_raddr;

	// "transparent" read
	assign rdata = mem[buffered_raddr];

	always @(posedge clk) begin
		if (wstrb[3]) mem[waddr][31:24] <= wdata[31:24];
		if (wstrb[2]) mem[waddr][23:16] <= wdata[23:16];
		if (wstrb[1]) mem[waddr][15: 8] <= wdata[15: 8];
		if (wstrb[0]) mem[waddr][ 7: 0] <= wdata[ 7: 0];
		buffered_raddr <= raddr;
	end
endmodule

module memory2 (
	input clk,
	input [3:0] wstrb,
	input [15:0] waddr,
	input [15:0] raddr,
	input [31:0] wdata,
	output [31:0] rdata
);
	reg [31:0] mem [0:2**16-1];
	reg [31:0] buffered_wdata;
	reg [31:0] buffered_rdata;
	reg [3:0] buffered_wstrb;
	reg waddr_is_not_raddr;

	wire [31:0] expanded_wstrb = {{8{wstrb[3]}}, {8{wstrb[2]}}, {8{wstrb[1]}}, {8{wstrb[0]}}};
	wire [31:0] expanded_buffered_wstrb = {{8{buffered_wstrb[3]}}, {8{buffered_wstrb[2]}},
	                                       {8{buffered_wstrb[1]}}, {8{buffered_wstrb[0]}}};

	assign rdata = waddr_is_not_raddr ? buffered_rdata :
			(buffered_wdata & expanded_buffered_wstrb) |
			(buffered_rdata & ~expanded_buffered_wstrb);

	always @(posedge clk) begin
		mem[waddr] <= (wdata & expanded_wstrb) | (mem[waddr] & ~expanded_wstrb);
		buffered_wstrb <= wstrb;
		buffered_wdata <= wdata;
		buffered_rdata <= mem[raddr];
		waddr_is_not_raddr <= waddr != raddr;
	end
endmodule