logfile

/home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom/u2plus.xise
xtclsh /home/usrp/uhd/fpga/usrp2/top/tcl/ise_helper.tcl ""
>>> Creating project: /home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom/u2plus.xise
Changed current working directory to the project directory:
"/home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom" 
>>> Setting: Project[family] = Spartan-3A DSP
>>> Setting: Project[device] = xc3sd1800a
>>> Setting: Project[package] = fg676
>>> Setting: Project[speed] = -5
>>> Setting: Project[top_level_module_type] = HDL
>>> Setting: Project[synthesis_tool] = XST (VHDL/Verilog)
>>> Setting: Project[simulator] = ISE Simulator (VHDL/Verilog)
WARNING:TclTasksC - The value(s) of this property has been changed in the
   current release to "ISim (VHDL/Verilog)". The property value has been set to
   "ISim (VHDL/Verilog)". Please update your script to use the new value to
   avoid this message in the future.
>>> Setting: Project[Preferred Language] = Verilog
>>> Setting: Project[Enable Message Filtering] = FALSE
>>> Setting: Project[Display Incremental Messages] = FALSE
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/top/N2x0/capture_ddrlvds.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/capture_ddrlvds.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v\" into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/top/N2x0/bootloader.rmi' in file
   "/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v" line 356
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v\" into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/top/N2x0/bootloader.rmi' in file
   "/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v" line 356
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus.ucf
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/add_routing_header.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/add_routing_header.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/buffer_int.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/buffer_int2.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int2.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/buffer_pool.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_pool.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/crossbar36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/crossbar36.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/dsp_framer36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/dsp_framer36.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock_cascade.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock_cascade.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/ll8_shortfifo.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_shortfifo.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo_short.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_short.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo_long.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_long.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo_cascade.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_cascade.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_ll8.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_ll8.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo36.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_ll8.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_ll8.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo19.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo19.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_fifo19.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_fifo19.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_fifo36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_fifo36.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo19_mux.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_mux.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo36_mux.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_mux.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo36_demux.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_demux.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_router.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_router.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/splitter36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/splitter36.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/valve36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/valve36.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo_pacer.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_pacer.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x3.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x3.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x4.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x4.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_generator32.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator32.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_generator.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_verifier32.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier32.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_verifier.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo19_pad.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_pad.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_padder36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_padder36.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/CRC16_D16.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/CRC16_D16.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/atr_controller.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/bin2gray.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/bin2gray.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/dcache.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dcache.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/decoder_3_8.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/decoder_3_8.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/dbsm.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dbsm.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/dpram32.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dpram32.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/double_buffer.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/double_buffer.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/gray2bin.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gray2bin.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/gray_send.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gray_send.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/icache.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/icache.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/mux4.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/mux4.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/mux8.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/mux8.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/nsgpio.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/ram_2port.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_2port.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/ram_harv_cache.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harv_cache.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard2.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard2.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/ram_loader.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_loader.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/setting_reg.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/setting_reg.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/settings_bus.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_crossclock.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_crossclock.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/srl.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/srl.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/system_control.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/system_control.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/wb_1master.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_1master.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux_16LE.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux_16LE.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/quad_uart.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/quad_uart.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/simple_uart.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_tx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_tx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_rx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_rx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/oneshot_2clk.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/oneshot_2clk.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/sd_spi.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/sd_spi_wb.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi_wb.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/wb_bridge_16_32.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_bridge_16_32.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/reset_sync.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/reset_sync.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/priority_enc.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/priority_enc.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/pic.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/pic.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/longfifo.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/longfifo.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/shortfifo.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/shortfifo.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/medfifo.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/medfifo.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/s3a_icap_wb.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/s3a_icap_wb.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/bootram.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/bootram.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/nsgpio16LE.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio16LE.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_16LE.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_16LE.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/atr_controller16.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller16.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/fifo_to_wb.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/fifo_to_wb.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/gpio_atr.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gpio_atr.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/user_settings.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/user_settings.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/settings_fifo_ctrl.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_fifo_ctrl.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/simple_spi_core.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_spi_core.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/simple_i2c_core.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_i2c_core.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/acc.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/acc.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/add2.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip_reg.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip_reg.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round_reg.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round_reg.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/add2_reg.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_reg.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cic_dec_shifter.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_dec_shifter.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cic_decim.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_decim.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cic_int_shifter.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_int_shifter.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cic_interp.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_interp.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cic_strober.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_strober.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/clip.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/clip_reg.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip_reg.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cordic.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_z24.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_z24.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_stage.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_stage.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/ddc_chain.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/ddc_chain.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/duc_chain.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/duc_chain.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_16to8.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_16to8.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_8to16.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_8to16.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/hb_dec.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_dec.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/hb_interp.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_interp.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/pipectrl.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipectrl.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/pipestage.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipestage.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/round.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/round_reg.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_reg.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/round_sd.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_sd.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/rx_dcoffset.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_dcoffset.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/rx_frontend.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_frontend.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/sign_extend.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/sign_extend.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_dec.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_dec.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_int.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_int.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/tx_frontend.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/tx_frontend.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_tx_glue.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_tx_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/serdes/serdes.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_rx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_rx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_tx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_tx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/serdes/serdes_rx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_rx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/serdes/serdes_tx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_tx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wb.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wb.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_tx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_tx.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_rx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_rx.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/crc.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/crc.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/delay_line.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/delay_line.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_tx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_tx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_rx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_rx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter_promisc.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter_promisc.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/ll8_to_txmac.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ll8_to_txmac.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/rxmac_to_ll8.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/rxmac_to_ll8.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_miim.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_miim.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_clockgen.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_clockgen.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/ethtx_realign.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethtx_realign.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/ethrx_realign.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethrx_realign.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/timing/time_64bit.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_64bit.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/timing/time_compare.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_compare.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/timing/time_receiver.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_receiver.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/timing/time_sender.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_sender.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/timing/time_sync.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_sync.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/timing/timer.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/timer.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/timing/simple_timer.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/simple_timer.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/8b10b/decode_8b10b.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/decode_8b10b.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/8b10b/encode_8b10b.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/encode_8b10b.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v\"
   into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
   line 131
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v\"
   into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
   line 131
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v\
   " into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
   line 73
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v
INFO:TclTasksC - File
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v" is
   already present in the project
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v"
   line 77
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v" line 41
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v
INFO:TclTasksC - File
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v" is
   already present in the project
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v" line 41
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v" line 45
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v" line 46
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_config.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_config.vhd" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpupkg.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpupkg.vhd" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_rx_control.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_control.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_rx_framer.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_framer.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_rx_chain.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_chain.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_tx_control.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_control.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_tx_deframer.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_deframer.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_tx_chain.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_chain.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/gen_context_pkt.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/gen_context_pkt.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/trigger_context_pkt.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/trigger_context_pkt.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_pkt_gen.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_pkt_gen.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_rx_engine_glue.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_engine_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_tx_engine_glue.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_engine_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/udp/udp_wrapper.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/udp_wrapper.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/udp/fifo19_rxrealign.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/fifo19_rxrealign.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/udp/prot_eng_tx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/prot_eng_tx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/udp/add_onescomp.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/add_onescomp.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
   Current Project:
    	Family: spartan3adsp
    	Device: xc3sd1800a
    	Package: fg676
   /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco:
    	Family: spartan3
    	Device: xc3s2000
    	Package: fg456
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
   Current Project:
    	Family: spartan3adsp
    	Device: xc3sd1800a
    	Package: fg676
   /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco:
    	Family: spartan3
    	Device: xc3s2000
    	Package: fg456
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
   Current Project:
    	Family: spartan3adsp
    	Device: xc3sd1800a
    	Package: fg676
   /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco:
    	Family: spartan3
    	Device: xc3s2000
    	Package: fg456
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
   Current Project:
    	Family: spartan3adsp
    	Device: xc3sd1800a
    	Package: fg676
   /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco:
    	Family: spartan3
    	Device: xc3s2000
    	Package: fg456
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
   Current Project:
    	Family: spartan3adsp
    	Device: xc3sd1800a
    	Package: fg676
   /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco:
    	Family: spartan3
    	Device: xc3s2000
    	Package: fg456
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
   Current Project:
    	Family: Spartan-3A DSP
    	Device: xc3sd1800a
    	Package: fg676
   /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco:
    	Family: Spartan3
    	Device: xc3s50
    	Package: pq208
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core 'fifo_xlnx_32x36_2clk' do
   not match the ISE project settings.
   Family mismatch "Spartan3" vs. "Spartan-3A DSP"
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
   Current Project:
    	Family: Spartan-3A DSP
    	Device: xc3sd1800a
    	Package: fg676
   /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco:
    	Family: Spartan3
    	Device: xc3s50
    	Package: pq208
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
   'fifo_xlnx_512x36_2clk_36to18' do not match the ISE project settings.
   Family mismatch "Spartan3" vs. "Spartan-3A DSP"
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
   Current Project:
    	Family: Spartan-3A DSP
    	Device: xc3sd1800a
    	Package: fg676
   /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco:
    	Family: Spartan3
    	Device: xc3s50
    	Package: pq208
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
   'fifo_xlnx_512x36_2clk_18to36' do not match the ISE project settings.
   Family mismatch "Spartan3" vs. "Spartan-3A DSP"
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
   Current Project:
    	Family: Spartan-3A DSP
    	Device: xc3sd1800a
    	Package: fg676
   /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco:
    	Family: Spartan3
    	Device: xc3s50
    	Package: pq208
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
   'fifo_xlnx_512x36_2clk_prog_full' do not match the ISE project settings.
   Family mismatch "Spartan3" vs. "Spartan-3A DSP"
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/ext_fifo.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/ext_fifo.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/nobl_if.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_if.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/nobl_fifo.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_fifo.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/icon.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
   Current Project:
    	Family: spartan3adsp
    	Device: xc3sd1800a
    	Package: fg676
   /home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco:
    	Family: spartan3
    	Device: xc3s2000
    	Package: fg456
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
   line 0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
   36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/ila.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
   line 0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
   36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
   Current Project:
    	Family: spartan3adsp
    	Device: xc3sd1800a
    	Package: fg676
   /home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco:
    	Family: spartan3
    	Device: xc3s2000
    	Package: fg456
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
   line 0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
   36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'ila' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
   36 
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/refill_randomizer.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/refill_randomizer.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
   line 0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
   36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'ila' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
   36 
>>> Adding custom source to project: /home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/CRC16_D16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller16.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/bin2gray.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/bootram.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dbsm.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dcache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/decoder_3_8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/double_buffer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dpram32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/fifo_to_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gpio_atr.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gray2bin.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gray_send.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/icache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/longfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/medfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/mux4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/mux8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio16LE.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/oneshot_2clk.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/pic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/priority_enc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/quad_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_2port.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harv_cache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_loader.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/reset_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/s3a_icap_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/setting_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_16LE.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_crossclock.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_fifo_ctrl.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_i2c_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_spi_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/srl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/system_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/user_settings.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_1master.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_bridge_16_32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux_16LE.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/ext_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_if.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/refill_randomizer.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/add_routing_header.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_pool.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/crossbar36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/dsp_framer36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_pad.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_demux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_long.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_pacer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_short.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x3.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_padder36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_router.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/splitter36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/valve36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/decode_8b10b.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/encode_8b10b.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v\"
   into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
   line 131
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v\
   " into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
   line 73
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v"
   line 77
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v" line 45
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v" line 46
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/acc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_dec_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_decim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_int_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_strober.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_stage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_z24.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/ddc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_tx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_16to8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_8to16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/duc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipectrl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipestage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_sd.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_dcoffset.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_frontend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/sign_extend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/tx_frontend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter_promisc.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/crc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/delay_line.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethrx_realign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethtx_realign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ll8_to_txmac.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_clockgen.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_miim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/rxmac_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_rx.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_tx.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wb.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/simple_timer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_64bit.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_compare.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_receiver.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_sender.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/timer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/capture_ddrlvds.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v\" into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/top/N2x0/bootloader.rmi' in file
   "/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v" line 356
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/add_onescomp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/fifo19_rxrealign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/prot_eng_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/udp_wrapper.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/gen_context_pkt.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/trigger_context_pkt.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_pkt_gen.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_engine_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_framer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_deframer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_engine_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
   line 0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
   36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'ila' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
   36 
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
>>> Setting: Synthesize - XST[Number of Clock Buffers] = 8
>>> Setting: Synthesize - XST[Pack I/O Registers into IOBs] = Yes
>>> Setting: Synthesize - XST[Optimization Effort] = High
>>> Setting: Synthesize - XST[Optimize Instantiated Primitives] = TRUE
>>> Setting: Synthesize - XST[Register Balancing] = Yes
>>> Setting: Synthesize - XST[Use Clock Enable] = Auto
>>> Setting: Synthesize - XST[Use Synchronous Reset] = Auto
>>> Setting: Synthesize - XST[Use Synchronous Set] = Auto
>>> Setting: Synthesize - XST[Verilog Macros] = LVDS=1|RX_DSP0_MODULE=custom_dsp_rx
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/CRC16_D16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller16.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/bin2gray.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/bootram.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dbsm.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dcache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/decoder_3_8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/double_buffer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dpram32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/fifo_to_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gpio_atr.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gray2bin.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gray_send.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/icache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/longfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/medfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/mux4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/mux8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio16LE.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/oneshot_2clk.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/pic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/priority_enc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/quad_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_2port.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harv_cache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_loader.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/reset_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/s3a_icap_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/setting_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_16LE.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_crossclock.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_fifo_ctrl.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_i2c_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_spi_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/srl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/system_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/user_settings.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_1master.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_bridge_16_32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux_16LE.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/ext_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_if.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/refill_randomizer.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/add_routing_header.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_pool.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/crossbar36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/dsp_framer36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_pad.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_demux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_long.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_pacer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_short.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x3.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_padder36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_router.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/splitter36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/valve36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/decode_8b10b.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/encode_8b10b.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v\"
   into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
   line 131
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v\
   " into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
   line 73
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v"
   line 77
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v" line 45
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v" line 46
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/acc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_dec_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_decim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_int_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_strober.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_stage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_z24.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/ddc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_tx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_16to8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_8to16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/duc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipectrl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipestage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_sd.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_dcoffset.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_frontend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/sign_extend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/tx_frontend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter_promisc.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/crc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/delay_line.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethrx_realign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethtx_realign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ll8_to_txmac.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_clockgen.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_miim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/rxmac_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_rx.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_tx.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wb.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/simple_timer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_64bit.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_compare.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_receiver.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_sender.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/timer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/capture_ddrlvds.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v\" into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/top/N2x0/bootloader.rmi' in file
   "/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v" line 356
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/add_onescomp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/fifo19_rxrealign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/prot_eng_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/udp_wrapper.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/gen_context_pkt.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/trigger_context_pkt.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_pkt_gen.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_engine_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_framer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_deframer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_engine_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
   line 0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
   36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'ila' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
   36 
>>> Setting: Translate[Macro Search Path] = /home/usrp/uhd/fpga/usrp2/top/N2x0/../../coregen/
>>> Setting: Map[Generate Detailed MAP Report] = TRUE
>>> Setting: Map[Allow Logic Optimization Across Hierarchy] = TRUE
>>> Setting: Map[Map to Input Functions] = 4
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/CRC16_D16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller16.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/bin2gray.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/bootram.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dbsm.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dcache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/decoder_3_8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/double_buffer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dpram32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/fifo_to_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gpio_atr.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gray2bin.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gray_send.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/icache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/longfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/medfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/mux4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/mux8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio16LE.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/oneshot_2clk.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/pic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/priority_enc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/quad_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_2port.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harv_cache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_loader.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/reset_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/s3a_icap_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/setting_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_16LE.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_crossclock.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_fifo_ctrl.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_i2c_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_spi_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/srl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/system_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/user_settings.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_1master.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_bridge_16_32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux_16LE.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/ext_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_if.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/refill_randomizer.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/add_routing_header.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_pool.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/crossbar36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/dsp_framer36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_pad.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_demux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_long.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_pacer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_short.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x3.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_padder36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_router.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/splitter36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/valve36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/decode_8b10b.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/encode_8b10b.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v\"
   into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
   line 128
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
   line 131
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v\
   " into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
   line 70
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
   line 73
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v" line
   74
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v"
   line 77
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v" line 45
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v" line 46
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_config.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpupkg.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/acc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_dec_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_decim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_int_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_strober.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_stage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_z24.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/ddc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_tx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_16to8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_8to16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/duc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipectrl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipestage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_sd.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_dcoffset.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_frontend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/sign_extend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/tx_frontend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter_promisc.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/crc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/delay_line.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethrx_realign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethtx_realign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ll8_to_txmac.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_clockgen.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_miim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/rxmac_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_rx.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_tx.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wb.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/simple_timer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_64bit.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_compare.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_receiver.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_sender.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/timer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/capture_ddrlvds.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v\" into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/top/N2x0/bootloader.rmi' in file
   "/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v" line 356
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/add_onescomp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/fifo19_rxrealign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/prot_eng_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/udp_wrapper.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/gen_context_pkt.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/trigger_context_pkt.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_pkt_gen.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_engine_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_framer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_deframer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_engine_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
   line 0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
   36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'ila' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
   36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'glbl' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 3778 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
   1225 
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
   5483 
WARNING:TclTasksC:2134 - The property 'Map to Input Functions' is not supported
   in the current release. The property setting is being ignored at this time.
   Please update your script to avoid this message in the future. 
>>> Setting: Map[Optimization Strategy (Cover Mode)] = Speed
>>> Setting: Map[Pack I/O Registers/Latches into IOBs] = For Inputs and Outputs
>>> Setting: Map[Perform Timing-Driven Packing and Placement] = TRUE
>>> Setting: Map[Map Effort Level] = High
>>> Setting: Map[Extra Effort] = Normal
>>> Setting: Map[Combinatorial Logic Optimization] = TRUE
>>> Setting: Map[Register Duplication] = TRUE
WARNING:TclTasksC - The value(s) of this property "Register Duplication" has
   been changed in the current release to "Off" "On". The property value has
   been set to "On". Please update your script to use the new value to avoid
   this message in the future.
>>> Setting: Place & Route[Place & Route Effort Level (Overall)] = High
>>> Setting: Generate Post-Place & Route Static Timing[Number of Paths in Error/Verbose Report] = 10
>>> Setting: Generate Post-Place & Route Static Timing[Report Type] = Error Report
>>> Setting: Generate Programming File[Configuration Rate] = 6
>>> Setting: Generate Programming File[Create Binary Configuration File] = TRUE
>>> Setting: Generate Programming File[Done (Output Events)] = 5
>>> Setting: Generate Programming File[Enable Bitstream Compression] = TRUE
>>> Setting: Generate Programming File[Enable Outputs (Output Events)] = 6
python /home/usrp/uhd/fpga/usrp2/top/python/check_inout.py u2plus.v u2plus.ucf
No errors found.
xtclsh /home/usrp/uhd/fpga/usrp2/top/tcl/ise_helper.tcl "Check Syntax"
>>> Opening project: /home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom/u2plus.xise
Changed current working directory to the project directory:
"/home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom" 
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core 'fifo_xlnx_32x36_2clk' do
   not match the ISE project settings.
   Family mismatch "Spartan3" vs. "Spartan-3A DSP"
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
   'fifo_xlnx_512x36_2clk_36to18' do not match the ISE project settings.
   Family mismatch "Spartan3" vs. "Spartan-3A DSP"
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
   'fifo_xlnx_512x36_2clk_18to36' do not match the ISE project settings.
   Family mismatch "Spartan3" vs. "Spartan-3A DSP"
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
   'fifo_xlnx_512x36_2clk_prog_full' do not match the ISE project settings.
   Family mismatch "Spartan3" vs. "Spartan-3A DSP"
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/CRC16_D16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller16.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/bin2gray.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/bootram.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dbsm.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dcache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/decoder_3_8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/double_buffer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dpram32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/fifo_to_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gpio_atr.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gray2bin.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gray_send.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/icache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/longfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/medfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/mux4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/mux8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio16LE.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/oneshot_2clk.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/pic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/priority_enc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/quad_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_2port.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harv_cache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_loader.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/reset_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/s3a_icap_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/setting_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_16LE.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_crossclock.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_fifo_ctrl.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_i2c_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_spi_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/srl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/system_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/user_settings.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_1master.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_bridge_16_32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux_16LE.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/ext_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_if.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/refill_randomizer.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/add_routing_header.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_pool.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/crossbar36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/dsp_framer36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_pad.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_demux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_long.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_pacer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_short.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x3.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_padder36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_router.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/splitter36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/valve36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/decode_8b10b.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/encode_8b10b.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v\"
   into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
   line 131
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v\
   " into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
   line 73
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v"
   line 77
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v" line 45
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v" line 46
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_config.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpupkg.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/acc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_dec_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_decim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_int_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_strober.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_stage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_z24.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/ddc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_tx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_16to8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_8to16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/duc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipectrl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipestage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_sd.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_dcoffset.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_frontend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/sign_extend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/tx_frontend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter_promisc.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/crc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/delay_line.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethrx_realign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethtx_realign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ll8_to_txmac.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_clockgen.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_miim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/rxmac_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_rx.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_tx.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wb.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/simple_timer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_64bit.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_compare.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_receiver.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_sender.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/timer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/capture_ddrlvds.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v\" into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/top/N2x0/bootloader.rmi' in file
   "/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v" line 356
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/add_onescomp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/fifo19_rxrealign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/prot_eng_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/udp_wrapper.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/gen_context_pkt.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/trigger_context_pkt.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_pkt_gen.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_engine_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_framer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_deframer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_engine_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
   line 0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
   36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'ila' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
   36 
>>> Running Process: Check Syntax
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'

Started : "Check Syntax for u2plus".
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
   line 0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
   36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'ila' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
   36 
Running xst...
Command Line: xst -intstyle ise -ifn /home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom/u2plus.xst -ofn u2plus.stx

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../../custom/custom_dsp_rx.v" in library work
/opt/Xilinx/12.2/ISE_DS/ISE/bin/lin64/unwrapped/xst: symbol lookup error: /opt/Xilinx/12.2/ISE_DS/ISE//lib/lin64/libTw.so: undefined symbol: _ZN11xalanc_1_1016XalanTransformer9terminateEv
Compiling verilog file "../../../sdr_lib/clip.v" in library work
Module <custom_dsp_rx> compiled
Compiling verilog file "../../../sdr_lib/pipestage.v" in library work
Module <clip> compiled
Compiling verilog file "../../../sdr_lib/add2_and_clip.v" in library work
Module <pipestage> compiled
Compiling verilog file "../../../control_lib/ram_2port.v" in library work
Module <add2_and_clip> compiled
Compiling verilog file "../../../simple_gemac/miim/eth_shiftreg.v" in library work
Module <ram_2port> compiled
Compiling verilog file "../../../simple_gemac/miim/eth_outputcontrol.v" in library work
Module <eth_shiftreg> compiled
Compiling verilog file "../../../simple_gemac/miim/eth_clockgen.v" in library work
Module <eth_outputcontrol> compiled
Compiling verilog file "../../../simple_gemac/delay_line.v" in library work
Module <eth_clockgen> compiled
Compiling verilog file "../../../simple_gemac/crc.v" in library work
Module <delay_line> compiled
Compiling verilog file "../../../simple_gemac/address_filter_promisc.v" in library work
Module <crc> compiled
Compiling verilog file "../../../simple_gemac/address_filter.v" in library work
Module <address_filter_promisc> compiled
Compiling verilog file "../../../sdr_lib/sign_extend.v" in library work
Module <address_filter> compiled
Compiling verilog file "../../../sdr_lib/round.v" in library work
Module <sign_extend> compiled
Compiling verilog file "../../../sdr_lib/pipectrl.v" in library work
Module <round> compiled
Compiling verilog file "../../../sdr_lib/clip_reg.v" in library work
Module <pipectrl> compiled
Compiling verilog file "../../../sdr_lib/add2_and_round.v" in library work
Module <clip_reg> compiled
Compiling verilog file "../../../sdr_lib/add2_and_clip_reg.v" in library work
Module <add2_and_round> compiled
Compiling verilog file "../../../sdr_lib/add2.v" in library work
Module <add2_and_clip_reg> compiled
Compiling verilog file "../../../fifo/fifo_short.v" in library work
Module <add2> compiled
Compiling verilog file "../../../fifo/fifo_long.v" in library work
Module <fifo_short> compiled
Compiling verilog file "../../../fifo/fifo_2clock.v" in library work
Module <fifo_long> compiled
Compiling verilog file "../../../control_lib/shortfifo.v" in library work
Module <fifo_2clock> compiled
Compiling verilog file "../../../control_lib/setting_reg.v" in library work
Module <shortfifo> compiled
Compiling verilog file "../../../control_lib/bin2gray.v" in library work
Module <setting_reg> compiled
Compiling verilog file "../../../udp/add_onescomp.v" in library work
Module <bin2gray> compiled
Compiling verilog file "../../../timing/time_compare.v" in library work
Module <add_onescomp> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac_tx.v" in library work
Module <time_compare> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac_rx.v" in library work
Module <simple_gemac_tx> compiled
Compiling verilog file "../../../simple_gemac/miim/eth_miim.v" in library work
Module <simple_gemac_rx> compiled
Compiling verilog file "../../../simple_gemac/flow_ctrl_tx.v" in library work
Module <eth_miim> compiled
Compiling verilog file "../../../sdr_lib/round_sd.v" in library work
Module <flow_ctrl_tx> compiled
Compiling verilog file "../../../sdr_lib/round_reg.v" in library work
Module <round_sd> compiled
Compiling verilog file "../../../sdr_lib/dspengine_8to16.v" in library work
Module <round_reg> compiled
Compiling verilog file "../../../sdr_lib/dspengine_16to8.v" in library work
Module <dspengine_8to16> compiled
Compiling verilog file "../../../sdr_lib/cordic_stage.v" in library work
Module <dspengine_16to8> compiled
Compiling verilog file "../../../sdr_lib/cic_int_shifter.v" in library work
Module <cordic_stage> compiled
Compiling verilog file "../../../sdr_lib/cic_dec_shifter.v" in library work
Module <cic_int_shifter> compiled
Compiling verilog file "../../../sdr_lib/add2_reg.v" in library work
Module <cic_dec_shifter> compiled
Compiling verilog file "../../../sdr_lib/add2_and_round_reg.v" in library work
Module <add2_reg> compiled
Compiling verilog file "../../../sdr_lib/acc.v" in library work
Module <add2_and_round_reg> compiled
Compiling verilog file "../../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" in library work
Compiling verilog include file "../../../opencores/i2c/rtl/verilog/i2c_master_defines.v"
Module <acc> compiled
Compiling verilog file "../../../opencores/8b10b/encode_8b10b.v" in library work
Module <i2c_master_bit_ctrl> compiled
Compiling verilog file "../../../opencores/8b10b/decode_8b10b.v" in library work
Module <encode_8b10b> compiled
Compiling verilog file "../../../fifo/splitter36.v" in library work
Module <decode_8b10b> compiled
Compiling verilog file "../../../fifo/ll8_shortfifo.v" in library work
Module <splitter36> compiled
Compiling verilog file "../../../fifo/fifo_cascade.v" in library work
Module <ll8_shortfifo> compiled
Compiling verilog file "../../../fifo/fifo_2clock_cascade.v" in library work
Module <fifo_cascade> compiled
Compiling verilog file "../../../fifo/fifo36_mux.v" in library work
Module <fifo_2clock_cascade> compiled
Compiling verilog file "../../../extramfifo/nobl_if.v" in library work
Module <fifo36_mux> compiled
Compiling verilog file "../../../control_lib/srl.v" in library work
Module <nobl_if> compiled
Compiling verilog file "../../../control_lib/reset_sync.v" in library work
Module <srl> compiled
Compiling verilog file "../../../control_lib/oneshot_2clk.v" in library work
Module <reset_sync> compiled
Compiling verilog file "../../../control_lib/medfifo.v" in library work
Module <oneshot_2clk> compiled
Compiling verilog file "../../../control_lib/dbsm.v" in library work
Module <medfifo> compiled
Module <dbsm> compiled
Compiling verilog file "../../../control_lib/CRC16_D16.v" in library work
Module <buff_sm> compiled
Compiling verilog file "../../../vrt/vita_tx_engine_glue.v" in library work
Module <CRC16_D16> compiled
Compiling verilog file "../../../vrt/vita_tx_deframer.v" in library work
Module <vita_tx_engine_glue> compiled
Compiling verilog file "../../../vrt/vita_tx_control.v" in library work
Module <vita_tx_deframer> compiled
Compiling verilog file "../../../vrt/vita_rx_framer.v" in library work
Module <vita_tx_control> compiled
Compiling verilog file "../../../vrt/vita_rx_engine_glue.v" in library work
Module <vita_rx_framer> compiled
Compiling verilog file "../../../vrt/vita_rx_control.v" in library work
Module <vita_rx_engine_glue> compiled
Compiling verilog file "../../../vrt/trigger_context_pkt.v" in library work
Module <vita_rx_control> compiled
Compiling verilog file "../../../vrt/gen_context_pkt.v" in library work
Module <trigger_context_pkt> compiled
Compiling verilog file "../../../udp/prot_eng_tx.v" in library work
Module <gen_context_pkt> compiled
Compiling verilog file "../../../udp/fifo19_rxrealign.v" in library work
Module <prot_eng_tx> compiled
Compiling verilog file "../../../timing/time_sender.v" in library work
Module <fifo19_rxrealign> compiled
Compiling verilog file "../../../timing/time_receiver.v" in library work
Module <time_sender> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac_wb.v" in library work
Module <time_receiver> compiled
Module <wb_reg> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac.v" in library work
Module <simple_gemac_wb> compiled
Compiling verilog file "../../../simple_gemac/rxmac_to_ll8.v" in library work
Module <simple_gemac> compiled
Compiling verilog file "../../../simple_gemac/ll8_to_txmac.v" in library work
Module <rxmac_to_ll8> compiled
Compiling verilog file "../../../simple_gemac/flow_ctrl_rx.v" in library work
Module <ll8_to_txmac> compiled
Compiling verilog file "../../../simple_gemac/ethtx_realign.v" in library work
Module <flow_ctrl_rx> compiled
Compiling verilog file "../../../serdes/serdes_tx.v" in library work
Module <ethtx_realign> compiled
Compiling verilog file "../../../serdes/serdes_rx.v" in library work
Module <serdes_tx> compiled
Compiling verilog file "../../../serdes/serdes_fc_tx.v" in library work
Module <serdes_rx> compiled
Compiling verilog file "../../../serdes/serdes_fc_rx.v" in library work
Module <serdes_fc_tx> compiled
Compiling verilog file "../../../sdr_lib/small_hb_int.v" in library work
Module <serdes_fc_rx> compiled
Compiling verilog file "../../../sdr_lib/small_hb_dec.v" in library work
Module <small_hb_int> compiled
Compiling verilog file "../../../sdr_lib/rx_dcoffset.v" in library work
Module <small_hb_dec> compiled
Compiling verilog file "../../../sdr_lib/hb_interp.v" in library work
Module <rx_dcoffset> compiled
Compiling verilog file "../../../sdr_lib/hb_dec.v" in library work
Module <hb_interp> compiled
Compiling verilog file "../../../sdr_lib/dsp_tx_glue.v" in library work
Module <hb_dec> compiled
Compiling verilog file "../../../sdr_lib/dsp_rx_glue.v" in library work
Module <dsp_tx_glue> compiled
Compiling verilog file "../../../sdr_lib/cordic_z24.v" in library work
Module <dsp_rx_glue> compiled
Compiling verilog file "../../../sdr_lib/cic_strober.v" in library work
Module <cordic_z24> compiled
Compiling verilog file "../../../sdr_lib/cic_interp.v" in library work
Module <cic_strober> compiled
Compiling verilog file "../../../sdr_lib/cic_decim.v" in library work
Module <cic_interp> compiled
Compiling verilog file "../../../opencores/spi/rtl/verilog/spi_shift.v" in library work
Compiling verilog include file "../../../opencores/spi/rtl/verilog/spi_defines.v"
Module <cic_decim> compiled
Compiling verilog file "../../../opencores/spi/rtl/verilog/spi_clgen.v" in library work
Compiling verilog include file "../../../opencores/spi/rtl/verilog/spi_defines.v"
Module <spi_shift> compiled
Compiling verilog file "../../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" in library work
Compiling verilog include file "../../../opencores/i2c/rtl/verilog/i2c_master_defines.v"
Module <spi_clgen> compiled
Compiling verilog file "../../../fifo/valve36.v" in library work
Module <i2c_master_byte_ctrl> compiled
Compiling verilog file "../../../fifo/packet_dispatcher36_x4.v" in library work
Module <valve36> compiled
Compiling verilog file "../../../fifo/ll8_to_fifo19.v" in library work
Module <packet_dispatcher36_x4> compiled
Compiling verilog file "../../../fifo/fifo36_to_ll8.v" in library work
Module <ll8_to_fifo19> compiled
Compiling verilog file "../../../fifo/fifo19_to_fifo36.v" in library work
Module <fifo36_to_ll8> compiled
Compiling verilog file "../../../fifo/crossbar36.v" in library work
Module <fifo19_to_fifo36> compiled
Compiling verilog file "../../../fifo/buffer_int2.v" in library work
Module <crossbar36> compiled
Compiling verilog file "../../../fifo/add_routing_header.v" in library work
Module <buffer_int2> compiled
Compiling verilog file "../../../extramfifo/refill_randomizer.v" in library work
Module <add_routing_header> compiled
Compiling verilog file "../../../extramfifo/nobl_fifo.v" in library work
Module <refill_randomizer> compiled
Compiling verilog file "../../../control_lib/simple_uart_tx.v" in library work
Module <nobl_fifo> compiled
Compiling verilog file "../../../control_lib/simple_uart_rx.v" in library work
Module <simple_uart_tx> compiled
Compiling verilog file "../../../control_lib/priority_enc.v" in library work
Module <simple_uart_rx> compiled
Compiling verilog file "../../../control_lib/double_buffer.v" in library work
Module <priority_enc> compiled
Compiling verilog file "../../../vrt/vita_tx_chain.v" in library work
Module <double_buffer> compiled
Compiling verilog file "../../../vrt/vita_rx_chain.v" in library work
Module <vita_tx_chain> compiled
Compiling verilog file "../../../timing/time_64bit.v" in library work
Module <vita_rx_chain> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac_wrapper.v" in library work
Module <time_64bit> compiled
Compiling verilog file "../../../serdes/serdes.v" in library work
Module <simple_gemac_wrapper> compiled
Compiling verilog file "../../../sdr_lib/tx_frontend.v" in library work
Module <serdes> compiled
Compiling verilog file "../../../sdr_lib/rx_frontend.v" in library work
Module <tx_frontend> compiled
Compiling verilog file "../../../sdr_lib/duc_chain.v" in library work
Module <rx_frontend> compiled
Compiling verilog file "../../../sdr_lib/ddc_chain.v" in library work
Module <duc_chain> compiled
Compiling verilog file "../../../opencores/spi/rtl/verilog/spi_top.v" in library work
Compiling verilog include file "../../../opencores/spi/rtl/verilog/spi_defines.v"
Module <ddc_chain> compiled
Compiling verilog file "../../../opencores/i2c/rtl/verilog/i2c_master_top.v" in library work
Compiling verilog include file "../../../opencores/i2c/rtl/verilog/i2c_master_defines.v"
Module <spi_top> compiled
Compiling verilog file "../../../fifo/packet_router.v" in library work
Module <i2c_master_top> compiled
Compiling verilog file "../../../extramfifo/ext_fifo.v" in library work
Module <packet_router> compiled
Compiling verilog file "../../../control_lib/wb_readback_mux.v" in library work
Module <ext_fifo> compiled
Compiling verilog file "../../../control_lib/wb_1master.v" in library work
Module <wb_readback_mux> compiled
Compiling verilog file "../../../control_lib/user_settings.v" in library work
Module <wb_1master> compiled
Compiling verilog file "../../../control_lib/system_control.v" in library work
Module <user_settings> compiled
Compiling verilog file "../../../control_lib/simple_spi_core.v" in library work
Module <system_control> compiled
Compiling verilog file "../../../control_lib/settings_fifo_ctrl.v" in library work
Module <simple_spi_core> compiled
Compiling verilog file "../../../control_lib/settings_bus_crossclock.v" in library work
Module <settings_fifo_ctrl> compiled
Compiling verilog file "../../../control_lib/settings_bus.v" in library work
Module <settings_bus_crossclock> compiled
Compiling verilog file "../../../control_lib/s3a_icap_wb.v" in library work
Module <settings_bus> compiled
Compiling verilog file "../../../control_lib/ram_harvard2.v" in library work
Module <s3a_icap_wb> compiled
Compiling verilog file "../../../control_lib/quad_uart.v" in library work
Module <ram_harvard2> compiled
Compiling verilog file "../../../control_lib/pic.v" in library work
Module <quad_uart> compiled
Compiling verilog file "../../../control_lib/gpio_atr.v" in library work
Module <pic> compiled
Compiling verilog file "../../../control_lib/bootram.v" in library work
Module <gpio_atr> compiled
Compiling verilog file "../u2plus_core.v" in library work
Module <bootram> compiled
Compiling verilog include file "../bootloader.rmi"
Compiling verilog file "../capture_ddrlvds.v" in library work
Module <u2plus_core> compiled
Compiling verilog file "../u2plus.v" in library work
Module <capture_ddrlvds> compiled
Module <u2plus> compiled
No errors in compilation
Analysis of file <"u2plus.prj"> succeeded.
 
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_config.vhd" in Library work.
Package <zpu_config> compiled.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpupkg.vhd" in Library work.
Package <zpupkg> compiled.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd" in Library work.
Package <wishbone_pkg> compiled.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd" in Library work.
Package <zpu_top_pkg> compiled.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd" in Library work.
Entity <zpu_core> compiled.
Entity <zpu_core> (Architecture <behave>) compiled.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd" in Library work.
Entity <zpu_wb_bridge> compiled.
Entity <zpu_wb_bridge> (Architecture <behave>INFO:TclTasksC:1850 - process run : Check Syntax is done.
) compiled.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd" in Library work.
Entity <zpu_system> compiled.
Entity <zpu_system> (Architecture <behave>) compiled.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd" in Library work.
Entity <zpu_wb_top> compiled.
Entity <zpu_wb_top> (Architecture <syn>) compiled.

Process "Check Syntax" failed
/home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom/u2plus.bin
xtclsh /home/usrp/uhd/fpga/usrp2/top/tcl/ise_helper.tcl "Generate Programming File" 2>&1 | tee /home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom/build.log
>>> Opening project: /home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom/u2plus.xise
Changed current working directory to the project directory:
"/home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom" 
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
   work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core 'fifo_xlnx_32x36_2clk' do
   not match the ISE project settings.
   Family mismatch "Spartan3" vs. "Spartan-3A DSP"
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
   'fifo_xlnx_512x36_2clk_36to18' do not match the ISE project settings.
   Family mismatch "Spartan3" vs. "Spartan-3A DSP"
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
   'fifo_xlnx_512x36_2clk_18to36' do not match the ISE project settings.
   Family mismatch "Spartan3" vs. "Spartan-3A DSP"
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
   library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
   'fifo_xlnx_512x36_2clk_prog_full' do not match the ISE project settings.
   Family mismatch "Spartan3" vs. "Spartan-3A DSP"
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/CRC16_D16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller16.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/bin2gray.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/bootram.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dbsm.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dcache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/decoder_3_8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/double_buffer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/dpram32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/fifo_to_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gpio_atr.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gray2bin.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/gray_send.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/icache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/longfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/medfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/mux4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/mux8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio16LE.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/oneshot_2clk.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/pic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/priority_enc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/quad_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_2port.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harv_cache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/ram_loader.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/reset_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/s3a_icap_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/setting_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_16LE.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_crossclock.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/settings_fifo_ctrl.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_i2c_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_spi_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/srl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/system_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/user_settings.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_1master.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_bridge_16_32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux_16LE.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/ext_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_if.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/extramfifo/refill_randomizer.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/add_routing_header.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/buffer_pool.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/crossbar36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/dsp_framer36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_pad.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_demux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_long.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_pacer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/fifo_short.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x3.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_padder36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_router.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/splitter36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/fifo/valve36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/decode_8b10b.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/encode_8b10b.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v\"
   into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
   line 131
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v\
   " into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file
   "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
   line 73
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
   file "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v"
   line 77
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v" line 45
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v\" into
   library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
   "/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v" line 46
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_config.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpupkg.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/acc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_dec_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_decim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_int_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_strober.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_stage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_z24.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/ddc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_tx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_16to8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_8to16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/duc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipectrl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipestage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_sd.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_dcoffset.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_frontend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/sign_extend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/sdr_lib/tx_frontend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/serdes/serdes_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter_promisc.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/crc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/delay_line.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethrx_realign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethtx_realign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/ll8_to_txmac.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_clockgen.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_miim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/rxmac_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_rx.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_tx.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wb.v\" into library
   work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v\" into
   library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/simple_timer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_64bit.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_compare.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_receiver.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_sender.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/time_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/timing/timer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/capture_ddrlvds.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v\" into library work
INFO:ProjectMgmt - Include file found:
   '/home/usrp/uhd/fpga/usrp2/top/N2x0/bootloader.rmi' in file
   "/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v" line 356
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/add_onescomp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/fifo19_rxrealign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/prot_eng_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/udp/udp_wrapper.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/gen_context_pkt.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/trigger_context_pkt.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_pkt_gen.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_engine_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_framer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_deframer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
   \"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_engine_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'ila' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
   36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
   line 0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
   36 
>>> Running Process: Generate Programming File
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
   found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
   (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit
   'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
    
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
   library 'work'
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -   
   "/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'ila' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco" line
   0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
   36 
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
   line 0 (active)
WARNING:ProjectMgmt:495 -    "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
   36 

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "/home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom/u2plus.xst" -ofn "/home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom/u2plus.syr"
Reading design: u2plus.prj

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../../custom/custom_dsp_rx.v" in library work
Compiling verilog file "../../../sdr_lib/clip.v" in library work
Module <custom_dsp_rx> compiled
Compiling verilog file "../../../sdr_lib/pipestage.v" in library work
Module <clip> compiled
Compiling verilog file "../../../sdr_lib/add2_and_clip.v" in library work
Module <pipestage> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_64x36_2clk.v" in library work
Module <add2_and_clip> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_512x36_2clk.v" in library work
Module <fifo_xlnx_64x36_2clk> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_2Kx36_2clk.v" in library work
Module <fifo_xlnx_512x36_2clk> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_16x19_2clk.v" in library work
Module <fifo_xlnx_2Kx36_2clk> compiled
Compiling verilog file "../../../control_lib/ram_2port.v" in library work
Module <fifo_xlnx_16x19_2clk> compiled
Compiling verilog file "../../../simple_gemac/miim/eth_shiftreg.v" in library work
Module <ram_2port> compiled
Compiling verilog file "../../../simple_gemac/miim/eth_outputcontrol.v" in library work
Module <eth_shiftreg> compiled
Compiling verilog file "../../../simple_gemac/miim/eth_clockgen.v" in library work
Module <eth_outputcontrol> compiled
Compiling verilog file "../../../simple_gemac/delay_line.v" in library work
Module <eth_clockgen> compiled
Compiling verilog file "../../../simple_gemac/crc.v" in library work
Module <delay_line> compiled
Compiling verilog file "../../../simple_gemac/address_filter_promisc.v" in library work
Module <crc> compiled
Compiling verilog file "../../../simple_gemac/address_filter.v" in library work
Module <address_filter_promisc> compiled
Compiling verilog file "../../../sdr_lib/sign_extend.v" in library work
Module <address_filter> compiled
Compiling verilog file "../../../sdr_lib/round.v" in library work
Module <sign_extend> compiled
Compiling verilog file "../../../sdr_lib/pipectrl.v" in library work
Module <round> compiled
Compiling verilog file "../../../sdr_lib/clip_reg.v" in library work
Module <pipectrl> compiled
Compiling verilog file "../../../sdr_lib/add2_and_round.v" in library work
Module <clip_reg> compiled
Compiling verilog file "../../../sdr_lib/add2_and_clip_reg.v" in library work
Module <add2_and_round> compiled
Compiling verilog file "../../../sdr_lib/add2.v" in library work
Module <add2_and_clip_reg> compiled
Compiling verilog file "../../../fifo/fifo_short.v" in library work
Module <add2> compiled
Compiling verilog file "../../../fifo/fifo_long.v" in library work
Module <fifo_short> compiled
Compiling verilog file "../../../fifo/fifo_2clock.v" in library work
Module <fifo_long> compiled
Compiling verilog file "../../../control_lib/shortfifo.v" in library work
Module <fifo_2clock> compiled
Compiling verilog file "../../../control_lib/setting_reg.v" in library work
Module <shortfifo> compiled
Compiling verilog file "../../../control_lib/bin2gray.v" in library work
Module <setting_reg> compiled
Compiling verilog file "../../../udp/add_onescomp.v" in library work
Module <bin2gray> compiled
Compiling verilog file "../../../timing/time_compare.v" in library work
Module <add_onescomp> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac_tx.v" in library work
Module <time_compare> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac_rx.v" in library work
Module <simple_gemac_tx> compiled
Compiling verilog file "../../../simple_gemac/miim/eth_miim.v" in library work
Module <simple_gemac_rx> compiled
Compiling verilog file "../../../simple_gemac/flow_ctrl_tx.v" in library work
Module <eth_miim> compiled
Compiling verilog file "../../../sdr_lib/round_sd.v" in library work
Module <flow_ctrl_tx> compiled
Compiling verilog file "../../../sdr_lib/round_reg.v" in library work
Module <round_sd> compiled
Compiling verilog file "../../../sdr_lib/dspengine_8to16.v" in library work
Module <round_reg> compiled
Compiling verilog file "../../../sdr_lib/dspengine_16to8.v" in library work
Module <dspengine_8to16> compiled
Compiling verilog file "../../../sdr_lib/cordic_stage.v" in library work
Module <dspengine_16to8> compiled
Compiling verilog file "../../../sdr_lib/cic_int_shifter.v" in library work
Module <cordic_stage> compiled
Compiling verilog file "../../../sdr_lib/cic_dec_shifter.v" in library work
Module <cic_int_shifter> compiled
Compiling verilog file "../../../sdr_lib/add2_reg.v" in library work
Module <cic_dec_shifter> compiled
Compiling verilog file "../../../sdr_lib/add2_and_round_reg.v" in library work
Module <add2_reg> compiled
Compiling verilog file "../../../sdr_lib/acc.v" in library work
Module <add2_and_round_reg> compiled
Compiling verilog file "../../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" in library work
Compiling verilog include file "../../../opencores/i2c/rtl/verilog/i2c_master_defines.v"
Module <acc> compiled
Compiling verilog file "../../../opencores/8b10b/encode_8b10b.v" in library work
Module <i2c_master_bit_ctrl> compiled
Compiling verilog file "../../../opencores/8b10b/decode_8b10b.v" in library work
Module <encode_8b10b> compiled
Compiling verilog file "../../../fifo/splitter36.v" in library work
Module <decode_8b10b> compiled
Compiling verilog file "../../../fifo/ll8_shortfifo.v" in library work
Module <splitter36> compiled
Compiling verilog file "../../../fifo/fifo_cascade.v" in library work
Module <ll8_shortfifo> compiled
Compiling verilog file "../../../fifo/fifo_2clock_cascade.v" in library work
Module <fifo_cascade> compiled
Compiling verilog file "../../../fifo/fifo36_mux.v" in library work
Module <fifo_2clock_cascade> compiled
Compiling verilog file "../../../extramfifo/nobl_if.v" in library work
Module <fifo36_mux> compiled
Compiling verilog file "../../../control_lib/srl.v" in library work
Module <nobl_if> compiled
Compiling verilog file "../../../control_lib/reset_sync.v" in library work
Module <srl> compiled
Compiling verilog file "../../../control_lib/oneshot_2clk.v" in library work
Module <reset_sync> compiled
Compiling verilog file "../../../control_lib/medfifo.v" in library work
Module <oneshot_2clk> compiled
Compiling verilog file "../../../control_lib/dbsm.v" in library work
Module <medfifo> compiled
Module <dbsm> compiled
Compiling verilog file "../../../control_lib/CRC16_D16.v" in library work
Module <buff_sm> compiled
Compiling verilog file "../../../vrt/vita_tx_engine_glue.v" in library work
Module <CRC16_D16> compiled
Compiling verilog file "../../../vrt/vita_tx_deframer.v" in library work
Module <vita_tx_engine_glue> compiled
Compiling verilog file "../../../vrt/vita_tx_control.v" in library work
Module <vita_tx_deframer> compiled
Compiling verilog file "../../../vrt/vita_rx_framer.v" in library work
Module <vita_tx_control> compiled
Compiling verilog file "../../../vrt/vita_rx_engine_glue.v" in library work
Module <vita_rx_framer> compiled
Compiling verilog file "../../../vrt/vita_rx_control.v" in library work
Module <vita_rx_engine_glue> compiled
Compiling verilog file "../../../vrt/trigger_context_pkt.v" in library work
Module <vita_rx_control> compiled
Compiling verilog file "../../../vrt/gen_context_pkt.v" in library work
Module <trigger_context_pkt> compiled
Compiling verilog file "../../../udp/prot_eng_tx.v" in library work
Module <gen_context_pkt> compiled
Compiling verilog file "../../../udp/fifo19_rxrealign.v" in library work
Module <prot_eng_tx> compiled
Compiling verilog file "../../../timing/time_sender.v" in library work
Module <fifo19_rxrealign> compiled
Compiling verilog file "../../../timing/time_receiver.v" in library work
Module <time_sender> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac_wb.v" in library work
Module <time_receiver> compiled
Module <wb_reg> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac.v" in library work
Module <simple_gemac_wb> compiled
Compiling verilog file "../../../simple_gemac/rxmac_to_ll8.v" in library work
Module <simple_gemac> compiled
Compiling verilog file "../../../simple_gemac/ll8_to_txmac.v" in library work
Module <rxmac_to_ll8> compiled
Compiling verilog file "../../../simple_gemac/flow_ctrl_rx.v" in library work
Module <ll8_to_txmac> compiled
Compiling verilog file "../../../simple_gemac/ethtx_realign.v" in library work
Module <flow_ctrl_rx> compiled
Compiling verilog file "../../../serdes/serdes_tx.v" in library work
Module <ethtx_realign> compiled
Compiling verilog file "../../../serdes/serdes_rx.v" in library work
Module <serdes_tx> compiled
Compiling verilog file "../../../serdes/serdes_fc_tx.v" in library work
Module <serdes_rx> compiled
Compiling verilog file "../../../serdes/serdes_fc_rx.v" in library work
Module <serdes_fc_tx> compiled
Compiling verilog file "../../../sdr_lib/small_hb_int.v" in library work
Module <serdes_fc_rx> compiled
Compiling verilog file "../../../sdr_lib/small_hb_dec.v" in library work
Module <small_hb_int> compiled
Compiling verilog file "../../../sdr_lib/rx_dcoffset.v" in library work
Module <small_hb_dec> compiled
Compiling verilog file "../../../sdr_lib/hb_interp.v" in library work
Module <rx_dcoffset> compiled
Compiling verilog file "../../../sdr_lib/hb_dec.v" in library work
Module <hb_interp> compiled
Compiling verilog file "../../../sdr_lib/dsp_tx_glue.v" in library work
Module <hb_dec> compiled
Compiling verilog file "../../../sdr_lib/dsp_rx_glue.v" in library work
Module <dsp_tx_glue> compiled
Compiling verilog file "../../../sdr_lib/cordic_z24.v" in library work
Module <dsp_rx_glue> compiled
Compiling verilog file "../../../sdr_lib/cic_strober.v" in library work
Module <cordic_z24> compiled
Compiling verilog file "../../../sdr_lib/cic_interp.v" in library work
Module <cic_strober> compiled
Compiling verilog file "../../../sdr_lib/cic_decim.v" in library work
Module <cic_interp> compiled
Compiling verilog file "../../../opencores/spi/rtl/verilog/spi_shift.v" in library work
Compiling verilog include file "../../../opencores/spi/rtl/verilog/spi_defines.v"
Module <cic_decim> compiled
Compiling verilog file "../../../opencores/spi/rtl/verilog/spi_clgen.v" in library work
Compiling verilog include file "../../../opencores/spi/rtl/verilog/spi_defines.v"
Module <spi_shift> compiled
Compiling verilog file "../../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" in library work
Compiling verilog include file "../../../opencores/i2c/rtl/verilog/i2c_master_defines.v"
Module <spi_clgen> compiled
Compiling verilog file "../../../fifo/valve36.v" in library work
Module <i2c_master_byte_ctrl> compiled
Compiling verilog file "../../../fifo/packet_dispatcher36_x4.v" in library work
Module <valve36> compiled
Compiling verilog file "../../../fifo/ll8_to_fifo19.v" in library work
Module <packet_dispatcher36_x4> compiled
Compiling verilog file "../../../fifo/fifo36_to_ll8.v" in library work
Module <ll8_to_fifo19> compiled
Compiling verilog file "../../../fifo/fifo19_to_fifo36.v" in library work
Module <fifo36_to_ll8> compiled
Compiling verilog file "../../../fifo/crossbar36.v" in library work
Module <fifo19_to_fifo36> compiled
Compiling verilog file "../../../fifo/buffer_int2.v" in library work
Module <crossbar36> compiled
Compiling verilog file "../../../fifo/add_routing_header.v" in library work
Module <buffer_int2> compiled
Compiling verilog file "../../../extramfifo/refill_randomizer.v" in library work
Module <add_routing_header> compiled
Compiling verilog file "../../../extramfifo/nobl_fifo.v" in library work
Module <refill_randomizer> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_512x36_2clk_prog_full.v" in library work
Module <nobl_fifo> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_512x36_2clk_36to18.v" in library work
Module <fifo_xlnx_512x36_2clk_prog_full> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_512x36_2clk_18to36.v" in library work
Module <fifo_xlnx_512x36_2clk_36to18> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_32x36_2clk.v" in library work
Module <fifo_xlnx_512x36_2clk_18to36> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_16x40_2clk.v" in library work
Module <fifo_xlnx_32x36_2clk> compiled
Compiling verilog file "../../../control_lib/simple_uart_tx.v" in library work
Module <fifo_xlnx_16x40_2clk> compiled
Compiling verilog file "../../../control_lib/simple_uart_rx.v" in library work
Module <simple_uart_tx> compiled
Compiling verilog file "../../../control_lib/priority_enc.v" in library work
Module <simple_uart_rx> compiled
Compiling verilog file "../../../control_lib/double_buffer.v" in library work
Module <priority_enc> compiled
Compiling verilog file "../../../vrt/vita_tx_chain.v" in library work
Module <double_buffer> compiled
Compiling verilog file "../../../vrt/vita_rx_chain.v" in library work
Module <vita_tx_chain> compiled
Compiling verilog file "../../../timing/time_64bit.v" in library work
Module <vita_rx_chain> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac_wrapper.v" in library work
Module <time_64bit> compiled
Compiling verilog file "../../../serdes/serdes.v" in library work
Module <simple_gemac_wrapper> compiled
Compiling verilog file "../../../sdr_lib/tx_frontend.v" in library work
Module <serdes> compiled
Compiling verilog file "../../../sdr_lib/rx_frontend.v" in library work
Module <tx_frontend> compiled
Compiling verilog file "../../../sdr_lib/duc_chain.v" in library work
Module <rx_frontend> compiled
Compiling verilog file "../../../sdr_lib/ddc_chain.v" in library work
Module <duc_chain> compiled
Compiling verilog file "../../../opencores/spi/rtl/verilog/spi_top.v" in library work
Compiling verilog include file "../../../opencores/spi/rtl/verilog/spi_defines.v"
Module <ddc_chain> compiled
Compiling verilog file "../../../opencores/i2c/rtl/verilog/i2c_master_top.v" in library work
Compiling verilog include file "../../../opencores/i2c/rtl/verilog/i2c_master_defines.v"
Module <spi_top> compiled
Compiling verilog file "../../../fifo/packet_router.v" in library work
Module <i2c_master_top> compiled
Compiling verilog file "../../../extramfifo/ext_fifo.v" in library work
Module <packet_router> compiled
Compiling verilog file "../../../control_lib/wb_readback_mux.v" in library work
Module <ext_fifo> compiled
Compiling verilog file "../../../control_lib/wb_1master.v" in library work
Module <wb_readback_mux> compiled
Compiling verilog file "../../../control_lib/user_settings.v" in library work
Module <wb_1master> compiled
Compiling verilog file "../../../control_lib/system_control.v" in library work
Module <user_settings> compiled
Compiling verilog file "../../../control_lib/simple_spi_core.v" in library work
Module <system_control> compiled
Compiling verilog file "../../../control_lib/settings_fifo_ctrl.v" in library work
Module <simple_spi_core> compiled
Compiling verilog file "../../../control_lib/settings_bus_crossclock.v" in library work
Module <settings_fifo_ctrl> compiled
Compiling verilog file "../../../control_lib/settings_bus.v" in library work
Module <settings_bus_crossclock> compiled
Compiling verilog file "../../../control_lib/s3a_icap_wb.v" in library work
Module <settings_bus> compiled
Compiling verilog file "../../../control_lib/ram_harvard2.v" in library work
Module <s3a_icap_wb> compiled
Compiling verilog file "../../../control_lib/quad_uart.v" in library work
Module <ram_harvard2> compiled
Compiling verilog file "../../../control_lib/pic.v" in library work
Module <quad_uart> compiled
Compiling verilog file "../../../control_lib/gpio_atr.v" in library work
Module <pic> compiled
Compiling verilog file "../../../control_lib/bootram.v" in library work
Module <gpio_atr> compiled
Compiling verilog file "../u2plus_core.v" in library work
Module <bootram> compiled
Compiling verilog include file "../bootloader.rmi"
Compiling verilog file "../capture_ddrlvds.v" in library work
Module <u2plus_core> compiled
Compiling verilog file "../u2plus.v" in library work
Module <capture_ddrlvds> compiled
Module <u2plus> compiled
No errors in compilation
Analysis of file <"u2plus.prj"> succeeded.
 
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_config.vhd" in Library work.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpupkg.vhd" in Library work.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd" in Library work.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd" in Library work.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd" in Library work.
Architecture behave of Entity zpu_core is up to date.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd" in Library work.
Architecture behave of Entity zpu_wb_bridge is up to date.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd" in Library work.
Architecture behave of Entity zpu_system is up to date.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd" in Library work.
Architecture syn of Entity zpu_wb_top is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <u2plus> in library <work>.

Analyzing hierarchy for module <capture_ddrlvds> in library <work> with parameters.
	WIDTH = "00000000000000000000000000001110"

Analyzing hierarchy for module <u2plus_core> in library <work> with parameters.
	CPU_BLDR_CTRL_DONE = "00000000000000000000000000000001"
	CPU_BLDR_CTRL_WAIT = "00000000000000000000000000000000"
	DSP_RX_FIFOSIZE = "00000000000000000000000000001010"
	DSP_TX_FIFOSIZE = "00000000000000000000000000001010"
	ETH_RX_FIFOSIZE = "00000000000000000000000000001011"
	ETH_TX_FIFOSIZE = "00000000000000000000000000001001"
	SERDES_RX_FIFOSIZE = "00000000000000000000000000001001"
	SERDES_TX_FIFOSIZE = "00000000000000000000000000001001"
	SR_BUF_POOL = "00000000000000000000000000010000"
	SR_GPIO = "00000000000000000000000010111000"
	SR_MISC = "00000000000000000000000000000000"
	SR_RX_CTRL0 = "00000000000000000000000000100000"
	SR_RX_CTRL1 = "00000000000000000000000001010000"
	SR_RX_DSP0 = "00000000000000000000000000110000"
	SR_RX_DSP1 = "00000000000000000000000001100000"
	SR_RX_FRONT = "00000000000000000000000000011000"
	SR_SPI_CORE = "00000000000000000000000000010100"
	SR_TIME64 = "00000000000000000000000000001010"
	SR_TX_CTRL = "00000000000000000000000010010000"
	SR_TX_DSP = "00000000000000000000000010100000"
	SR_TX_FRONT = "00000000000000000000000010000000"
	SR_UDP_SM = "00000000000000000000000011000000"
	SR_USER_REGS = "00000000000000000000000000001000"
	aw = "00000000000000000000000000010000"
	compat_num = "00000000000010100000000000000001"
	dw = "00000000000000000000000000100000"
	sw = "00000000000000000000000000000100"

Analyzing hierarchy for module <wb_1master> in library <work> with parameters.
	aw = "00000000000000000000000000010000"
	decode_w = "00000000000000000000000000001000"
	dw = "00000000000000000000000000100000"
	s0_addr = "00000000"
	s0_mask = "11000000"
	s1_addr = "01000000"
	s1_mask = "11110000"
	s2_addr = "01010000"
	s2_mask = "11111100"
	s3_addr = "01010100"
	s3_mask = "11111100"
	s4_addr = "01011000"
	s4_mask = "11111100"
	s5_addr = "01011100"
	s5_mask = "11111100"
	s6_addr = "01100000"
	s6_mask = "11110000"
	s7_addr = "01110000"
	s7_mask = "11110000"
	s8_addr = "10000000"
	s8_mask = "11111100"
	s9_addr = "10000100"
	s9_mask = "11111100"
	sa_addr = "10001000"
	sa_mask = "11111100"
	sb_addr = "10001100"
	sb_mask = "11111100"
	sc_addr = "10010000"
	sc_mask = "11110000"
	sd_addr = "10100000"
	sd_mask = "11110000"
	se_addr = "10110000"
	se_mask = "11110000"
	sf_addr = "11000000"
	sf_mask = "11000000"
	sw = "00000000000000000000000000000100"

Analyzing hierarchy for module <system_control> in library <work>.

Analyzing hierarchy for entity <zpu_wb_top> in library <work> (architecture <syn>) with generics.
	adr_w = 16
	dat_w = 32
	sel_w = 4

Analyzing hierarchy for module <bootram> in library <work>.

Analyzing hierarchy for module <ram_harvard2> in library <work> with parameters.
	AWIDTH = "00000000000000000000000000001110"
	RAM_SIZE = "00000000000000000100000000000000"

Analyzing hierarchy for module <packet_router> in library <work> with parameters.
	BUF_SIZE = "00000000000000000000000000001001"
	CTRL_BASE = "00000000000000000000000000010000"
	UDP_BASE = "00000000000000000000000011000000"

Analyzing hierarchy for module <simple_spi_core> in library <work> with parameters.
	BASE = "00000000000000000000000000010100"
	CLK_IDLE = "00000000000000000000000000000000"
	CLK_INV = "00000000000000000000000000000011"
	CLK_REG = "00000000000000000000000000000010"
	IDLE_SEN = "00000000000000000000000000000101"
	POST_IDLE = "00000000000000000000000000000100"
	PRE_IDLE = "00000000000000000000000000000001"
	SEN_IDLE = "111111111111111111111111"
	WAIT_TRIG = "00000000000000000000000000000000"
	WIDTH = "00000000000000000000000000001001"

Analyzing hierarchy for module <i2c_master_top> in library <work> with parameters.
	ARST_LVL = "00000000000000000000000000000001"

Analyzing hierarchy for module <gpio_atr> in library <work> with parameters.
	BASE = "00000000000000000000000010111000"
	WIDTH = "00000000000000000000000000100000"

Analyzing hierarchy for module <wb_readback_mux> in library <work>.

Analyzing hierarchy for module <simple_gemac_wrapper> in library <work> with parameters.
	RXFIFOSIZE = "00000000000000000000000000001011"
	RX_FLOW_CTRL = "00000000000000000000000000000000"
	TXFIFOSIZE = "00000000000000000000000000001001"

Analyzing hierarchy for module <settings_bus> in library <work> with parameters.
	AWIDTH = "00000000000000000000000000010000"
	DWIDTH = "00000000000000000000000000100000"

Analyzing hierarchy for module <settings_bus_crossclock> in library <work> with parameters.
	FLOW_CTRL = "00000000000000000000000000000001"

Analyzing hierarchy for module <user_settings> in library <work> with parameters.
	BASE = "00000000000000000000000000001000"

Analyzing hierarchy for module <settings_fifo_ctrl> in library <work> with parameters.
	ACK_SID = "00000000000000000000000000000000"
	EVENT_CMD = "00000000000000000000000000000001"
	LOAD_CMD = "00000000000000000000000000000000"
	PROT_DEST = "00000000000000000000000000000011"
	PROT_HDR = "00000000000000000000000000000001"
	READ_DATA = "00000000000000000000000000001001"
	READ_HDR = "00000000000000000000000000001000"
	READ_LINE0 = "00000000000000000000000000000000"
	START_STATE = "00000000000000000000000000000000"
	STORE_CMD = "00000000000000000000000000001011"
	VITA_CID0 = "00000000000000000000000000000011"
	VITA_CID1 = "00000000000000000000000000000100"
	VITA_HDR = "00000000000000000000000000000001"
	VITA_SID = "00000000000000000000000000000010"
	VITA_TSF0 = "00000000000000000000000000000110"
	VITA_TSF1 = "00000000000000000000000000000111"
	VITA_TSI = "00000000000000000000000000000101"
	WAIT_EOF = "00000000000000000000000000001010"
	WRITE_PKT_HDR = "00000000000000000000000000000000"
	WRITE_PROT_HDR = "00000000000000000000000000000000"
	WRITE_RB_DATA = "00000000000000000000000000000100"
	WRITE_RB_HDR = "00000000000000000000000000000011"
	WRITE_VRT_HDR = "00000000000000000000000000000001"
	WRITE_VRT_SID = "00000000000000000000000000000010"
	XPORT_HDR = "00000000000000000000000000000001"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000010001"
	width = "00000000000000000000000000000001"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000000000"
	width = "00000000000000000000000000001000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000000001"
	width = "00000000000000000000000000001000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000000010"
	width = "00000000000000000000000000001000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000000100"
	width = "00000000000000000000000000000001"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000000101"
	width = "00000000000000000000000000000001"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000000011"
	width = "00000000000000000000000000001000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00011110"
	my_addr = "00000000000000000000000000000110"
	width = "00000000000000000000000000001000"

Analyzing hierarchy for module <pic> in library <work>.

Analyzing hierarchy for module <quad_uart> in library <work> with parameters.
	RXDEPTH = "00000000000000000000000000000011"
	SUART_CLKDIV = "00000000000000000000000000000000"
	SUART_RXCHAR = "00000000000000000000000000000100"
	SUART_RXLEVEL = "00000000000000000000000000000010"
	SUART_TXCHAR = "00000000000000000000000000000011"
	SUART_TXLEVEL = "00000000000000000000000000000001"
	TXDEPTH = "00000000000000000000000000000011"

Analyzing hierarchy for module <s3a_icap_wb> in library <work> with parameters.
	ICAP_IDLE = "00000000000000000000000000000000"
	ICAP_RD0 = "00000000000000000000000000000010"
	ICAP_RD1 = "00000000000000000000000000000011"
	ICAP_WR0 = "00000000000000000000000000000001"
	ICAP_WR1 = "00000000000000000000000000000101"

Analyzing hierarchy for module <spi_top> in library <work>.

Analyzing hierarchy for module <rx_frontend> in library <work> with parameters.
	BASE = "00000000000000000000000000011000"
	IQCOMP_EN = "00000000000000000000000000000001"

Analyzing hierarchy for module <ddc_chain> in library <work> with parameters.
	BASE = "00000000000000000000000000110000"
	DSPNO = "00000000000000000000000000000000"
	WIDTH = "00000000000000000000000000011000"
	cwidth = "00000000000000000000000000011001"
	zwidth = "00000000000000000000000000011000"

Analyzing hierarchy for module <vita_rx_chain> in library <work> with parameters.
	BASE = "00000000000000000000000000100000"
	DSP_NUMBER = "00000000000000000000000000000000"
	FIFOSIZE = "00000000000000000000000000001010"
	PROT_ENG_FLAGS = "00000000000000000000000000000001"
	UNIT = "00000000000000000000000000000000"

Analyzing hierarchy for module <ddc_chain> in library <work> with parameters.
	BASE = "00000000000000000000000001100000"
	DSPNO = "00000000000000000000000000000001"
	WIDTH = "00000000000000000000000000011000"
	cwidth = "00000000000000000000000000011001"
	zwidth = "00000000000000000000000000011000"

Analyzing hierarchy for module <vita_rx_chain> in library <work> with parameters.
	BASE = "00000000000000000000000001010000"
	DSP_NUMBER = "00000000000000000000000000000001"
	FIFOSIZE = "00000000000000000000000000001010"
	PROT_ENG_FLAGS = "00000000000000000000000000000001"
	UNIT = "00000000000000000000000000000010"

Analyzing hierarchy for module <ext_fifo> in library <work> with parameters.
	EXT_WIDTH = "00000000000000000000000000100100"
	FIFO_DEPTH = "00000000000000000000000000010010"
	INT_WIDTH = "00000000000000000000000000100100"
	RAM_DEPTH = "00000000000000000000000000010010"

Analyzing hierarchy for module <vita_tx_chain> in library <work> with parameters.
	BASE = "00000000000000000000000010010000"
	DO_FLOW_CONTROL = "00000000000000000000000000000001"
	DSP_NUMBER = "00000000000000000000000000000000"
	FIFOSIZE = "00000000000000000000000000001010"
	FIFOWIDTH = "00000000000000000000000001110101"
	MAXCHAN = "00000000000000000000000000000001"
	POST_ENGINE_FIFOSIZE = "00000000000000000000000000001010"
	PROT_ENG_FLAGS = "00000000000000000000000000000001"
	REPORT_ERROR = "00000000000000000000000000000001"
	USE_TRANS_HEADER = "00000000000000000000000000000001"

Analyzing hierarchy for module <duc_chain> in library <work> with parameters.
	BASE = "00000000000000000000000010100000"
	DSPNO = "00000000000000000000000000000000"
	WIDTH = "00000000000000000000000000011000"
	cwidth = "00000000000000000000000000011000"
	zwidth = "00000000000000000000000000011000"

Analyzing hierarchy for module <tx_frontend> in library <work> with parameters.
	BASE = "00000000000000000000000010000000"
	IQCOMP_EN = "00000000000000000000000000000001"
	WIDTH_OUT = "00000000000000000000000000010000"

Analyzing hierarchy for module <serdes> in library <work> with parameters.
	RXFIFOSIZE = "00000000000000000000000000001001"
	TXFIFOSIZE = "00000000000000000000000000001001"

Analyzing hierarchy for module <time_64bit> in library <work> with parameters.
	BASE = "00000000000000000000000000001010"
	MIMO_SYNC = "00000000000000000000000000000101"
	NEXT_TICKS_HI = "00000000000000000000000000000000"
	NEXT_TICKS_LO = "00000000000000000000000000000001"
	PPS_IMM = "00000000000000000000000000000011"
	PPS_POLSRC = "00000000000000000000000000000010"

Analyzing hierarchy for entity <zpu_system> in library <work> (architecture <behave>) with generics.
	simulate = false

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000010000"
	width = "00000000000000000000000000000001"

Analyzing hierarchy for module <valve36> in library <work>.

Analyzing hierarchy for module <crossbar36> in library <work>.

Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <fifo36_mux> in library <work> with parameters.
	MUX_DATA0 = "00000000000000000000000000000001"
	MUX_DATA1 = "00000000000000000000000000000011"
	MUX_IDLE0 = "00000000000000000000000000000000"
	MUX_IDLE1 = "00000000000000000000000000000010"
	prio = "00000000000000000000000000000000"

Analyzing hierarchy for module <fifo36_mux> in library <work> with parameters.
	MUX_DATA0 = "00000000000000000000000000000001"
	MUX_DATA1 = "00000000000000000000000000000011"
	MUX_IDLE0 = "00000000000000000000000000000000"
	MUX_IDLE1 = "00000000000000000000000000000010"
	prio = "00000000000000000000000000000001"

Analyzing hierarchy for module <buffer_int2> in library <work> with parameters.
	BASE = "00000000000000000000000000010011"
	BUF_SIZE = "00000000000000000000000000001001"
	DONE = "101"
	ERROR = "100"
	IDLE = "000"
	PRE_READ = "001"
	READING = "010"
	WRITING = "011"

Analyzing hierarchy for module <packet_dispatcher36_x4> in library <work> with parameters.
	BASE = "00000000000000000000000000010001"
	PD_DEST_BOF = "00000000000000000000000000000011"
	PD_DEST_CPU = "00000000000000000000000000000010"
	PD_DEST_CTL = "00000000000000000000000000000100"
	PD_DEST_DSP = "00000000000000000000000000000000"
	PD_DEST_EXT = "00000000000000000000000000000001"
	PD_DREGS_DSP_OFFSET = "00000000000000000000000000001011"
	PD_MAX_NUM_DREGS = "00000000000000000000000000001101"
	PD_STATE_READ_COM = "00000000000000000000000000000001"
	PD_STATE_READ_COM_PRE = "00000000000000000000000000000000"
	PD_STATE_WRITE_LIVE = "00000000000000000000000000000011"
	PD_STATE_WRITE_REGS = "00000000000000000000000000000010"

Analyzing hierarchy for module <fifo_cascade> in library <work> with parameters.
	SIZE = "00000000000000000000000000001001"
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <prot_eng_tx> in library <work> with parameters.
	BASE = "00000000000000000000000011000000"

Analyzing hierarchy for module <fifo36_mux> in library <work> with parameters.
	MUX_DATA0 = "00000000000000000000000000000001"
	MUX_DATA1 = "00000000000000000000000000000011"
	MUX_IDLE0 = "00000000000000000000000000000000"
	MUX_IDLE1 = "00000000000000000000000000000010"
	prio = "00000000000000000000000000000000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000010100"
	width = "00000000000000000000000000010000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000010101"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000010110"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <i2c_master_byte_ctrl> in library <work> with parameters.
	ST_ACK = "01000"
	ST_IDLE = "00000"
	ST_READ = "00010"
	ST_START = "00001"
	ST_STOP = "10000"
	ST_WRITE = "00100"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010111000"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010111001"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010111010"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010111011"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010111100"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <reset_sync> in library <work>.

Analyzing hierarchy for module <simple_gemac> in library <work> with parameters.
	SGE_IFG = "00001100"

Analyzing hierarchy for module <simple_gemac_wb> in library <work>.

Analyzing hierarchy for module <rxmac_to_ll8> in library <work> with parameters.
	XFER_ACTIVE = "00000000000000000000000000000001"
	XFER_ERROR = "00000000000000000000000000000010"
	XFER_ERROR2 = "00000000000000000000000000000011"
	XFER_IDLE = "00000000000000000000000000000000"
	XFER_OVERRUN = "00000000000000000000000000000100"
	XFER_OVERRUN2 = "00000000000000000000000000000101"

Analyzing hierarchy for module <ll8_to_fifo19> in library <work> with parameters.
	XFER_EMPTY = "00000000000000000000000000000000"
	XFER_HALF = "00000000000000000000000000000001"
	XFER_HALF_WRITE = "00000000000000000000000000000011"

Analyzing hierarchy for module <fifo19_rxrealign> in library <work> with parameters.
	RXRE_DUMMY = "00000000000000000000000000000000"
	RXRE_PKT = "00000000000000000000000000000001"

Analyzing hierarchy for module <fifo19_to_fifo36> in library <work> with parameters.
	LE = "00000000000000000000000000000000"

Analyzing hierarchy for module <fifo_2clock_cascade> in library <work> with parameters.
	SIZE = "00000000000000000000000000001011"
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <fifo_2clock_cascade> in library <work> with parameters.
	SIZE = "00000000000000000000000000001001"
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <ethtx_realign> in library <work> with parameters.
	RE_DONE = "00000000000000000000000000000010"
	RE_HELD = "00000000000000000000000000000001"
	RE_IDLE = "00000000000000000000000000000000"

Analyzing hierarchy for module <fifo36_to_ll8> in library <work>.

Analyzing hierarchy for module <ll8_to_txmac> in library <work> with parameters.
	XFER_ACTIVE = "00000000000000000000000000000001"
	XFER_DROP = "00000000000000000000000000000100"
	XFER_IDLE = "00000000000000000000000000000000"
	XFER_UNDERRUN = "00000000000000000000000000000011"
	XFER_WAIT1 = "00000000000000000000000000000010"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000001000"
	width = "00000000000000000000000000001000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000001001"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <shortfifo> in library <work> with parameters.
	WIDTH = "00000000000000000000000010000001"

Analyzing hierarchy for module <shortfifo> in library <work> with parameters.
	WIDTH = "00000000000000000000000001000000"

Analyzing hierarchy for module <time_compare> in library <work>.

Analyzing hierarchy for module <priority_enc> in library <work>.

Analyzing hierarchy for module <simple_uart_tx> in library <work> with parameters.
	DEPTH = "00000000000000000000000000000011"

Analyzing hierarchy for module <simple_uart_rx> in library <work> with parameters.
	DEPTH = "00000000000000000000000000000011"

Analyzing hierarchy for module <spi_clgen> in library <work>.

Analyzing hierarchy for module <spi_shift> in library <work>.

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000011000"
	width = "00000000000000000000000000000001"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000011001"
	width = "00000000000000000000000000010010"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000011010"
	width = "00000000000000000000000000010010"

Analyzing hierarchy for module <rx_dcoffset> in library <work> with parameters.
	ADDR = "00000000000000000000000000011011"
	WIDTH = "00000000000000000000000000010010"
	alpha_shift = "00000000000000000000000000010100"
	int_width = "00000000000000000000000000100110"

Analyzing hierarchy for module <rx_dcoffset> in library <work> with parameters.
	ADDR = "00000000000000000000000000011100"
	WIDTH = "00000000000000000000000000010010"
	alpha_shift = "00000000000000000000000000010100"
	int_width = "00000000000000000000000000100110"

Analyzing hierarchy for module <add2_and_clip_reg> in library <work> with parameters.
	WIDTH = "00000000000000000000000000011000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000110000"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000110001"
	width = "00000000000000000000000000010010"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000110010"
	width = "00000000000000000000000000001010"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000110011"
	width = "00000000000000000000000000000010"

Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
	bits_in = "00000000000000000000000000011000"
	bits_out = "00000000000000000000000000011001"

Analyzing hierarchy for module <cordic_z24> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011001"
	c00 = "01000000000000000000000"
	c01 = "00100101110010000000101"
	c02 = "00010011111101100111000"
	c03 = "00001010001000100010010"
	c04 = "00000101000101100001101"
	c05 = "00000010100010111011000"
	c06 = "00000001010001011110110"
	c07 = "00000000101000101111100"
	c08 = "00000000010100010111110"
	c09 = "00000000001010001011111"
	c10 = "00000000000101000110000"
	c11 = "00000000000010100011000"
	c12 = "00000000000001010001100"
	c13 = "00000000000000101000110"
	c14 = "00000000000000010100011"
	c15 = "00000000000000001010001"
	c16 = "00000000000000000101001"
	c17 = "00000000000000000010100"
	c18 = "00000000000000000001010"
	c19 = "00000000000000000000101"
	c20 = "00000000000000000000011"
	c21 = "00000000000000000000001"
	c22 = "00000000000000000000001"
	c23 = "00000000000000000000000"
	stages = "00000000000000000000000000010011"
	zwidth = "00000000000000000000000000011000"

Analyzing hierarchy for module <clip_reg> in library <work> with parameters.
	STROBED = "0"
	bits_in = "00000000000000000000000000011001"
	bits_out = "00000000000000000000000000011000"

Analyzing hierarchy for module <cic_strober> in library <work> with parameters.
	WIDTH = "00000000000000000000000000001000"

Analyzing hierarchy for module <cic_decim> in library <work> with parameters.
	N = "00000000000000000000000000000100"
	bw = "00000000000000000000000000011000"
	log2_of_max_rate = "00000000000000000000000000000111"
	maxbitgain = "00000000000000000000000000011100"

Analyzing hierarchy for module <small_hb_dec> in library <work> with parameters.
	ACCWIDTH = "00000000000000000000000000011110"
	INTWIDTH = "00000000000000000000000000010001"
	WIDTH = "00000000000000000000000000011000"

Analyzing hierarchy for module <hb_dec> in library <work> with parameters.
	ACCWIDTH = "00000000000000000000000000011011"
	INTWIDTH = "00000000000000000000000000010001"
	SHIFT_FACTOR = "00000000000000000000000000000110"
	WIDTH = "00000000000000000000000000011000"

Analyzing hierarchy for module <round_sd> in library <work> with parameters.
	DISABLE_SD = "00000000000000000000000000000000"
	ERR_WIDTH = "00000000000000000000000000001001"
	WIDTH_IN = "00000000000000000000000000011000"
	WIDTH_OUT = "00000000000000000000000000010000"

Analyzing hierarchy for module <dsp_rx_glue> in library <work> with parameters.
	DSPNO = "00000000000000000000000000000000"
	WIDTH = "00000000000000000000000000011000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000101000"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <vita_rx_control> in library <work> with parameters.
	BASE = "00000000000000000000000000100000"
	IBS_BROKENCHAIN = "00000000000000000000000000000101"
	IBS_IDLE = "00000000000000000000000000000000"
	IBS_LATECMD = "00000000000000000000000000000110"
	IBS_OVERRUN = "00000000000000000000000000000100"
	IBS_RUNNING = "00000000000000000000000000000010"
	IBS_WAITING = "00000000000000000000000000000001"
	IBS_ZEROLEN = "00000000000000000000000000000111"
	WIDTH = "00000000000000000000000000100000"

Analyzing hierarchy for module <vita_rx_framer> in library <work> with parameters.
	BASE = "00000000000000000000000000100000"
	MAXCHAN = "00000000000000000000000000000001"
	SAMP_WIDTH = "00000000000000000000000001100101"
	VITA_ERR_HEADER = "00000000000000000000000000000111"
	VITA_ERR_PAYLOAD = "00000000000000000000000000001011"
	VITA_ERR_STREAMID = "00000000000000000000000000001000"
	VITA_ERR_TICS = "00000000000000000000000000001001"
	VITA_ERR_TICS2 = "00000000000000000000000000001010"
	VITA_ERR_TRAILER = "00000000000000000000000000001100"
	VITA_HEADER = "00000000000000000000000000000001"
	VITA_IDLE = "00000000000000000000000000000000"
	VITA_PAYLOAD = "00000000000000000000000000000101"
	VITA_STREAMID = "00000000000000000000000000000010"
	VITA_TICS = "00000000000000000000000000000011"
	VITA_TICS2 = "00000000000000000000000000000100"
	VITA_TRAILER = "00000000000000000000000000000110"

Analyzing hierarchy for module <double_buffer> in library <work> with parameters.
	BUF_SIZE = "00000000000000000000000000001010"
	IDLE = "00000000000000000000000000000000"
	PRE_READ = "00000000000000000000000000000001"
	READING = "00000000000000000000000000000010"

Analyzing hierarchy for module <vita_rx_engine_glue> in library <work> with parameters.
	BUF_SIZE = "00000000000000000000000000001010"
	DSPNO = "00000000000000000000000000000000"
	MAIN_SETTINGS_BASE = "00000000000000000000000000100011"

Analyzing hierarchy for module <add_routing_header> in library <work> with parameters.
	PORT_SEL = "00000000000000000000000000000000"
	PROT_ENG_FLAGS = "00000000000000000000000000000001"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000001100000"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000001100001"
	width = "00000000000000000000000000010010"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000001100010"
	width = "00000000000000000000000000001010"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000001100011"
	width = "00000000000000000000000000000010"

Analyzing hierarchy for module <dsp_rx_glue> in library <work> with parameters.
	DSPNO = "00000000000000000000000000000001"
	WIDTH = "00000000000000000000000000011000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000001011000"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <vita_rx_control> in library <work> with parameters.
	BASE = "00000000000000000000000001010000"
	IBS_BROKENCHAIN = "00000000000000000000000000000101"
	IBS_IDLE = "00000000000000000000000000000000"
	IBS_LATECMD = "00000000000000000000000000000110"
	IBS_OVERRUN = "00000000000000000000000000000100"
	IBS_RUNNING = "00000000000000000000000000000010"
	IBS_WAITING = "00000000000000000000000000000001"
	IBS_ZEROLEN = "00000000000000000000000000000111"
	WIDTH = "00000000000000000000000000100000"

Analyzing hierarchy for module <vita_rx_framer> in library <work> with parameters.
	BASE = "00000000000000000000000001010000"
	MAXCHAN = "00000000000000000000000000000001"
	SAMP_WIDTH = "00000000000000000000000001100101"
	VITA_ERR_HEADER = "00000000000000000000000000000111"
	VITA_ERR_PAYLOAD = "00000000000000000000000000001011"
	VITA_ERR_STREAMID = "00000000000000000000000000001000"
	VITA_ERR_TICS = "00000000000000000000000000001001"
	VITA_ERR_TICS2 = "00000000000000000000000000001010"
	VITA_ERR_TRAILER = "00000000000000000000000000001100"
	VITA_HEADER = "00000000000000000000000000000001"
	VITA_IDLE = "00000000000000000000000000000000"
	VITA_PAYLOAD = "00000000000000000000000000000101"
	VITA_STREAMID = "00000000000000000000000000000010"
	VITA_TICS = "00000000000000000000000000000011"
	VITA_TICS2 = "00000000000000000000000000000100"
	VITA_TRAILER = "00000000000000000000000000000110"

Analyzing hierarchy for module <vita_rx_engine_glue> in library <work> with parameters.
	BUF_SIZE = "00000000000000000000000000001010"
	DSPNO = "00000000000000000000000000000001"
	MAIN_SETTINGS_BASE = "00000000000000000000000001010011"

Analyzing hierarchy for module <add_routing_header> in library <work> with parameters.
	PORT_SEL = "00000000000000000000000000000010"
	PROT_ENG_FLAGS = "00000000000000000000000000000001"

Analyzing hierarchy for module <nobl_fifo> in library <work> with parameters.
	FIFO_DEPTH = "00000000000000000000000000010010"
	RAM_DEPTH = "00000000000000000000000000010010"
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <refill_randomizer> in library <work> with parameters.
	BITS = "00000000000000000000000000000111"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010010000"
	width = "00000000000000000000000000000001"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010010010"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <vita_tx_deframer> in library <work> with parameters.
	BASE = "00000000000000000000000010010000"
	FIFOWIDTH = "00000000000000000000000001110101"
	MAXCHAN = "00000000000000000000000000000001"
	USE_TRANS_HEADER = "00000000000000000000000000000001"
	VITA_CLASSID = "00000000000000000000000000000011"
	VITA_CLASSID2 = "00000000000000000000000000000100"
	VITA_DUMP = "00000000000000000000000000001011"
	VITA_HEADER = "00000000000000000000000000000001"
	VITA_PAYLOAD = "00000000000000000000000000001000"
	VITA_SECS = "00000000000000000000000000000101"
	VITA_STREAMID = "00000000000000000000000000000010"
	VITA_TICS = "00000000000000000000000000000110"
	VITA_TICS2 = "00000000000000000000000000000111"
	VITA_TRAILER = "00000000000000000000000000001010"
	VITA_TRANS_HEADER = "00000000000000000000000000000000"

Analyzing hierarchy for module <vita_tx_control> in library <work> with parameters.
	BASE = "00000000000000000000000010010000"
	IBS_CONT_BURST = "00000000000000000000000000000010"
	IBS_ERROR = "00000000000000000000000000000011"
	IBS_ERROR_DONE = "00000000000000000000000000000100"
	IBS_ERROR_WAIT = "00000000000000000000000000000101"
	IBS_IDLE = "00000000000000000000000000000000"
	IBS_RUN = "00000000000000000000000000000001"
	MAX_IDLE = "00000000000011110100001001000000"
	WIDTH = "00000000000000000000000000100000"

Analyzing hierarchy for module <gen_context_pkt> in library <work> with parameters.
	CTXT_DONE = "00000000000000000000000000001000"
	CTXT_FLOWCTRL = "00000000000000000000000000000111"
	CTXT_HEADER = "00000000000000000000000000000010"
	CTXT_IDLE = "00000000000000000000000000000000"
	CTXT_MESSAGE = "00000000000000000000000000000110"
	CTXT_PROT_ENG = "00000000000000000000000000000001"
	CTXT_STREAMID = "00000000000000000000000000000011"
	CTXT_TICS = "00000000000000000000000000000100"
	CTXT_TICS2 = "00000000000000000000000000000101"
	DSP_NUMBER = "00000000000000000000000000000000"
	PROT_ENG_FLAGS = "00000000000000000000000000000001"

Analyzing hierarchy for module <trigger_context_pkt> in library <work> with parameters.
	BASE = "00000000000000000000000010010000"

Analyzing hierarchy for module <vita_tx_engine_glue> in library <work> with parameters.
	BUF_SIZE = "00000000000000000000000000001010"
	DSPNO = "00000000000000000000000000000000"
	HEADER_OFFSET = "00000000000000000000000000000001"
	MAIN_SETTINGS_BASE = "00000000000000000000000010010001"

Analyzing hierarchy for module <fifo_cascade> in library <work> with parameters.
	SIZE = "00000000000000000000000000001010"
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010100000"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010100001"
	width = "00000000000000000000000000010010"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010100010"
	width = "00000000000000000000000000001010"

Analyzing hierarchy for module <cic_strober> in library <work> with parameters.
	WIDTH = "00000000000000000000000000001000"

Analyzing hierarchy for module <cic_strober> in library <work> with parameters.
	WIDTH = "00000000000000000000000000000010"

Analyzing hierarchy for module <hb_interp> in library <work> with parameters.
	ACCWIDTH = "00000000000000000000000000011000"
	CWIDTH = "00000000000000000000000000010010"
	IWIDTH = "00000000000000000000000000010010"
	MWIDTH = "00000000000000000000000000010110"
	OWIDTH = "00000000000000000000000000010010"

Analyzing hierarchy for module <small_hb_int> in library <work> with parameters.
	MWIDTH = "00000000000000000000000000100100"
	WIDTH = "00000000000000000000000000010010"

Analyzing hierarchy for module <cic_interp> in library <work> with parameters.
	N = "00000000000000000000000000000100"
	bw = "00000000000000000000000000010010"
	log2_of_max_rate = "00000000000000000000000000000111"
	maxbitgain = "00000000000000000000000000010101"

Analyzing hierarchy for module <cordic_z24> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011000"
	c00 = "01000000000000000000000"
	c01 = "00100101110010000000101"
	c02 = "00010011111101100111000"
	c03 = "00001010001000100010010"
	c04 = "00000101000101100001101"
	c05 = "00000010100010111011000"
	c06 = "00000001010001011110110"
	c07 = "00000000101000101111100"
	c08 = "00000000010100010111110"
	c09 = "00000000001010001011111"
	c10 = "00000000000101000110000"
	c11 = "00000000000010100011000"
	c12 = "00000000000001010001100"
	c13 = "00000000000000101000110"
	c14 = "00000000000000010100011"
	c15 = "00000000000000001010001"
	c16 = "00000000000000000101001"
	c17 = "00000000000000000010100"
	c18 = "00000000000000000001010"
	c19 = "00000000000000000000101"
	c20 = "00000000000000000000011"
	c21 = "00000000000000000000001"
	c22 = "00000000000000000000001"
	c23 = "00000000000000000000000"
	stages = "00000000000000000000000000010011"
	zwidth = "00000000000000000000000000011000"

Analyzing hierarchy for module <dsp_tx_glue> in library <work> with parameters.
	DSPNO = "00000000000000000000000000000000"
	WIDTH = "00000000000000000000000000011000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010000000"
	width = "00000000000000000000000000011000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010000001"
	width = "00000000000000000000000000011000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010000010"
	width = "00000000000000000000000000010010"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010000011"
	width = "00000000000000000000000000010010"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010000100"
	width = "00000000000000000000000000001000"

Analyzing hierarchy for module <serdes_tx> in library <work> with parameters.
	DONE = "011"
	D_56 = "11000101"
	FIFOSIZE = "00000000000000000000000000001001"
	IDLE = "000"
	K_COMMA = "10111100"
	K_ERROR = "00000000"
	K_IDLE = "00111100"
	K_LOS = "11111111"
	K_PKT_END = "10011100"
	K_PKT_START = "11011100"
	K_XOFF = "01111100"
	K_XON = "01011100"
	RUN1 = "001"
	RUN2 = "010"
	SENDCRC = "100"
	WAIT = "101"

Analyzing hierarchy for module <serdes_rx> in library <work> with parameters.
	CRC_CHECK = "101"
	DONE = "111"
	D_56 = "11000101"
	ERROR = "110"
	FIFOSIZE = "00000000000000000000000000001001"
	FIRSTLINE1 = "001"
	FIRSTLINE2 = "010"
	IDLE = "000"
	K_COMMA = "10111100"
	K_ERROR = "00000000"
	K_IDLE = "00111100"
	K_LOS = "11111111"
	K_PKT_END = "10011100"
	K_PKT_START = "11011100"
	K_XOFF = "01111100"
	K_XON = "01011100"
	PKT1 = "011"
	PKT2 = "100"

Analyzing hierarchy for module <serdes_fc_tx> in library <work>.

Analyzing hierarchy for module <serdes_fc_rx> in library <work> with parameters.
	HWMARK = "00000000000000000000000010000000"
	LWMARK = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000001011"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000001010"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000001100"
	width = "00000000000000000000000000000010"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000001101"
	width = "00000000000000000000000000000001"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000001111"
	width = "00000000000000000000000000001001"

Analyzing hierarchy for module <time_sender> in library <work> with parameters.
	COMMA = "10111100"
	HEAD = "00111100"
	SEND_HEAD = "00000000000000000000000000000001"
	SEND_IDLE = "00000000000000000000000000000000"
	SEND_T0 = "00000000000000000000000000000010"
	SEND_T1 = "00000000000000000000000000000011"
	SEND_T2 = "00000000000000000000000000000100"
	SEND_T3 = "00000000000000000000000000000101"
	SEND_T4 = "00000000000000000000000000000110"
	SEND_T5 = "00000000000000000000000000000111"
	SEND_T6 = "00000000000000000000000000001000"
	SEND_T7 = "00000000000000000000000000001001"
	SEND_TAIL = "00000000000000000000000000001010"
	TAIL = "11110111"

Analyzing hierarchy for module <time_receiver> in library <work> with parameters.
	COMMA_0 = "1010000011"
	COMMA_1 = "0101111100"
	HEAD = "100111100"
	STATE_IDLE = "00000000000000000000000000000000"
	STATE_T0 = "00000000000000000000000000000001"
	STATE_T1 = "00000000000000000000000000000010"
	STATE_T2 = "00000000000000000000000000000011"
	STATE_T3 = "00000000000000000000000000000100"
	STATE_T4 = "00000000000000000000000000000101"
	STATE_T5 = "00000000000000000000000000000110"
	STATE_T6 = "00000000000000000000000000000111"
	STATE_T7 = "00000000000000000000000000001000"
	STATE_TAIL = "00000000000000000000000000001001"
	TAIL = "111110111"

Analyzing hierarchy for entity <zpu_core> in library <work> (architecture <behave>).

Analyzing hierarchy for entity <zpu_wb_bridge> in library <work> (architecture <behave>).

Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <ram_2port> in library <work> with parameters.
	AWIDTH = "00000000000000000000000000001001"
	DWIDTH = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000010011"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000010001"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000010010"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <splitter36> in library <work> with parameters.
	STATE_COPY_BOTH = "00000000000000000000000000000000"
	STATE_COPY_ONE = "00000000000000000000000000000010"
	STATE_COPY_ZERO = "00000000000000000000000000000001"

Analyzing hierarchy for module <fifo36_mux> in library <work> with parameters.
	MUX_DATA0 = "00000000000000000000000000000001"
	MUX_DATA1 = "00000000000000000000000000000011"
	MUX_IDLE0 = "00000000000000000000000000000000"
	MUX_IDLE1 = "00000000000000000000000000000010"
	prio = "00000000000000000000000000000000"

Analyzing hierarchy for module <fifo36_mux> in library <work> with parameters.
	MUX_DATA0 = "00000000000000000000000000000001"
	MUX_DATA1 = "00000000000000000000000000000011"
	MUX_IDLE0 = "00000000000000000000000000000000"
	MUX_IDLE1 = "00000000000000000000000000000010"
	prio = "00000000000000000000000000000000"

Analyzing hierarchy for module <fifo_long> in library <work> with parameters.
	EMPTY = "00000000000000000000000000000000"
	NUMLINES = "00000000000000000000000111111110"
	PRE_READ = "00000000000000000000000000000001"
	READING = "00000000000000000000000000000010"
	SIZE = "00000000000000000000000000001001"
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <add_onescomp> in library <work> with parameters.
	WIDTH = "00000000000000000000000000010000"

Analyzing hierarchy for module <i2c_master_bit_ctrl> in library <work> with parameters.
	idle = "00000000000000000"
	rd_a = "00000001000000000"
	rd_b = "00000010000000000"
	rd_c = "00000100000000000"
	rd_d = "00001000000000000"
	start_a = "00000000000000001"
	start_b = "00000000000000010"
	start_c = "00000000000000100"
	start_d = "00000000000001000"
	start_e = "00000000000010000"
	stop_a = "00000000000100000"
	stop_b = "00000000001000000"
	stop_c = "00000000010000000"
	stop_d = "00000000100000000"
	wr_a = "00010000000000000"
	wr_b = "00100000000000000"
	wr_c = "01000000000000000"
	wr_d = "10000000000000000"

Analyzing hierarchy for module <reset_sync> in library <work>.

Analyzing hierarchy for module <simple_gemac_tx> in library <work> with parameters.
	MAX_FRAME_LEN = "00000000000000000010000000000000"
	MIN_FRAME_LEN = "00000000000000000000000001000100"
	SGE_FLOW_CTRL_ADDR = "000000011000000011000010000000000000000000000001"
	TX_CRC_0 = "00000000000000000000000000010000"
	TX_CRC_1 = "00000000000000000000000000010001"
	TX_CRC_2 = "00000000000000000000000000010010"
	TX_CRC_3 = "00000000000000000000000000010011"
	TX_ERROR = "00000000000000000000000000100000"
	TX_FIRSTBYTE = "00000000000000000000000000001001"
	TX_IDLE = "00000000000000000000000000000000"
	TX_IN_FRAME = "00000000000000000000000000001010"
	TX_IN_FRAME_2 = "00000000000000000000000000001011"
	TX_PAD = "00000000000000000000000000001100"
	TX_PAUSE = "00000000000000000000000000110111"
	TX_PAUSE_END = "00000000000000000000000001010000"
	TX_PAUSE_FIRST = "00000000000000000000000000111111"
	TX_PAUSE_SOF = "00000000000000000000000000111110"
	TX_PREAMBLE = "00000000000000000000000000000001"
	TX_SOF_DEL = "00000000000000000000000000001000"

Analyzing hierarchy for module <simple_gemac_rx> in library <work> with parameters.
	DELAY = "00000000000000000000000000000110"
	MIN_PAUSE_LEN = "00000000000000000000000001000111"
	RX_DO_PAUSE = "00000000000000000000000000000100"
	RX_DROP = "00000000000000000000000000000110"
	RX_ERROR = "00000000000000000000000000000101"
	RX_FRAME = "00000000000000000000000000000010"
	RX_GOODFRAME = "00000000000000000000000000000011"
	RX_IDLE = "00000000000000000000000000000000"
	RX_PAUSE = "00000000000000000000000000010000"
	RX_PAUSE_CHK00 = "00000000000000000000000000010111"
	RX_PAUSE_CHK01 = "00000000000000000000000000011000"
	RX_PAUSE_CHK08 = "00000000000000000000000000010110"
	RX_PAUSE_CHK88 = "00000000000000000000000000010101"
	RX_PAUSE_STORE_LSB = "00000000000000000000000000011010"
	RX_PAUSE_STORE_MSB = "00000000000000000000000000011001"
	RX_PAUSE_WAIT_CRC = "00000000000000000000000000011011"
	RX_PREAMBLE = "00000000000000000000000000000001"

Analyzing hierarchy for module <flow_ctrl_tx> in library <work>.

Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
	ADDR = "00000000000000000000000000000000"
	DEFAULT = "0111011"
	WIDTH = "00000000000000000000000000000111"

Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
	ADDR = "00000000000000000000000000000001"
	DEFAULT = "00000000000000000000000000000000"
	WIDTH = "00000000000000000000000000010000"

Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
	ADDR = "00000000000000000000000000000010"
	DEFAULT = "00000000000000000000000000000000"
	WIDTH = "00000000000000000000000000100000"

Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
	ADDR = "00000000000000000000000000000011"
	DEFAULT = "00000000000000000000000000000000"
	WIDTH = "00000000000000000000000000010000"

Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
	ADDR = "00000000000000000000000000000100"
	DEFAULT = "00000000000000000000000000000000"
	WIDTH = "00000000000000000000000000100000"

Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
	ADDR = "00000000000000000000000000000101"
	DEFAULT = "00000000000000000000000000000000"
	WIDTH = "00000000000000000000000000001001"

Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
	ADDR = "00000000000000000000000000000110"
	DEFAULT = "00000000000000000000000000000000"
	WIDTH = "00000000000000000000000000001101"

Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
	ADDR = "00000000000000000000000000000111"
	DEFAULT = "00000000000000000000000000000000"
	WIDTH = "00000000000000000000000000010000"

Analyzing hierarchy for module <eth_miim> in library <work>.

Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
	ADDR = "00000000000000000000000000001011"
	DEFAULT = "00000000000000000000000000000000"
	WIDTH = "00000000000000000000000000010000"

Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
	ADDR = "00000000000000000000000000001100"
	DEFAULT = "00000000000000000000000000000000"
	WIDTH = "00000000000000000000000000010000"

Analyzing hierarchy for module <ll8_shortfifo> in library <work>.

Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
	WIDTH = "00000000000000000000000000010011"

Analyzing hierarchy for module <fifo_2clock> in library <work> with parameters.
	SIZE = "00000000000000000000000000001011"
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <fifo_2clock> in library <work> with parameters.
	SIZE = "00000000000000000000000000001001"
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <medfifo> in library <work> with parameters.
	DEPTH = "00000000000000000000000000000011"
	NUM_FIFOS = "00000000000000000000000000001000"
	WIDTH = "00000000000000000000000000001000"

Analyzing hierarchy for module <round_sd> in library <work> with parameters.
	DISABLE_SD = "00000000000000000000000000000000"
	ERR_WIDTH = "00000000000000000000000000010101"
	WIDTH_IN = "00000000000000000000000000100110"
	WIDTH_OUT = "00000000000000000000000000010010"

Analyzing hierarchy for module <add2_and_clip_reg> in library <work> with parameters.
	WIDTH = "00000000000000000000000000010010"

Analyzing hierarchy for module <add2_and_clip> in library <work> with parameters.
	WIDTH = "00000000000000000000000000011000"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000000000"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000000001"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000000010"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000000011"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000000100"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000000101"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000000110"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000000111"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000001000"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000001001"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000001010"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000001011"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000001100"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000001101"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000001110"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000001111"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000010000"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000010001"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000010010"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011011"
	shift = "00000000000000000000000000010011"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <clip> in library <work> with parameters.
	bits_in = "00000000000000000000000000011001"
	bits_out = "00000000000000000000000000011000"

Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
	bits_in = "00000000000000000000000000011000"
	bits_out = "00000000000000000000000000110100"

Analyzing hierarchy for module <cic_dec_shifter> in library <work> with parameters.
	bw = "00000000000000000000000000011000"
	maxbitgain = "00000000000000000000000000011100"

Analyzing hierarchy for module <round_sd> in library <work> with parameters.
	DISABLE_SD = "00000000000000000000000000000000"
	ERR_WIDTH = "00000000000000000000000000001000"
	WIDTH_IN = "00000000000000000000000000011000"
	WIDTH_OUT = "00000000000000000000000000010001"

Analyzing hierarchy for module <round_sd> in library <work> with parameters.
	DISABLE_SD = "00000000000000000000000000000000"
	ERR_WIDTH = "00000000000000000000000000000110"
	WIDTH_IN = "00000000000000000000000000011110"
	WIDTH_OUT = "00000000000000000000000000011001"

Analyzing hierarchy for module <srl> in library <work> with parameters.
	WIDTH = "00000000000000000000000000010001"

Analyzing hierarchy for module <acc> in library <work> with parameters.
	IWIDTH = "00000000000000000000000000011001"
	OWIDTH = "00000000000000000000000000011011"

Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
	bits_in = "00000000000000000000000000010001"
	bits_out = "00000000000000000000000000010101"

Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
	bits_in = "00000000000000000000000000001001"
	bits_out = "00000000000000000000000000011000"

Analyzing hierarchy for module <add2_and_clip_reg> in library <work> with parameters.
	WIDTH = "00000000000000000000000000011000"

Analyzing hierarchy for module <round> in library <work> with parameters.
	bits_in = "00000000000000000000000000011000"
	bits_out = "00000000000000000000000000010000"
	round_to_nearest = "00000000000000000000000000000001"
	round_to_zero = "00000000000000000000000000000000"
	trunc = "00000000000000000000000000000000"

Analyzing hierarchy for module <custom_dsp_rx> in library <work> with parameters.
	WIDTH = "00000000000000000000000000011000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000100000"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000100001"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000100010"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
	WIDTH = "00000000000000000000000001100000"

Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
	WIDTH = "00000000000000000000000001100101"

Analyzing hierarchy for module <time_compare> in library <work>.

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000100100"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000100101"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000100110"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000100111"
	width = "00000000000000000000000000010000"

Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
	WIDTH = "00000000000000000000000000100010"

Analyzing hierarchy for module <dbsm> in library <work> with parameters.
	BUFF_ACCESSIBLE = "00000000000000000000000000000001"
	BUFF_ERROR = "00000000000000000000000000000011"
	BUFF_READABLE = "00000000000000000000000000000010"
	BUFF_WRITABLE = "00000000000000000000000000000000"
	PORT_USE_0 = "00000000000000000000000000000001"
	PORT_USE_1 = "00000000000000000000000000000011"
	PORT_WAIT_0 = "00000000000000000000000000000000"
	PORT_WAIT_1 = "00000000000000000000000000000010"

Analyzing hierarchy for module <ram_2port> in library <work> with parameters.
	AWIDTH = "00000000000000000000000000001010"
	DWIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <dspengine_16to8> in library <work> with parameters.
	BASE = "00000000000000000000000000100011"
	BUF_SIZE = "00000000000000000000000000001010"
	DSP_CONVERT = "00000000000000000000000000000010"
	DSP_CONVERT_DRAIN_PIPE = "00000000000000000000000000000011"
	DSP_DONE = "00000000000000000000000000000111"
	DSP_IDLE = "00000000000000000000000000000000"
	DSP_PARSE_HEADER = "00000000000000000000000000000001"
	DSP_READ_TRAILER = "00000000000000000000000000000100"
	DSP_WRITE_HEADER = "00000000000000000000000000000110"
	DSP_WRITE_TRAILER = "00000000000000000000000000000101"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000001010000"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000001010001"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000001010010"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000001010100"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000001010101"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000001010110"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000001010111"
	width = "00000000000000000000000000010000"

Analyzing hierarchy for module <dspengine_16to8> in library <work> with parameters.
	BASE = "00000000000000000000000001010011"
	BUF_SIZE = "00000000000000000000000000001010"
	DSP_CONVERT = "00000000000000000000000000000010"
	DSP_CONVERT_DRAIN_PIPE = "00000000000000000000000000000011"
	DSP_DONE = "00000000000000000000000000000111"
	DSP_IDLE = "00000000000000000000000000000000"
	DSP_PARSE_HEADER = "00000000000000000000000000000001"
	DSP_READ_TRAILER = "00000000000000000000000000000100"
	DSP_WRITE_HEADER = "00000000000000000000000000000110"
	DSP_WRITE_TRAILER = "00000000000000000000000000000101"

Analyzing hierarchy for module <nobl_if> in library <work> with parameters.
	DEPTH = "00000000000000000000000000010010"
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
	WIDTH = "00000000000000000000000001110101"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010010011"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010010100"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010010101"
	width = "00000000000000000000000000100000"

Analyzing hierarchy for module <dspengine_8to16> in library <work> with parameters.
	BASE = "00000000000000000000000010010001"
	BUF_SIZE = "00000000000000000000000000001010"
	DSP_DONE = "00000000000000000000000000001010"
	DSP_IDLE = "00000000000000000000000000000000"
	DSP_IDLE_RD = "00000000000000000000000000000001"
	DSP_PARSE_HEADER = "00000000000000000000000000000010"
	DSP_READ = "00000000000000000000000000000011"
	DSP_READ_TRAILER = "00000000000000000000000000000111"
	DSP_READ_WAIT = "00000000000000000000000000000100"
	DSP_WRITE_0 = "00000000000000000000000000000110"
	DSP_WRITE_1 = "00000000000000000000000000000101"
	DSP_WRITE_HEADER = "00000000000000000000000000001001"
	DSP_WRITE_TRAILER = "00000000000000000000000000001000"
	HEADER_OFFSET = "00000000000000000000000000000001"

Analyzing hierarchy for module <fifo_long> in library <work> with parameters.
	EMPTY = "00000000000000000000000000000000"
	NUMLINES = "00000000000000000000001111111110"
	PRE_READ = "00000000000000000000000000000001"
	READING = "00000000000000000000000000000010"
	SIZE = "00000000000000000000000000001010"
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <srl> in library <work> with parameters.
	WIDTH = "00000000000000000000000000010010"

Analyzing hierarchy for module <add2_reg> in library <work> with parameters.
	WIDTH = "00000000000000000000000000010010"

Analyzing hierarchy for module <add2_and_round_reg> in library <work> with parameters.
	WIDTH = "00000000000000000000000000010110"

Analyzing hierarchy for module <acc> in library <work> with parameters.
	IWIDTH = "00000000000000000000000000010110"
	OWIDTH = "00000000000000000000000000011000"

Analyzing hierarchy for module <clip> in library <work> with parameters.
	bits_in = "00000000000000000000000000011000"
	bits_out = "00000000000000000000000000010011"

Analyzing hierarchy for module <round> in library <work> with parameters.
	bits_in = "00000000000000000000000000010011"
	bits_out = "00000000000000000000000000010010"
	round_to_nearest = "00000000000000000000000000000001"
	round_to_zero = "00000000000000000000000000000000"
	trunc = "00000000000000000000000000000000"

Analyzing hierarchy for module <add2_and_round_reg> in library <work> with parameters.
	WIDTH = "00000000000000000000000000010010"

Analyzing hierarchy for module <acc> in library <work> with parameters.
	IWIDTH = "00000000000000000000000000100100"
	OWIDTH = "00000000000000000000000000100101"

Analyzing hierarchy for module <round_reg> in library <work> with parameters.
	bits_in = "00000000000000000000000000100101"
	bits_out = "00000000000000000000000000010101"

Analyzing hierarchy for module <clip_reg> in library <work> with parameters.
	STROBED = "0"
	bits_in = "00000000000000000000000000010101"
	bits_out = "00000000000000000000000000010010"

Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
	bits_in = "00000000000000000000000000010010"
	bits_out = "00000000000000000000000000100111"

Analyzing hierarchy for module <cic_int_shifter> in library <work> with parameters.
	bw = "00000000000000000000000000010010"
	maxbitgain = "00000000000000000000000000010101"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000000000"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000000001"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000000010"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000000011"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000000100"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000000101"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000000110"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000000111"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000001000"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000001001"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000001010"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000001011"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000001100"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000001101"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000001110"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000001111"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000010000"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000010001"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000010010"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
	bitwidth = "00000000000000000000000000011010"
	shift = "00000000000000000000000000010011"
	zwidth = "00000000000000000000000000010111"

Analyzing hierarchy for module <fifo_cascade> in library <work> with parameters.
	SIZE = "00000000000000000000000000001001"
	WIDTH = "00000000000000000000000000100010"

Analyzing hierarchy for module <CRC16_D16> in library <work>.

Analyzing hierarchy for module <oneshot_2clk> in library <work>.

Analyzing hierarchy for module <fifo_2clock_cascade> in library <work> with parameters.
	SIZE = "00000000000000000000000000001001"
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <encode_8b10b> in library <work>.

Analyzing hierarchy for module <decode_8b10b> in library <work>.

Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <ram_2port> in library <work> with parameters.
	AWIDTH = "00000000000000000000000000001001"
	DWIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <crc> in library <work>.

Analyzing hierarchy for module <delay_line> in library <work> with parameters.
	WIDTH = "00000000000000000000000000001010"

Analyzing hierarchy for module <address_filter> in library <work>.

Analyzing hierarchy for module <address_filter_promisc> in library <work>.

Analyzing hierarchy for module <eth_clockgen> in library <work>.

Analyzing hierarchy for module <eth_shiftreg> in library <work>.

Analyzing hierarchy for module <eth_outputcontrol> in library <work>.

Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
	WIDTH = "00000000000000000000000000001011"

Analyzing hierarchy for module <shortfifo> in library <work> with parameters.
	WIDTH = "00000000000000000000000000001000"

Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
	bits_in = "00000000000000000000000000010101"
	bits_out = "00000000000000000000000000100110"

Analyzing hierarchy for module <add2_and_clip_reg> in library <work> with parameters.
	WIDTH = "00000000000000000000000000100110"

Analyzing hierarchy for module <round> in library <work> with parameters.
	bits_in = "00000000000000000000000000100110"
	bits_out = "00000000000000000000000000010010"
	round_to_nearest = "00000000000000000000000000000001"
	round_to_zero = "00000000000000000000000000000000"
	trunc = "00000000000000000000000000000000"

Analyzing hierarchy for module <add2_and_clip> in library <work> with parameters.
	WIDTH = "00000000000000000000000000010010"

Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
	bits_in = "00000000000000000000000000001000"
	bits_out = "00000000000000000000000000011000"

Analyzing hierarchy for module <round> in library <work> with parameters.
	bits_in = "00000000000000000000000000011000"
	bits_out = "00000000000000000000000000010001"
	round_to_nearest = "00000000000000000000000000000001"
	round_to_zero = "00000000000000000000000000000000"
	trunc = "00000000000000000000000000000000"

Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
	bits_in = "00000000000000000000000000000110"
	bits_out = "00000000000000000000000000011110"

Analyzing hierarchy for module <add2_and_clip_reg> in library <work> with parameters.
	WIDTH = "00000000000000000000000000011110"

Analyzing hierarchy for module <round> in library <work> with parameters.
	bits_in = "00000000000000000000000000011110"
	bits_out = "00000000000000000000000000011001"
	round_to_nearest = "00000000000000000000000000000001"
	round_to_zero = "00000000000000000000000000000000"
	trunc = "00000000000000000000000000000000"

Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
	bits_in = "00000000000000000000000000011001"
	bits_out = "00000000000000000000000000011011"

Analyzing hierarchy for module <add2_and_clip> in library <work> with parameters.
	WIDTH = "00000000000000000000000000011000"

Analyzing hierarchy for module <buff_sm> in library <work> with parameters.
	BUFF_ACCESSIBLE = "00000000000000000000000000000001"
	BUFF_ERROR = "00000000000000000000000000000011"
	BUFF_READABLE = "00000000000000000000000000000010"
	BUFF_WRITABLE = "00000000000000000000000000000000"
	PORT_USE_FLAG = "00000000000000000000000000000001"

Analyzing hierarchy for module <buff_sm> in library <work> with parameters.
	BUFF_ACCESSIBLE = "00000000000000000000000000000001"
	BUFF_ERROR = "00000000000000000000000000000011"
	BUFF_READABLE = "00000000000000000000000000000010"
	BUFF_WRITABLE = "00000000000000000000000000000000"
	PORT_USE_FLAG = "00000000000000000000000000000011"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000000100011"
	width = "00000000000000000000000000000001"

Analyzing hierarchy for module <pipectrl> in library <work> with parameters.
	STAGES = "00000000000000000000000000000010"
	TAGWIDTH = "00000000000000000000000000000010"

Analyzing hierarchy for module <clip_reg> in library <work> with parameters.
	STROBED = "00000000000000000000000000000001"
	bits_in = "00000000000000000000000000010000"
	bits_out = "00000000000000000000000000001000"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000001010011"
	width = "00000000000000000000000000000001"

Analyzing hierarchy for module <bin2gray> in library <work> with parameters.
	WIDTH = "00000000000000000000000000010010"

Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
	at_reset = "00000000000000000000000000000000"
	my_addr = "00000000000000000000000010010001"
	width = "00000000000000000000000000000001"

Analyzing hierarchy for module <ram_2port> in library <work> with parameters.
	AWIDTH = "00000000000000000000000000001010"
	DWIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <add2> in library <work> with parameters.
	WIDTH = "00000000000000000000000000010010"

Analyzing hierarchy for module <add2_and_round> in library <work> with parameters.
	WIDTH = "00000000000000000000000000010110"

Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
	bits_in = "00000000000000000000000000010110"
	bits_out = "00000000000000000000000000011000"

Analyzing hierarchy for module <add2_and_round> in library <work> with parameters.
	WIDTH = "00000000000000000000000000010010"

Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
	bits_in = "00000000000000000000000000100100"
	bits_out = "00000000000000000000000000100101"

Analyzing hierarchy for module <round> in library <work> with parameters.
	bits_in = "00000000000000000000000000100101"
	bits_out = "00000000000000000000000000010101"
	round_to_nearest = "00000000000000000000000000000001"
	round_to_zero = "00000000000000000000000000000000"
	trunc = "00000000000000000000000000000000"

Analyzing hierarchy for module <clip> in library <work> with parameters.
	bits_in = "00000000000000000000000000010101"
	bits_out = "00000000000000000000000000010010"

Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
	WIDTH = "00000000000000000000000000100010"

Analyzing hierarchy for module <fifo_long> in library <work> with parameters.
	EMPTY = "00000000000000000000000000000000"
	NUMLINES = "00000000000000000000000111111110"
	PRE_READ = "00000000000000000000000000000001"
	READING = "00000000000000000000000000000010"
	SIZE = "00000000000000000000000000001001"
	WIDTH = "00000000000000000000000000100010"

Analyzing hierarchy for module <fifo_2clock> in library <work> with parameters.
	SIZE = "00000000000000000000000000001001"
	WIDTH = "00000000000000000000000000100100"

Analyzing hierarchy for module <add2_and_clip> in library <work> with parameters.
	WIDTH = "00000000000000000000000000100110"

Analyzing hierarchy for module <clip> in library <work> with parameters.
	bits_in = "00000000000000000000000000010011"
	bits_out = "00000000000000000000000000010010"

Analyzing hierarchy for module <add2_and_clip> in library <work> with parameters.
	WIDTH = "00000000000000000000000000011110"

Analyzing hierarchy for module <clip> in library <work> with parameters.
	bits_in = "00000000000000000000000000011001"
	bits_out = "00000000000000000000000000011000"

Analyzing hierarchy for module <pipestage> in library <work> with parameters.
	TAGWIDTH = "00000000000000000000000000000010"

Analyzing hierarchy for module <clip> in library <work> with parameters.
	bits_in = "00000000000000000000000000010000"
	bits_out = "00000000000000000000000000001000"

Analyzing hierarchy for module <ram_2port> in library <work> with parameters.
	AWIDTH = "00000000000000000000000000001001"
	DWIDTH = "00000000000000000000000000100010"

Analyzing hierarchy for module <clip> in library <work> with parameters.
	bits_in = "00000000000000000000000000100111"
	bits_out = "00000000000000000000000000100110"

Analyzing hierarchy for module <clip> in library <work> with parameters.
	bits_in = "00000000000000000000000000011111"
	bits_out = "00000000000000000000000000011110"


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <u2plus>.
WARNING:Xst:863 - "../u2plus.v" line 64: Name conflict (<clk_func> and <CLK_FUNC>, renaming clk_func as clk_func_rnm0).
WARNING:Xst:852 - "../u2plus.v" line 375: Unconnected input port 'por' of instance 'u2p_c' is tied to GND.
Module <u2plus> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <phyclk> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <phyclk> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <phyclk> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <phyclk> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <clk_fpga_pin> in unit <u2plus>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <clk_fpga_pin> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <clk_fpga_pin> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <clk_fpga_pin> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVPECL_25" for instance <clk_fpga_pin> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <exp_time_in_pin> in unit <u2plus>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <exp_time_in_pin> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <exp_time_in_pin> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <exp_time_in_pin> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <exp_time_in_pin> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVDS_25" for instance <exp_time_in_pin> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <exp_time_out_pin> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVDS_25" for instance <exp_time_out_pin> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <exp_user_in_pin> in unit <u2plus>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <exp_user_in_pin> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <exp_user_in_pin> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <exp_user_in_pin> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <exp_user_in_pin> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVDS_25" for instance <exp_user_in_pin> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <exp_user_out_pin> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVDS_25" for instance <exp_user_out_pin> in unit <u2plus>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "CLKFX_DIVIDE =  1" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "CLKIN_PERIOD =  10.000000" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "FACTORY_JF =  8080" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "SIM_MODE =  SAFE" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <DCM_INST> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <scl_pin> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <scl_pin> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <scl_pin> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <scl_pin> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <scl_pin> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <scl_pin> in unit <u2plus>.
    Set user-defined property "SLEW =  SLOW" for instance <scl_pin> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <sda_pin> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <sda_pin> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <sda_pin> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <sda_pin> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <sda_pin> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <sda_pin> in unit <u2plus>.
    Set user-defined property "SLEW =  SLOW" for instance <sda_pin> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[0].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[0].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[0].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[0].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[0].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[0].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[0].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[1].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[1].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[1].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[1].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[1].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[1].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[1].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[2].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[2].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[2].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[2].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[2].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[2].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[2].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[3].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[3].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[3].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[3].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[3].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[3].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[3].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[4].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[4].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[4].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[4].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[4].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[4].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[4].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[5].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[5].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[5].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[5].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[5].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[5].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[5].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[6].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[6].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[6].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[6].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[6].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[6].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[6].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[7].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[7].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[7].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[7].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[7].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[7].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[7].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[8].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[8].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[8].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[8].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[8].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[8].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[8].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[9].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[9].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[9].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[9].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[9].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[9].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[9].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[10].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[10].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[10].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[10].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[10].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[10].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[10].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[11].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[11].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[11].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[11].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[11].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[11].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[11].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[12].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[12].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[12].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[12].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[12].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[12].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[12].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[13].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[13].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[13].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[13].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[13].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[13].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[13].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[14].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[14].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[14].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[14].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[14].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[14].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[14].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[15].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[15].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[15].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[15].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[15].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[15].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[15].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[16].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[16].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[16].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[16].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[16].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[16].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[16].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[17].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[17].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[17].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[17].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[17].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[17].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[17].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[18].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[18].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[18].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[18].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[18].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[18].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[18].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[19].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[19].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[19].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[19].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[19].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[19].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[19].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[20].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[20].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[20].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[20].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[20].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[20].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[20].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[21].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[21].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[21].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[21].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[21].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[21].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[21].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[22].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[22].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[22].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[22].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[22].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[22].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[22].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[23].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[23].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[23].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[23].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[23].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[23].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[23].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[24].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[24].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[24].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[24].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[24].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[24].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[24].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[25].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[25].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[25].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[25].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[25].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[25].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[25].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[26].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[26].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[26].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[26].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[26].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[26].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[26].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[27].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[27].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[27].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[27].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[27].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[27].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[27].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[28].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[28].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[28].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[28].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[28].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[28].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[28].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[29].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[29].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[29].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[29].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[29].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[29].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[29].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[30].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[30].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[30].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[30].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[30].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[30].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[30].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[31].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[31].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[31].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[31].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[31].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[31].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[31].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[32].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[32].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[32].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[32].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[32].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[32].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[32].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[33].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[33].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[33].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[33].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[33].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[33].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[33].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[34].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[34].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[34].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[34].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[34].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[34].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[34].RAM_D_i> in unit <u2plus>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_RAM_D_IO[35].RAM_D_i> in unit <u2plus>.
    Set user-defined property "DRIVE =  12" for instance <gen_RAM_D_IO[35].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_RAM_D_IO[35].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_RAM_D_IO[35].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_RAM_D_IO[35].RAM_D_i> in unit <u2plus>.
    Set user-defined property "IOSTANDARD =  LVCMOS25" for instance <gen_RAM_D_IO[35].RAM_D_i> in unit <u2plus>.
    Set user-defined property "SLEW =  FAST" for instance <gen_RAM_D_IO[35].RAM_D_i> in unit <u2plus>.
Analyzing module <capture_ddrlvds> in library <work>.
	WIDTH = 32'sb00000000000000000000000000001110
Module <capture_ddrlvds> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <clkbuf> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  TRUE" for instance <clkbuf> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <clkbuf> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <clkbuf> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <clkbuf> in unit <capture_ddrlvds>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_lvds_pins[0].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <gen_lvds_pins[0].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_lvds_pins[0].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_lvds_pins[0].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_lvds_pins[0].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <gen_lvds_pins[0].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DDR_ALIGNMENT =  C1" for instance <gen_lvds_pins[0].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q0 =  0" for instance <gen_lvds_pins[0].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q1 =  0" for instance <gen_lvds_pins[0].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "SRTYPE =  SYNC" for instance <gen_lvds_pins[0].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_lvds_pins[1].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <gen_lvds_pins[1].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_lvds_pins[1].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_lvds_pins[1].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_lvds_pins[1].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <gen_lvds_pins[1].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DDR_ALIGNMENT =  C1" for instance <gen_lvds_pins[1].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q0 =  0" for instance <gen_lvds_pins[1].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q1 =  0" for instance <gen_lvds_pins[1].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "SRTYPE =  SYNC" for instance <gen_lvds_pins[1].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_lvds_pins[2].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <gen_lvds_pins[2].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_lvds_pins[2].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_lvds_pins[2].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_lvds_pins[2].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <gen_lvds_pins[2].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DDR_ALIGNMENT =  C1" for instance <gen_lvds_pins[2].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q0 =  0" for instance <gen_lvds_pins[2].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q1 =  0" for instance <gen_lvds_pins[2].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "SRTYPE =  SYNC" for instance <gen_lvds_pins[2].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_lvds_pins[3].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <gen_lvds_pins[3].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_lvds_pins[3].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_lvds_pins[3].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_lvds_pins[3].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <gen_lvds_pins[3].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DDR_ALIGNMENT =  C1" for instance <gen_lvds_pins[3].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q0 =  0" for instance <gen_lvds_pins[3].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q1 =  0" for instance <gen_lvds_pins[3].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "SRTYPE =  SYNC" for instance <gen_lvds_pins[3].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_lvds_pins[4].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <gen_lvds_pins[4].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_lvds_pins[4].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_lvds_pins[4].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_lvds_pins[4].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <gen_lvds_pins[4].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DDR_ALIGNMENT =  C1" for instance <gen_lvds_pins[4].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q0 =  0" for instance <gen_lvds_pins[4].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q1 =  0" for instance <gen_lvds_pins[4].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "SRTYPE =  SYNC" for instance <gen_lvds_pins[4].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_lvds_pins[5].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <gen_lvds_pins[5].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_lvds_pins[5].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_lvds_pins[5].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_lvds_pins[5].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <gen_lvds_pins[5].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DDR_ALIGNMENT =  C1" for instance <gen_lvds_pins[5].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q0 =  0" for instance <gen_lvds_pins[5].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q1 =  0" for instance <gen_lvds_pins[5].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "SRTYPE =  SYNC" for instance <gen_lvds_pins[5].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_lvds_pins[6].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <gen_lvds_pins[6].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_lvds_pins[6].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_lvds_pins[6].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_lvds_pins[6].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <gen_lvds_pins[6].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DDR_ALIGNMENT =  C1" for instance <gen_lvds_pins[6].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q0 =  0" for instance <gen_lvds_pins[6].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q1 =  0" for instance <gen_lvds_pins[6].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "SRTYPE =  SYNC" for instance <gen_lvds_pins[6].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_lvds_pins[7].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <gen_lvds_pins[7].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_lvds_pins[7].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_lvds_pins[7].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_lvds_pins[7].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <gen_lvds_pins[7].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DDR_ALIGNMENT =  C1" for instance <gen_lvds_pins[7].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q0 =  0" for instance <gen_lvds_pins[7].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q1 =  0" for instance <gen_lvds_pins[7].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "SRTYPE =  SYNC" for instance <gen_lvds_pins[7].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_lvds_pins[8].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <gen_lvds_pins[8].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_lvds_pins[8].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_lvds_pins[8].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_lvds_pins[8].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <gen_lvds_pins[8].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DDR_ALIGNMENT =  C1" for instance <gen_lvds_pins[8].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q0 =  0" for instance <gen_lvds_pins[8].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q1 =  0" for instance <gen_lvds_pins[8].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "SRTYPE =  SYNC" for instance <gen_lvds_pins[8].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_lvds_pins[9].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <gen_lvds_pins[9].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_lvds_pins[9].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_lvds_pins[9].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_lvds_pins[9].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <gen_lvds_pins[9].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DDR_ALIGNMENT =  C1" for instance <gen_lvds_pins[9].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q0 =  0" for instance <gen_lvds_pins[9].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q1 =  0" for instance <gen_lvds_pins[9].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "SRTYPE =  SYNC" for instance <gen_lvds_pins[9].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_lvds_pins[10].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <gen_lvds_pins[10].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_lvds_pins[10].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_lvds_pins[10].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_lvds_pins[10].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <gen_lvds_pins[10].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DDR_ALIGNMENT =  C1" for instance <gen_lvds_pins[10].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q0 =  0" for instance <gen_lvds_pins[10].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q1 =  0" for instance <gen_lvds_pins[10].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "SRTYPE =  SYNC" for instance <gen_lvds_pins[10].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_lvds_pins[11].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <gen_lvds_pins[11].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_lvds_pins[11].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_lvds_pins[11].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_lvds_pins[11].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <gen_lvds_pins[11].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DDR_ALIGNMENT =  C1" for instance <gen_lvds_pins[11].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q0 =  0" for instance <gen_lvds_pins[11].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q1 =  0" for instance <gen_lvds_pins[11].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "SRTYPE =  SYNC" for instance <gen_lvds_pins[11].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_lvds_pins[12].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <gen_lvds_pins[12].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_lvds_pins[12].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_lvds_pins[12].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_lvds_pins[12].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <gen_lvds_pins[12].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DDR_ALIGNMENT =  C1" for instance <gen_lvds_pins[12].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q0 =  0" for instance <gen_lvds_pins[12].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q1 =  0" for instance <gen_lvds_pins[12].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "SRTYPE =  SYNC" for instance <gen_lvds_pins[12].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_lvds_pins[13].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <gen_lvds_pins[13].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_lvds_pins[13].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_lvds_pins[13].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_lvds_pins[13].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "IOSTANDARD =  LVDS_33" for instance <gen_lvds_pins[13].ibufds> in unit <capture_ddrlvds>.
    Set user-defined property "DDR_ALIGNMENT =  C1" for instance <gen_lvds_pins[13].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q0 =  0" for instance <gen_lvds_pins[13].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "INIT_Q1 =  0" for instance <gen_lvds_pins[13].iddr2> in unit <capture_ddrlvds>.
    Set user-defined property "SRTYPE =  SYNC" for instance <gen_lvds_pins[13].iddr2> in unit <capture_ddrlvds>.
Analyzing module <u2plus_core> in library <work>.
	CPU_BLDR_CTRL_DONE = 32'sb00000000000000000000000000000001
	CPU_BLDR_CTRL_WAIT = 32'sb00000000000000000000000000000000
	DSP_RX_FIFOSIZE = 32'sb00000000000000000000000000001010
	DSP_TX_FIFOSIZE = 32'sb00000000000000000000000000001010
	ETH_RX_FIFOSIZE = 32'sb00000000000000000000000000001011
	ETH_TX_FIFOSIZE = 32'sb00000000000000000000000000001001
	SERDES_RX_FIFOSIZE = 32'sb00000000000000000000000000001001
	SERDES_TX_FIFOSIZE = 32'sb00000000000000000000000000001001
	SR_BUF_POOL = 32'sb00000000000000000000000000010000
	SR_GPIO = 32'sb00000000000000000000000010111000
	SR_MISC = 32'sb00000000000000000000000000000000
	SR_RX_CTRL0 = 32'sb00000000000000000000000000100000
	SR_RX_CTRL1 = 32'sb00000000000000000000000001010000
	SR_RX_DSP0 = 32'sb00000000000000000000000000110000
	SR_RX_DSP1 = 32'sb00000000000000000000000001100000
	SR_RX_FRONT = 32'sb00000000000000000000000000011000
	SR_SPI_CORE = 32'sb00000000000000000000000000010100
	SR_TIME64 = 32'sb00000000000000000000000000001010
	SR_TX_CTRL = 32'sb00000000000000000000000010010000
	SR_TX_DSP = 32'sb00000000000000000000000010100000
	SR_TX_FRONT = 32'sb00000000000000000000000010000000
	SR_UDP_SM = 32'sb00000000000000000000000011000000
	SR_USER_REGS = 32'sb00000000000000000000000000001000
	aw = 32'sb00000000000000000000000000010000
	compat_num = 32'b00000000000010100000000000000001
	dw = 32'sb00000000000000000000000000100000
	sw = 32'sb00000000000000000000000000000100
Module <u2plus_core> is correct for synthesis.
 
Analyzing module <wb_1master> in library <work>.
	aw = 32'sb00000000000000000000000000010000
	decode_w = 32'sb00000000000000000000000000001000
	dw = 32'sb00000000000000000000000000100000
	s0_addr = 8'b00000000
	s0_mask = 8'b11000000
	s1_addr = 8'b01000000
	s1_mask = 8'b11110000
	s2_addr = 8'b01010000
	s2_mask = 8'b11111100
	s3_addr = 8'b01010100
	s3_mask = 8'b11111100
	s4_addr = 8'b01011000
	s4_mask = 8'b11111100
	s5_addr = 8'b01011100
	s5_mask = 8'b11111100
	s6_addr = 8'b01100000
	s6_mask = 8'b11110000
	s7_addr = 8'b01110000
	s7_mask = 8'b11110000
	s8_addr = 8'b10000000
	s8_mask = 8'b11111100
	s9_addr = 8'b10000100
	s9_mask = 8'b11111100
	sa_addr = 8'b10001000
	sa_mask = 8'b11111100
	sb_addr = 8'b10001100
	sb_mask = 8'b11111100
	sc_addr = 8'b10010000
	sc_mask = 8'b11110000
	sd_addr = 8'b10100000
	sd_mask = 8'b11110000
	se_addr = 8'b10110000
	se_mask = 8'b11110000
	sf_addr = 8'b11000000
	sf_mask = 8'b11000000
	sw = 32'sb00000000000000000000000000000100
Module <wb_1master> is correct for synthesis.
 
Analyzing module <system_control> in library <work>.
WARNING:Xst:916 - "../../../control_lib/system_control.v" line 45: Delay is ignored for synthesis.
Module <system_control> is correct for synthesis.
 
Analyzing generic Entity <zpu_wb_top> in library <work> (Architecture <syn>).
	adr_w = 16
	dat_w = 32
	sel_w = 4
Entity <zpu_wb_top> analyzed. Unit <zpu_wb_top> generated.

Analyzing generic Entity <zpu_system> in library <work> (Architecture <behave>).
	simulate = false
WARNING:Xst:753 - "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd" line 75: Unconnected output port 'break' of component 'zpu_core'.
Entity <zpu_system> analyzed. Unit <zpu_system> generated.

Analyzing Entity <zpu_core> in library <work> (Architecture <behave>).
INFO:Xst:1749 - "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd" line 801: report: Break instruction encountered
INFO:Xst:1749 - "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd" line 829: report: Illegal instruction
INFO:Xst:1749 - "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd" line 900: report: ZPU jumped to interrupt!
INFO:Xst:1749 - "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd" line 940: report: Illegal state
INFO:Xst:2679 - Register <mem_writeMask> in unit <zpu_core> has a constant value of 1111 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <decodedOpcode<0>> in unit <zpu_core> has a constant value of 100111 during circuit operation. The register is replaced by logic.
Entity <zpu_core> analyzed. Unit <zpu_core> generated.

Analyzing Entity <zpu_wb_bridge> in library <work> (Architecture <behave>).
Entity <zpu_wb_bridge> analyzed. Unit <zpu_wb_bridge> generated.

Analyzing module <bootram> in library <work>.
Module <bootram> is correct for synthesis.
 
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_00 =  000000000000000000000000DBAA04003A0B0B8080E7E80C82700B0B0B0B0B0B" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_01 =  000000000000000000000000800C0400880C840C80DBF42D88080B0B80088408" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_02 =  000000000000000004000000FFFF0652832B2A83810582057283060971FD0608" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_03 =  83A704000B0B0B0B7383FFFF2B2B0906058205838306098183FFFF7371FD0608" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_04 =  000000000000000053510400070A810673097306090609067205737372098105" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_05 =  000000000000000000000000000000000000000051040000732E075372722473" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_06 =  0000000053510400810651510A31050A0A720A1030720A107106810671737109" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_07 =  000000000000000000000000000000000000000051040000732E075372722673" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_09 =  000000000000000000000000000000000000000000000000C40400000B0B0B88" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000A535104720A722B" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_0B =  00000000000000000000000000000000050400000B0B88A70981050B72729F06" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_0C =  000000000000000004000000060753518106FF050974090A739F062A72722AFF" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_0D =  000000000C5151040772FC06832B0B2B8105820573830609020D040671715351" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_0E =  000000000000000000000000510400000A810653810509067205097072098105" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_0F =  000000000000000000000000535104000A098106810509067205097072098105" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000005204000071098105" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000040000000505535172720981" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000075351047373090672097206" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_13 =  00000000000000000400000081FF06521010102A810583057283060971FC0608" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_14 =  000000000000000088AA0400060B0B0B10100508D47383060B0B80E771FC0608" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_15 =  000000000C5104000C840C8080085688CB2D50500B0B80D28808757580088408" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_16 =  000000000C5104000C840C8080085688FD2D50500B0B80D38808757580088408" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_17 =  040000000751515105FF050673097274705471068106FF050509060A72097081" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_18 =  51040000060751517405FF050673097205705471098106FF0509060A72097081" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000005FF0504" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_1A =  00000000000000000000000000000000000000005104000080E7E40C810B0B0B" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000400000071810552" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000040000001010055202840572" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000020D040005715351717105FF" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_20 =  101010101010101010101010101010101010101010101010D3F13F0482813F80" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_21 =  FC060C51102B07728305101006098105FF067383510473811010105310101010" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_22 =  5153510472ED38510A100A5371105272097206058106FF057272807251043C04" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_23 =  800B80E8B40C82A00B0B80E88380800B822EBD3880E7E808802EA43880E7E408" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_24 =  0B80E8B880808280E8B40CF80B0B0B80808080A4BC0C04F8800B80E8B80C8290" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_25 =  940B80E880C0A88080E8B40C8C0B0B0B80C0A880E8BC0C0484800B800CF88080" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_26 =  7008525280E7F0085170A73880E8C03304FF3D0D80E8BC0C80DCA40BB80C0B0B" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_27 =  C034833D810B80E85270EE38087008522D80E7F0E7F00C703884128070802E94" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_28 =  38823D0D09810685800B802E0B0B0B0B802E8E3880E8B0083D0D0B0B0D040480" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_29 =  389D3D225B7A80C40DA13D080404E63D3F823D0D0B0BF5D4E8B0510B040B0B80" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_2A =  862E8C38397983808E3882FB8380842E248B387979838085852EAC385A798380" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_2B =  0C82D4397A80E8C481E4D00C0C86397A0B81E2CC0C8E39810B81E18C82F13981" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_2C =  82B53979842E9F38387983808085248BA73879838380852E225B4079800BA03D" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_2D =  4288539D83409A3D81408339824087393882A43980872E8C8B3879838380862E" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_2E =  9D3DF405963D705380CBE43F3D5262514388539DF23F983D615180CB3D880552" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_2F =  3F80080868458CDE22993D2308498E1BFB38881B3D0827803F8F0BA35241ACB8" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_30 =  9C3DE40508456052CF3F80082E88388C5B5B7A7A06657B068008087A5A8CCD3F" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_31 =  FF5B7A4451A0DA3F9C3DE40581068B38797B2E09065A805B800881FF51ABF93F" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_32 =  887C26ED34811C5C5B79337B3D7D055B5C7B1D9E0B833D5EE005548084559C3D" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_33 =  621D5B5B5E5C7B1D800B883D615B5F5F080284058BDC3F80519FF53F389F3D22" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_34 =  811C5C8879337B34631D5B5B5E5C7B1D800B901F7C26EF38811C5C8879337B34" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_35 =  805C7B1E7C26EF38811C5C8679337B347F1D5B5B5E5C7B1D800B881F7C26EF38" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_36 =  841208593D0D686A3D0D04EE9AF13F9C7C26EF38811C5C8679337B34611D5B5B" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_37 =  95E93F8080DCA85175538C52802E8C382E9438750856758C279C38775A588379" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_38 =  FF9F17568818085D8C5BA05CD63FA057DCF8519553A45280268E3878E15778A3" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_39 =  EB39951808085E818A9A3F800480C15C055675082980DEE88138758475922682" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_3A =  971933570852800B08538C183354901876559618833884577580F22E33568257" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_3B =  3DEA055333705495B3398D1880D35C813F80085F76519791833881575775772E" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_3C =  3F80C85C52568ECC538C193370548E19398D183380C95C94568DBF3F8C193352" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_3D =  058C19082980DFB4C23875847585268033FF0556FF399418B505348075028405" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_3E =  397684292277239BA23992181808770C5FA93990AE3976220476085F58567508" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_3F =  785E80CCD25CAD39710C5680059019082980E8C48E3976847008405680E8C405" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_A =  000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INIT_B =  000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <RAM0> in unit <bootram>.
    Set user-defined property "SRVAL_A =  000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "SRVAL_B =  000000000" for instance <RAM0> in unit <bootram>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <RAM0> in unit <bootram>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <RAM0> in unit <bootram>.
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_00 =  8118588875337734790557577719963D833D5A580554800B55943DDC5C8C1808" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_01 =  577533773D790557587719960B833D5ADC055480A455943DA439A05C7826ED38" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_02 =  C4525393705380DDFE3D0D74943D0D04519C8D3F38838080887826ED34811858" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_03 =  88B33F72A0527251A33F8D3990B83F9DC43F815152A051882E9238A0863F7280" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_04 =  805192C78A5280DE5189A43F3F80DDE4973FA5DEFA3D0D82843D0D045190A73F" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_05 =  90FC3F883F800851E23F878EABE53F8780E8E00CBE3F820BDEA051923F8C5280" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_06 =  95B83F865280085186F03F733F800854B53F878091963F883F800851C13F878C" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_07 =  838084513F8AB252805195FED752838095C23F8D518F873F85528008EF3F8380" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_08 =  875195D6B252838095E03F8A838085513F8AB252865195EAB252838095F43F8A" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_09 =  8E3FAEA090D451AC518EF33FA7BB3F80838092515195CB3F528380823F80C3CF" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_0A =  82FDEE2E2255557380088E0580C938768008802E3F80085605518EEA3F883DFC" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_0B =  90E93F9480DECC5180089A3880C6F03F08900551DEC4528038845380098106AD" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_0C =  8E3F8CE18DEF3FA7519C863F3974527585E03F88F93F73518FDA3F8616705254" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_0D =  51868F3F3F9F5280963F88E687EA3F8C3F82B73FC23F92B1FE3D0D863FFF9E39" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_0E =  885185D1C83F885282AC518B5185DE3F3F845284AC518BD585EB3F829F528051" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_0F =  3F80E451805185B582539F52518BAE3FC43F82AC529051858BBB3F903F82AC51" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_10 =  85B03F9F9F529E518025DF38FF135372518B923FA83F80E4529C51858B9F3F9F" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_11 =  8B2A8106808C0870803D0D82843D0D04810B800C81E0840C8C3F890B52815185" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_12 =  5758595782055A5730708025A70533707F028C053D0D7A7D3D0D04F9800C5182" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_13 =  5153805430709F2A388A557388557383832E8838880555753872802575822E93" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_14 =  54548054842B0751FE0570720577713176812CFF802E9738387254728177259E" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_15 =  51B0B43F7352811851B0BC3FFF065277C63F7281527B51B08180547486397353" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_16 =  527551FE54BD5378815580CA9F053356FB3D0D02893D0D0451B0AC3F815280DA" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_17 =  81FF0653BB3F800851D63FFE3F815281C551B0830D8152800D04FE3DE63F873D" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_18 =  81705654787A575704FA3D0D53843D0D81E0800C087090073881E08072802EF3" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_19 =  3880558181FF2E8371335271833880545270802E17703352279E387280537276" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_1A =  335574810D80E8E40D04FC3D800C883D3881517070802E83747407511353DF39" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_1B =  74802E9581FF06559E3F800880D051B0E8538252865480E880E8E434E138810B" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_1C =  E8E85180DFCC52803886538074802E8F81FF06558C3F8008E8E851FF38865280" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_1D =  845280E8802E9538FF0655743F800881D051AFE3538C52805480E8F0C0993F84" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_1E =  F453B852845480E880E8F00C80DFD408802E8938FF0655743F800881F051FED1" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_1F =  81FF06559C3F8008E8F451FE3884528074802E9581FF0655AE3F800880D051AF" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_20 =  0881FF06AEF93F805280D051E8F853880C8454800880E8F43880DFD874802E89" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_21 =  DC0880E8893880DF5574802E0881FF06FDE73F8080E8F851953884525574802E" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_22 =  3F80E8F80C04FDFAE8F00B80FE843F800B800C043F80E8E80D04FE8EF80C863D" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_23 =  AD993F805280D0515475538C0D7756840C04FB3DE8F40B80FDF03F800B800C04" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_24 =  80E8E4343D0D810B3D0D04FE74800C8780E8F00C873875085574802E0881FF06" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_25 =  FC080607067180E87309737504803D0D3F843D0DE851BE8FCC5280E8945380DF" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_26 =  077080E9E9800806750671800D7309730D04803D0C51823D0C81E08C7080E8FC" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_27 =  800C843D81C73F72535380513D0D7470AF3F04FE3D0D0481980C5182800C81E0" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_28 =  06545472337081FF79565674FB3D0D77833D0D045181B63F0D8A52800D04FF3D" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_29 =  3D0D73523D0D04FF0B800C873FE5398052558191FF06537681157481802E9038" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_2A =  0B800C8480E73F808A52725153FFBD3F76537052FE3D0D74833D0D048051CD3F" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_2B =  1234823D3380E7F451028F05803D0D72833D0D048051DD3F3D0D73523D0D04FF" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_2C =  FE3D0D80833D0D04720C5351E0057022751080DF829080050D73A0290D04FF3D" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_2D =  38843D0D827325E53F811353527251CEE7F8133351C63F80133352725380E7F4" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_2E =  87388D522E0981063353728180E7F41481069538748A2E097678565404FC3D0D" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_2F =  04FE3D0D0C863D0D38748C1572802EF8841408539080055473A029827351DE3F" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_30 =  0D04FF3D800C843D120853722E853890FF537080110852529080058874A02982" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_31 =  800B81A8840C5181882A81A8A8800C7081FF0681E8802270A8880C800D800B81" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_32 =  81A890082E8186388151718033555354880597050D7678020D04FD3D880C833D" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_33 =  A8900870A8900C8181900B8181A88C0C721081075170F1388106515170862A70" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_34 =  70802EBA5151515106708132872A7081A890087070F1388106515151812A7081" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_35 =  708106510870812A0C81A8907081A8908338A0515171812EB13880E83871802E" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_36 =  0B81A890883980C0CC39815134FF125270810556085170743881A88C515170F1" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_37 =  2A70810690087086535481A89705335578028805FD3D0D76853D0D040C70800C" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_38 =  81A8900881A8900C81905170802E843881D0517181A88C0CF138721051515170" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_39 =  5170802E325151518106708170872A7081A890085170F1388106515170812A70" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_3A =  900C81A8517081A82E833890D0517181A88C0C8038733381802E80C580CF3871" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_3B =  51515170708132512A70810690087087F13881A8515151702A70810690087081" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_3C =  0C853D0D8051708081A8900C3980C00B3981518A5354FFB78114FF13802E8E38" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_3D =  8D9F712731515186AC087073085281B83881B8AC7274259B7554805304FD3D0D" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_3E =  0B82808480800CEF81E20B828280880C3D0DFF0B3D0D04FF53E23985F1388113" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_3F =  38833D0D708025F10CFF11517084055451A0F172F3A85287808C0C800CFF0B82" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_A =  000000000" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INIT_B =  000000000" for instance <RAM1> in unit <bootram>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <RAM1> in unit <bootram>.
    Set user-defined property "SRVAL_A =  000000000" for instance <RAM1> in unit <bootram>.
    Set user-defined property "SRVAL_B =  000000000" for instance <RAM1> in unit <bootram>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <RAM1> in unit <bootram>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <RAM1> in unit <bootram>.
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_00 =  74760652F3A8555553810B80585152808C087106700982808280880804FB3D0D" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_01 =  877325DC10575553138415760C8F39817482808C0852712D3872517371802E8F" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_02 =  2B7009820C518172A8057571842980F3269F38717352718704FF3D0D38873D0D" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_03 =  81E0C40C227470080D0292050404FF3D52833D0D880C53517206828080880870" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_04 =  802EF33806515170A0087084CC0C81B8810B81E004803D0D0C833D0D5281E0C8" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_05 =  54527280087081060D81B8A00C04FE3D7181E0C00D04DE3FCC0C823D820B81E0" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_06 =  5271802E708106513971812A8080529A0C53538171902A71B8A008752E933881" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_07 =  7080C00681B8A00804803D0D0C843D0D725271803FFF9E3FEC51F8D38B3880DF" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_08 =  0781E0CC70902B88028E052204FF3D0D0C823D0D80800B802EF2388151517080" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_09 =  0D7554800D04FD3DCC0C833D840B81E0802EF33806515170A00870900C5281B8" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_0A =  853D0D047327E6388113538552A6FF3F14703352F7A53F728638BA515372802E" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_0B =  3D0D04F680ED3F8780DFF05170335356811133548211335583113356FB3D0D77" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_0C =  3875802E7680258F5D5B59572A515B5F7030709F05BB0533616302903D0D7C7E" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_0D =  3F8008517651AEC580537752795578547726943876305777AD51782D8A387952" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_0E =  8B053351803D0D028C3D0D043351782D80DFFC05DD3F8008527651AEFFBD3F77" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_0F =  06575775337081FF5C5A58785208A3D8707084053D0D8C3D3D0D04F7F68D3F82" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_10 =  2E80FB38597580F01970335780DB38812E098106065675A5387681FF802E81D1" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_11 =  80E42E80819539752E819E388A3875807580E324E32EB938A03875807580F024" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_12 =  80F82EBA80F539752E80DB38387580F380F5248B2EAC3875397580F5C638818B" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_13 =  5956805519710852DA39778451792D805680527512335259778419833880EC39" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_14 =  197108529239778481538A5255A3D854525956808419710853903977A3D85480" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_15 =  5675802E59567633197108599E39778451FDD03F53905275A3D8548059568055" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_16 =  048A0B810C8B3D0D39800B801959FEA32DEC398158335179767081058E388052" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_17 =  04FC3D0D38823D0D515170EF708106518C2A8132B8B40870803D0D81E0D00C04" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_18 =  0A075272863871815570802E555556540772810672982B7B059B0533797B0288" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_19 =  7181E0D451FFA93F79712B5152A0753171820A07802E863806515170822A7081" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_1A =  FC3D0D76863D0D045170800C81B8800838FF953F73802E89D80C73510C7081E0" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_1B =  2A517080EE39719015555351227305817210157074278F3855805372787A5455" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_1C =  5280E9880D8653750D04FD3D800C863D52EC397172902A0583FFFF062E8D3871" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_1D =  8812FF125180720CE9985289FF3D0D80853D0D04E9900C547670088051B0983F" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_1E =  5472742E525270220B80E994052253803D0D02963D0D04FD25F3388352527080" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_1F =  83FFFF060D787A710D04FA3D800C853D38805170897225EE881252528E388112" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_20 =  555555730B80E9940880E9980CAD3980800884052E8938763F800880535856C7" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_21 =  84140C8875732376389DAD3F897525EB881454558F3881155271802E08881555" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_22 =  913DDC053D8805523F7353925254AEE7923DD60554933D533D0D86703D0D04F1" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_23 =  8C3D23810523800B028405A68B3D2380818A800B05A205239080028451AED83F" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_24 =  8A52913D665E80530523685D028405AE8D3D238080C0910B05AA052380800284" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_25 =  23800B918405BA05963D220222903D230523983D028405AEB73F8008E40551FD" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_26 =  913D0D04519FB03F81E684056980C0293DD4055223AC53918405BE053D238002" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_27 =  529A3DF85380E988ADC53F863DF205519B3D529A3D2386535B800B97E83D0D80" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_28 =  9B3DC411585A800B8008800823F7E23F0580E205052202843F0280F20551ADB7" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_29 =  8305FC065FA33D085EA13D085C905D6E084659840845A33D6E44A13D43F00543" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_2A =  0C75085484387376557375273151565A31908071701A787C84587508408C3D56" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_2B =  E63F7508E09851EF2E883880065473809416088354738C383873830673802E9A" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_2C =  BF268438FFAC38785777802517FF195984055708823F75705276519E53941608" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_2D =  7F1F94050B943D2340818A800D6B6E400D04EA3DE83F9A3D822A51F680C05978" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_2E =  075A79966980C08080CE0523800284053D23818023800B950580CA055A790284" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_2F =  3F800809525CFAE052933D704780538A90084668052380E9840580D23D238002" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_30 =  7992388081FF065A873F8008535C5E8C53983D7023913D700580D2055A790284" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_31 =  7B549080575D94555960586B027F5A6DD53FA939F6B63FEDC23F7A51E0C451F7" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_32 =  F73D0D7F983D0D0438FD893F867C26EF34811C5C5B79337B1D7C1F5B53805C7B" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_33 =  A605237780028405768B3D23238818578405A2058D3D2202228A3D235802AE05" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_34 =  23908002810B8E3D04EE3D0D3F8B3D0D7D51FE9E05539152548B3DF8567E5588" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_35 =  53800852EB8C3F8605B60523348102848405B5053D34840223860B8F8405B205" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_36 =  943DF6058653805251A9E43F943DF20553800852EB863F8451A9F43F943DEC05" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_37 =  53805B7A0554908655943DE45780569C598058805A025C806470084451AAF13F" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_38 =  0B8E3D23EE3D0D81943D0D0438FBCD3F867B26EF34811B5B901B337A1C5A80E0" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_39 =  893F8653B60523EA8102840505B5053434840284860B8F3D05B2052390800284" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_3A =  53805294A8E13F863DF2055180085294833F8453A8F13FEA3DEC055180085294" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_3B =  E40554909C55943D80578056805980580843025CE73F8008A9EE3FE93DF60551" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_3C =  04D83D0D3F943D0DEF38FAC85B867B267A34811BE0901B337A1C5A808653805B" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_3D =  5C799B2629F2055BAD3D0884CC38901D098106827E90862E1122405DAB3D088E" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_3E =  225A79909138821C098106875A79812E9D397B22F49D3F8780E0F4518D387952" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_3F =  2E098106225A7982F538861C09810686798C842E841C225A06878338802E0981" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_A =  000000000" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INIT_B =  000000000" for instance <RAM2> in unit <bootram>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <RAM2> in unit <bootram>.
    Set user-defined property "SRVAL_A =  000000000" for instance <RAM2> in unit <bootram>.
    Set user-defined property "SRVAL_B =  000000000" for instance <RAM2> in unit <bootram>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <RAM2> in unit <bootram>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <RAM2> in unit <bootram>.
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_00 =  79527A5151A7A03F981D52793D5A8653A7AD3FA81D527A515B84539EA238943D" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_01 =  5B888C3FA81D70524088943F9E1D70520686BB38812E09811C225A7987953F86" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_02 =  5A8653809138A83D5E800886F63F8008A40551A552AA3DFF5380E99080084384" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_03 =  34851C331C33A33D820523840284058123821C227B22A23D51A6D43FE9885279" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_04 =  70547B53A6A13F843DE40551537952AA86052386028405818505348202840581" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_05 =  AA3DF40579537F5251A6843F981D527A055B86533F028192525AA693AB3DEA05" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_06 =  AA3DDC05575D9C55597E587E027E5A7E51A5EC3F537A527F9F3D408651A5F83F" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_07 =  397E9080E73F84EE26EF38F71C5C867C337B34811D5B5B795C7B1D60547E537D" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_08 =  2A708F06D1387988098106845B60842E8C2A435B1D70227084E438902E098106" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_09 =  E09052825E86538084B4387EFF065F7E1B2280FF84C038862E098106515A7985" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_0A =  08833881A3ED3F8070535B5C80E99054901C625538815E7E3F8008831D51A483" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_0B =  5D407F8122EC11401B33821C84C53F89529C1D518138881D7B802E845C7D8738" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_0C =  7A2E8F385D42407D8411225D7A08A41F388C1B08810683DE7F912E092E81BB38" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_0D =  08428008F4913F8022535D5DE41D821DBD39AC1DF0BD3F8380E1945179537D52" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_0E =  3D408853A3E13F9D7D5279515F5A88539B3D9A3D3D237F4A387A229A802E83A6" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_0F =  8853795251A3C03FB405527953AA3DFF236048881B22983DA3D53F8279527F51" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_10 =  7C26EF38811C5C8879337B347C1F5B5B5E5C7B1D557E843D3F7B567C7D51A3B7" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_11 =  AD398C1B5A792D82618405087B26EF38811B5B8884051C345A793302805B7F1B" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_12 =  2E098106335A79839539811A81BB3882387D882E7D832E8A33405B4208A41E70" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_13 =  3F8008412251F2CF81F4387C2E0981065E5C79918912335C1D80C01E81A238AC" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_14 =  7D51A29B88537A529C3D5C5E794C993D229C3D231C085A7C80FE388C8008802E" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_15 =  3DCC05524E8853AA9E3D23795A821D223F901C087F51A28F88537D523F973D40" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_16 =  5B79337B1D7C1F5B3D5E5C7B7E557E84EE3F7E56527D51A13F88537A7A51A1F7" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_17 =  38608405887B26EF34811B5B0284051C1B5A793338805B7F887C26EF34811C5C" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_18 =  D105347E02840580963D347E1D5D5D7E39AC1DE4E63F80DE80E951E3085A792D" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_19 =  3D70525B53605295D605237E0284058023861A221A22973DD205238402840580" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_1A =  567C557DD205237B0284058008095A79F08E3F802A527C5108537B81F09A3F80" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_1B =  3D0D800BE80C04FC800B80E980E9E40C0D04800BC53FAA3D526151F4547A537F" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_1C =  2E0981065351707571088C13EC545651700880E927A438765553727480E9E408" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_1D =  715357553D0D77793D0D04FB70800C86E738FF51537373268B39811385387251" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_1E =  E9E808810C8E39801480E9E426893881085473873880E9E4088025BAFFB93F80" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_1F =  E9F01451537552800C51548680E9EC12822B760873101470E9E80C5411870680" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_20 =  FD3D0D75873D0D04519FA43F80E9F00552738429548653751080080594398008" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_21 =  5276519E80E9F005537384290805548680081080082499388054738051FED83F" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_22 =  14337088902B078271982B71338112333D0D75703D0D04FD73800C85FA3F8154" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_23 =  225659577F80EACCF93D0D7D853D0D0454565452800C5253163371072B720783" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_24 =  902980EA9029147080D3387354738326723152568B3D227083FFFF0676A83873" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_25 =  38749029748326AD315757543D227072FFFF068DC039738376742380D0055154" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_26 =  335354743875177075782791EA3F8056D005519D902980EA8A3D527315548853" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_27 =  D0545480800B80EA80EACC23029A052204FC3D0D39893D0D811656EC51E1DE3F" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_28 =  14829014EDDC3F81227405515280EACC140CB8F4800B828C8288140C7323800B" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_29 =  06515675813270815C847C2C80EAD05A3D0D800B3D0D04F427D9388654548374" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_2A =  08FF2E80E1A33F80055B7B5138781A88FF2680D65B5D798182881A0881BE3875" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_2B =  58587680535159517180250730728025728D32708A32703081FF0670C5388008" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_2C =  811A5A81828C1A0C1A0C800B810582888288190881055D345D777B702E833881" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_2D =  568B7627828C1B0C190881119138828C80D2387C1908802EB1388288FF7A27FF" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_2E =  57577533771A781A833D5B581954800B19085588AB3882885675802EBF387822" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_2F =  828C1A0C1A0C800B800B828851F0E93FCC227C05EF3880EA5888782677348118" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_30 =  685194BA5780C052883D705404EA3D0D388E3D0D7C27FEA91A5A5C83811C8290" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_31 =  943874162E098106387381AA81FF2E9D3351547355741770059D05573F800284" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_32 =  800C983D38805473BE7527D1398115553881548B098106857381992E70335154" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_33 =  CA3F8008527351995380E1B83F805584795193EA545484520D863D700D04F93D" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_34 =  3F8AC23F3D0D8DD7940C04FC810B81E0893D0D045574800C06833881752E0981" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_35 =  E1BC518173883880065151548D2A7081B8B4087089C13F8106558051800881FF" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_36 =  51DD843F3880E2A008802E9AFEBF3F80B0800A5151DD983F3880E1F4833974B5" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_37 =  51FEE33F3998800AD85180CCB53F80E2800A5184E1B73FB03F82AC5181518987" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_38 =  80E3D0515192BF3F5298800A5380FFFF3F838080A451DCD7BB3880E38008802E" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_39 =  E93F88393F805183AC51E0E9DCB13F8280E3F4513FFEE53FAC51E0F9DCC13F82" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_3A =  E5893FA0E4FC52547570538004FD3D0D80F3900C3D0D0471DC9D3F8680E4B051" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_3B =  528051DAFE3D0DA0853D0D047351722D802E853890085372CC3F80F352A051DA" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_3C =  FF0B800851898D3FFC3D0D9A843D0D048051722D802E853890085372B03F80F3" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_3D =  7182802E5580E45486800653820B80082E80EC388155718006515354862A7081" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_3E =  845188C88338FF547184802E3987E8542E8E388A8A54718080248A389B387182" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_3F =  7080F39CE5F41133067207808A2C70838C0680083F71882A855188C03F800852" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_A =  000000000" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INIT_B =  000000000" for instance <RAM3> in unit <bootram>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <RAM3> in unit <bootram>.
    Set user-defined property "SRVAL_A =  000000000" for instance <RAM3> in unit <bootram>.
    Set user-defined property "SRVAL_B =  000000000" for instance <RAM3> in unit <bootram>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <RAM3> in unit <bootram>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <RAM3> in unit <bootram>.
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_00 =  80F39408DAC93F74110852520680E88871822B8C52DAB03F555351540C80E5B4" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_01 =  2E0981069E39748238FEC13F098106A33874812E74822EA680F3940C2E983874" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_02 =  863D0D045187CD3FFDFB3F99A73F7351F3980CFE8E387380F398082E96387380" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_03 =  3F8D5298995187AC80F3980C940CFF0B800B80F35187A23FE13F8008FD3D0DD7" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_04 =  908007F48F3F80083F8451878451DFB13FBF94529C5187CD81AE80525187D63F" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_05 =  CC51E2A7735280E53880085380082E8D86FA3F73B03F8451548451879F067053" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_06 =  70852A820297053304FD3D0D3F853D0D8051878984800752E33F80083F805186" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_07 =  71730707832BA00610900674730707732A880671840672810771832A0671872A" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_08 =  515552550C5152530682C080077081FF0778872BC006707276852B807081FF06" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_09 =  983F81AA81FF51FF51FF9E3F075381FF0681D00A0D74D00A0D04FE3D5552853D" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_0A =  5252FEF57081FF063F72882AE151FF81FF873F808C3FB251819951FF51FF923F" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_0B =  902A7081FEDB3F7272982A5151FEE23FE83F81813FB251FE0651FEED3F7281FF" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_0C =  A051FEB551FEBA3FFEBF3F8EC43F805181A151FE51FECA3FFECF3FB0FF065253" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_0D =  0553805254873DFCFB3D0D82843D0D0451FEA63FFEAB3F80B03FA0513F8051FE" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_0E =  12085859D73D0884D53D0880B23D0D803D0D04FF22800C87CE3F863D80D05183" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_0F =  2681B23816567596BC39FF9FDFF53F8180E68451538294522690387757778293" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_10 =  0B81E2CCE18C0C815E810B813F800808C15CD4C075080480E6D0055675842980" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_11 =  FEF63F805C80F839085F80C68C9D3F803F80085E8A398C99E4D00C810C800B81" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_12 =  C55C80D389F53F8080F3C8518C170852901708535C80E839065E80D60883FFFF" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_13 =  3994175380C25CB7C45CBC392E86388006567580800881FF518ABA3F3980F3C8" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_14 =  1708518B1708528C8005539080D03DFED75CA43988DC3F808C17085190170852" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_15 =  54800B833DFDEC05945580D039A05C82FCF83F83D35C80515C8D3980B93F80D2" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_16 =  E6FE3F80838082517826EC388118588875337734790557571980D23D3D5A5877" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_17 =  05AB0533053302843D0D02A783973FF9CE3FFF51E7AC51D4803D0D80D03D0D04" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_18 =  7F7F5A573D0D7A7C3D0D04F8DFEB3F8981528051985475535757825571882B07" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_19 =  8405A105055833023476708154738A3D758117577425B73816565480575874FF" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_1A =  802E8538D8C73F7306548A51800881FF51D7993F7781FF063DFC05523482538A" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_1B =  883D348138DC5675DE567483053355803D0D02A33D0D04FA73800C8AC1398154" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_1C =  893D348102AB05333D0D7C573D0D04F9FF893F885280D051055381F754883DFC" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_1D =  3880772573802E9E06705654800881FF56D6B93F05337052055202A753893DFC" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_1E =  0C893D0D81557480802E8338705654730881FF06D4FC3F807B52755197387653" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_1F =  80DE2E0933565674800B883D51FFA03FF75280D0FC0553818154883D04FA3D0D" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_20 =  81C0AC0C800CA60BEB0B81C0C0940C8004990B810C883D0D8156758081068338" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_21 =  C0A00C8151820B8181C0980C06708107882BBE80803D0D72C0B00C0489B00B81" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_22 =  72882BBE04803D0D0C823D0DC0A8088070F1388106515151812A7081C0A40870" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_23 =  708106510870812A0C81C0A40B81C0A0C09C0C840C5173810781C09880067081" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_24 =  8306527171913875555557577C7283063D0D787A04FF39FA38823D0D515170F1" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_25 =  822B7711279438735555737572822A725188CA3F2E863881065271808A387283" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_26 =  80E7B8112A708F060D7470840D04FE3DE939883D52811454720C525477127008" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_27 =  82E0900804803D0D3F843D0D5253CFFBE7B81133728F068053D0883F33545153" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_28 =  8C80060780FF067A93053378FE3D0D02823D0D045170F1388106515170882A70" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_29 =  82E0900CE0800C71F1387682515151702A70810690087088535382E080C08007" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_2A =  882A7081E09008702E9638827251728082E0900C7182800782E0980C7581FF06" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_2B =  8880558882E0940C3D0D810B3D0D04FC70800C84E080085170F1388206515151" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_2C =  51FEF13F5381528190548A800D8880550D04FC3D873F863D528051FF54805380" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_2D =  863D0D0451FED53F53815280558854863D0D88803D0D04FC06800C86800881FF" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_2E =  70802EF481FF0651EB3F800804803D0D0C823D0D328106803F800881803D0DCA" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_2F =  5475FE9B888055A03FFFB43F269B38DD3F758008775684E304FB3D0D38823D0D" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_30 =  08FF11560880CB3D0D80C93D04FFBA3D3F873D0D8051FE84075381520A069B0A" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_31 =  FF52883D828053812681A7383F7380081754849F81B438757381FF2657578055" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_32 =  82E0980CFD9F3F743FFED43FEA3FFEFD5273518A80CB3D088F3F75537052548C" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_33 =  0B82E090980C88A0810B82E082E0800C80C00A07FEC00A06E0900C7688800B82" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_34 =  841570088C0C54FE700882E056FE8015C83D558FFCEF3F8082E0900C0C8AA00B" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_35 =  82E0900C5488800B82E0800C8C157008840C54FE700882E054FE881582E0880C" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_36 =  8155748082E0980CBC38800B758025FF90165656B03FFF16E0900CFC8A800B82" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_37 =  CB388157800826803F805773565682DB7212575A0D797B7D0D04F93D0C80C83D" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_38 =  76547753752783387555577682807431802EA238FF065473C338758174802E80" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_39 =  E1388280828075278E3874545674802E7631575916741976FDEB3F7373527551" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_3A =  3873135473802E8D7A5654553D0D76783D0D04FC76800C898C3F815754DC39FD" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_3B =  0830707481CB3F80750CA63984160C80160C800B38800B880874279081ED3F80" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_3C =  3F863D0D7151FCC97188160C0684160C72760C743F800830515281BD06FF1656" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_3D =  15082E94881408849F3881535271802EFF0670543F8008817554FC9804FD3D0D" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_3E =  3D0D88803D0D04FC72800C85943F8053160C51FC08057088881408803881823F" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_3F =  0D80F3A00D04FF3D800C863DFE800A06A33F8008528151FAF90A538155A05481" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_A =  000000000" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INIT_B =  000000000" for instance <RAM4> in unit <bootram>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <RAM4> in unit <bootram>.
    Set user-defined property "SRVAL_A =  000000000" for instance <RAM4> in unit <bootram>.
    Set user-defined property "SRVAL_B =  000000000" for instance <RAM4> in unit <bootram>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <RAM4> in unit <bootram>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <RAM4> in unit <bootram>.
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_00 =  387180F3098106935170A02EFF065451068008812A7081FF3F80088808A038D7" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_01 =  0880E88204C03F800C833D0DB33F7180278438F552528271A008EA11A00C80F3" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_02 =  0D7D56F90C04F63D80082B80A93F810B800C04FF0B80082B04F33F810533800C" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_03 =  810B82E082E0800C0C7C882B0B82E084E0900C8B88800B8282E0980C983F800B" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_04 =  3888800B762780D355805473F8E73F7E82E0900C0C8AA80B0B82E090980C88A8" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_05 =  5A82E08082E08408E08808598C085882CC3F82E0E0900CF88A800B8282E0900C" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_06 =  70337570387117517173279170538052732783385790537076753152085B883D" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_07 =  7251F78904803D0D0C8C3D0D0B82E098FFA9398039721454811252EC81055734" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_08 =  70800C54DE3F800805085182528C0888088C05080D80538C8C0CFD3D3F8C0802" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_09 =  82B93F808805085108528C088C088C053D0D8153028C0CFD0C048C08853D0D8C" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_0A =  88050880050C8C080B8C08FCF93D0D8008028C0C8C0C048C54853D0D0870800C" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_0B =  810B8C08050888380C8C08FC8C08F405050C800B308C08880888050825AB388C" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_0C =  8C088C058C050830AB388C08050880250C8C088C8C08FC0508F40508F4050C8C" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_0D =  08FC050CF005088C050C8C080B8C08F0088838818C08FC0508F0050C0C800B8C" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_0E =  FC0508800C548C088C08F8053F800870085181A78C0888058C05085280538C08" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_0F =  048C08023D0D8C0C800C5489F8050870050C8C08308C08F808F805082E8C388C" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_10 =  0888050C0508308C388C0888088025938C08880508FC050C0D800B8C8C0CFB3D" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_11 =  538C088C8C050C8108308C088C088C0580258C38088C0508FC050C8C810B8C08" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_12 =  388C08F808802E8C8C08FC05F8050C5408708C0851AD3F80088805080508528C" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_13 =  FD3D0D8108028C0C8C0C048C54873D0D0870800C8C08F80508F8050C0508308C" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_14 =  FC050880AC388C088805082705088C080C8C088C8C08F805050C800B0B8C08FC" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_15 =  08108C088C08FC05088C050C0508108C388C088C050824990B8C088C2EA33880" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_16 =  8C0888050826A1388C088805088C050880C9388C0508802E398C08FCFC050CC9" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_17 =  8C08FC0508F8050C0508078C088C08FC8C08F8050888050C0508318C088C088C" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_18 =  802E8F3808900508FFAF398C088C050C08812A8C8C088C0508FC050C08812A8C" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_19 =  F40508800C518C088C08F405F80508708D398C08F4050C5108708C088C088805" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_1A =  802EB03883065170387474078372278C795656523D0D78778C0C04FC0C853D0D" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_1B =  545555718115FF14BD3881152E0981065253727174337433FF2EA038FF125271" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_1C =  388411840981068F0873082E745451703D0D04740B800C8606E23880FF2E0981" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_1D =  3D0D76703D0D04FC31800C86AF397271735555FF26E938705451718314FC1454" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_1E =  983872705271FF2EA738FF125170802E75078306278C387255558F72797B5555" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_1F =  74517270863D0D043874800C098106EA5271FF2E5634FF127470810581055433" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_20 =  7170840584055408530C72707170840584055408530C72707170840584055408" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_21 =  7084055427953872C938837252718F26530CF0127170840584055408530C7270" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_22 =  059F05337971028CFC3D0D7654FF833926ED38701252718305530CFC08717084" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_23 =  70810555933873735271FF2EA238FF125170802E387483068372278A57555355" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_24 =  2B0751540770719074882B753D0D047474800C868106EF3871FF2E0934FF1252" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_25 =  7170840505530C72727170848405530C0C72717070840553A5387271518F7227" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_26 =  F238705352718326530CFC127170840527903872DD38837252718F26530CF012" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_27 =  2E80D43806517080717407832E80D938555272807C7054553D0D787AFF9039FA" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_28 =  7081FF062E818738A93872802E0981065651747171337433FF2EB138FF135372" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_29 =  56517081713374338106D13872FF2E0915555552128115FF80FC38815170802E" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_2A =  7108740873278838745755833D0D047170800C8831515252FF067171FF067581" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_2B =  70F88482FDFF12067009F7FBB13874085372802E9739FC13765552FF2E883874" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_2C =  765552FE2ED03874740876087327D03817575583388415845151709A81800651" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_2D =  F3A40CFF9E3873805472812EE7E808540D800B800D04FD3D800C883DDF39800B" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_2E =  FFAD813F80F3A40CF6A33F723F80085151FFB5B8E89C5281ACBA3F80AD9E3FFF" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_2F =  A40BFC053D0D80E800FF39FF51F6863F9B3F80088151FFB580E89C52FFAC9D3F" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_30 =  0404FFAD38833D0D098106F15270FF2E1270085238702DFC70FF2E9170085252" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_31 =  636B65746C2070616E74726F6E20636F6F7220692145727200000040AC3F0400" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_32 =  6C697479746962696F6D706165642063706563743A204578646C65722068616E" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_33 =  6F7220692145727225640A00676F74206275742025642C2062657220206E756D" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_34 =  706563743A204578646C65722068616E636B65746C2070616E74726F6E20636F" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_35 =  742025647420676F2C20627568202564656E67746164206C61796C6F65642070" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_36 =  203D202570656564643A2073616E67656B206368206C696E0A6574680A000000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_37 =  720A00006F6164656F6F746C445020623130205550204E320A555352640A0000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_38 =  640A0000723A2025756D62657479206E62696C697061746920636F6D46504741" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_39 =  723A2025756D62657479206E62696C697061746920636F6D776172654669726D" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_3A =  7061636B6572792065636F7669702072476F74200000000061646472640A0000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_3B =  0000082600000826000008260000082600000826000007310000000065743A20" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_3C =  0000082600000826000007FC0000082600000826000007760000078D00000826" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_3D =  000007CF000007CA000007C50000073E000007AA000008260000082600000826" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_3E =  FFFFFF00C0A80A01C0A80A023FFF00000050C285000007EA000007DD000007D6" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_3F =  303132332E256400642E256425642E254500000001B200D90516036414580A2C" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_A =  000000000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INIT_B =  000000000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <RAM5> in unit <bootram>.
    Set user-defined property "SRVAL_A =  000000000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "SRVAL_B =  000000000" for instance <RAM5> in unit <bootram>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <RAM5> in unit <bootram>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <RAM5> in unit <bootram>.
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_00 =  5F706B7473656E64FFFF0000FFFFFFFF00000000434445463839414234353637" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_01 =  722062756E642F6F656E20616F66206C656E742069676E6D6420616C3A206261" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_02 =  742063616F206869656420746661696C6F6E3A20636F6D6D6E65745F66000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_03 =  6172703A646C655F0A68616E00000000666F7220696E67206C6F6F6B63686520" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_04 =  6E736973696E636F554450200A0000003D202564697A65207264207320776569" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_05 =  537461720B0B0B0B000000002025640A3A20256467746873206C656E74656E74" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_06 =  6164696E2E204C6F6D6F646561666520696E207350322B202055535274696E67" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_07 =  20666F726B696E6743686563000000006172652E69726D776665206667207361" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_08 =  2E2E2E006D616765474120696E2046506374696F726F6475696420702076616C" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_09 =  666F756E616765204120696D2046504774696F6E6F6475636420707256616C69" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_0A =  616C69644E6F2076742E000020626F6F6720746F7074696E7474656D642E2041" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_0B =  2E0A46616F756E646765206620696D6146504741696F6E20647563742070726F" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_0C =  726D77616E2066696C742D69206275696820746F726F7567672074686C6C696E" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_0D =  6520666F6D7761722066697274696F6E6F6475636420707256616C6972652E00" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_0E =  64696E67206C6F617368656446696E692E2E2E0064696E67204C6F61756E642E" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_0F =  65747572523A20524552524F2E0000006D6167656E672069617274692E205374" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_10 =  6F756C64732073682054686972616D2170726F6761696E206F6D206D6E206672" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_11 =  647563742070726F616C69644E6F20766E2100006170706565722068206E6576" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_12 =  7468726F696E672046616C6C6E642E2020666F75776172656669726D696F6E20" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_13 =  537065652E000000776172656669726D2D696E2075696C74746F206275676820" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_14 =  5800000057455F54000000004E4F4E45000000002025640A7420746F64207365" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_15 =  20666C6F726E657465746865430000004554524953594D4D5800000057455F52" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_16 =  2077726F4144563A4E45475F4155544F5048595F6C3A20006E74726F7720636F" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_17 =  000000010003000300000000780A00002030782520676F747825782C74652030" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_18 =  68616E646B65742020706163646174656E2075706F7220692145727200030203" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_19 =  2025642C6E67746864206C65796C6F616420706165637465204578706C65723A" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_1A =  00002261000022B1000022B10000220B000000002025640A20676F7420627574" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_1B =  000022B1000022B1000022B1000022B1000022B1000022B10000222A0000224C" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_1C =  000022B1000022A700002290000022B1000022B1000022B1000022B1000022B1" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_1D =  3435363730313233000000006F72740A0A0A61620000227D0000223C000022B1" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_1E =  FFFF00FFFF00FFFF00FFFFFF65000000792E657864756D6D4344454638394142" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_1F =  FFFF003105050400010101000000342C000000000000000000000000FFFFFF00" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_20 =  000033C810101200000032A8000032A00000329800003290000B00000018000F" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000FFFFFFFF00000000FFFFFFFF" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_A =  000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INIT_B =  000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <RAM6> in unit <bootram>.
    Set user-defined property "SRVAL_A =  000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "SRVAL_B =  000000000" for instance <RAM6> in unit <bootram>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <RAM6> in unit <bootram>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <RAM6> in unit <bootram>.
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_A =  000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "INIT_B =  000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <RAM7> in unit <bootram>.
    Set user-defined property "SRVAL_A =  000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "SRVAL_B =  000000000" for instance <RAM7> in unit <bootram>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <RAM7> in unit <bootram>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <RAM7> in unit <bootram>.
Analyzing module <ram_harvard2> in library <work>.
	AWIDTH = 32'sb00000000000000000000000000001110
	RAM_SIZE = 32'sb00000000000000000100000000000000
Module <ram_harvard2> is correct for synthesis.
 
Analyzing module <packet_router> in library <work>.
	BUF_SIZE = 32'sb00000000000000000000000000001001
	CTRL_BASE = 32'sb00000000000000000000000000010000
	UDP_BASE = 32'sb00000000000000000000000011000000
Module <packet_router> is correct for synthesis.
 
Analyzing module <setting_reg.9> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000010000
	width = 32'sb00000000000000000000000000000001
Module <setting_reg.9> is correct for synthesis.
 
Analyzing module <valve36> in library <work>.
Module <valve36> is correct for synthesis.
 
Analyzing module <crossbar36> in library <work>.
Module <crossbar36> is correct for synthesis.
 
Analyzing module <fifo_short.1> in library <work>.
	WIDTH = 32'sb00000000000000000000000000100100
Module <fifo_short.1> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <gen_srl16[0].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[1].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[2].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[3].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[4].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[5].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[6].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[7].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[8].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[9].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[10].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[11].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[12].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[13].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[14].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[15].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[16].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[17].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[18].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[19].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[20].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[21].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[22].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[23].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[24].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[25].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[26].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[27].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[28].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[29].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[30].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[31].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[32].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[33].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[34].srl16e> in unit <fifo_short.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[35].srl16e> in unit <fifo_short.1>.
Analyzing module <fifo36_mux.1> in library <work>.
	MUX_DATA0 = 32'sb00000000000000000000000000000001
	MUX_DATA1 = 32'sb00000000000000000000000000000011
	MUX_IDLE0 = 32'sb00000000000000000000000000000000
	MUX_IDLE1 = 32'sb00000000000000000000000000000010
	prio = 32'sb00000000000000000000000000000000
Module <fifo36_mux.1> is correct for synthesis.
 
Analyzing module <fifo36_mux.2> in library <work>.
	MUX_DATA0 = 32'sb00000000000000000000000000000001
	MUX_DATA1 = 32'sb00000000000000000000000000000011
	MUX_IDLE0 = 32'sb00000000000000000000000000000000
	MUX_IDLE1 = 32'sb00000000000000000000000000000010
	prio = 32'sb00000000000000000000000000000001
Module <fifo36_mux.2> is correct for synthesis.
 
Analyzing module <buffer_int2> in library <work>.
	BASE = 32'sb00000000000000000000000000010011
	BUF_SIZE = 32'sb00000000000000000000000000001001
	DONE = 3'b101
	ERROR = 3'b100
	IDLE = 3'b000
	PRE_READ = 3'b001
	READING = 3'b010
	WRITING = 3'b011
Module <buffer_int2> is correct for synthesis.
 
Analyzing module <ram_2port.1> in library <work>.
	AWIDTH = 32'sb00000000000000000000000000001001
	DWIDTH = 32'sb00000000000000000000000000100000
Module <ram_2port.1> is correct for synthesis.
 
Analyzing module <setting_reg.48> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000010011
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.48> is correct for synthesis.
 
Analyzing module <packet_dispatcher36_x4> in library <work>.
	BASE = 32'sb00000000000000000000000000010001
	PD_DEST_BOF = 32'sb00000000000000000000000000000011
	PD_DEST_CPU = 32'sb00000000000000000000000000000010
	PD_DEST_CTL = 32'sb00000000000000000000000000000100
	PD_DEST_DSP = 32'sb00000000000000000000000000000000
	PD_DEST_EXT = 32'sb00000000000000000000000000000001
	PD_DREGS_DSP_OFFSET = 32'sb00000000000000000000000000001011
	PD_MAX_NUM_DREGS = 32'sb00000000000000000000000000001101
	PD_STATE_READ_COM = 32'sb00000000000000000000000000000001
	PD_STATE_READ_COM_PRE = 32'sb00000000000000000000000000000000
	PD_STATE_WRITE_LIVE = 32'sb00000000000000000000000000000011
	PD_STATE_WRITE_REGS = 32'sb00000000000000000000000000000010
Module <packet_dispatcher36_x4> is correct for synthesis.
 
Analyzing module <setting_reg.49> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000010001
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.49> is correct for synthesis.
 
Analyzing module <setting_reg.50> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000010010
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.50> is correct for synthesis.
 
Analyzing module <splitter36> in library <work>.
	STATE_COPY_BOTH = 32'sb00000000000000000000000000000000
	STATE_COPY_ONE = 32'sb00000000000000000000000000000010
	STATE_COPY_ZERO = 32'sb00000000000000000000000000000001
Module <splitter36> is correct for synthesis.
 
Analyzing module <fifo_cascade.1> in library <work>.
	SIZE = 32'sb00000000000000000000000000001001
	WIDTH = 32'sb00000000000000000000000000100100
Module <fifo_cascade.1> is correct for synthesis.
 
Analyzing module <fifo_long.1> in library <work>.
	EMPTY = 32'sb00000000000000000000000000000000
	NUMLINES = 32'sb00000000000000000000000111111110
	PRE_READ = 32'sb00000000000000000000000000000001
	READING = 32'sb00000000000000000000000000000010
	SIZE = 32'sb00000000000000000000000000001001
	WIDTH = 32'sb00000000000000000000000000100100
Module <fifo_long.1> is correct for synthesis.
 
Analyzing module <ram_2port.3> in library <work>.
	AWIDTH = 32'sb00000000000000000000000000001001
	DWIDTH = 32'sb00000000000000000000000000100100
Module <ram_2port.3> is correct for synthesis.
 
Analyzing module <prot_eng_tx> in library <work>.
	BASE = 32'sb00000000000000000000000011000000
Module <prot_eng_tx> is correct for synthesis.
 
Analyzing module <add_onescomp> in library <work>.
	WIDTH = 32'sb00000000000000000000000000010000
Module <add_onescomp> is correct for synthesis.
 
Analyzing module <fifo36_mux.3> in library <work>.
	MUX_DATA0 = 32'sb00000000000000000000000000000001
	MUX_DATA1 = 32'sb00000000000000000000000000000011
	MUX_IDLE0 = 32'sb00000000000000000000000000000000
	MUX_IDLE1 = 32'sb00000000000000000000000000000010
	prio = 32'sb00000000000000000000000000000000
Module <fifo36_mux.3> is correct for synthesis.
 
Analyzing module <simple_spi_core> in library <work>.
	BASE = 32'sb00000000000000000000000000010100
	CLK_IDLE = 32'sb00000000000000000000000000000000
	CLK_INV = 32'sb00000000000000000000000000000011
	CLK_REG = 32'sb00000000000000000000000000000010
	IDLE_SEN = 32'sb00000000000000000000000000000101
	POST_IDLE = 32'sb00000000000000000000000000000100
	PRE_IDLE = 32'sb00000000000000000000000000000001
	SEN_IDLE = 24'b111111111111111111111111
	WAIT_TRIG = 32'sb00000000000000000000000000000000
	WIDTH = 32'sb00000000000000000000000000001001
Module <simple_spi_core> is correct for synthesis.
 
Analyzing module <setting_reg.10> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000010100
	width = 32'sb00000000000000000000000000010000
Module <setting_reg.10> is correct for synthesis.
 
Analyzing module <setting_reg.11> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000010101
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.11> is correct for synthesis.
 
Analyzing module <setting_reg.12> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000010110
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.12> is correct for synthesis.
 
Analyzing module <i2c_master_top> in library <work>.
	ARST_LVL = 32'sb00000000000000000000000000000001
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_top.v" line 160: Delay is ignored for synthesis.
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_top.v" line 166: Delay is ignored for synthesis.
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_top.v" line 167: Delay is ignored for synthesis.
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_top.v" line 168: Delay is ignored for synthesis.
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_top.v" line 169: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <i2c_master_top> is correct for synthesis.
 
Analyzing module <i2c_master_byte_ctrl> in library <work>.
	ST_ACK = 5'b01000
	ST_IDLE = 5'b00000
	ST_READ = 5'b00010
	ST_START = 5'b00001
	ST_STOP = 5'b10000
	ST_WRITE = 5'b00100
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" line 175: Delay is ignored for synthesis.
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" line 177: Delay is ignored for synthesis.
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" line 179: Delay is ignored for synthesis.
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" line 181: Delay is ignored for synthesis.
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" line 186: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
"../../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" line 230: Found FullParallel Case directive in module <i2c_master_byte_ctrl>.
Module <i2c_master_byte_ctrl> is correct for synthesis.
 
Analyzing module <i2c_master_bit_ctrl> in library <work>.
	idle = 17'b00000000000000000
	rd_a = 17'b00000001000000000
	rd_b = 17'b00000010000000000
	rd_c = 17'b00000100000000000
	rd_d = 17'b00001000000000000
	start_a = 17'b00000000000000001
	start_b = 17'b00000000000000010
	start_c = 17'b00000000000000100
	start_d = 17'b00000000000001000
	start_e = 17'b00000000000010000
	stop_a = 17'b00000000000100000
	stop_b = 17'b00000000001000000
	stop_c = 17'b00000000010000000
	stop_d = 17'b00000000100000000
	wr_a = 17'b00010000000000000
	wr_b = 17'b00100000000000000
	wr_c = 17'b01000000000000000
	wr_d = 17'b10000000000000000
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" line 194: Delay is ignored for synthesis.
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" line 203: Delay is ignored for synthesis.
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" line 204: Delay is ignored for synthesis.
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" line 208: Delay is ignored for synthesis.
WARNING:Xst:916 - "../../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" line 209: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
"../../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" line 364: Found FullParallel Case directive in module <i2c_master_bit_ctrl>.
"../../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" line 360: Found FullParallel Case directive in module <i2c_master_bit_ctrl>.
Module <i2c_master_bit_ctrl> is correct for synthesis.
 
Analyzing module <gpio_atr> in library <work>.
	BASE = 32'sb00000000000000000000000010111000
	WIDTH = 32'sb00000000000000000000000000100000
Module <gpio_atr> is correct for synthesis.
 
Analyzing module <setting_reg.13> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010111000
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.13> is correct for synthesis.
 
Analyzing module <setting_reg.14> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010111001
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.14> is correct for synthesis.
 
Analyzing module <setting_reg.15> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010111010
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.15> is correct for synthesis.
 
Analyzing module <setting_reg.16> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010111011
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.16> is correct for synthesis.
 
Analyzing module <setting_reg.17> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010111100
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.17> is correct for synthesis.
 
Analyzing module <wb_readback_mux> in library <work>.
Module <wb_readback_mux> is correct for synthesis.
 
Analyzing module <simple_gemac_wrapper> in library <work>.
	RXFIFOSIZE = 32'sb00000000000000000000000000001011
	RX_FLOW_CTRL = 32'sb00000000000000000000000000000000
	TXFIFOSIZE = 32'sb00000000000000000000000000001001
Module <simple_gemac_wrapper> is correct for synthesis.
 
Analyzing module <reset_sync> in library <work>.
Module <reset_sync> is correct for synthesis.
 
Analyzing module <simple_gemac> in library <work>.
	SGE_IFG = 8'b00001100
Module <simple_gemac> is correct for synthesis.
 
Analyzing module <simple_gemac_tx> in library <work>.
	MAX_FRAME_LEN = 32'sb00000000000000000010000000000000
	MIN_FRAME_LEN = 32'sb00000000000000000000000001000100
	SGE_FLOW_CTRL_ADDR = 48'b000000011000000011000010000000000000000000000001
	TX_CRC_0 = 32'sb00000000000000000000000000010000
	TX_CRC_1 = 32'sb00000000000000000000000000010001
	TX_CRC_2 = 32'sb00000000000000000000000000010010
	TX_CRC_3 = 32'sb00000000000000000000000000010011
	TX_ERROR = 32'sb00000000000000000000000000100000
	TX_FIRSTBYTE = 32'sb00000000000000000000000000001001
	TX_IDLE = 32'sb00000000000000000000000000000000
	TX_IN_FRAME = 32'sb00000000000000000000000000001010
	TX_IN_FRAME_2 = 32'sb00000000000000000000000000001011
	TX_PAD = 32'sb00000000000000000000000000001100
	TX_PAUSE = 32'sb00000000000000000000000000110111
	TX_PAUSE_END = 32'sb00000000000000000000000001010000
	TX_PAUSE_FIRST = 32'sb00000000000000000000000000111111
	TX_PAUSE_SOF = 32'sb00000000000000000000000000111110
	TX_PREAMBLE = 32'sb00000000000000000000000000000001
	TX_SOF_DEL = 32'sb00000000000000000000000000001000
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 168: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 170: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 172: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 174: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 176: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 178: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 180: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 182: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 184: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 186: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 188: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 190: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 192: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 194: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 196: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 198: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../../simple_gemac/simple_gemac_tx.v" line 200: Size mismatch between case item and case selector.
Module <simple_gemac_tx> is correct for synthesis.
 
Analyzing module <crc> in library <work>.
	Calling function <NextCRC>.
Module <crc> is correct for synthesis.
 
Analyzing module <simple_gemac_rx> in library <work>.
	DELAY = 32'sb00000000000000000000000000000110
	MIN_PAUSE_LEN = 32'sb00000000000000000000000001000111
	RX_DO_PAUSE = 32'sb00000000000000000000000000000100
	RX_DROP = 32'sb00000000000000000000000000000110
	RX_ERROR = 32'sb00000000000000000000000000000101
	RX_FRAME = 32'sb00000000000000000000000000000010
	RX_GOODFRAME = 32'sb00000000000000000000000000000011
	RX_IDLE = 32'sb00000000000000000000000000000000
	RX_PAUSE = 32'sb00000000000000000000000000010000
	RX_PAUSE_CHK00 = 32'sb00000000000000000000000000010111
	RX_PAUSE_CHK01 = 32'sb00000000000000000000000000011000
	RX_PAUSE_CHK08 = 32'sb00000000000000000000000000010110
	RX_PAUSE_CHK88 = 32'sb00000000000000000000000000010101
	RX_PAUSE_STORE_LSB = 32'sb00000000000000000000000000011010
	RX_PAUSE_STORE_MSB = 32'sb00000000000000000000000000011001
	RX_PAUSE_WAIT_CRC = 32'sb00000000000000000000000000011011
	RX_PREAMBLE = 32'sb00000000000000000000000000000001
Module <simple_gemac_rx> is correct for synthesis.
 
Analyzing module <delay_line> in library <work>.
	WIDTH = 32'sb00000000000000000000000000001010
Module <delay_line> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <gen_delay[0].srl16e> in unit <delay_line>.
    Set user-defined property "INIT =  0000" for instance <gen_delay[1].srl16e> in unit <delay_line>.
    Set user-defined property "INIT =  0000" for instance <gen_delay[2].srl16e> in unit <delay_line>.
    Set user-defined property "INIT =  0000" for instance <gen_delay[3].srl16e> in unit <delay_line>.
    Set user-defined property "INIT =  0000" for instance <gen_delay[4].srl16e> in unit <delay_line>.
    Set user-defined property "INIT =  0000" for instance <gen_delay[5].srl16e> in unit <delay_line>.
    Set user-defined property "INIT =  0000" for instance <gen_delay[6].srl16e> in unit <delay_line>.
    Set user-defined property "INIT =  0000" for instance <gen_delay[7].srl16e> in unit <delay_line>.
    Set user-defined property "INIT =  0000" for instance <gen_delay[8].srl16e> in unit <delay_line>.
    Set user-defined property "INIT =  0000" for instance <gen_delay[9].srl16e> in unit <delay_line>.
Analyzing module <address_filter> in library <work>.
Module <address_filter> is correct for synthesis.
 
Analyzing module <address_filter_promisc> in library <work>.
Module <address_filter_promisc> is correct for synthesis.
 
Analyzing module <flow_ctrl_tx> in library <work>.
Module <flow_ctrl_tx> is correct for synthesis.
 
Analyzing module <simple_gemac_wb> in library <work>.
Module <simple_gemac_wb> is correct for synthesis.
 
Analyzing module <wb_reg.1> in library <work>.
	ADDR = 32'sb00000000000000000000000000000000
	DEFAULT = 7'b0111011
	WIDTH = 32'sb00000000000000000000000000000111
Module <wb_reg.1> is correct for synthesis.
 
Analyzing module <wb_reg.2> in library <work>.
	ADDR = 32'sb00000000000000000000000000000001
	DEFAULT = 32'sb00000000000000000000000000000000
	WIDTH = 32'sb00000000000000000000000000010000
Module <wb_reg.2> is correct for synthesis.
 
Analyzing module <wb_reg.3> in library <work>.
	ADDR = 32'sb00000000000000000000000000000010
	DEFAULT = 32'sb00000000000000000000000000000000
	WIDTH = 32'sb00000000000000000000000000100000
Module <wb_reg.3> is correct for synthesis.
 
Analyzing module <wb_reg.4> in library <work>.
	ADDR = 32'sb00000000000000000000000000000011
	DEFAULT = 32'sb00000000000000000000000000000000
	WIDTH = 32'sb00000000000000000000000000010000
Module <wb_reg.4> is correct for synthesis.
 
Analyzing module <wb_reg.5> in library <work>.
	ADDR = 32'sb00000000000000000000000000000100
	DEFAULT = 32'sb00000000000000000000000000000000
	WIDTH = 32'sb00000000000000000000000000100000
Module <wb_reg.5> is correct for synthesis.
 
Analyzing module <wb_reg.6> in library <work>.
	ADDR = 32'sb00000000000000000000000000000101
	DEFAULT = 32'sb00000000000000000000000000000000
	WIDTH = 32'sb00000000000000000000000000001001
Module <wb_reg.6> is correct for synthesis.
 
Analyzing module <wb_reg.7> in library <work>.
	ADDR = 32'sb00000000000000000000000000000110
	DEFAULT = 32'sb00000000000000000000000000000000
	WIDTH = 32'sb00000000000000000000000000001101
Module <wb_reg.7> is correct for synthesis.
 
Analyzing module <wb_reg.8> in library <work>.
	ADDR = 32'sb00000000000000000000000000000111
	DEFAULT = 32'sb00000000000000000000000000000000
	WIDTH = 32'sb00000000000000000000000000010000
Module <wb_reg.8> is correct for synthesis.
 
Analyzing module <eth_miim> in library <work>.
Module <eth_miim> is correct for synthesis.
 
Analyzing module <eth_clockgen> in library <work>.
Module <eth_clockgen> is correct for synthesis.
 
Analyzing module <eth_shiftreg> in library <work>.
Module <eth_shiftreg> is correct for synthesis.
 
Analyzing module <eth_outputcontrol> in library <work>.
Module <eth_outputcontrol> is correct for synthesis.
 
Analyzing module <wb_reg.9> in library <work>.
	ADDR = 32'sb00000000000000000000000000001011
	DEFAULT = 32'sb00000000000000000000000000000000
	WIDTH = 32'sb00000000000000000000000000010000
Module <wb_reg.9> is correct for synthesis.
 
Analyzing module <wb_reg.10> in library <work>.
	ADDR = 32'sb00000000000000000000000000001100
	DEFAULT = 32'sb00000000000000000000000000000000
	WIDTH = 32'sb00000000000000000000000000010000
Module <wb_reg.10> is correct for synthesis.
 
Analyzing module <rxmac_to_ll8> in library <work>.
	XFER_ACTIVE = 32'sb00000000000000000000000000000001
	XFER_ERROR = 32'sb00000000000000000000000000000010
	XFER_ERROR2 = 32'sb00000000000000000000000000000011
	XFER_IDLE = 32'sb00000000000000000000000000000000
	XFER_OVERRUN = 32'sb00000000000000000000000000000100
	XFER_OVERRUN2 = 32'sb00000000000000000000000000000101
Module <rxmac_to_ll8> is correct for synthesis.
 
Analyzing module <ll8_to_fifo19> in library <work>.
	XFER_EMPTY = 32'sb00000000000000000000000000000000
	XFER_HALF = 32'sb00000000000000000000000000000001
	XFER_HALF_WRITE = 32'sb00000000000000000000000000000011
Module <ll8_to_fifo19> is correct for synthesis.
 
Analyzing module <ll8_shortfifo> in library <work>.
Module <ll8_shortfifo> is correct for synthesis.
 
Analyzing module <fifo_short.7> in library <work>.
	WIDTH = 32'sb00000000000000000000000000001011
Module <fifo_short.7> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <gen_srl16[0].srl16e> in unit <fifo_short.7>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[1].srl16e> in unit <fifo_short.7>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[2].srl16e> in unit <fifo_short.7>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[3].srl16e> in unit <fifo_short.7>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[4].srl16e> in unit <fifo_short.7>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[5].srl16e> in unit <fifo_short.7>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[6].srl16e> in unit <fifo_short.7>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[7].srl16e> in unit <fifo_short.7>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[8].srl16e> in unit <fifo_short.7>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[9].srl16e> in unit <fifo_short.7>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[10].srl16e> in unit <fifo_short.7>.
Analyzing module <fifo_short.2> in library <work>.
	WIDTH = 32'sb00000000000000000000000000010011
Module <fifo_short.2> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <gen_srl16[0].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[1].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[2].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[3].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[4].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[5].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[6].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[7].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[8].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[9].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[10].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[11].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[12].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[13].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[14].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[15].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[16].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[17].srl16e> in unit <fifo_short.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[18].srl16e> in unit <fifo_short.2>.
Analyzing module <fifo19_rxrealign> in library <work>.
	RXRE_DUMMY = 32'sb00000000000000000000000000000000
	RXRE_PKT = 32'sb00000000000000000000000000000001
Module <fifo19_rxrealign> is correct for synthesis.
 
Analyzing module <fifo19_to_fifo36> in library <work>.
	LE = 32'sb00000000000000000000000000000000
Module <fifo19_to_fifo36> is correct for synthesis.
 
Analyzing module <fifo_2clock_cascade.1> in library <work>.
	SIZE = 32'sb00000000000000000000000000001011
	WIDTH = 32'sb00000000000000000000000000100100
Module <fifo_2clock_cascade.1> is correct for synthesis.
 
Analyzing module <fifo_2clock.1> in library <work>.
	SIZE = 32'sb00000000000000000000000000001011
	WIDTH = 32'sb00000000000000000000000000100100
Module <fifo_2clock.1> is correct for synthesis.
 
Analyzing module <fifo_2clock_cascade.2> in library <work>.
	SIZE = 32'sb00000000000000000000000000001001
	WIDTH = 32'sb00000000000000000000000000100100
Module <fifo_2clock_cascade.2> is correct for synthesis.
 
Analyzing module <fifo_2clock.2> in library <work>.
	SIZE = 32'sb00000000000000000000000000001001
	WIDTH = 32'sb00000000000000000000000000100100
WARNING:Xst:2211 - "../../../coregen/fifo_xlnx_512x36_2clk.v" line 41: Instantiating black box module <fifo_xlnx_512x36_2clk>.
Module <fifo_2clock.2> is correct for synthesis.
 
Analyzing module <ethtx_realign> in library <work>.
	RE_DONE = 32'sb00000000000000000000000000000010
	RE_HELD = 32'sb00000000000000000000000000000001
	RE_IDLE = 32'sb00000000000000000000000000000000
Module <ethtx_realign> is correct for synthesis.
 
Analyzing module <fifo36_to_ll8> in library <work>.
Module <fifo36_to_ll8> is correct for synthesis.
 
Analyzing module <ll8_to_txmac> in library <work>.
	XFER_ACTIVE = 32'sb00000000000000000000000000000001
	XFER_DROP = 32'sb00000000000000000000000000000100
	XFER_IDLE = 32'sb00000000000000000000000000000000
	XFER_UNDERRUN = 32'sb00000000000000000000000000000011
	XFER_WAIT1 = 32'sb00000000000000000000000000000010
Module <ll8_to_txmac> is correct for synthesis.
 
Analyzing module <settings_bus> in library <work>.
	AWIDTH = 32'sb00000000000000000000000000010000
	DWIDTH = 32'sb00000000000000000000000000100000
Module <settings_bus> is correct for synthesis.
 
Analyzing module <settings_bus_crossclock> in library <work>.
	FLOW_CTRL = 32'sb00000000000000000000000000000001
WARNING:Xst:2211 - "../../../coregen/fifo_xlnx_16x40_2clk.v" line 31: Instantiating black box module <fifo_xlnx_16x40_2clk>.
Module <settings_bus_crossclock> is correct for synthesis.
 
Analyzing module <user_settings> in library <work>.
	BASE = 32'sb00000000000000000000000000001000
Module <user_settings> is correct for synthesis.
 
Analyzing module <setting_reg.18> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000001000
	width = 32'sb00000000000000000000000000001000
Module <setting_reg.18> is correct for synthesis.
 
Analyzing module <setting_reg.19> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000001001
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.19> is correct for synthesis.
 
Analyzing module <settings_fifo_ctrl> in library <work>.
	ACK_SID = 32'sb00000000000000000000000000000000
	EVENT_CMD = 32'sb00000000000000000000000000000001
	LOAD_CMD = 32'sb00000000000000000000000000000000
	PROT_DEST = 32'sb00000000000000000000000000000011
	PROT_HDR = 32'sb00000000000000000000000000000001
	READ_DATA = 32'sb00000000000000000000000000001001
	READ_HDR = 32'sb00000000000000000000000000001000
	READ_LINE0 = 32'sb00000000000000000000000000000000
	START_STATE = 32'sb00000000000000000000000000000000
	STORE_CMD = 32'sb00000000000000000000000000001011
	VITA_CID0 = 32'sb00000000000000000000000000000011
	VITA_CID1 = 32'sb00000000000000000000000000000100
	VITA_HDR = 32'sb00000000000000000000000000000001
	VITA_SID = 32'sb00000000000000000000000000000010
	VITA_TSF0 = 32'sb00000000000000000000000000000110
	VITA_TSF1 = 32'sb00000000000000000000000000000111
	VITA_TSI = 32'sb00000000000000000000000000000101
	WAIT_EOF = 32'sb00000000000000000000000000001010
	WRITE_PKT_HDR = 32'sb00000000000000000000000000000000
	WRITE_PROT_HDR = 32'sb00000000000000000000000000000000
	WRITE_RB_DATA = 32'sb00000000000000000000000000000100
	WRITE_RB_HDR = 32'sb00000000000000000000000000000011
	WRITE_VRT_HDR = 32'sb00000000000000000000000000000001
	WRITE_VRT_SID = 32'sb00000000000000000000000000000010
	XPORT_HDR = 32'sb00000000000000000000000000000001
Module <settings_fifo_ctrl> is correct for synthesis.
 
Analyzing module <shortfifo.1> in library <work>.
	WIDTH = 32'sb00000000000000000000000010000001
Module <shortfifo.1> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <gen_srl16[0].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[1].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[2].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[3].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[4].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[5].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[6].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[7].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[8].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[9].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[10].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[11].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[12].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[13].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[14].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[15].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[16].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[17].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[18].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[19].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[20].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[21].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[22].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[23].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[24].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[25].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[26].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[27].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[28].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[29].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[30].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[31].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[32].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[33].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[34].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[35].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[36].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[37].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[38].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[39].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[40].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[41].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[42].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[43].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[44].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[45].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[46].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[47].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[48].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[49].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[50].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[51].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[52].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[53].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[54].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[55].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[56].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[57].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[58].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[59].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[60].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[61].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[62].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[63].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[64].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[65].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[66].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[67].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[68].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[69].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[70].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[71].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[72].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[73].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[74].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[75].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[76].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[77].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[78].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[79].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[80].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[81].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[82].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[83].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[84].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[85].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[86].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[87].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[88].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[89].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[90].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[91].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[92].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[93].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[94].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[95].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[96].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[97].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[98].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[99].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[100].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[101].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[102].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[103].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[104].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[105].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[106].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[107].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[108].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[109].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[110].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[111].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[112].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[113].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[114].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[115].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[116].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[117].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[118].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[119].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[120].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[121].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[122].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[123].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[124].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[125].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[126].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[127].srl16e> in unit <shortfifo.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[128].srl16e> in unit <shortfifo.1>.
Analyzing module <shortfifo.2> in library <work>.
	WIDTH = 32'sb00000000000000000000000001000000
Module <shortfifo.2> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <gen_srl16[0].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[1].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[2].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[3].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[4].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[5].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[6].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[7].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[8].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[9].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[10].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[11].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[12].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[13].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[14].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[15].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[16].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[17].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[18].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[19].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[20].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[21].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[22].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[23].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[24].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[25].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[26].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[27].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[28].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[29].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[30].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[31].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[32].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[33].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[34].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[35].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[36].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[37].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[38].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[39].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[40].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[41].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[42].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[43].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[44].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[45].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[46].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[47].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[48].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[49].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[50].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[51].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[52].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[53].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[54].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[55].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[56].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[57].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[58].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[59].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[60].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[61].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[62].srl16e> in unit <shortfifo.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[63].srl16e> in unit <shortfifo.2>.
Analyzing module <time_compare> in library <work>.
Module <time_compare> is correct for synthesis.
 
Analyzing module <setting_reg.1> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000010001
	width = 32'sb00000000000000000000000000000001
Module <setting_reg.1> is correct for synthesis.
 
Analyzing module <setting_reg.2> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000000000
	width = 32'sb00000000000000000000000000001000
Module <setting_reg.2> is correct for synthesis.
 
Analyzing module <setting_reg.3> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000000001
	width = 32'sb00000000000000000000000000001000
Module <setting_reg.3> is correct for synthesis.
 
Analyzing module <setting_reg.4> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000000010
	width = 32'sb00000000000000000000000000001000
Module <setting_reg.4> is correct for synthesis.
 
Analyzing module <setting_reg.5> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000000100
	width = 32'sb00000000000000000000000000000001
Module <setting_reg.5> is correct for synthesis.
 
Analyzing module <setting_reg.6> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000000101
	width = 32'sb00000000000000000000000000000001
Module <setting_reg.6> is correct for synthesis.
 
Analyzing module <setting_reg.7> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000000011
	width = 32'sb00000000000000000000000000001000
Module <setting_reg.7> is correct for synthesis.
 
Analyzing module <setting_reg.8> in library <work>.
	at_reset = 8'b00011110
	my_addr = 32'sb00000000000000000000000000000110
	width = 32'sb00000000000000000000000000001000
Module <setting_reg.8> is correct for synthesis.
 
Analyzing module <pic> in library <work>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
	Calling function <trigger>.
"../../../control_lib/pic.v" line 145: Found FullParallel Case directive in module <pic>.
"../../../control_lib/pic.v" line 166: Found FullParallel Case directive in module <pic>.
Module <pic> is correct for synthesis.
 
Analyzing module <priority_enc> in library <work>.
Module <priority_enc> is correct for synthesis.
 
Analyzing module <quad_uart> in library <work>.
	RXDEPTH = 32'sb00000000000000000000000000000011
	SUART_CLKDIV = 32'sb00000000000000000000000000000000
	SUART_RXCHAR = 32'sb00000000000000000000000000000100
	SUART_RXLEVEL = 32'sb00000000000000000000000000000010
	SUART_TXCHAR = 32'sb00000000000000000000000000000011
	SUART_TXLEVEL = 32'sb00000000000000000000000000000001
	TXDEPTH = 32'sb00000000000000000000000000000011
Module <quad_uart> is correct for synthesis.
 
Analyzing module <simple_uart_tx> in library <work>.
	DEPTH = 32'sb00000000000000000000000000000011
Module <simple_uart_tx> is correct for synthesis.
 
Analyzing module <medfifo> in library <work>.
	DEPTH = 32'sb00000000000000000000000000000011
	NUM_FIFOS = 32'sb00000000000000000000000000001000
	WIDTH = 32'sb00000000000000000000000000001000
Module <medfifo> is correct for synthesis.
 
Analyzing module <shortfifo.3> in library <work>.
	WIDTH = 32'sb00000000000000000000000000001000
Module <shortfifo.3> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <gen_srl16[0].srl16e> in unit <shortfifo.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[1].srl16e> in unit <shortfifo.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[2].srl16e> in unit <shortfifo.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[3].srl16e> in unit <shortfifo.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[4].srl16e> in unit <shortfifo.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[5].srl16e> in unit <shortfifo.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[6].srl16e> in unit <shortfifo.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[7].srl16e> in unit <shortfifo.3>.
Analyzing module <simple_uart_rx> in library <work>.
	DEPTH = 32'sb00000000000000000000000000000011
Module <simple_uart_rx> is correct for synthesis.
 
Analyzing module <s3a_icap_wb> in library <work>.
	ICAP_IDLE = 32'sb00000000000000000000000000000000
	ICAP_RD0 = 32'sb00000000000000000000000000000010
	ICAP_RD1 = 32'sb00000000000000000000000000000011
	ICAP_WR0 = 32'sb00000000000000000000000000000001
	ICAP_WR1 = 32'sb00000000000000000000000000000101
Module <s3a_icap_wb> is correct for synthesis.
 
Analyzing module <spi_top> in library <work>.
Module <spi_top> is correct for synthesis.
 
Analyzing module <spi_clgen> in library <work>.
Module <spi_clgen> is correct for synthesis.
 
Analyzing module <spi_shift> in library <work>.
Module <spi_shift> is correct for synthesis.
 
Analyzing module <rx_frontend> in library <work>.
	BASE = 32'sb00000000000000000000000000011000
	IQCOMP_EN = 32'sb00000000000000000000000000000001
Module <rx_frontend> is correct for synthesis.
 
Analyzing module <setting_reg.20> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000011000
	width = 32'sb00000000000000000000000000000001
Module <setting_reg.20> is correct for synthesis.
 
Analyzing module <setting_reg.21> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000011001
	width = 32'sb00000000000000000000000000010010
Module <setting_reg.21> is correct for synthesis.
 
Analyzing module <setting_reg.22> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000011010
	width = 32'sb00000000000000000000000000010010
Module <setting_reg.22> is correct for synthesis.
 
Analyzing module <rx_dcoffset.1> in library <work>.
	ADDR = 32'sb00000000000000000000000000011011
	WIDTH = 32'sb00000000000000000000000000010010
	alpha_shift = 32'sb00000000000000000000000000010100
	int_width = 32'sb00000000000000000000000000100110
Module <rx_dcoffset.1> is correct for synthesis.
 
Analyzing module <round_sd.2> in library <work>.
	DISABLE_SD = 32'sb00000000000000000000000000000000
	ERR_WIDTH = 32'sb00000000000000000000000000010101
	WIDTH_IN = 32'sb00000000000000000000000000100110
	WIDTH_OUT = 32'sb00000000000000000000000000010010
Module <round_sd.2> is correct for synthesis.
 
Analyzing module <sign_extend.6> in library <work>.
	bits_in = 32'sb00000000000000000000000000010101
	bits_out = 32'sb00000000000000000000000000100110
Module <sign_extend.6> is correct for synthesis.
 
Analyzing module <add2_and_clip_reg.3> in library <work>.
	WIDTH = 32'sb00000000000000000000000000100110
Module <add2_and_clip_reg.3> is correct for synthesis.
 
Analyzing module <add2_and_clip.3> in library <work>.
	WIDTH = 32'sb00000000000000000000000000100110
Module <add2_and_clip.3> is correct for synthesis.
 
Analyzing module <clip.6> in library <work>.
	bits_in = 32'sb00000000000000000000000000100111
	bits_out = 32'sb00000000000000000000000000100110
Module <clip.6> is correct for synthesis.
 
Analyzing module <round.3> in library <work>.
	bits_in = 32'sb00000000000000000000000000100110
	bits_out = 32'sb00000000000000000000000000010010
	round_to_nearest = 32'sb00000000000000000000000000000001
	round_to_zero = 32'sb00000000000000000000000000000000
	trunc = 32'sb00000000000000000000000000000000
Module <round.3> is correct for synthesis.
 
Analyzing module <add2_and_clip_reg.2> in library <work>.
	WIDTH = 32'sb00000000000000000000000000010010
Module <add2_and_clip_reg.2> is correct for synthesis.
 
Analyzing module <add2_and_clip.2> in library <work>.
	WIDTH = 32'sb00000000000000000000000000010010
Module <add2_and_clip.2> is correct for synthesis.
 
Analyzing module <clip.4> in library <work>.
	bits_in = 32'sb00000000000000000000000000010011
	bits_out = 32'sb00000000000000000000000000010010
Module <clip.4> is correct for synthesis.
 
Analyzing module <rx_dcoffset.2> in library <work>.
	ADDR = 32'sb00000000000000000000000000011100
	WIDTH = 32'sb00000000000000000000000000010010
	alpha_shift = 32'sb00000000000000000000000000010100
	int_width = 32'sb00000000000000000000000000100110
Module <rx_dcoffset.2> is correct for synthesis.
 
Analyzing module <add2_and_clip_reg.1> in library <work>.
	WIDTH = 32'sb00000000000000000000000000011000
Module <add2_and_clip_reg.1> is correct for synthesis.
 
Analyzing module <add2_and_clip.1> in library <work>.
	WIDTH = 32'sb00000000000000000000000000011000
Module <add2_and_clip.1> is correct for synthesis.
 
Analyzing module <clip.1> in library <work>.
	bits_in = 32'sb00000000000000000000000000011001
	bits_out = 32'sb00000000000000000000000000011000
Module <clip.1> is correct for synthesis.
 
Analyzing module <ddc_chain.1> in library <work>.
	BASE = 32'sb00000000000000000000000000110000
	DSPNO = 32'sb00000000000000000000000000000000
	WIDTH = 32'sb00000000000000000000000000011000
	cwidth = 32'sb00000000000000000000000000011001
	zwidth = 32'sb00000000000000000000000000011000
Module <ddc_chain.1> is correct for synthesis.
 
Analyzing module <setting_reg.23> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000110000
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.23> is correct for synthesis.
 
Analyzing module <setting_reg.24> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000110001
	width = 32'sb00000000000000000000000000010010
Module <setting_reg.24> is correct for synthesis.
 
Analyzing module <setting_reg.25> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000110010
	width = 32'sb00000000000000000000000000001010
Module <setting_reg.25> is correct for synthesis.
 
Analyzing module <setting_reg.26> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000110011
	width = 32'sb00000000000000000000000000000010
Module <setting_reg.26> is correct for synthesis.
 
Analyzing module <sign_extend.1> in library <work>.
	bits_in = 32'sb00000000000000000000000000011000
	bits_out = 32'sb00000000000000000000000000011001
Module <sign_extend.1> is correct for synthesis.
 
Analyzing module <cordic_z24.1> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011001
	c00 = 23'b01000000000000000000000
	c01 = 23'b00100101110010000000101
	c02 = 23'b00010011111101100111000
	c03 = 23'b00001010001000100010010
	c04 = 23'b00000101000101100001101
	c05 = 23'b00000010100010111011000
	c06 = 23'b00000001010001011110110
	c07 = 23'b00000000101000101111100
	c08 = 23'b00000000010100010111110
	c09 = 23'b00000000001010001011111
	c10 = 23'b00000000000101000110000
	c11 = 23'b00000000000010100011000
	c12 = 23'b00000000000001010001100
	c13 = 23'b00000000000000101000110
	c14 = 23'b00000000000000010100011
	c15 = 23'b00000000000000001010001
	c16 = 23'b00000000000000000101001
	c17 = 23'b00000000000000000010100
	c18 = 23'b00000000000000000001010
	c19 = 23'b00000000000000000000101
	c20 = 23'b00000000000000000000011
	c21 = 23'b00000000000000000000001
	c22 = 23'b00000000000000000000001
	c23 = 23'b00000000000000000000000
	stages = 32'sb00000000000000000000000000010011
	zwidth = 32'sb00000000000000000000000000011000
Module <cordic_z24.1> is correct for synthesis.
 
Analyzing module <cordic_stage.1> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000000000
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.1> is correct for synthesis.
 
Analyzing module <cordic_stage.2> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000000001
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.2> is correct for synthesis.
 
Analyzing module <cordic_stage.3> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000000010
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.3> is correct for synthesis.
 
Analyzing module <cordic_stage.4> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000000011
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.4> is correct for synthesis.
 
Analyzing module <cordic_stage.5> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000000100
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.5> is correct for synthesis.
 
Analyzing module <cordic_stage.6> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000000101
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.6> is correct for synthesis.
 
Analyzing module <cordic_stage.7> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000000110
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.7> is correct for synthesis.
 
Analyzing module <cordic_stage.8> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000000111
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.8> is correct for synthesis.
 
Analyzing module <cordic_stage.9> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000001000
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.9> is correct for synthesis.
 
Analyzing module <cordic_stage.10> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000001001
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.10> is correct for synthesis.
 
Analyzing module <cordic_stage.11> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000001010
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.11> is correct for synthesis.
 
Analyzing module <cordic_stage.12> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000001011
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.12> is correct for synthesis.
 
Analyzing module <cordic_stage.13> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000001100
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.13> is correct for synthesis.
 
Analyzing module <cordic_stage.14> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000001101
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.14> is correct for synthesis.
 
Analyzing module <cordic_stage.15> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000001110
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.15> is correct for synthesis.
 
Analyzing module <cordic_stage.16> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000001111
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.16> is correct for synthesis.
 
Analyzing module <cordic_stage.17> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000010000
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.17> is correct for synthesis.
 
Analyzing module <cordic_stage.18> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000010001
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.18> is correct for synthesis.
 
Analyzing module <cordic_stage.19> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000010010
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.19> is correct for synthesis.
 
Analyzing module <cordic_stage.20> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011011
	shift = 32'sb00000000000000000000000000010011
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.20> is correct for synthesis.
 
Analyzing module <clip_reg.1> in library <work>.
	STROBED = 1'b0
	bits_in = 32'sb00000000000000000000000000011001
	bits_out = 32'sb00000000000000000000000000011000
Module <clip_reg.1> is correct for synthesis.
 
Analyzing module <cic_strober.1> in library <work>.
	WIDTH = 32'sb00000000000000000000000000001000
Module <cic_strober.1> is correct for synthesis.
 
Analyzing module <cic_decim> in library <work>.
	N = 32'sb00000000000000000000000000000100
	bw = 32'sb00000000000000000000000000011000
	log2_of_max_rate = 32'sb00000000000000000000000000000111
	maxbitgain = 32'sb00000000000000000000000000011100
Module <cic_decim> is correct for synthesis.
 
Analyzing module <sign_extend.2> in library <work>.
	bits_in = 32'sb00000000000000000000000000011000
	bits_out = 32'sb00000000000000000000000000110100
Module <sign_extend.2> is correct for synthesis.
 
Analyzing module <cic_dec_shifter> in library <work>.
	bw = 32'sb00000000000000000000000000011000
	maxbitgain = 32'sb00000000000000000000000000011100
	Calling function <bitgain>.
Module <cic_dec_shifter> is correct for synthesis.
 
Analyzing module <small_hb_dec> in library <work>.
	ACCWIDTH = 32'sb00000000000000000000000000011110
	INTWIDTH = 32'sb00000000000000000000000000010001
	WIDTH = 32'sb00000000000000000000000000011000
Module <small_hb_dec> is correct for synthesis.
 
Analyzing module <round_sd.3> in library <work>.
	DISABLE_SD = 32'sb00000000000000000000000000000000
	ERR_WIDTH = 32'sb00000000000000000000000000001000
	WIDTH_IN = 32'sb00000000000000000000000000011000
	WIDTH_OUT = 32'sb00000000000000000000000000010001
Module <round_sd.3> is correct for synthesis.
 
Analyzing module <sign_extend.7> in library <work>.
	bits_in = 32'sb00000000000000000000000000001000
	bits_out = 32'sb00000000000000000000000000011000
Module <sign_extend.7> is correct for synthesis.
 
Analyzing module <round.4> in library <work>.
	bits_in = 32'sb00000000000000000000000000011000
	bits_out = 32'sb00000000000000000000000000010001
	round_to_nearest = 32'sb00000000000000000000000000000001
	round_to_zero = 32'sb00000000000000000000000000000000
	trunc = 32'sb00000000000000000000000000000000
Module <round.4> is correct for synthesis.
 
Analyzing module <round_sd.4> in library <work>.
	DISABLE_SD = 32'sb00000000000000000000000000000000
	ERR_WIDTH = 32'sb00000000000000000000000000000110
	WIDTH_IN = 32'sb00000000000000000000000000011110
	WIDTH_OUT = 32'sb00000000000000000000000000011001
Module <round_sd.4> is correct for synthesis.
 
Analyzing module <sign_extend.8> in library <work>.
	bits_in = 32'sb00000000000000000000000000000110
	bits_out = 32'sb00000000000000000000000000011110
Module <sign_extend.8> is correct for synthesis.
 
Analyzing module <add2_and_clip_reg.4> in library <work>.
	WIDTH = 32'sb00000000000000000000000000011110
Module <add2_and_clip_reg.4> is correct for synthesis.
 
Analyzing module <add2_and_clip.4> in library <work>.
	WIDTH = 32'sb00000000000000000000000000011110
Module <add2_and_clip.4> is correct for synthesis.
 
Analyzing module <clip.7> in library <work>.
	bits_in = 32'sb00000000000000000000000000011111
	bits_out = 32'sb00000000000000000000000000011110
Module <clip.7> is correct for synthesis.
 
Analyzing module <round.5> in library <work>.
	bits_in = 32'sb00000000000000000000000000011110
	bits_out = 32'sb00000000000000000000000000011001
	round_to_nearest = 32'sb00000000000000000000000000000001
	round_to_zero = 32'sb00000000000000000000000000000000
	trunc = 32'sb00000000000000000000000000000000
Module <round.5> is correct for synthesis.
 
Analyzing module <hb_dec> in library <work>.
	ACCWIDTH = 32'sb00000000000000000000000000011011
	INTWIDTH = 32'sb00000000000000000000000000010001
	SHIFT_FACTOR = 32'sb00000000000000000000000000000110
	WIDTH = 32'sb00000000000000000000000000011000
Module <hb_dec> is correct for synthesis.
 
Analyzing module <srl.1> in library <work>.
	WIDTH = 32'sb00000000000000000000000000010001
Module <srl.1> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <gen_srl[0].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[1].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[2].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[3].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[4].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[5].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[6].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[7].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[8].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[9].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[10].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[11].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[12].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[13].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[14].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[15].srl16e> in unit <srl.1>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[16].srl16e> in unit <srl.1>.
Analyzing module <acc.1> in library <work>.
	IWIDTH = 32'sb00000000000000000000000000011001
	OWIDTH = 32'sb00000000000000000000000000011011
Module <acc.1> is correct for synthesis.
 
Analyzing module <sign_extend.9> in library <work>.
	bits_in = 32'sb00000000000000000000000000011001
	bits_out = 32'sb00000000000000000000000000011011
Module <sign_extend.9> is correct for synthesis.
 
Analyzing module <sign_extend.3> in library <work>.
	bits_in = 32'sb00000000000000000000000000010001
	bits_out = 32'sb00000000000000000000000000010101
Module <sign_extend.3> is correct for synthesis.
 
Analyzing module <round_sd.1> in library <work>.
	DISABLE_SD = 32'sb00000000000000000000000000000000
	ERR_WIDTH = 32'sb00000000000000000000000000001001
	WIDTH_IN = 32'sb00000000000000000000000000011000
	WIDTH_OUT = 32'sb00000000000000000000000000010000
Module <round_sd.1> is correct for synthesis.
 
Analyzing module <sign_extend.4> in library <work>.
	bits_in = 32'sb00000000000000000000000000001001
	bits_out = 32'sb00000000000000000000000000011000
Module <sign_extend.4> is correct for synthesis.
 
Analyzing module <round.1> in library <work>.
	bits_in = 32'sb00000000000000000000000000011000
	bits_out = 32'sb00000000000000000000000000010000
	round_to_nearest = 32'sb00000000000000000000000000000001
	round_to_zero = 32'sb00000000000000000000000000000000
	trunc = 32'sb00000000000000000000000000000000
Module <round.1> is correct for synthesis.
 
Analyzing module <dsp_rx_glue.1> in library <work>.
	DSPNO = 32'sb00000000000000000000000000000000
	WIDTH = 32'sb00000000000000000000000000011000
Module <dsp_rx_glue.1> is correct for synthesis.
 
Analyzing module <custom_dsp_rx> in library <work>.
	WIDTH = 32'sb00000000000000000000000000011000
Module <custom_dsp_rx> is correct for synthesis.
 
Analyzing module <vita_rx_chain.1> in library <work>.
	BASE = 32'sb00000000000000000000000000100000
	DSP_NUMBER = 32'sb00000000000000000000000000000000
	FIFOSIZE = 32'sb00000000000000000000000000001010
	PROT_ENG_FLAGS = 32'sb00000000000000000000000000000001
	UNIT = 32'sb00000000000000000000000000000000
Module <vita_rx_chain.1> is correct for synthesis.
 
Analyzing module <setting_reg.27> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000101000
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.27> is correct for synthesis.
 
Analyzing module <vita_rx_control.1> in library <work>.
	BASE = 32'sb00000000000000000000000000100000
	IBS_BROKENCHAIN = 32'sb00000000000000000000000000000101
	IBS_IDLE = 32'sb00000000000000000000000000000000
	IBS_LATECMD = 32'sb00000000000000000000000000000110
	IBS_OVERRUN = 32'sb00000000000000000000000000000100
	IBS_RUNNING = 32'sb00000000000000000000000000000010
	IBS_WAITING = 32'sb00000000000000000000000000000001
	IBS_ZEROLEN = 32'sb00000000000000000000000000000111
	WIDTH = 32'sb00000000000000000000000000100000
Module <vita_rx_control.1> is correct for synthesis.
 
Analyzing module <setting_reg.51> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000100000
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.51> is correct for synthesis.
 
Analyzing module <setting_reg.52> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000100001
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.52> is correct for synthesis.
 
Analyzing module <setting_reg.53> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000100010
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.53> is correct for synthesis.
 
Analyzing module <fifo_short.3> in library <work>.
	WIDTH = 32'sb00000000000000000000000001100000
Module <fifo_short.3> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <gen_srl16[0].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[1].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[2].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[3].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[4].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[5].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[6].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[7].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[8].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[9].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[10].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[11].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[12].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[13].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[14].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[15].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[16].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[17].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[18].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[19].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[20].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[21].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[22].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[23].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[24].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[25].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[26].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[27].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[28].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[29].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[30].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[31].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[32].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[33].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[34].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[35].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[36].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[37].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[38].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[39].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[40].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[41].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[42].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[43].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[44].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[45].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[46].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[47].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[48].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[49].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[50].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[51].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[52].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[53].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[54].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[55].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[56].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[57].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[58].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[59].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[60].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[61].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[62].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[63].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[64].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[65].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[66].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[67].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[68].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[69].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[70].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[71].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[72].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[73].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[74].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[75].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[76].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[77].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[78].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[79].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[80].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[81].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[82].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[83].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[84].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[85].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[86].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[87].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[88].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[89].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[90].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[91].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[92].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[93].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[94].srl16e> in unit <fifo_short.3>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[95].srl16e> in unit <fifo_short.3>.
Analyzing module <fifo_short.4> in library <work>.
	WIDTH = 32'sb00000000000000000000000001100101
Module <fifo_short.4> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <gen_srl16[0].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[1].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[2].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[3].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[4].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[5].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[6].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[7].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[8].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[9].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[10].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[11].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[12].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[13].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[14].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[15].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[16].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[17].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[18].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[19].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[20].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[21].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[22].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[23].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[24].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[25].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[26].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[27].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[28].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[29].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[30].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[31].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[32].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[33].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[34].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[35].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[36].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[37].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[38].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[39].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[40].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[41].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[42].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[43].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[44].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[45].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[46].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[47].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[48].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[49].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[50].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[51].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[52].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[53].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[54].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[55].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[56].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[57].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[58].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[59].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[60].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[61].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[62].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[63].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[64].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[65].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[66].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[67].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[68].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[69].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[70].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[71].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[72].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[73].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[74].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[75].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[76].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[77].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[78].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[79].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[80].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[81].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[82].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[83].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[84].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[85].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[86].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[87].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[88].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[89].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[90].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[91].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[92].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[93].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[94].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[95].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[96].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[97].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[98].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[99].srl16e> in unit <fifo_short.4>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[100].srl16e> in unit <fifo_short.4>.
Analyzing module <vita_rx_framer.1> in library <work>.
	BASE = 32'sb00000000000000000000000000100000
	MAXCHAN = 32'sb00000000000000000000000000000001
	SAMP_WIDTH = 32'sb00000000000000000000000001100101
	VITA_ERR_HEADER = 32'sb00000000000000000000000000000111
	VITA_ERR_PAYLOAD = 32'sb00000000000000000000000000001011
	VITA_ERR_STREAMID = 32'sb00000000000000000000000000001000
	VITA_ERR_TICS = 32'sb00000000000000000000000000001001
	VITA_ERR_TICS2 = 32'sb00000000000000000000000000001010
	VITA_ERR_TRAILER = 32'sb00000000000000000000000000001100
	VITA_HEADER = 32'sb00000000000000000000000000000001
	VITA_IDLE = 32'sb00000000000000000000000000000000
	VITA_PAYLOAD = 32'sb00000000000000000000000000000101
	VITA_STREAMID = 32'sb00000000000000000000000000000010
	VITA_TICS = 32'sb00000000000000000000000000000011
	VITA_TICS2 = 32'sb00000000000000000000000000000100
	VITA_TRAILER = 32'sb00000000000000000000000000000110
Module <vita_rx_framer.1> is correct for synthesis.
 
Analyzing module <setting_reg.54> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000100100
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.54> is correct for synthesis.
 
Analyzing module <setting_reg.55> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000100101
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.55> is correct for synthesis.
 
Analyzing module <setting_reg.56> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000100110
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.56> is correct for synthesis.
 
Analyzing module <setting_reg.57> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000100111
	width = 32'sb00000000000000000000000000010000
Module <setting_reg.57> is correct for synthesis.
 
Analyzing module <fifo_short.5> in library <work>.
	WIDTH = 32'sb00000000000000000000000000100010
Module <fifo_short.5> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <gen_srl16[0].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[1].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[2].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[3].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[4].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[5].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[6].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[7].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[8].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[9].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[10].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[11].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[12].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[13].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[14].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[15].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[16].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[17].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[18].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[19].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[20].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[21].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[22].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[23].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[24].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[25].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[26].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[27].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[28].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[29].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[30].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[31].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[32].srl16e> in unit <fifo_short.5>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[33].srl16e> in unit <fifo_short.5>.
Analyzing module <double_buffer> in library <work>.
	BUF_SIZE = 32'sb00000000000000000000000000001010
	IDLE = 32'sb00000000000000000000000000000000
	PRE_READ = 32'sb00000000000000000000000000000001
	READING = 32'sb00000000000000000000000000000010
Module <double_buffer> is correct for synthesis.
 
Analyzing module <dbsm> in library <work>.
	BUFF_ACCESSIBLE = 32'sb00000000000000000000000000000001
	BUFF_ERROR = 32'sb00000000000000000000000000000011
	BUFF_READABLE = 32'sb00000000000000000000000000000010
	BUFF_WRITABLE = 32'sb00000000000000000000000000000000
	PORT_USE_0 = 32'sb00000000000000000000000000000001
	PORT_USE_1 = 32'sb00000000000000000000000000000011
	PORT_WAIT_0 = 32'sb00000000000000000000000000000000
	PORT_WAIT_1 = 32'sb00000000000000000000000000000010
Module <dbsm> is correct for synthesis.
 
Analyzing module <buff_sm.1> in library <work>.
	BUFF_ACCESSIBLE = 32'sb00000000000000000000000000000001
	BUFF_ERROR = 32'sb00000000000000000000000000000011
	BUFF_READABLE = 32'sb00000000000000000000000000000010
	BUFF_WRITABLE = 32'sb00000000000000000000000000000000
	PORT_USE_FLAG = 32'sb00000000000000000000000000000001
Module <buff_sm.1> is correct for synthesis.
 
Analyzing module <buff_sm.2> in library <work>.
	BUFF_ACCESSIBLE = 32'sb00000000000000000000000000000001
	BUFF_ERROR = 32'sb00000000000000000000000000000011
	BUFF_READABLE = 32'sb00000000000000000000000000000010
	BUFF_WRITABLE = 32'sb00000000000000000000000000000000
	PORT_USE_FLAG = 32'sb00000000000000000000000000000011
Module <buff_sm.2> is correct for synthesis.
 
Analyzing module <ram_2port.2> in library <work>.
	AWIDTH = 32'sb00000000000000000000000000001010
	DWIDTH = 32'sb00000000000000000000000000100100
Module <ram_2port.2> is correct for synthesis.
 
Analyzing module <vita_rx_engine_glue.1> in library <work>.
	BUF_SIZE = 32'sb00000000000000000000000000001010
	DSPNO = 32'sb00000000000000000000000000000000
	MAIN_SETTINGS_BASE = 32'sb00000000000000000000000000100011
Module <vita_rx_engine_glue.1> is correct for synthesis.
 
Analyzing module <dspengine_16to8.1> in library <work>.
	BASE = 32'sb00000000000000000000000000100011
	BUF_SIZE = 32'sb00000000000000000000000000001010
	DSP_CONVERT = 32'sb00000000000000000000000000000010
	DSP_CONVERT_DRAIN_PIPE = 32'sb00000000000000000000000000000011
	DSP_DONE = 32'sb00000000000000000000000000000111
	DSP_IDLE = 32'sb00000000000000000000000000000000
	DSP_PARSE_HEADER = 32'sb00000000000000000000000000000001
	DSP_READ_TRAILER = 32'sb00000000000000000000000000000100
	DSP_WRITE_HEADER = 32'sb00000000000000000000000000000110
	DSP_WRITE_TRAILER = 32'sb00000000000000000000000000000101
Module <dspengine_16to8.1> is correct for synthesis.
 
Analyzing module <setting_reg.68> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000100011
	width = 32'sb00000000000000000000000000000001
Module <setting_reg.68> is correct for synthesis.
 
Analyzing module <pipectrl> in library <work>.
	STAGES = 32'sb00000000000000000000000000000010
	TAGWIDTH = 32'sb00000000000000000000000000000010
Module <pipectrl> is correct for synthesis.
 
Analyzing module <pipestage> in library <work>.
	TAGWIDTH = 32'sb00000000000000000000000000000010
Module <pipestage> is correct for synthesis.
 
Analyzing module <clip_reg.3> in library <work>.
	STROBED = 32'sb00000000000000000000000000000001
	bits_in = 32'sb00000000000000000000000000010000
	bits_out = 32'sb00000000000000000000000000001000
Module <clip_reg.3> is correct for synthesis.
 
Analyzing module <clip.5> in library <work>.
	bits_in = 32'sb00000000000000000000000000010000
	bits_out = 32'sb00000000000000000000000000001000
Module <clip.5> is correct for synthesis.
 
Analyzing module <add_routing_header.1> in library <work>.
	PORT_SEL = 32'sb00000000000000000000000000000000
	PROT_ENG_FLAGS = 32'sb00000000000000000000000000000001
Module <add_routing_header.1> is correct for synthesis.
 
Analyzing module <ddc_chain.2> in library <work>.
	BASE = 32'sb00000000000000000000000001100000
	DSPNO = 32'sb00000000000000000000000000000001
	WIDTH = 32'sb00000000000000000000000000011000
	cwidth = 32'sb00000000000000000000000000011001
	zwidth = 32'sb00000000000000000000000000011000
Module <ddc_chain.2> is correct for synthesis.
 
Analyzing module <setting_reg.28> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000001100000
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.28> is correct for synthesis.
 
Analyzing module <setting_reg.29> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000001100001
	width = 32'sb00000000000000000000000000010010
Module <setting_reg.29> is correct for synthesis.
 
Analyzing module <setting_reg.30> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000001100010
	width = 32'sb00000000000000000000000000001010
Module <setting_reg.30> is correct for synthesis.
 
Analyzing module <setting_reg.31> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000001100011
	width = 32'sb00000000000000000000000000000010
Module <setting_reg.31> is correct for synthesis.
 
Analyzing module <dsp_rx_glue.2> in library <work>.
	DSPNO = 32'sb00000000000000000000000000000001
	WIDTH = 32'sb00000000000000000000000000011000
Module <dsp_rx_glue.2> is correct for synthesis.
 
Analyzing module <vita_rx_chain.2> in library <work>.
	BASE = 32'sb00000000000000000000000001010000
	DSP_NUMBER = 32'sb00000000000000000000000000000001
	FIFOSIZE = 32'sb00000000000000000000000000001010
	PROT_ENG_FLAGS = 32'sb00000000000000000000000000000001
	UNIT = 32'sb00000000000000000000000000000010
Module <vita_rx_chain.2> is correct for synthesis.
 
Analyzing module <setting_reg.32> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000001011000
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.32> is correct for synthesis.
 
Analyzing module <vita_rx_control.2> in library <work>.
	BASE = 32'sb00000000000000000000000001010000
	IBS_BROKENCHAIN = 32'sb00000000000000000000000000000101
	IBS_IDLE = 32'sb00000000000000000000000000000000
	IBS_LATECMD = 32'sb00000000000000000000000000000110
	IBS_OVERRUN = 32'sb00000000000000000000000000000100
	IBS_RUNNING = 32'sb00000000000000000000000000000010
	IBS_WAITING = 32'sb00000000000000000000000000000001
	IBS_ZEROLEN = 32'sb00000000000000000000000000000111
	WIDTH = 32'sb00000000000000000000000000100000
Module <vita_rx_control.2> is correct for synthesis.
 
Analyzing module <setting_reg.58> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000001010000
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.58> is correct for synthesis.
 
Analyzing module <setting_reg.59> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000001010001
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.59> is correct for synthesis.
 
Analyzing module <setting_reg.60> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000001010010
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.60> is correct for synthesis.
 
Analyzing module <vita_rx_framer.2> in library <work>.
	BASE = 32'sb00000000000000000000000001010000
	MAXCHAN = 32'sb00000000000000000000000000000001
	SAMP_WIDTH = 32'sb00000000000000000000000001100101
	VITA_ERR_HEADER = 32'sb00000000000000000000000000000111
	VITA_ERR_PAYLOAD = 32'sb00000000000000000000000000001011
	VITA_ERR_STREAMID = 32'sb00000000000000000000000000001000
	VITA_ERR_TICS = 32'sb00000000000000000000000000001001
	VITA_ERR_TICS2 = 32'sb00000000000000000000000000001010
	VITA_ERR_TRAILER = 32'sb00000000000000000000000000001100
	VITA_HEADER = 32'sb00000000000000000000000000000001
	VITA_IDLE = 32'sb00000000000000000000000000000000
	VITA_PAYLOAD = 32'sb00000000000000000000000000000101
	VITA_STREAMID = 32'sb00000000000000000000000000000010
	VITA_TICS = 32'sb00000000000000000000000000000011
	VITA_TICS2 = 32'sb00000000000000000000000000000100
	VITA_TRAILER = 32'sb00000000000000000000000000000110
Module <vita_rx_framer.2> is correct for synthesis.
 
Analyzing module <setting_reg.61> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000001010100
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.61> is correct for synthesis.
 
Analyzing module <setting_reg.62> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000001010101
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.62> is correct for synthesis.
 
Analyzing module <setting_reg.63> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000001010110
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.63> is correct for synthesis.
 
Analyzing module <setting_reg.64> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000001010111
	width = 32'sb00000000000000000000000000010000
Module <setting_reg.64> is correct for synthesis.
 
Analyzing module <vita_rx_engine_glue.2> in library <work>.
	BUF_SIZE = 32'sb00000000000000000000000000001010
	DSPNO = 32'sb00000000000000000000000000000001
	MAIN_SETTINGS_BASE = 32'sb00000000000000000000000001010011
Module <vita_rx_engine_glue.2> is correct for synthesis.
 
Analyzing module <dspengine_16to8.2> in library <work>.
	BASE = 32'sb00000000000000000000000001010011
	BUF_SIZE = 32'sb00000000000000000000000000001010
	DSP_CONVERT = 32'sb00000000000000000000000000000010
	DSP_CONVERT_DRAIN_PIPE = 32'sb00000000000000000000000000000011
	DSP_DONE = 32'sb00000000000000000000000000000111
	DSP_IDLE = 32'sb00000000000000000000000000000000
	DSP_PARSE_HEADER = 32'sb00000000000000000000000000000001
	DSP_READ_TRAILER = 32'sb00000000000000000000000000000100
	DSP_WRITE_HEADER = 32'sb00000000000000000000000000000110
	DSP_WRITE_TRAILER = 32'sb00000000000000000000000000000101
Module <dspengine_16to8.2> is correct for synthesis.
 
Analyzing module <setting_reg.69> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000001010011
	width = 32'sb00000000000000000000000000000001
Module <setting_reg.69> is correct for synthesis.
 
Analyzing module <add_routing_header.2> in library <work>.
	PORT_SEL = 32'sb00000000000000000000000000000010
	PROT_ENG_FLAGS = 32'sb00000000000000000000000000000001
Module <add_routing_header.2> is correct for synthesis.
 
Analyzing module <ext_fifo> in library <work>.
	EXT_WIDTH = 32'sb00000000000000000000000000100100
	FIFO_DEPTH = 32'sb00000000000000000000000000010010
	INT_WIDTH = 32'sb00000000000000000000000000100100
	RAM_DEPTH = 32'sb00000000000000000000000000010010
WARNING:Xst:2211 - "../../../coregen/fifo_xlnx_32x36_2clk.v" line 140: Instantiating black box module <fifo_xlnx_32x36_2clk>.
WARNING:Xst:2211 - "../../../coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 152: Instantiating black box module <fifo_xlnx_512x36_2clk_prog_full>.
Module <ext_fifo> is correct for synthesis.
 
    Set user-defined property "SYN_BLACK_BOX =  1" for instance <fifo_g1.fifo_xlnx_32x36_2clk_i1> in unit <ext_fifo>.
    Set user-defined property "SYN_NOPRUNE =  1" for instance <fifo_g1.fifo_xlnx_32x36_2clk_i1> in unit <ext_fifo>.
Analyzing module <nobl_fifo> in library <work>.
	FIFO_DEPTH = 32'sb00000000000000000000000000010010
	RAM_DEPTH = 32'sb00000000000000000000000000010010
	WIDTH = 32'sb00000000000000000000000000100100
Module <nobl_fifo> is correct for synthesis.
 
Analyzing module <nobl_if> in library <work>.
	DEPTH = 32'sb00000000000000000000000000010010
	WIDTH = 32'sb00000000000000000000000000100100
Module <nobl_if> is correct for synthesis.
 
Analyzing module <bin2gray> in library <work>.
	WIDTH = 32'sb00000000000000000000000000010010
Module <bin2gray> is correct for synthesis.
 
Analyzing module <refill_randomizer> in library <work>.
	BITS = 32'sb00000000000000000000000000000111
Module <refill_randomizer> is correct for synthesis.
 
    Set property "SYN_NOPRUNE = 1" for unit <fifo_xlnx_32x36_2clk>.
Analyzing module <vita_tx_chain> in library <work>.
	BASE = 32'sb00000000000000000000000010010000
	DO_FLOW_CONTROL = 32'sb00000000000000000000000000000001
	DSP_NUMBER = 32'sb00000000000000000000000000000000
	FIFOSIZE = 32'sb00000000000000000000000000001010
	FIFOWIDTH = 32'sb00000000000000000000000001110101
	MAXCHAN = 32'sb00000000000000000000000000000001
	POST_ENGINE_FIFOSIZE = 32'sb00000000000000000000000000001010
	PROT_ENG_FLAGS = 32'sb00000000000000000000000000000001
	REPORT_ERROR = 32'sb00000000000000000000000000000001
	USE_TRANS_HEADER = 32'sb00000000000000000000000000000001
Module <vita_tx_chain> is correct for synthesis.
 
Analyzing module <setting_reg.33> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010010000
	width = 32'sb00000000000000000000000000000001
Module <setting_reg.33> is correct for synthesis.
 
Analyzing module <setting_reg.34> in library <work>.
	at_reset = 32'sb00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010010010
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.34> is correct for synthesis.
 
Analyzing module <vita_tx_deframer> in library <work>.
	BASE = 32'sb00000000000000000000000010010000
	FIFOWIDTH = 32'sb00000000000000000000000001110101
	MAXCHAN = 32'sb00000000000000000000000000000001
	USE_TRANS_HEADER = 32'sb00000000000000000000000000000001
	VITA_CLASSID = 32'sb00000000000000000000000000000011
	VITA_CLASSID2 = 32'sb00000000000000000000000000000100
	VITA_DUMP = 32'sb00000000000000000000000000001011
	VITA_HEADER = 32'sb00000000000000000000000000000001
	VITA_PAYLOAD = 32'sb00000000000000000000000000001000
	VITA_SECS = 32'sb00000000000000000000000000000101
	VITA_STREAMID = 32'sb00000000000000000000000000000010
	VITA_TICS = 32'sb00000000000000000000000000000110
	VITA_TICS2 = 32'sb00000000000000000000000000000111
	VITA_TRAILER = 32'sb00000000000000000000000000001010
	VITA_TRANS_HEADER = 32'sb00000000000000000000000000000000
INFO:Xst:1433 - Contents of array <sample_reg> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
Module <vita_tx_deframer> is correct for synthesis.
 
Analyzing module <fifo_short.6> in library <work>.
	WIDTH = 32'sb00000000000000000000000001110101
Module <fifo_short.6> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <gen_srl16[0].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[1].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[2].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[3].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[4].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[5].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[6].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[7].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[8].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[9].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[10].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[11].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[12].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[13].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[14].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[15].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[16].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[17].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[18].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[19].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[20].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[21].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[22].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[23].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[24].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[25].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[26].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[27].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[28].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[29].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[30].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[31].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[32].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[33].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[34].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[35].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[36].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[37].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[38].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[39].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[40].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[41].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[42].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[43].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[44].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[45].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[46].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[47].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[48].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[49].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[50].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[51].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[52].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[53].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[54].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[55].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[56].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[57].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[58].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[59].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[60].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[61].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[62].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[63].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[64].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[65].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[66].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[67].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[68].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[69].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[70].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[71].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[72].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[73].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[74].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[75].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[76].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[77].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[78].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[79].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[80].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[81].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[82].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[83].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[84].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[85].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[86].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[87].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[88].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[89].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[90].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[91].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[92].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[93].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[94].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[95].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[96].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[97].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[98].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[99].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[100].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[101].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[102].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[103].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[104].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[105].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[106].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[107].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[108].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[109].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[110].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[111].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[112].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[113].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[114].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[115].srl16e> in unit <fifo_short.6>.
    Set user-defined property "INIT =  0000" for instance <gen_srl16[116].srl16e> in unit <fifo_short.6>.
Analyzing module <vita_tx_control> in library <work>.
	BASE = 32'sb00000000000000000000000010010000
	IBS_CONT_BURST = 32'sb00000000000000000000000000000010
	IBS_ERROR = 32'sb00000000000000000000000000000011
	IBS_ERROR_DONE = 32'sb00000000000000000000000000000100
	IBS_ERROR_WAIT = 32'sb00000000000000000000000000000101
	IBS_IDLE = 32'sb00000000000000000000000000000000
	IBS_RUN = 32'sb00000000000000000000000000000001
	MAX_IDLE = 32'sb00000000000011110100001001000000
	WIDTH = 32'sb00000000000000000000000000100000
Module <vita_tx_control> is correct for synthesis.
 
Analyzing module <setting_reg.65> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010010011
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.65> is correct for synthesis.
 
Analyzing module <gen_context_pkt> in library <work>.
	CTXT_DONE = 32'sb00000000000000000000000000001000
	CTXT_FLOWCTRL = 32'sb00000000000000000000000000000111
	CTXT_HEADER = 32'sb00000000000000000000000000000010
	CTXT_IDLE = 32'sb00000000000000000000000000000000
	CTXT_MESSAGE = 32'sb00000000000000000000000000000110
	CTXT_PROT_ENG = 32'sb00000000000000000000000000000001
	CTXT_STREAMID = 32'sb00000000000000000000000000000011
	CTXT_TICS = 32'sb00000000000000000000000000000100
	CTXT_TICS2 = 32'sb00000000000000000000000000000101
	DSP_NUMBER = 32'sb00000000000000000000000000000000
	PROT_ENG_FLAGS = 32'sb00000000000000000000000000000001
Module <gen_context_pkt> is correct for synthesis.
 
Analyzing module <trigger_context_pkt> in library <work>.
	BASE = 32'sb00000000000000000000000010010000
Module <trigger_context_pkt> is correct for synthesis.
 
Analyzing module <setting_reg.66> in library <work>.
	at_reset = 32'sb00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010010100
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.66> is correct for synthesis.
 
Analyzing module <setting_reg.67> in library <work>.
	at_reset = 32'sb00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010010101
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.67> is correct for synthesis.
 
Analyzing module <vita_tx_engine_glue> in library <work>.
	BUF_SIZE = 32'sb00000000000000000000000000001010
	DSPNO = 32'sb00000000000000000000000000000000
	HEADER_OFFSET = 32'sb00000000000000000000000000000001
	MAIN_SETTINGS_BASE = 32'sb00000000000000000000000010010001
Module <vita_tx_engine_glue> is correct for synthesis.
 
Analyzing module <dspengine_8to16> in library <work>.
	BASE = 32'sb00000000000000000000000010010001
	BUF_SIZE = 32'sb00000000000000000000000000001010
	DSP_DONE = 32'sb00000000000000000000000000001010
	DSP_IDLE = 32'sb00000000000000000000000000000000
	DSP_IDLE_RD = 32'sb00000000000000000000000000000001
	DSP_PARSE_HEADER = 32'sb00000000000000000000000000000010
	DSP_READ = 32'sb00000000000000000000000000000011
	DSP_READ_TRAILER = 32'sb00000000000000000000000000000111
	DSP_READ_WAIT = 32'sb00000000000000000000000000000100
	DSP_WRITE_0 = 32'sb00000000000000000000000000000110
	DSP_WRITE_1 = 32'sb00000000000000000000000000000101
	DSP_WRITE_HEADER = 32'sb00000000000000000000000000001001
	DSP_WRITE_TRAILER = 32'sb00000000000000000000000000001000
	HEADER_OFFSET = 32'sb00000000000000000000000000000001
Module <dspengine_8to16> is correct for synthesis.
 
Analyzing module <setting_reg.70> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010010001
	width = 32'sb00000000000000000000000000000001
Module <setting_reg.70> is correct for synthesis.
 
Analyzing module <fifo_cascade.2> in library <work>.
	SIZE = 32'sb00000000000000000000000000001010
	WIDTH = 32'sb00000000000000000000000000100100
Module <fifo_cascade.2> is correct for synthesis.
 
Analyzing module <fifo_long.2> in library <work>.
	EMPTY = 32'sb00000000000000000000000000000000
	NUMLINES = 32'sb00000000000000000000001111111110
	PRE_READ = 32'sb00000000000000000000000000000001
	READING = 32'sb00000000000000000000000000000010
	SIZE = 32'sb00000000000000000000000000001010
	WIDTH = 32'sb00000000000000000000000000100100
Module <fifo_long.2> is correct for synthesis.
 
Analyzing module <duc_chain> in library <work>.
	BASE = 32'sb00000000000000000000000010100000
	DSPNO = 32'sb00000000000000000000000000000000
	WIDTH = 32'sb00000000000000000000000000011000
	cwidth = 32'sb00000000000000000000000000011000
	zwidth = 32'sb00000000000000000000000000011000
Module <duc_chain> is correct for synthesis.
 
Analyzing module <setting_reg.35> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010100000
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.35> is correct for synthesis.
 
Analyzing module <setting_reg.36> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010100001
	width = 32'sb00000000000000000000000000010010
Module <setting_reg.36> is correct for synthesis.
 
Analyzing module <setting_reg.37> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010100010
	width = 32'sb00000000000000000000000000001010
Module <setting_reg.37> is correct for synthesis.
 
Analyzing module <cic_strober.2> in library <work>.
	WIDTH = 32'sb00000000000000000000000000001000
Module <cic_strober.2> is correct for synthesis.
 
Analyzing module <cic_strober.3> in library <work>.
	WIDTH = 32'sb00000000000000000000000000000010
Module <cic_strober.3> is correct for synthesis.
 
Analyzing module <hb_interp> in library <work>.
	ACCWIDTH = 32'sb00000000000000000000000000011000
	CWIDTH = 32'sb00000000000000000000000000010010
	IWIDTH = 32'sb00000000000000000000000000010010
	MWIDTH = 32'sb00000000000000000000000000010110
	OWIDTH = 32'sb00000000000000000000000000010010
Module <hb_interp> is correct for synthesis.
 
Analyzing module <srl.2> in library <work>.
	WIDTH = 32'sb00000000000000000000000000010010
Module <srl.2> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <gen_srl[0].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[1].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[2].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[3].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[4].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[5].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[6].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[7].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[8].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[9].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[10].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[11].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[12].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[13].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[14].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[15].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[16].srl16e> in unit <srl.2>.
    Set user-defined property "INIT =  0000" for instance <gen_srl[17].srl16e> in unit <srl.2>.
Analyzing module <add2_reg> in library <work>.
	WIDTH = 32'sb00000000000000000000000000010010
Module <add2_reg> is correct for synthesis.
 
Analyzing module <add2> in library <work>.
	WIDTH = 32'sb00000000000000000000000000010010
Module <add2> is correct for synthesis.
 
Analyzing module <add2_and_round_reg.1> in library <work>.
	WIDTH = 32'sb00000000000000000000000000010110
Module <add2_and_round_reg.1> is correct for synthesis.
 
Analyzing module <add2_and_round.1> in library <work>.
	WIDTH = 32'sb00000000000000000000000000010110
Module <add2_and_round.1> is correct for synthesis.
 
Analyzing module <acc.2> in library <work>.
	IWIDTH = 32'sb00000000000000000000000000010110
	OWIDTH = 32'sb00000000000000000000000000011000
Module <acc.2> is correct for synthesis.
 
Analyzing module <sign_extend.10> in library <work>.
	bits_in = 32'sb00000000000000000000000000010110
	bits_out = 32'sb00000000000000000000000000011000
Module <sign_extend.10> is correct for synthesis.
 
Analyzing module <clip.2> in library <work>.
	bits_in = 32'sb00000000000000000000000000011000
	bits_out = 32'sb00000000000000000000000000010011
Module <clip.2> is correct for synthesis.
 
Analyzing module <round.2> in library <work>.
	bits_in = 32'sb00000000000000000000000000010011
	bits_out = 32'sb00000000000000000000000000010010
	round_to_nearest = 32'sb00000000000000000000000000000001
	round_to_zero = 32'sb00000000000000000000000000000000
	trunc = 32'sb00000000000000000000000000000000
Module <round.2> is correct for synthesis.
 
Analyzing module <small_hb_int> in library <work>.
	MWIDTH = 32'sb00000000000000000000000000100100
	WIDTH = 32'sb00000000000000000000000000010010
Module <small_hb_int> is correct for synthesis.
 
Analyzing module <add2_and_round_reg.2> in library <work>.
	WIDTH = 32'sb00000000000000000000000000010010
Module <add2_and_round_reg.2> is correct for synthesis.
 
Analyzing module <add2_and_round.2> in library <work>.
	WIDTH = 32'sb00000000000000000000000000010010
Module <add2_and_round.2> is correct for synthesis.
 
Analyzing module <acc.3> in library <work>.
	IWIDTH = 32'sb00000000000000000000000000100100
	OWIDTH = 32'sb00000000000000000000000000100101
Module <acc.3> is correct for synthesis.
 
Analyzing module <sign_extend.11> in library <work>.
	bits_in = 32'sb00000000000000000000000000100100
	bits_out = 32'sb00000000000000000000000000100101
Module <sign_extend.11> is correct for synthesis.
 
Analyzing module <round_reg> in library <work>.
	bits_in = 32'sb00000000000000000000000000100101
	bits_out = 32'sb00000000000000000000000000010101
Module <round_reg> is correct for synthesis.
 
Analyzing module <round.6> in library <work>.
	bits_in = 32'sb00000000000000000000000000100101
	bits_out = 32'sb00000000000000000000000000010101
	round_to_nearest = 32'sb00000000000000000000000000000001
	round_to_zero = 32'sb00000000000000000000000000000000
	trunc = 32'sb00000000000000000000000000000000
Module <round.6> is correct for synthesis.
 
Analyzing module <clip_reg.2> in library <work>.
	STROBED = 1'b0
	bits_in = 32'sb00000000000000000000000000010101
	bits_out = 32'sb00000000000000000000000000010010
Module <clip_reg.2> is correct for synthesis.
 
Analyzing module <clip.3> in library <work>.
	bits_in = 32'sb00000000000000000000000000010101
	bits_out = 32'sb00000000000000000000000000010010
Module <clip.3> is correct for synthesis.
 
Analyzing module <cic_interp> in library <work>.
	N = 32'sb00000000000000000000000000000100
	bw = 32'sb00000000000000000000000000010010
	log2_of_max_rate = 32'sb00000000000000000000000000000111
	maxbitgain = 32'sb00000000000000000000000000010101
Module <cic_interp> is correct for synthesis.
 
Analyzing module <sign_extend.5> in library <work>.
	bits_in = 32'sb00000000000000000000000000010010
	bits_out = 32'sb00000000000000000000000000100111
Module <sign_extend.5> is correct for synthesis.
 
Analyzing module <cic_int_shifter> in library <work>.
	bw = 32'sb00000000000000000000000000010010
	maxbitgain = 32'sb00000000000000000000000000010101
	Calling function <bitgain>.
Module <cic_int_shifter> is correct for synthesis.
 
Analyzing module <cordic_z24.2> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011000
	c00 = 23'b01000000000000000000000
	c01 = 23'b00100101110010000000101
	c02 = 23'b00010011111101100111000
	c03 = 23'b00001010001000100010010
	c04 = 23'b00000101000101100001101
	c05 = 23'b00000010100010111011000
	c06 = 23'b00000001010001011110110
	c07 = 23'b00000000101000101111100
	c08 = 23'b00000000010100010111110
	c09 = 23'b00000000001010001011111
	c10 = 23'b00000000000101000110000
	c11 = 23'b00000000000010100011000
	c12 = 23'b00000000000001010001100
	c13 = 23'b00000000000000101000110
	c14 = 23'b00000000000000010100011
	c15 = 23'b00000000000000001010001
	c16 = 23'b00000000000000000101001
	c17 = 23'b00000000000000000010100
	c18 = 23'b00000000000000000001010
	c19 = 23'b00000000000000000000101
	c20 = 23'b00000000000000000000011
	c21 = 23'b00000000000000000000001
	c22 = 23'b00000000000000000000001
	c23 = 23'b00000000000000000000000
	stages = 32'sb00000000000000000000000000010011
	zwidth = 32'sb00000000000000000000000000011000
Module <cordic_z24.2> is correct for synthesis.
 
Analyzing module <cordic_stage.21> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000000000
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.21> is correct for synthesis.
 
Analyzing module <cordic_stage.22> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000000001
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.22> is correct for synthesis.
 
Analyzing module <cordic_stage.23> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000000010
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.23> is correct for synthesis.
 
Analyzing module <cordic_stage.24> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000000011
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.24> is correct for synthesis.
 
Analyzing module <cordic_stage.25> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000000100
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.25> is correct for synthesis.
 
Analyzing module <cordic_stage.26> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000000101
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.26> is correct for synthesis.
 
Analyzing module <cordic_stage.27> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000000110
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.27> is correct for synthesis.
 
Analyzing module <cordic_stage.28> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000000111
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.28> is correct for synthesis.
 
Analyzing module <cordic_stage.29> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000001000
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.29> is correct for synthesis.
 
Analyzing module <cordic_stage.30> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000001001
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.30> is correct for synthesis.
 
Analyzing module <cordic_stage.31> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000001010
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.31> is correct for synthesis.
 
Analyzing module <cordic_stage.32> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000001011
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.32> is correct for synthesis.
 
Analyzing module <cordic_stage.33> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000001100
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.33> is correct for synthesis.
 
Analyzing module <cordic_stage.34> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000001101
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.34> is correct for synthesis.
 
Analyzing module <cordic_stage.35> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000001110
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.35> is correct for synthesis.
 
Analyzing module <cordic_stage.36> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000001111
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.36> is correct for synthesis.
 
Analyzing module <cordic_stage.37> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000010000
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.37> is correct for synthesis.
 
Analyzing module <cordic_stage.38> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000010001
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.38> is correct for synthesis.
 
Analyzing module <cordic_stage.39> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000010010
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.39> is correct for synthesis.
 
Analyzing module <cordic_stage.40> in library <work>.
	bitwidth = 32'sb00000000000000000000000000011010
	shift = 32'sb00000000000000000000000000010011
	zwidth = 32'sb00000000000000000000000000010111
Module <cordic_stage.40> is correct for synthesis.
 
Analyzing module <dsp_tx_glue> in library <work>.
	DSPNO = 32'sb00000000000000000000000000000000
	WIDTH = 32'sb00000000000000000000000000011000
Module <dsp_tx_glue> is correct for synthesis.
 
Analyzing module <tx_frontend> in library <work>.
	BASE = 32'sb00000000000000000000000010000000
	IQCOMP_EN = 32'sb00000000000000000000000000000001
	WIDTH_OUT = 32'sb00000000000000000000000000010000
Module <tx_frontend> is correct for synthesis.
 
Analyzing module <setting_reg.38> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010000000
	width = 32'sb00000000000000000000000000011000
Module <setting_reg.38> is correct for synthesis.
 
Analyzing module <setting_reg.39> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010000001
	width = 32'sb00000000000000000000000000011000
Module <setting_reg.39> is correct for synthesis.
 
Analyzing module <setting_reg.40> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010000010
	width = 32'sb00000000000000000000000000010010
Module <setting_reg.40> is correct for synthesis.
 
Analyzing module <setting_reg.41> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010000011
	width = 32'sb00000000000000000000000000010010
Module <setting_reg.41> is correct for synthesis.
 
Analyzing module <setting_reg.42> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000010000100
	width = 32'sb00000000000000000000000000001000
Module <setting_reg.42> is correct for synthesis.
 
Analyzing module <serdes> in library <work>.
	RXFIFOSIZE = 32'sb00000000000000000000000000001001
	TXFIFOSIZE = 32'sb00000000000000000000000000001001
Module <serdes> is correct for synthesis.
 
Analyzing module <serdes_tx> in library <work>.
	DONE = 3'b011
	D_56 = 8'b11000101
	FIFOSIZE = 32'sb00000000000000000000000000001001
	IDLE = 3'b000
	K_COMMA = 8'b10111100
	K_ERROR = 8'b00000000
	K_IDLE = 8'b00111100
	K_LOS = 8'b11111111
	K_PKT_END = 8'b10011100
	K_PKT_START = 8'b11011100
	K_XOFF = 8'b01111100
	K_XON = 8'b01011100
	RUN1 = 3'b001
	RUN2 = 3'b010
	SENDCRC = 3'b100
	WAIT = 3'b101
Module <serdes_tx> is correct for synthesis.
 
Analyzing module <fifo_cascade.3> in library <work>.
	SIZE = 32'sb00000000000000000000000000001001
	WIDTH = 32'sb00000000000000000000000000100010
Module <fifo_cascade.3> is correct for synthesis.
 
Analyzing module <fifo_long.3> in library <work>.
	EMPTY = 32'sb00000000000000000000000000000000
	NUMLINES = 32'sb00000000000000000000000111111110
	PRE_READ = 32'sb00000000000000000000000000000001
	READING = 32'sb00000000000000000000000000000010
	SIZE = 32'sb00000000000000000000000000001001
	WIDTH = 32'sb00000000000000000000000000100010
Module <fifo_long.3> is correct for synthesis.
 
Analyzing module <ram_2port.4> in library <work>.
	AWIDTH = 32'sb00000000000000000000000000001001
	DWIDTH = 32'sb00000000000000000000000000100010
Module <ram_2port.4> is correct for synthesis.
 
Analyzing module <CRC16_D16> in library <work>.
	Calling function <nextCRC16_D16>.
Module <CRC16_D16> is correct for synthesis.
 
Analyzing module <serdes_rx> in library <work>.
	CRC_CHECK = 3'b101
	DONE = 3'b111
	D_56 = 8'b11000101
	ERROR = 3'b110
	FIFOSIZE = 32'sb00000000000000000000000000001001
	FIRSTLINE1 = 3'b001
	FIRSTLINE2 = 3'b010
	IDLE = 3'b000
	K_COMMA = 8'b10111100
	K_ERROR = 8'b00000000
	K_IDLE = 8'b00111100
	K_LOS = 8'b11111111
	K_PKT_END = 8'b10011100
	K_PKT_START = 8'b11011100
	K_XOFF = 8'b01111100
	K_XON = 8'b01011100
	PKT1 = 3'b011
	PKT2 = 3'b100
Module <serdes_rx> is correct for synthesis.
 
Analyzing module <oneshot_2clk> in library <work>.
Module <oneshot_2clk> is correct for synthesis.
 
Analyzing module <serdes_fc_tx> in library <work>.
Module <serdes_fc_tx> is correct for synthesis.
 
Analyzing module <serdes_fc_rx> in library <work>.
	HWMARK = 32'sb00000000000000000000000010000000
	LWMARK = 32'sb00000000000000000000000000100000
Module <serdes_fc_rx> is correct for synthesis.
 
Analyzing module <time_64bit> in library <work>.
	BASE = 32'sb00000000000000000000000000001010
	MIMO_SYNC = 32'sb00000000000000000000000000000101
	NEXT_TICKS_HI = 32'sb00000000000000000000000000000000
	NEXT_TICKS_LO = 32'sb00000000000000000000000000000001
	PPS_IMM = 32'sb00000000000000000000000000000011
	PPS_POLSRC = 32'sb00000000000000000000000000000010
Module <time_64bit> is correct for synthesis.
 
Analyzing module <setting_reg.43> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000001011
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.43> is correct for synthesis.
 
Analyzing module <setting_reg.44> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000001010
	width = 32'sb00000000000000000000000000100000
Module <setting_reg.44> is correct for synthesis.
 
Analyzing module <setting_reg.45> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000001100
	width = 32'sb00000000000000000000000000000010
Module <setting_reg.45> is correct for synthesis.
 
Analyzing module <setting_reg.46> in library <work>.
	at_reset = 32'b00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000001101
	width = 32'sb00000000000000000000000000000001
Module <setting_reg.46> is correct for synthesis.
 
Analyzing module <setting_reg.47> in library <work>.
	at_reset = 32'sb00000000000000000000000000000000
	my_addr = 32'sb00000000000000000000000000001111
	width = 32'sb00000000000000000000000000001001
Module <setting_reg.47> is correct for synthesis.
 
Analyzing module <time_sender> in library <work>.
	COMMA = 8'b10111100
	HEAD = 8'b00111100
	SEND_HEAD = 32'sb00000000000000000000000000000001
	SEND_IDLE = 32'sb00000000000000000000000000000000
	SEND_T0 = 32'sb00000000000000000000000000000010
	SEND_T1 = 32'sb00000000000000000000000000000011
	SEND_T2 = 32'sb00000000000000000000000000000100
	SEND_T3 = 32'sb00000000000000000000000000000101
	SEND_T4 = 32'sb00000000000000000000000000000110
	SEND_T5 = 32'sb00000000000000000000000000000111
	SEND_T6 = 32'sb00000000000000000000000000001000
	SEND_T7 = 32'sb00000000000000000000000000001001
	SEND_TAIL = 32'sb00000000000000000000000000001010
	TAIL = 8'b11110111
Module <time_sender> is correct for synthesis.
 
Analyzing module <encode_8b10b> in library <work>.
Module <encode_8b10b> is correct for synthesis.
 
Analyzing module <time_receiver> in library <work>.
	COMMA_0 = 10'b1010000011
	COMMA_1 = 10'b0101111100
	HEAD = 9'b100111100
	STATE_IDLE = 32'sb00000000000000000000000000000000
	STATE_T0 = 32'sb00000000000000000000000000000001
	STATE_T1 = 32'sb00000000000000000000000000000010
	STATE_T2 = 32'sb00000000000000000000000000000011
	STATE_T3 = 32'sb00000000000000000000000000000100
	STATE_T4 = 32'sb00000000000000000000000000000101
	STATE_T5 = 32'sb00000000000000000000000000000110
	STATE_T6 = 32'sb00000000000000000000000000000111
	STATE_T7 = 32'sb00000000000000000000000000001000
	STATE_TAIL = 32'sb00000000000000000000000000001001
	TAIL = 9'b111110111
Module <time_receiver> is correct for synthesis.
 
Analyzing module <decode_8b10b> in library <work>.
Module <decode_8b10b> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...
INFO:Xst:2679 - Register <rd_occ> in unit <buffer_int2> has a constant value of 00 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <i> in unit <quad_uart> has a constant value of 100 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <i> in unit <cic_decim> has a constant value of 100 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <i> in unit <cic_decim> has a constant value of 100 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <new_header<15>> in unit <dspengine_16to8_1> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <new_header<14>> in unit <dspengine_16to8_1> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <new_header<13>> in unit <dspengine_16to8_1> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <new_header<12>> in unit <dspengine_16to8_1> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <new_header<11>> in unit <dspengine_16to8_1> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <new_header<15>> in unit <dspengine_16to8_2> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <new_header<14>> in unit <dspengine_16to8_2> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <new_header<13>> in unit <dspengine_16to8_2> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <new_header<12>> in unit <dspengine_16to8_2> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <new_header<11>> in unit <dspengine_16to8_2> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <strobe_out> in unit <clip_reg_2> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <i> in unit <cic_interp> has a constant value of 100 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <i> in unit <cic_interp> has a constant value of 100 during circuit operation. The register is replaced by logic.

Synthesizing Unit <wb_1master>.
    Related source file is "../../../control_lib/wb_1master.v".
WARNING:Xst:647 - Input <rst_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <wb_1master> synthesized.


Synthesizing Unit <system_control>.
    Related source file is "../../../control_lib/system_control.v".
    Found 1-bit register for signal <wb_rst_o>.
    Found 1-bit register for signal <ram_loader_rst_o>.
    Found 1-bit register for signal <delayed_rst>.
    Found 1-bit register for signal <POR>.
    Found 4-bit up counter for signal <POR_ctr>.
    Summary:
	inferred   1 Counter(s).
	inferred   4 D-type flip-flop(s).
Unit <system_control> synthesized.


Synthesizing Unit <ram_harvard2>.
    Related source file is "../../../control_lib/ram_harvard2.v".
WARNING:Xst:647 - Input <if_adr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dwb_adr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 4096x8-bit dual-port RAM <Mram_ram3> for signal <ram3>.
    Found 4096x8-bit dual-port RAM <Mram_ram2> for signal <ram2>.
    Found 4096x8-bit dual-port RAM <Mram_ram1> for signal <ram1>.
    Found 4096x8-bit dual-port RAM <Mram_ram0> for signal <ram0>.
    Found 32-bit register for signal <if_data>.
    Found 32-bit register for signal <dwb_dat_o>.
    Found 1-bit register for signal <ack_d1>.
    Found 1-bit register for signal <stb_d1>.
    Summary:
	inferred   4 RAM(s).
	inferred  66 D-type flip-flop(s).
Unit <ram_harvard2> synthesized.


Synthesizing Unit <wb_readback_mux>.
    Related source file is "../../../control_lib/wb_readback_mux.v".
WARNING:Xst:647 - Input <wb_adr_i<15:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wb_adr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit register for signal <wb_dat_o>.
    Found 1-bit register for signal <wb_ack_o>.
    Found 32-bit 16-to-1 multiplexer for signal <wb_dat_o$mux0000> created at line 56.
    Summary:
	inferred  33 D-type flip-flop(s).
	inferred  32 Multiplexer(s).
Unit <wb_readback_mux> synthesized.


Synthesizing Unit <settings_bus>.
    Related source file is "../../../control_lib/settings_bus.v".
WARNING:Xst:647 - Input <wb_adr_i<15:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wb_adr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <stb_int_d1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <stb_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Found 8-bit register for signal <addr>.
    Found 1-bit register for signal <strobe>.
    Found 1-bit register for signal <wb_ack_o>.
    Found 32-bit register for signal <data>.
    Summary:
	inferred  42 D-type flip-flop(s).
Unit <settings_bus> synthesized.


Synthesizing Unit <setting_reg_1>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 1-bit register for signal <out<0>>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <setting_reg_1> synthesized.


Synthesizing Unit <setting_reg_2>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 8-bit register for signal <out>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <setting_reg_2> synthesized.


Synthesizing Unit <setting_reg_3>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 8-bit register for signal <out>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <setting_reg_3> synthesized.


Synthesizing Unit <setting_reg_4>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 8-bit register for signal <out>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <setting_reg_4> synthesized.


Synthesizing Unit <setting_reg_5>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 1-bit register for signal <out<0>>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <setting_reg_5> synthesized.


Synthesizing Unit <setting_reg_6>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 1-bit register for signal <out<0>>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <setting_reg_6> synthesized.


Synthesizing Unit <setting_reg_7>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 8-bit register for signal <out>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <setting_reg_7> synthesized.


Synthesizing Unit <setting_reg_8>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 8-bit register for signal <out>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <setting_reg_8> synthesized.


Synthesizing Unit <zpu_core>.
    Related source file is "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd".
WARNING:Xst:1305 - Output <zpu_status<63>> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <zpu_status<61:41>> is never assigned. Tied to value 000000000000000000000.
WARNING:Xst:1305 - Output <zpu_status<30:16>> is never assigned. Tied to value 000000000000000.
WARNING:Xst:646 - Signal <trace_topOfStackB> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trace_topOfStack> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trace_sp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mem_readEnable> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mem_delayReadEnable> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mem_delayAddr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <busy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <begin_inst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 22                                             |
    | Transitions        | 83                                             |
    | Inputs             | 29                                             |
    | Outputs            | 24                                             |
    | Clock              | clk                       (rising_edge)        |
    | Reset              | areset                    (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | state_idle                                     |
    | Power Up State     | state_idle                                     |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit register for signal <mem_write>.
    Found 1-bit register for signal <break>.
    Found 1-bit register for signal <mem_we>.
    Found 6-bit 4-to-1 multiplexer for signal <$varindex0000> created at line 396.
    Found 32-bit register for signal <binaryOpResult>.
    Found 32-bit subtractor for signal <binaryOpResult$addsub0000> created at line 575.
    Found 32-bit comparator equal for signal <binaryOpResult$cmp_eq0000> created at line 631.
    Found 32-bit comparator lessequal for signal <binaryOpResult$cmp_le0000> created at line 649.
    Found 32-bit comparator lessequal for signal <binaryOpResult$cmp_le0001> created at line 667.
    Found 32-bit comparator less for signal <binaryOpResult$cmp_lt0000> created at line 640.
    Found 32-bit comparator less for signal <binaryOpResult$cmp_lt0001> created at line 658.
    Found 18-bit register for signal <decodedOpcode<1:3>>.
    Found 32-bit register for signal <decodeWord>.
    Found 14-bit subtractor for signal <decSp$sub0000> created at line 188.
    Found 1-bit register for signal <idim_flag>.
    Found 14-bit adder for signal <incIncSp$add0000> created at line 187.
    Found 14-bit adder for signal <incSp$add0000> created at line 186.
    Found 1-bit register for signal <inInterrupt>.
    Found 6-bit register for signal <insn>.
    Found 14-bit register for signal <mem_addr>.
    Found 14-bit adder carry in for signal <mem_addr$share0000> created at line 248.
    Found 32-bit register for signal <multA>.
    Found 32-bit register for signal <multB>.
    Found 32-bit register for signal <multResult>.
    Found 32-bit register for signal <multResult2>.
    Found 32-bit register for signal <multResult3>.
    Found 16-bit adder for signal <nextPC$add0000> created at line 228.
    Found 32-bit register for signal <opcode>.
    Found 1-bit register for signal <out_mem_req>.
    Found 16-bit register for signal <pc>.
    Found 16-bit adder for signal <pc$add0000> created at line 485.
    Found 14-bit register for signal <sp>.
    Found 8-bit 4-to-1 multiplexer for signal <spOffset_4$varindex0000> created at line 226.
    Found 32-bit register for signal <stackA>.
    Found 32-bit adder for signal <stackA$add0000> created at line 563.
    Found 32-bit adder for signal <stackA$add0001> created at line 857.
    Found 14-bit adder for signal <stackA_15_2$add0000> created at line 780.
    Found 2-bit adder for signal <stackA_7_0$sub0000> created at line 868.
    Found 32-bit register for signal <stackB>.
    Found 32x32-bit multiplier for signal <tMultResult$mult0000> created at line 220.
    Found 8-bit register for signal <trace_opcode>.
    Found 16-bit register for signal <trace_pc>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred 435 D-type flip-flop(s).
	inferred  11 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
	inferred   5 Comparator(s).
	inferred  14 Multiplexer(s).
Unit <zpu_core> synthesized.


Synthesizing Unit <zpu_wb_bridge>.
    Related source file is "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd".
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <areset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <zpu_wb_bridge> synthesized.


Synthesizing Unit <setting_reg_9>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 1-bit register for signal <out<0>>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <setting_reg_9> synthesized.


Synthesizing Unit <valve36>.
    Related source file is "../../../fifo/valve36.v".
    Found 1-bit register for signal <active>.
    Found 1-bit register for signal <shutoff_int>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <valve36> synthesized.


Synthesizing Unit <crossbar36>.
    Related source file is "../../../fifo/crossbar36.v".
    Found 1-bit register for signal <active0>.
    Found 1-bit register for signal <active1>.
    Found 1-bit register for signal <cross_int>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <crossbar36> synthesized.


Synthesizing Unit <ram_2port_1>.
    Related source file is "../../../control_lib/ram_2port.v".
    Found 512x32-bit dual-port RAM <Mram_ram> for signal <ram>.
    Found 32-bit register for signal <doa>.
    Found 32-bit register for signal <dob>.
    Summary:
	inferred   1 RAM(s).
	inferred  64 D-type flip-flop(s).
Unit <ram_2port_1> synthesized.


Synthesizing Unit <setting_reg_48>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_48> synthesized.


Synthesizing Unit <setting_reg_49>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_49> synthesized.


Synthesizing Unit <setting_reg_50>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_50> synthesized.


Synthesizing Unit <splitter36>.
    Related source file is "../../../fifo/splitter36.v".
    Found 36-bit register for signal <data_reg>.
    Found 2-bit register for signal <state>.
    Summary:
	inferred  38 D-type flip-flop(s).
Unit <splitter36> synthesized.


Synthesizing Unit <ram_2port_3>.
    Related source file is "../../../control_lib/ram_2port.v".
    Found 512x36-bit dual-port RAM <Mram_ram> for signal <ram>.
    Found 36-bit register for signal <doa>.
    Found 36-bit register for signal <dob>.
    Summary:
	inferred   1 RAM(s).
	inferred  72 D-type flip-flop(s).
Unit <ram_2port_3> synthesized.


Synthesizing Unit <add_onescomp>.
    Related source file is "../../../udp/add_onescomp.v".
    Found 16-bit adder for signal <SUM>.
    Found 17-bit adder for signal <SUM_INT>.
    Summary:
	inferred   2 Adder/Subtractor(s).
Unit <add_onescomp> synthesized.


Synthesizing Unit <setting_reg_10>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 16-bit register for signal <out>.
    Summary:
	inferred  17 D-type flip-flop(s).
Unit <setting_reg_10> synthesized.


Synthesizing Unit <setting_reg_11>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_11> synthesized.


Synthesizing Unit <setting_reg_12>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_12> synthesized.


Synthesizing Unit <i2c_master_bit_ctrl>.
    Related source file is "../../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v".
    Found finite state machine <FSM_1> for signal <c_state>.
    -----------------------------------------------------------------------
    | States             | 18                                             |
    | Transitions        | 50                                             |
    | Inputs             | 6                                              |
    | Outputs            | 20                                             |
    | Clock              | clk                       (rising_edge)        |
    | Clock enable       | c_state$not0000           (positive)           |
    | Reset              | nReset                    (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00000000000000000                              |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <sda_oen>.
    Found 1-bit register for signal <al>.
    Found 1-bit register for signal <cmd_ack>.
    Found 1-bit register for signal <busy>.
    Found 1-bit register for signal <scl_oen>.
    Found 1-bit register for signal <dout>.
    Found 1-bit register for signal <clk_en>.
    Found 1-bit register for signal <cmd_stop>.
    Found 16-bit register for signal <cnt>.
    Found 16-bit subtractor for signal <cnt$addsub0000> created at line 223.
    Found 1-bit register for signal <dSCL>.
    Found 1-bit register for signal <dscl_oen>.
    Found 1-bit register for signal <dSDA>.
    Found 1-bit register for signal <sda_chk>.
    Found 1-bit register for signal <sSCL>.
    Found 1-bit register for signal <sSDA>.
    Found 1-bit register for signal <sta_condition>.
    Found 1-bit register for signal <sto_condition>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  32 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <i2c_master_bit_ctrl> synthesized.


Synthesizing Unit <setting_reg_13>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_13> synthesized.


Synthesizing Unit <setting_reg_14>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_14> synthesized.


Synthesizing Unit <setting_reg_15>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_15> synthesized.


Synthesizing Unit <setting_reg_16>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_16> synthesized.


Synthesizing Unit <setting_reg_17>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_17> synthesized.


Synthesizing Unit <reset_sync>.
    Related source file is "../../../control_lib/reset_sync.v".
    Found 1-bit register for signal <reset_out>.
    Found 1-bit register for signal <reset_int>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <reset_sync> synthesized.


Synthesizing Unit <rxmac_to_ll8>.
    Related source file is "../../../simple_gemac/rxmac_to_ll8.v".
    Found 3-bit register for signal <xfer_state>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <rxmac_to_ll8> synthesized.


Synthesizing Unit <fifo19_rxrealign>.
    Related source file is "../../../udp/fifo19_rxrealign.v".
    Found 1-bit register for signal <rxre_state>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <fifo19_rxrealign> synthesized.


Synthesizing Unit <ethtx_realign>.
    Related source file is "../../../simple_gemac/ethtx_realign.v".
    Found 16-bit register for signal <held>.
    Found 2-bit register for signal <held_occ>.
    Found 1-bit register for signal <held_sof>.
    Found 1-bit xor2 for signal <occ_low>.
    Found 2-bit register for signal <state>.
    Summary:
	inferred  21 D-type flip-flop(s).
Unit <ethtx_realign> synthesized.


Synthesizing Unit <ll8_to_txmac>.
    Related source file is "../../../simple_gemac/ll8_to_txmac.v".
WARNING:Xst:647 - Input <ll_sof> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 3-bit register for signal <xfer_state>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <ll8_to_txmac> synthesized.


Synthesizing Unit <flow_ctrl_tx>.
    Related source file is "../../../simple_gemac/flow_ctrl_tx.v".
    Found 22-bit down counter for signal <pause_quanta_counter>.
    Found 1-bit register for signal <pqval_d1>.
    Found 1-bit register for signal <pqval_d2>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <flow_ctrl_tx> synthesized.


Synthesizing Unit <crc>.
    Related source file is "../../../simple_gemac/crc.v".
    Found 32-bit register for signal <crc_reg>.
    Found 1-bit xor2 for signal <crc_reg$xor0000> created at line 64.
    Found 1-bit xor3 for signal <crc_reg$xor0001> created at line 63.
    Found 1-bit xor4 for signal <crc_reg$xor0002> created at line 62.
    Found 1-bit xor4 for signal <crc_reg$xor0003> created at line 61.
    Found 1-bit xor4 for signal <crc_reg$xor0004> created at line 60.
    Found 1-bit xor4 for signal <crc_reg$xor0005> created at line 59.
    Found 1-bit xor3 for signal <crc_reg$xor0006> created at line 58.
    Found 1-bit xor3 for signal <crc_reg$xor0007> created at line 57.
    Found 1-bit xor3 for signal <crc_reg$xor0008> created at line 56.
    Found 1-bit xor2 for signal <crc_reg$xor0009> created at line 55.
    Found 1-bit xor2 for signal <crc_reg$xor0010> created at line 54.
    Found 1-bit xor2 for signal <crc_reg$xor0011> created at line 53.
    Found 1-bit xor3 for signal <crc_reg$xor0012> created at line 52.
    Found 1-bit xor4 for signal <crc_reg$xor0013> created at line 51.
    Found 1-bit xor4 for signal <crc_reg$xor0014> created at line 50.
    Found 1-bit xor4 for signal <crc_reg$xor0015> created at line 49.
    Found 1-bit xor4 for signal <crc_reg$xor0016> created at line 48.
    Found 1-bit xor4 for signal <crc_reg$xor0017> created at line 47.
    Found 1-bit xor6 for signal <crc_reg$xor0018> created at line 46.
    Found 1-bit xor6 for signal <crc_reg$xor0019> created at line 45.
    Found 1-bit xor4 for signal <crc_reg$xor0020> created at line 44.
    Found 1-bit xor3 for signal <crc_reg$xor0021> created at line 43.
    Found 1-bit xor3 for signal <crc_reg$xor0022> created at line 42.
    Found 1-bit xor3 for signal <crc_reg$xor0023> created at line 41.
    Found 1-bit xor3 for signal <crc_reg$xor0024> created at line 40.
    Found 1-bit xor4 for signal <crc_reg$xor0025> created at line 39.
    Found 1-bit xor4 for signal <crc_reg$xor0026> created at line 38.
    Found 1-bit xor4 for signal <crc_reg$xor0027> created at line 37.
    Found 1-bit xor3 for signal <crc_reg$xor0028> created at line 36.
    Found 1-bit xor3 for signal <crc_reg$xor0029> created at line 35.
    Found 1-bit xor3 for signal <crc_reg$xor0030> created at line 34.
    Found 1-bit xor2 for signal <crc_reg$xor0031> created at line 33.
    Found 1-bit xor2 for signal <crc_reg$xor0032> created at line 64.
    Found 1-bit xor2 for signal <crc_reg$xor0033> created at line 63.
    Found 1-bit xor2 for signal <crc_reg$xor0034> created at line 63.
    Found 1-bit xor2 for signal <crc_reg$xor0035> created at line 62.
    Found 1-bit xor2 for signal <crc_reg$xor0036> created at line 62.
    Found 1-bit xor2 for signal <crc_reg$xor0037> created at line 61.
    Found 1-bit xor2 for signal <crc_reg$xor0038> created at line 60.
    Found 1-bit xor2 for signal <crc_reg$xor0040> created at line 59.
    Found 1-bit xor2 for signal <crc_reg$xor0044> created at line 56.
    Found 1-bit xor2 for signal <crc_reg$xor0045> created at line 55.
    Found 1-bit xor2 for signal <crc_reg$xor0050> created at line 48.
    Found 1-bit xor2 for signal <crc_reg$xor0052> created at line 47.
    Found 1-bit xor2 for signal <crc_reg$xor0058> created at line 45.
    Found 1-bit xor2 for signal <crc_reg$xor0060> created at line 44.
    Found 1-bit xor2 for signal <crc_reg$xor0061> created at line 43.
    Found 1-bit xor2 for signal <crc_reg$xor0065> created at line 39.
    Found 1-bit xor2 for signal <crc_reg$xor0067> created at line 38.
    Found 1-bit xor2 for signal <crc_reg$xor0071> created at line 36.
    Found 1-bit xor2 for signal <crc_reg$xor0072> created at line 35.
    Summary:
	inferred  32 D-type flip-flop(s).
	inferred  27 Xor(s).
Unit <crc> synthesized.


Synthesizing Unit <address_filter>.
    Related source file is "../../../simple_gemac/address_filter.v".
    Found finite state machine <FSM_2> for signal <af_state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 29                                             |
    | Inputs             | 7                                              |
    | Outputs            | 2                                              |
    | Clock              | clk                       (rising_edge)        |
    | Reset              | reset                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit comparator equal for signal <af_state$cmp_eq0000> created at line 36.
    Found 8-bit comparator equal for signal <af_state$cmp_eq0001> created at line 39.
    Found 8-bit comparator equal for signal <af_state$cmp_eq0002> created at line 40.
    Found 8-bit comparator equal for signal <af_state$cmp_eq0003> created at line 41.
    Found 8-bit comparator equal for signal <af_state$cmp_eq0004> created at line 42.
    Found 8-bit comparator equal for signal <af_state$cmp_eq0005> created at line 43.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   6 Comparator(s).
Unit <address_filter> synthesized.


Synthesizing Unit <address_filter_promisc>.
    Related source file is "../../../simple_gemac/address_filter_promisc.v".
WARNING:Xst:647 - Input <data<7:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found finite state machine <FSM_3> for signal <af_state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 24                                             |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | clk                       (rising_edge)        |
    | Reset              | reset                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 Finite State Machine(s).
Unit <address_filter_promisc> synthesized.


Synthesizing Unit <wb_reg_1>.
    Related source file is "../../../simple_gemac/simple_gemac_wb.v".
WARNING:Xst:647 - Input <dat_i<31:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 7-bit register for signal <dat_o>.
    Summary:
	inferred   7 D-type flip-flop(s).
Unit <wb_reg_1> synthesized.


Synthesizing Unit <wb_reg_2>.
    Related source file is "../../../simple_gemac/simple_gemac_wb.v".
WARNING:Xst:647 - Input <dat_i<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16-bit register for signal <dat_o>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <wb_reg_2> synthesized.


Synthesizing Unit <wb_reg_3>.
    Related source file is "../../../simple_gemac/simple_gemac_wb.v".
    Found 32-bit register for signal <dat_o>.
    Summary:
	inferred  32 D-type flip-flop(s).
Unit <wb_reg_3> synthesized.


Synthesizing Unit <wb_reg_4>.
    Related source file is "../../../simple_gemac/simple_gemac_wb.v".
WARNING:Xst:647 - Input <dat_i<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16-bit register for signal <dat_o>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <wb_reg_4> synthesized.


Synthesizing Unit <wb_reg_5>.
    Related source file is "../../../simple_gemac/simple_gemac_wb.v".
    Found 32-bit register for signal <dat_o>.
    Summary:
	inferred  32 D-type flip-flop(s).
Unit <wb_reg_5> synthesized.


Synthesizing Unit <wb_reg_6>.
    Related source file is "../../../simple_gemac/simple_gemac_wb.v".
WARNING:Xst:647 - Input <dat_i<31:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 9-bit register for signal <dat_o>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <wb_reg_6> synthesized.


Synthesizing Unit <wb_reg_7>.
    Related source file is "../../../simple_gemac/simple_gemac_wb.v".
WARNING:Xst:647 - Input <dat_i<31:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 13-bit register for signal <dat_o>.
    Summary:
	inferred  13 D-type flip-flop(s).
Unit <wb_reg_7> synthesized.


Synthesizing Unit <wb_reg_8>.
    Related source file is "../../../simple_gemac/simple_gemac_wb.v".
WARNING:Xst:647 - Input <dat_i<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16-bit register for signal <dat_o>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <wb_reg_8> synthesized.


Synthesizing Unit <wb_reg_9>.
    Related source file is "../../../simple_gemac/simple_gemac_wb.v".
WARNING:Xst:647 - Input <dat_i<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16-bit register for signal <dat_o>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <wb_reg_9> synthesized.


Synthesizing Unit <wb_reg_10>.
    Related source file is "../../../simple_gemac/simple_gemac_wb.v".
WARNING:Xst:647 - Input <dat_i<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16-bit register for signal <dat_o>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <wb_reg_10> synthesized.


Synthesizing Unit <eth_clockgen>.
    Related source file is "../../../simple_gemac/miim/eth_clockgen.v".
    Found 1-bit register for signal <Mdc>.
    Found 8-bit down counter for signal <Counter>.
    Found 8-bit subtractor for signal <CounterPreset>.
    Found 8-bit comparator less for signal <TempDivider$cmp_lt0000> created at line 101.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <eth_clockgen> synthesized.


Synthesizing Unit <eth_shiftreg>.
    Related source file is "../../../simple_gemac/miim/eth_shiftreg.v".
    Found 1-bit register for signal <LinkFail>.
    Found 16-bit register for signal <Prsd>.
    Found 8-bit register for signal <ShiftReg>.
    Summary:
	inferred  25 D-type flip-flop(s).
Unit <eth_shiftreg> synthesized.


Synthesizing Unit <eth_outputcontrol>.
    Related source file is "../../../simple_gemac/miim/eth_outputcontrol.v".
    Found 1-bit register for signal <Mdo>.
    Found 1-bit register for signal <MdoEn>.
    Found 1-bit register for signal <Mdo_2d>.
    Found 1-bit register for signal <Mdo_d>.
    Found 1-bit register for signal <MdoEn_2d>.
    Found 7-bit comparator less for signal <MdoEn_2d$cmp_lt0000> created at line 128.
    Found 1-bit register for signal <MdoEn_d>.
    Found 7-bit comparator greater for signal <SerialEn$cmp_gt0000> created at line 111.
    Found 7-bit comparator less for signal <SerialEn$cmp_lt0000> created at line 111.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   3 Comparator(s).
Unit <eth_outputcontrol> synthesized.


Synthesizing Unit <setting_reg_18>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 8-bit register for signal <out>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <setting_reg_18> synthesized.


Synthesizing Unit <setting_reg_19>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_19> synthesized.


Synthesizing Unit <time_compare>.
    Related source file is "../../../timing/time_compare.v".
    Found 64-bit comparator greater for signal <late>.
    Found 64-bit comparator equal for signal <now>.
    Summary:
	inferred   2 Comparator(s).
Unit <time_compare> synthesized.


Synthesizing Unit <priority_enc>.
    Related source file is "../../../control_lib/priority_enc.v".
Unit <priority_enc> synthesized.


Synthesizing Unit <spi_clgen>.
    Related source file is "../../../opencores/spi/rtl/verilog/spi_clgen.v".
    Found 1-bit register for signal <clk_out>.
    Found 1-bit register for signal <pos_edge>.
    Found 1-bit register for signal <neg_edge>.
    Found 8-bit down counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred   3 D-type flip-flop(s).
Unit <spi_clgen> synthesized.


Synthesizing Unit <spi_shift>.
    Related source file is "../../../opencores/spi/rtl/verilog/spi_shift.v".
WARNING:Xst:646 - Signal <tx_bit_pos<7>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <rx_bit_pos<7>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <s_out>.
    Found 1-bit register for signal <tip>.
    Found 1-bit 128-to-1 multiplexer for signal <$varindex0000> created at line 119.
    Found 8-bit register for signal <cnt>.
    Found 128-bit register for signal <data>.
    Found 8-bit subtractor for signal <rx_bit_pos$addsub0000> created at line 80.
    Found 8-bit adder for signal <rx_bit_pos$addsub0001> created at line 80.
    Found 8-bit subtractor for signal <tx_bit_pos$addsub0000> created at line 79.
    Found 8-bit subtractor for signal <tx_bit_pos$sub0000> created at line 79.
    Summary:
	inferred 138 D-type flip-flop(s).
	inferred   4 Adder/Subtractor(s).
	inferred   2 Multiplexer(s).
Unit <spi_shift> synthesized.


Synthesizing Unit <setting_reg_20>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 1-bit register for signal <out<0>>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <setting_reg_20> synthesized.


Synthesizing Unit <setting_reg_21>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:18>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 18-bit register for signal <out>.
    Summary:
	inferred  19 D-type flip-flop(s).
Unit <setting_reg_21> synthesized.


Synthesizing Unit <setting_reg_22>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:18>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 18-bit register for signal <out>.
    Summary:
	inferred  19 D-type flip-flop(s).
Unit <setting_reg_22> synthesized.


Synthesizing Unit <sign_extend_6>.
    Related source file is "../../../sdr_lib/sign_extend.v".
Unit <sign_extend_6> synthesized.


Synthesizing Unit <round_3>.
    Related source file is "../../../sdr_lib/round.v".
WARNING:Xst:646 - Signal <round_corr_trunc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <round_corr_rtz> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 21-bit subtractor for signal <err>.
    Found 18-bit adder for signal <out>.
    Summary:
	inferred   2 Adder/Subtractor(s).
Unit <round_3> synthesized.


Synthesizing Unit <clip_6>.
    Related source file is "../../../sdr_lib/clip.v".
    Found 38-bit 4-to-1 multiplexer for signal <out>.
    Summary:
	inferred  38 Multiplexer(s).
Unit <clip_6> synthesized.


Synthesizing Unit <clip_4>.
    Related source file is "../../../sdr_lib/clip.v".
Unit <clip_4> synthesized.


Synthesizing Unit <clip_1>.
    Related source file is "../../../sdr_lib/clip.v".
Unit <clip_1> synthesized.


Synthesizing Unit <setting_reg_23>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_23> synthesized.


Synthesizing Unit <setting_reg_24>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:18>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 18-bit register for signal <out>.
    Summary:
	inferred  19 D-type flip-flop(s).
Unit <setting_reg_24> synthesized.


Synthesizing Unit <setting_reg_25>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 10-bit register for signal <out>.
    Summary:
	inferred  11 D-type flip-flop(s).
Unit <setting_reg_25> synthesized.


Synthesizing Unit <setting_reg_26>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 2-bit register for signal <out>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <setting_reg_26> synthesized.


Synthesizing Unit <sign_extend_1>.
    Related source file is "../../../sdr_lib/sign_extend.v".
Unit <sign_extend_1> synthesized.


Synthesizing Unit <cic_strober_1>.
    Related source file is "../../../sdr_lib/cic_strober.v".
    Found 8-bit register for signal <counter>.
    Found 8-bit subtractor for signal <counter$addsub0000> created at line 43.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <cic_strober_1> synthesized.


Synthesizing Unit <cordic_stage_1>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_1> synthesized.


Synthesizing Unit <cordic_stage_2>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_2> synthesized.


Synthesizing Unit <cordic_stage_3>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_3> synthesized.


Synthesizing Unit <cordic_stage_4>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_4> synthesized.


Synthesizing Unit <cordic_stage_5>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_5> synthesized.


Synthesizing Unit <cordic_stage_6>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_6> synthesized.


Synthesizing Unit <cordic_stage_7>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_7> synthesized.


Synthesizing Unit <cordic_stage_8>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_8> synthesized.


Synthesizing Unit <cordic_stage_9>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_9> synthesized.


Synthesizing Unit <cordic_stage_10>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_10> synthesized.


Synthesizing Unit <cordic_stage_11>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_11> synthesized.


Synthesizing Unit <cordic_stage_12>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_12> synthesized.


Synthesizing Unit <cordic_stage_13>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_13> synthesized.


Synthesizing Unit <cordic_stage_14>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_14> synthesized.


Synthesizing Unit <cordic_stage_15>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_15> synthesized.


Synthesizing Unit <cordic_stage_16>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_16> synthesized.


Synthesizing Unit <cordic_stage_17>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_17> synthesized.


Synthesizing Unit <cordic_stage_18>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_18> synthesized.


Synthesizing Unit <cordic_stage_19>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_19> synthesized.


Synthesizing Unit <cordic_stage_20>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 27-bit register for signal <xo>.
    Found 27-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 27-bit addsub for signal <xo$mux0000>.
    Found 27-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  77 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_20> synthesized.


Synthesizing Unit <sign_extend_2>.
    Related source file is "../../../sdr_lib/sign_extend.v".
Unit <sign_extend_2> synthesized.


Synthesizing Unit <cic_dec_shifter>.
    Related source file is "../../../sdr_lib/cic_dec_shifter.v".
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <shift> of Case statement line 77 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'INIT' attribute on signal <shift> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Using one-hot encoding for signal <shift>.
Unit <cic_dec_shifter> synthesized.


Synthesizing Unit <sign_extend_7>.
    Related source file is "../../../sdr_lib/sign_extend.v".
Unit <sign_extend_7> synthesized.


Synthesizing Unit <round_4>.
    Related source file is "../../../sdr_lib/round.v".
WARNING:Xst:646 - Signal <round_corr_trunc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <round_corr_rtz> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 8-bit subtractor for signal <err>.
    Found 17-bit adder for signal <out>.
    Summary:
	inferred   2 Adder/Subtractor(s).
Unit <round_4> synthesized.


Synthesizing Unit <sign_extend_8>.
    Related source file is "../../../sdr_lib/sign_extend.v".
Unit <sign_extend_8> synthesized.


Synthesizing Unit <round_5>.
    Related source file is "../../../sdr_lib/round.v".
WARNING:Xst:646 - Signal <round_corr_trunc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <round_corr_rtz> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 6-bit subtractor for signal <err>.
    Found 25-bit adder for signal <out>.
    Summary:
	inferred   2 Adder/Subtractor(s).
Unit <round_5> synthesized.


Synthesizing Unit <clip_7>.
    Related source file is "../../../sdr_lib/clip.v".
Unit <clip_7> synthesized.


Synthesizing Unit <sign_extend_3>.
    Related source file is "../../../sdr_lib/sign_extend.v".
Unit <sign_extend_3> synthesized.


Synthesizing Unit <sign_extend_9>.
    Related source file is "../../../sdr_lib/sign_extend.v".
Unit <sign_extend_9> synthesized.


Synthesizing Unit <sign_extend_4>.
    Related source file is "../../../sdr_lib/sign_extend.v".
Unit <sign_extend_4> synthesized.


Synthesizing Unit <round_1>.
    Related source file is "../../../sdr_lib/round.v".
WARNING:Xst:646 - Signal <round_corr_trunc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <round_corr_rtz> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 9-bit subtractor for signal <err>.
    Found 16-bit adder for signal <out>.
    Summary:
	inferred   2 Adder/Subtractor(s).
Unit <round_1> synthesized.


Synthesizing Unit <custom_dsp_rx>.
    Related source file is "../../../custom/custom_dsp_rx.v".
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <set_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <set_data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <set_addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <custom_dsp_rx> synthesized.


Synthesizing Unit <setting_reg_27>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_27> synthesized.


Synthesizing Unit <add_routing_header_1>.
    Related source file is "../../../fifo/add_routing_header.v".
WARNING:Xst:647 - Input <clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <len<15:14>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 36-bit 4-to-1 multiplexer for signal <data_o>.
    Found 2-bit up counter for signal <line>.
    Summary:
	inferred   1 Counter(s).
	inferred  36 Multiplexer(s).
Unit <add_routing_header_1> synthesized.


Synthesizing Unit <setting_reg_51>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_51> synthesized.


Synthesizing Unit <setting_reg_52>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_52> synthesized.


Synthesizing Unit <setting_reg_53>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_53> synthesized.


Synthesizing Unit <setting_reg_54>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_54> synthesized.


Synthesizing Unit <setting_reg_55>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_55> synthesized.


Synthesizing Unit <setting_reg_56>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_56> synthesized.


Synthesizing Unit <setting_reg_57>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 16-bit register for signal <out>.
    Summary:
	inferred  17 D-type flip-flop(s).
Unit <setting_reg_57> synthesized.


Synthesizing Unit <ram_2port_2>.
    Related source file is "../../../control_lib/ram_2port.v".
    Found 1024x36-bit dual-port RAM <Mram_ram> for signal <ram>.
    Found 36-bit register for signal <doa>.
    Found 36-bit register for signal <dob>.
    Summary:
	inferred   1 RAM(s).
	inferred  72 D-type flip-flop(s).
Unit <ram_2port_2> synthesized.


Synthesizing Unit <buff_sm_1>.
    Related source file is "../../../control_lib/dbsm.v".
    Found 2-bit register for signal <buff_state>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <buff_sm_1> synthesized.


Synthesizing Unit <buff_sm_2>.
    Related source file is "../../../control_lib/dbsm.v".
    Found 2-bit register for signal <buff_state>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <buff_sm_2> synthesized.


Synthesizing Unit <setting_reg_68>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 1-bit register for signal <out<0>>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <setting_reg_68> synthesized.


Synthesizing Unit <pipestage>.
    Related source file is "../../../sdr_lib/pipestage.v".
    Found 2-bit register for signal <tag_out>.
    Found 1-bit register for signal <valid>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <pipestage> synthesized.


Synthesizing Unit <clip_5>.
    Related source file is "../../../sdr_lib/clip.v".
Unit <clip_5> synthesized.


Synthesizing Unit <setting_reg_28>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_28> synthesized.


Synthesizing Unit <setting_reg_29>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:18>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 18-bit register for signal <out>.
    Summary:
	inferred  19 D-type flip-flop(s).
Unit <setting_reg_29> synthesized.


Synthesizing Unit <setting_reg_30>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 10-bit register for signal <out>.
    Summary:
	inferred  11 D-type flip-flop(s).
Unit <setting_reg_30> synthesized.


Synthesizing Unit <setting_reg_31>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 2-bit register for signal <out>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <setting_reg_31> synthesized.


Synthesizing Unit <dsp_rx_glue_2>.
    Related source file is "../../../sdr_lib/dsp_rx_glue.v".
WARNING:Xst:1305 - Output <debug> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <set_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <set_data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <set_addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <dsp_rx_glue_2> synthesized.


Synthesizing Unit <setting_reg_32>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_32> synthesized.


Synthesizing Unit <add_routing_header_2>.
    Related source file is "../../../fifo/add_routing_header.v".
WARNING:Xst:647 - Input <clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <len<15:14>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 36-bit 4-to-1 multiplexer for signal <data_o>.
    Found 2-bit up counter for signal <line>.
    Summary:
	inferred   1 Counter(s).
	inferred  36 Multiplexer(s).
Unit <add_routing_header_2> synthesized.


Synthesizing Unit <setting_reg_58>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_58> synthesized.


Synthesizing Unit <setting_reg_59>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_59> synthesized.


Synthesizing Unit <setting_reg_60>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_60> synthesized.


Synthesizing Unit <setting_reg_61>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_61> synthesized.


Synthesizing Unit <setting_reg_62>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_62> synthesized.


Synthesizing Unit <setting_reg_63>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_63> synthesized.


Synthesizing Unit <setting_reg_64>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 16-bit register for signal <out>.
    Summary:
	inferred  17 D-type flip-flop(s).
Unit <setting_reg_64> synthesized.


Synthesizing Unit <setting_reg_69>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 1-bit register for signal <out<0>>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <setting_reg_69> synthesized.


Synthesizing Unit <refill_randomizer>.
    Related source file is "../../../extramfifo/refill_randomizer.v".
    Found 7-bit register for signal <count>.
    Found 7-bit subtractor for signal <count$addsub0000> created at line 76.
    Found 1-bit register for signal <delayed_fall>.
    Found 1-bit xor2 for signal <feedback>.
    Found 1-bit register for signal <full_last>.
    Found 7-bit register for signal <shift_reg>.
    Summary:
	inferred  16 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <refill_randomizer> synthesized.


Synthesizing Unit <bin2gray>.
    Related source file is "../../../control_lib/bin2gray.v".
    Found 1-bit xor2 for signal <gray$xor0000> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0001> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0002> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0003> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0004> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0005> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0006> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0007> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0008> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0009> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0010> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0011> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0012> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0013> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0014> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0015> created at line 25.
    Found 1-bit xor2 for signal <gray$xor0016> created at line 25.
Unit <bin2gray> synthesized.


Synthesizing Unit <setting_reg_33>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 1-bit register for signal <out<0>>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <setting_reg_33> synthesized.


Synthesizing Unit <setting_reg_34>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_34> synthesized.


Synthesizing Unit <setting_reg_65>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_65> synthesized.


Synthesizing Unit <setting_reg_66>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_66> synthesized.


Synthesizing Unit <setting_reg_67>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_67> synthesized.


Synthesizing Unit <setting_reg_70>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 1-bit register for signal <out<0>>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <setting_reg_70> synthesized.


Synthesizing Unit <setting_reg_35>.
    Related source file is "../../../control_lib/setting_reg.v".
    Found 1-bit register for signal <changed>.
    Found 32-bit register for signal <out>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <setting_reg_35> synthesized.


Synthesizing Unit <setting_reg_36>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:18>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 18-bit register for signal <out>.
    Summary:
	inferred  19 D-type flip-flop(s).
Unit <setting_reg_36> synthesized.


Synthesizing Unit <setting_reg_37>.
    Related source file is "../../../control_lib/setting_reg.v".
WARNING:Xst:647 - Input <in<31:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <changed>.
    Found 10-bit register for signal <out>.
    Summary:
	inferred  11 D-type flip-flop(s).
Unit <setting_reg_37> synthesized.


Synthesizing Unit <cic_strober_2>.
    Related source file is "../../../sdr_lib/cic_strober.v".
    Found 8-bit register for signal <counter>.
    Found 8-bit subtractor for signal <counter$addsub0000> created at line 43.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <cic_strober_2> synthesized.


Synthesizing Unit <cic_strober_3>.
    Related source file is "../../../sdr_lib/cic_strober.v".
    Found 2-bit register for signal <counter>.
    Found 2-bit subtractor for signal <counter$addsub0000> created at line 43.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <cic_strober_3> synthesized.


Synthesizing Unit <dsp_tx_glue>.
    Related source file is "../../../sdr_lib/dsp_tx_glue.v".
WARNING:Xst:1305 - Output <debug> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <set_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <set_data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <set_addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <dsp_tx_glue> synthesized.


Synthesizing Unit <clip_2>.
    Related source file is "../../../sdr_lib/clip.v".
Unit <clip_2> synthesized.


Synthesizing Unit <round_2>.
    Related source file is "../../../sdr_lib/round.v".
WARNING:Xst:646 - Signal <round_corr_trunc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <round_corr_rtz> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 2-bit subtractor for signal <err>.
    Found 18-bit adder for signal <out>.
    Summary:
	inferred   2 Adder/Subtractor(s).
Unit <round_2> synthesized.


Synthesizing Unit <add2>.
    Related source file is "../../../sdr_lib/add2.v".
WARNING:Xst:646 - Signal <sum_int<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 19-bit adder for signal <sum_int>.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <add2> synthesized.


Synthesizing Unit <add2_and_round_1>.
    Related source file is "../../../sdr_lib/add2_and_round.v".
    Found 22-bit adder for signal <sum>.
    Found 23-bit adder for signal <sum_int>.
    Summary:
	inferred   2 Adder/Subtractor(s).
Unit <add2_and_round_1> synthesized.


Synthesizing Unit <sign_extend_10>.
    Related source file is "../../../sdr_lib/sign_extend.v".
Unit <sign_extend_10> synthesized.


Synthesizing Unit <add2_and_round_2>.
    Related source file is "../../../sdr_lib/add2_and_round.v".
    Found 18-bit adder for signal <sum>.
    Found 19-bit adder for signal <sum_int>.
    Summary:
	inferred   2 Adder/Subtractor(s).
Unit <add2_and_round_2> synthesized.


Synthesizing Unit <sign_extend_11>.
    Related source file is "../../../sdr_lib/sign_extend.v".
Unit <sign_extend_11> synthesized.


Synthesizing Unit <round_6>.
    Related source file is "../../../sdr_lib/round.v".
WARNING:Xst:646 - Signal <round_corr_trunc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <round_corr_rtz> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 17-bit subtractor for signal <err>.
    Found 21-bit adder for signal <out>.
    Summary:
	inferred   2 Adder/Subtractor(s).
Unit <round_6> synthesized.


Synthesizing Unit <clip_3>.
    Related source file is "../../../sdr_lib/clip.v".
Unit <clip_3> synthesized.


Synthesizing Unit <sign_extend_5>.
    Related source file is "../../../sdr_lib/sign_extend.v".
Unit <sign_extend_5> synthesized.


Synthesizing Unit <cic_int_shifter>.
    Related source file is "../../../sdr_lib/cic_int_shifter.v".
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <shift> of Case statement line 74 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'INIT' attribute on signal <shift> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Using one-hot encoding for signal <shift>.
Unit <cic_int_shifter> synthesized.


Synthesizing Unit <cordic_stage_21>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 26-bit register for signal <xo>.
    Found 26-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 26-bit addsub for signal <xo$mux0000>.
    Found 26-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  75 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_21> synthesized.


Synthesizing Unit <cordic_stage_22>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 26-bit register for signal <xo>.
    Found 26-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 26-bit addsub for signal <xo$mux0000>.
    Found 26-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  75 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_22> synthesized.


Synthesizing Unit <cordic_stage_23>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 26-bit register for signal <xo>.
    Found 26-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 26-bit addsub for signal <xo$mux0000>.
    Found 26-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  75 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_23> synthesized.


Synthesizing Unit <cordic_stage_24>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 26-bit register for signal <xo>.
    Found 26-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 26-bit addsub for signal <xo$mux0000>.
    Found 26-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  75 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_24> synthesized.


Synthesizing Unit <cordic_stage_25>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 26-bit register for signal <xo>.
    Found 26-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 26-bit addsub for signal <xo$mux0000>.
    Found 26-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  75 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_25> synthesized.


Synthesizing Unit <cordic_stage_26>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 26-bit register for signal <xo>.
    Found 26-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 26-bit addsub for signal <xo$mux0000>.
    Found 26-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  75 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_26> synthesized.


Synthesizing Unit <cordic_stage_27>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 26-bit register for signal <xo>.
    Found 26-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 26-bit addsub for signal <xo$mux0000>.
    Found 26-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  75 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_27> synthesized.


Synthesizing Unit <cordic_stage_28>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 26-bit register for signal <xo>.
    Found 26-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 26-bit addsub for signal <xo$mux0000>.
    Found 26-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  75 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_28> synthesized.


Synthesizing Unit <cordic_stage_29>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 26-bit register for signal <xo>.
    Found 26-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 26-bit addsub for signal <xo$mux0000>.
    Found 26-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  75 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_29> synthesized.


Synthesizing Unit <cordic_stage_30>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 26-bit register for signal <xo>.
    Found 26-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 26-bit addsub for signal <xo$mux0000>.
    Found 26-bit addsub for signal <yo$mux0000>.
    Found 23-bit addsub for signal <zo$mux0000>.
    Summary:
	inferred  75 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
Unit <cordic_stage_30> synthesized.


Synthesizing Unit <cordic_stage_31>.
    Related source file is "../../../sdr_lib/cordic_stage.v".
WARNING:Xst:647 - Input <enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 26-bit register for signal <xo>.
    Found 26-bit register for signal <yo>.
    Found 23-bit register for signal <zo>.
    Found 26-bit addsub for signal <xo$mux0000>.
    Fo