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Created Sep 3, 2014
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/home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom/u2plus.xise
xtclsh /home/usrp/uhd/fpga/usrp2/top/tcl/ise_helper.tcl ""
>>> Creating project: /home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom/u2plus.xise
Changed current working directory to the project directory:
"/home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom"
>>> Setting: Project[family] = Spartan-3A DSP
>>> Setting: Project[device] = xc3sd1800a
>>> Setting: Project[package] = fg676
>>> Setting: Project[speed] = -5
>>> Setting: Project[top_level_module_type] = HDL
>>> Setting: Project[synthesis_tool] = XST (VHDL/Verilog)
>>> Setting: Project[simulator] = ISE Simulator (VHDL/Verilog)
WARNING:TclTasksC - The value(s) of this property has been changed in the
current release to "ISim (VHDL/Verilog)". The property value has been set to
"ISim (VHDL/Verilog)". Please update your script to use the new value to
avoid this message in the future.
>>> Setting: Project[Preferred Language] = Verilog
>>> Setting: Project[Enable Message Filtering] = FALSE
>>> Setting: Project[Display Incremental Messages] = FALSE
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/top/N2x0/capture_ddrlvds.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/top/N2x0/capture_ddrlvds.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v\" into library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/top/N2x0/bootloader.rmi' in file
"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v" line 356
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v\" into library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/top/N2x0/bootloader.rmi' in file
"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v" line 356
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus.ucf
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/add_routing_header.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/add_routing_header.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/buffer_int.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/buffer_int2.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int2.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/buffer_pool.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/buffer_pool.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/crossbar36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/crossbar36.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/dsp_framer36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/dsp_framer36.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock_cascade.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock_cascade.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/ll8_shortfifo.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/ll8_shortfifo.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo_short.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_short.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo_long.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_long.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo_cascade.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_cascade.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_ll8.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_ll8.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo36.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_ll8.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_ll8.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo19.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo19.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_fifo19.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_fifo19.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_fifo36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_fifo36.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo19_mux.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_mux.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo36_mux.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_mux.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo36_demux.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_demux.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_router.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_router.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/splitter36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/splitter36.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/valve36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/valve36.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo_pacer.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_pacer.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x3.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x3.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x4.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x4.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_generator32.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator32.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_generator.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_verifier32.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier32.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_verifier.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/fifo19_pad.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_pad.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/fifo/packet_padder36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_padder36.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/CRC16_D16.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/CRC16_D16.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/atr_controller.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/bin2gray.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/bin2gray.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/dcache.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/dcache.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/decoder_3_8.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/decoder_3_8.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/dbsm.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/dbsm.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/dpram32.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/dpram32.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/double_buffer.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/double_buffer.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/gray2bin.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/gray2bin.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/gray_send.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/gray_send.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/icache.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/icache.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/mux4.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/mux4.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/mux8.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/mux8.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/nsgpio.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/ram_2port.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_2port.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/ram_harv_cache.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harv_cache.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard2.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard2.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/ram_loader.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_loader.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/setting_reg.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/setting_reg.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/settings_bus.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_crossclock.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_crossclock.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/srl.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/srl.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/system_control.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/system_control.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/wb_1master.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_1master.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux_16LE.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux_16LE.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/quad_uart.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/quad_uart.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/simple_uart.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_tx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_tx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_rx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_rx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/oneshot_2clk.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/oneshot_2clk.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/sd_spi.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/sd_spi_wb.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi_wb.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/wb_bridge_16_32.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_bridge_16_32.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/reset_sync.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/reset_sync.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/priority_enc.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/priority_enc.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/pic.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/pic.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/longfifo.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/longfifo.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/shortfifo.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/shortfifo.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/medfifo.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/medfifo.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/s3a_icap_wb.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/s3a_icap_wb.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/bootram.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/bootram.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/nsgpio16LE.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio16LE.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_16LE.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_16LE.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/atr_controller16.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller16.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/fifo_to_wb.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/fifo_to_wb.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/gpio_atr.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/gpio_atr.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/user_settings.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/user_settings.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/settings_fifo_ctrl.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_fifo_ctrl.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/simple_spi_core.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_spi_core.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/control_lib/simple_i2c_core.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_i2c_core.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/acc.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/acc.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/add2.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip_reg.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip_reg.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round_reg.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round_reg.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/add2_reg.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_reg.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cic_dec_shifter.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_dec_shifter.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cic_decim.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_decim.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cic_int_shifter.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_int_shifter.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cic_interp.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_interp.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cic_strober.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_strober.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/clip.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/clip_reg.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip_reg.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cordic.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_z24.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_z24.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_stage.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_stage.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/ddc_chain.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/ddc_chain.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/duc_chain.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/duc_chain.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_16to8.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_16to8.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_8to16.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_8to16.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/hb_dec.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_dec.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/hb_interp.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_interp.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/pipectrl.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipectrl.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/pipestage.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipestage.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/round.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/round.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/round_reg.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_reg.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/round_sd.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_sd.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/rx_dcoffset.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_dcoffset.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/rx_frontend.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_frontend.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/sign_extend.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/sign_extend.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_dec.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_dec.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_int.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_int.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/tx_frontend.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/tx_frontend.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_tx_glue.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_tx_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/serdes/serdes.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_rx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_rx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_tx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_tx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/serdes/serdes_rx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes_rx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/serdes/serdes_tx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes_tx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wb.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wb.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_tx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_tx.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_rx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_rx.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/crc.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/crc.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/delay_line.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/delay_line.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_tx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_tx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_rx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_rx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter_promisc.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter_promisc.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/ll8_to_txmac.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/ll8_to_txmac.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/rxmac_to_ll8.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/rxmac_to_ll8.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_miim.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_miim.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_clockgen.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_clockgen.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/ethtx_realign.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethtx_realign.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/simple_gemac/ethrx_realign.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethrx_realign.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/timing/time_64bit.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_64bit.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/timing/time_compare.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_compare.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/timing/time_receiver.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_receiver.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/timing/time_sender.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_sender.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/timing/time_sync.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_sync.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/timing/timer.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/timer.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/timing/simple_timer.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/simple_timer.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/8b10b/decode_8b10b.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/decode_8b10b.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/8b10b/encode_8b10b.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/encode_8b10b.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v\"
into library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
file
"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
line 131
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v\"
into library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
file
"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
line 131
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v\
" into library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
file
"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
line 73
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v
INFO:TclTasksC - File
"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v" is
already present in the project
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
file "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v"
line 77
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v" line 41
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v
INFO:TclTasksC - File
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v" is
already present in the project
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v" line 41
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v" line 45
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v" line 46
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_config.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_config.vhd" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpupkg.vhd
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpupkg.vhd" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_rx_control.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_control.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_rx_framer.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_framer.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_rx_chain.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_chain.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_tx_control.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_control.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_tx_deframer.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_deframer.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_tx_chain.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_chain.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/gen_context_pkt.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/gen_context_pkt.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/trigger_context_pkt.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/trigger_context_pkt.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_pkt_gen.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_pkt_gen.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_rx_engine_glue.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_engine_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/vrt/vita_tx_engine_glue.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_engine_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/udp/udp_wrapper.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/udp/udp_wrapper.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/udp/fifo19_rxrealign.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/udp/fifo19_rxrealign.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/udp/prot_eng_tx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/udp/prot_eng_tx.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/udp/add_onescomp.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/udp/add_onescomp.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
Current Project:
Family: spartan3adsp
Device: xc3sd1800a
Package: fg676
/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco:
Family: spartan3
Device: xc3s2000
Package: fg456
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
Current Project:
Family: spartan3adsp
Device: xc3sd1800a
Package: fg676
/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco:
Family: spartan3
Device: xc3s2000
Package: fg456
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
Current Project:
Family: spartan3adsp
Device: xc3sd1800a
Package: fg676
/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco:
Family: spartan3
Device: xc3s2000
Package: fg456
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
Current Project:
Family: spartan3adsp
Device: xc3sd1800a
Package: fg676
/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco:
Family: spartan3
Device: xc3s2000
Package: fg456
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
Current Project:
Family: spartan3adsp
Device: xc3sd1800a
Package: fg676
/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco:
Family: spartan3
Device: xc3s2000
Package: fg456
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
Current Project:
Family: Spartan-3A DSP
Device: xc3sd1800a
Package: fg676
/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco:
Family: Spartan3
Device: xc3s50
Package: pq208
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core 'fifo_xlnx_32x36_2clk' do
not match the ISE project settings.
Family mismatch "Spartan3" vs. "Spartan-3A DSP"
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
Current Project:
Family: Spartan-3A DSP
Device: xc3sd1800a
Package: fg676
/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco:
Family: Spartan3
Device: xc3s50
Package: pq208
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
'fifo_xlnx_512x36_2clk_36to18' do not match the ISE project settings.
Family mismatch "Spartan3" vs. "Spartan-3A DSP"
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
Current Project:
Family: Spartan-3A DSP
Device: xc3sd1800a
Package: fg676
/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco:
Family: Spartan3
Device: xc3s50
Package: pq208
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
'fifo_xlnx_512x36_2clk_18to36' do not match the ISE project settings.
Family mismatch "Spartan3" vs. "Spartan-3A DSP"
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
Current Project:
Family: Spartan-3A DSP
Device: xc3sd1800a
Package: fg676
/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco:
Family: Spartan3
Device: xc3s50
Package: pq208
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
'fifo_xlnx_512x36_2clk_prog_full' do not match the ISE project settings.
Family mismatch "Spartan3" vs. "Spartan-3A DSP"
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit
'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/ext_fifo.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/ext_fifo.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit
'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/nobl_if.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_if.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit
'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/nobl_fifo.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_fifo.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit
'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/icon.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit
'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
Current Project:
Family: spartan3adsp
Device: xc3sd1800a
Package: fg676
/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco:
Family: spartan3
Device: xc3s2000
Package: fg456
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
line 0 (active)
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
36
WARNING:ProjectMgmt:565 - Duplicate Design Unit
'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/ila.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
line 0 (active)
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
36
WARNING:ProjectMgmt:565 - Duplicate Design Unit
'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco
WARNING:ProjectMgmt:687 - Settings mismatch:
Current Project:
Family: spartan3adsp
Device: xc3sd1800a
Package: fg676
/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco:
Family: spartan3
Device: xc3s2000
Package: fg456
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
line 0 (active)
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
36
WARNING:ProjectMgmt:565 - Duplicate Design Unit
'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'ila' found in library 'work'
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco" line
0 (active)
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
36
>>> Adding source to project: /home/usrp/uhd/fpga/usrp2/extramfifo/refill_randomizer.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/refill_randomizer.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
line 0 (active)
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
36
WARNING:ProjectMgmt:565 - Duplicate Design Unit
'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'ila' found in library 'work'
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco" line
0 (active)
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
36
>>> Adding custom source to project: /home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/CRC16_D16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller16.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/bin2gray.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/bootram.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/dbsm.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/dcache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/decoder_3_8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/double_buffer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/dpram32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/fifo_to_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/gpio_atr.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/gray2bin.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/gray_send.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/icache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/longfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/medfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/mux4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/mux8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio16LE.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/oneshot_2clk.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/pic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/priority_enc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/quad_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_2port.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harv_cache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_loader.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/reset_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/s3a_icap_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/setting_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_16LE.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_crossclock.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_fifo_ctrl.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_i2c_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_spi_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/srl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/system_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/user_settings.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_1master.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_bridge_16_32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux_16LE.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/ext_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_if.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/refill_randomizer.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/add_routing_header.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/buffer_pool.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/crossbar36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/dsp_framer36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_pad.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_demux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_long.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_pacer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_short.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/ll8_shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x3.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_padder36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_router.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/splitter36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/valve36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/decode_8b10b.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/encode_8b10b.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v\"
into library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
file
"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
line 131
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v\
" into library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
file
"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
line 73
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
file "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v"
line 77
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v" line 45
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v" line 46
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/acc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_dec_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_decim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_int_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_strober.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_stage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_z24.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/ddc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_tx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_16to8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_8to16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/duc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipectrl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipestage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_sd.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_dcoffset.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_frontend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/sign_extend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/tx_frontend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter_promisc.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/crc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/delay_line.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethrx_realign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethtx_realign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/ll8_to_txmac.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_clockgen.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_miim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/rxmac_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_rx.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_tx.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wb.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/simple_timer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_64bit.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_compare.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_receiver.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_sender.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/timer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/top/N2x0/capture_ddrlvds.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v\" into library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/top/N2x0/bootloader.rmi' in file
"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v" line 356
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/udp/add_onescomp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/udp/fifo19_rxrealign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/udp/prot_eng_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/udp/udp_wrapper.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/gen_context_pkt.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/trigger_context_pkt.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_pkt_gen.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_engine_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_framer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_deframer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_engine_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
line 0 (active)
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
36
WARNING:ProjectMgmt:565 - Duplicate Design Unit
'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'ila' found in library 'work'
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco" line
0 (active)
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
36
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
Please set the new top explicitly by running the "project set top" command.
To re-calculate the new top automatically, set the "Auto Implementation Top"
property to true.
>>> Setting: Synthesize - XST[Number of Clock Buffers] = 8
>>> Setting: Synthesize - XST[Pack I/O Registers into IOBs] = Yes
>>> Setting: Synthesize - XST[Optimization Effort] = High
>>> Setting: Synthesize - XST[Optimize Instantiated Primitives] = TRUE
>>> Setting: Synthesize - XST[Register Balancing] = Yes
>>> Setting: Synthesize - XST[Use Clock Enable] = Auto
>>> Setting: Synthesize - XST[Use Synchronous Reset] = Auto
>>> Setting: Synthesize - XST[Use Synchronous Set] = Auto
>>> Setting: Synthesize - XST[Verilog Macros] = LVDS=1|RX_DSP0_MODULE=custom_dsp_rx
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/CRC16_D16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller16.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/bin2gray.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/bootram.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/dbsm.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/dcache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/decoder_3_8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/double_buffer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/dpram32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/fifo_to_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/gpio_atr.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/gray2bin.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/gray_send.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/icache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/longfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/medfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/mux4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/mux8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio16LE.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/oneshot_2clk.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/pic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/priority_enc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/quad_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_2port.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harv_cache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_loader.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/reset_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/s3a_icap_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/setting_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_16LE.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_crossclock.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_fifo_ctrl.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_i2c_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_spi_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/srl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/system_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/user_settings.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_1master.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_bridge_16_32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux_16LE.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/ext_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_if.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/refill_randomizer.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/add_routing_header.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/buffer_pool.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/crossbar36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/dsp_framer36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_pad.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_demux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_long.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_pacer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_short.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/ll8_shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x3.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_padder36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_router.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/splitter36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/valve36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/decode_8b10b.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/encode_8b10b.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v\"
into library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
file
"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
line 131
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v\
" into library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
file
"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
line 73
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
file "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v"
line 77
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v" line 45
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v" line 46
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/acc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_dec_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_decim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_int_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_strober.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_stage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_z24.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/ddc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_tx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_16to8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_8to16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/duc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipectrl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipestage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_sd.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_dcoffset.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_frontend.v\" into library work