gistfile1.vhdl

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity UARTM is
    Port ( inRST : in  STD_LOGIC;
           iCLK : in  STD_LOGIC;
           RXD : in  STD_LOGIC;
           DATAout : out  STD_LOGIC_VECTOR (7 downto 0);
			  test_tick : out STD_LOGIC;
			  test_big_tick : out STD_LOGIC);
end UARTM;

architecture Behavioral of UARTM is

		type tSTATE is (STANDBY, RECEIVE);
		
		signal sSTATE : tSTATE; --Current state
		signal nSTATE : tSTATE; --Next state
		 
		signal tick : std_logic; -- 16x baud rate
		signal tick_counter : std_logic_vector (6 downto 0);
		
		signal FRAME : std_logic_vector (7 downto 0); -- Data frame
		signal data_counter : std_logic_vector (3 downto 0);
		signal cycle_counter :std_logic_vector (3 downto 0);	
		
		signal big_tick : std_logic;
		
begin

-----------CLOCK GEN 16x baud--------------------

		process (iCLK, inRST) begin
        if (inRST = '0') then
		  
            tick <= '0';
				tick_counter <= (others => '0');		
				
        elsif (iCLK'event and iCLK = '1') then
		  
				if (tick_counter = 87) then -- 27 MHz oscillator, baud 19200

					tick <= '1';
					tick_counter <= (others => '0');
					
				else
				
					tick <= '0';
					tick_counter <= tick_counter + 1;
					
				end if;

		  end if;
		  
		end process;
		
		test_tick <= tick;
		
		
-----------STATE SWITCH-------------------------
		
		process (iCLK, inRST) begin
        if (inRST = '0') then
		  
            sSTATE <= STANDBY;
				
        elsif (iCLK'event and iCLK = '1') then
		  
				sSTATE <= nSTATE;		

		  end if;
		  
		end process;
		
		
----------STATES-------------------------------

		process (sSTATE, RXD, tick) begin

			case (sSTATE) is
			
				when STANDBY =>
				
					FRAME <= (others => '0');
					data_counter <= (others => '0');
					cycle_counter <= (others => '0');
				
					if (RXD = '0') then
						
						nSTATE <= RECEIVE;
						
					else
					
						nSTATE <= STANDBY;
				
					end if;
				
				when RECEIVE =>
				
					nSTATE <= sSTATE;
				
					if (tick = '1') then
				
						if (cycle_counter = 8) then
						
							big_tick <= '1';
				
							if (data_counter = 9) then
				
								nSTATE <= STANDBY;
								data_counter <= (others => '0');
				
							else 
				
								FRAME <= RXD & FRAME (7 downto 1);
								data_counter <= data_counter + 1;
							
							end if;
							
						else
						
							big_tick <= '0';

						end if;	

						cycle_counter <= cycle_counter + 1;
						
					end if;
					
			end case;
					
		end process;
		
		test_big_tick <= big_tick;

----------SEND DATA--------------------------------------

		process (sSTATE) begin
		
			DATAout <= FRAME;
			
		end process;

end Behavioral;