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Created September 7, 2017 05:18
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diff --git a/arch/arm/cpu/armv7/sunxi/fel_utils.S b/arch/arm/cpu/armv7/sunxi/fel_utils.S
index bf0033552d..8912782cac 100644
--- a/arch/arm/cpu/armv7/sunxi/fel_utils.S
+++ b/arch/arm/cpu/armv7/sunxi/fel_utils.S
@@ -27,9 +27,9 @@ ENTRY(save_boot_params)
ENDPROC(save_boot_params)
ENTRY(return_to_fel)
- mov sp, r0
- mov lr, r1
ldr r0, =fel_stash
+ ldr sp, [r0, #0]
+ ldr lr, [r0, #4]
ldr r1, [r0, #20]
mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
ldr r1, [r0, #16]
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 1249547436..e372488d11 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -29,5 +29,6 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
obj-$(CONFIG_S32V234) += s32v234/
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
+obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_ARMV8_PSCI) += psci.o
obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
diff --git a/arch/arm/cpu/armv8/sunxi/Makefile b/arch/arm/cpu/armv8/sunxi/Makefile
new file mode 100644
index 0000000000..863e274f81
--- /dev/null
+++ b/arch/arm/cpu/armv8/sunxi/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2017 Vasily Khoruzhick <anarsoul@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += fel_utils.o
diff --git a/arch/arm/cpu/armv8/sunxi/fel_utils.S b/arch/arm/cpu/armv8/sunxi/fel_utils.S
new file mode 100644
index 0000000000..28998f8b8e
--- /dev/null
+++ b/arch/arm/cpu/armv8/sunxi/fel_utils.S
@@ -0,0 +1,44 @@
+/*
+ * Utility functions for FEL mode.
+ *
+ * Copyright (c) 2015 Google, Inc
+ * Copyright (c) 2017 Vasily Khoruzhick <anarsoul@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+ENTRY(return_to_fel)
+ ldr x1, =0x017000a0 // MMIO mapped RVBAR[0] register
+ ldr x0, =return_to_fel32 // return_to_fel32
+ str x0, [x1]
+ dsb sy
+ isb sy
+ mrs x0, rmr_el3 // read RMR register
+ and x0, x0, #~1 // AArch32
+ orr x0, x0, #2 // request reset
+ msr rmr_el3, x0 // write RMR register
+ isb sy
+1: wfi
+ b 1b
+ENDPROC(return_to_fel)
+
+ENTRY(return_to_fel32)
+ .word 0xe59f0028 // ldr r0, [pc, #40]
+ .word 0xe590d000 // ldr sp, [r0]
+ .word 0xe590e004 // ldr lr, [r0, #4]
+ .word 0xe5901014 // ldr r1, [r0, #20]
+ .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0}
+ .word 0xe5901010 // ldr r1, [r0, #16]
+ .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0}
+ .word 0xe590100c // ldr r1, [r0, #12]
+ .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0}
+ .word 0xe5901008 // ldr r1, [r0, #8]
+ .word 0xe129f001 // msr CPSR_fc, r1
+ .word 0xe12fff1e // bx lr
+ .word fel_stash
+ENDPROC(return_to_fel32)
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index 9c6d82dda1..df72b03215 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -16,23 +16,37 @@
tst x0, x0 // this is "b #0x84" in ARM
b reset
.space 0x7c
- .word 0xe59f1024 // ldr r1, [pc, #36] ; 0x170000a0
- .word 0xe59f0024 // ldr r0, [pc, #36] ; CONFIG_*_TEXT_BASE
- .word 0xe5810000 // str r0, [r1]
- .word 0xf57ff04f // dsb sy
- .word 0xf57ff06f // isb sy
- .word 0xee1c0f50 // mrc 15, 0, r0, cr12, cr0, {2} ; RMR
- .word 0xe3800003 // orr r0, r0, #3
- .word 0xee0c0f50 // mcr 15, 0, r0, cr12, cr0, {2} ; RMR
- .word 0xf57ff06f // isb sy
+
+ .word 0xe59f0050 // ldr r0, [pc, #80] ; 58 <.text+0x58>
+ .word 0xe580d000 // str sp, [r0]
+ .word 0xe580e004 // str lr, [r0, #4]
+ .word 0xe10fe000 // mrs lr, CPSR
+ .word 0xe580e008 // str lr, [r0, #8]
+ .word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0}
+ .word 0xe580e00c // str lr, [r0, #12]
+ .word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0}
+ .word 0xe580e010 // str lr, [r0, #16]
+ .word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0}
+ .word 0xe580e014 // str lr, [r0, #20]
+ .word 0xe59f1028 // ldr r1, [pc, #40] ; 5c <.text+0x5c>
+ .word 0xe59f0028 // ldr r0, [pc, #40] ; 60 <.text+0x60>
+ .word 0xe5810000 // str r0, [r1]
+ .word 0xf57ff04f // dsb sy
+ .word 0xf57ff06f // isb sy
+ .word 0xee1c0f50 // mrc 15, 0, r0, cr12, cr0, {2}
+ .word 0xe3800003 // orr r0, r0, #3
+ .word 0xee0c0f50 // mcr 15, 0, r0, cr12, cr0, {2}
+ .word 0xf57ff06f // isb sy
.word 0xe320f003 // wfi
- .word 0xeafffffd // b @wfi
- .word 0x017000a0 // writeable RVBAR mapping address
+ .word 0xeafffffd // b 50 <.text+0x50>
+ .word fel_stash // .word 0x57ab7add
+ .word 0x017000a0 // .word 0x017000a0
#ifdef CONFIG_SPL_BUILD
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
+
#else
/* normal execution */
b reset
diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h
index 096510b787..2625c9ebc0 100644
--- a/arch/arm/include/asm/arch-sunxi/sys_proto.h
+++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
@@ -16,12 +16,9 @@ void sdelay(unsigned long);
/* return_to_fel() - Return to BROM from SPL
*
* This returns back into the BROM after U-Boot SPL has performed its initial
- * init. It uses the provided lr and sp to do so.
- *
- * @lr: BROM link register value (return address)
- * @sp: BROM stack pointer
+ * init.
*/
-void return_to_fel(uint32_t lr, uint32_t sp);
+void return_to_fel();
/* Board / SoC level designware gmac init */
#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I_GMAC
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index f5b0fd9bf2..58b96c74c4 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -1,3 +1,4 @@
+#define DEBUG 1
/*
* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
*
@@ -150,7 +151,7 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
- return_to_fel(fel_stash.sp, fel_stash.lr);
+ return_to_fel();
return 0;
}
diff --git a/arch/arm/mach-sunxi/rmr_switch.S b/arch/arm/mach-sunxi/rmr_switch.S
index cefa93001b..58f2789ba0 100644
--- a/arch/arm/mach-sunxi/rmr_switch.S
+++ b/arch/arm/mach-sunxi/rmr_switch.S
@@ -27,6 +27,17 @@
@ code found in encoded form in boot0.h.
.text
+ ldr r0, =0x57aB7add
+ str sp, [r0]
+ str lr, [r0, #4]
+ mrs lr, CPSR
+ str lr, [r0, #8]
+ mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
+ str lr, [r0, #12]
+ mrc p15, 0, lr, c12, c0, 0 @ Read VBAR
+ str lr, [r0, #16]
+ mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
+ str lr, [r0, #20]
ldr r1, =0x017000a0 @ MMIO mapped RVBAR[0] register
ldr r0, =0x57aA7add @ start address, to be replaced
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 02d7be0849..d6ea4f7a99 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -177,9 +177,7 @@
#define CONFIG_SPL_FRAMEWORK
-#ifndef CONFIG_ARM64 /* AArch64 FEL support is not ready yet */
#define CONFIG_SPL_BOARD_LOAD_IMAGE
-#endif
#ifdef CONFIG_SUNXI_HIGH_SRAM
#define CONFIG_SPL_TEXT_BASE 0x10060 /* sram start+header */
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