Created
February 21, 2018 01:36
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00000000: 0200 lsls r0, r0, #8 | |
00000002: 2000 movs r0, #0 | |
00000004: 0CD3 lsrs r3, r2, #0x13 | |
00000006: 0000 movs r0, r0 | |
00000008: 0CE1 lsrs r1, r4, #0x13 | |
0000000a: 0000 movs r0, r0 | |
0000000c: 07DF lsls r7, r3, #0x1f | |
0000000e: 0000 movs r0, r0 | |
00000010: 0BE7 lsrs r7, r4, #0xf | |
00000012: 0000 movs r0, r0 | |
00000014: 0BE7 lsrs r7, r4, #0xf | |
00000016: 0000 movs r0, r0 | |
00000018: 0BE7 lsrs r7, r4, #0xf | |
0000001a: 0000 movs r0, r0 | |
0000001c: 0000 movs r0, r0 | |
0000001e: 0000 movs r0, r0 | |
00000020: 0000 movs r0, r0 | |
00000022: 0000 movs r0, r0 | |
00000024: 0000 movs r0, r0 | |
00000026: 0000 movs r0, r0 | |
00000028: 0000 movs r0, r0 | |
0000002a: 0000 movs r0, r0 | |
0000002c: 0BE7 lsrs r7, r4, #0xf | |
0000002e: 0000 movs r0, r0 | |
00000030: 0BE7 lsrs r7, r4, #0xf | |
00000032: 0000 movs r0, r0 | |
00000034: 0000 movs r0, r0 | |
00000036: 0000 movs r0, r0 | |
00000038: 0BE7 lsrs r7, r4, #0xf | |
0000003a: 0000 movs r0, r0 | |
0000003c: 0BE7 lsrs r7, r4, #0xf | |
0000003e: 0000 movs r0, r0 | |
00000040: 0BE7 lsrs r7, r4, #0xf | |
00000042: 0000 movs r0, r0 | |
00000044: 0BE7 lsrs r7, r4, #0xf | |
00000046: 0000 movs r0, r0 | |
00000048: 0BE7 lsrs r7, r4, #0xf | |
0000004a: 0000 movs r0, r0 | |
0000004c: 0BE7 lsrs r7, r4, #0xf | |
0000004e: 0000 movs r0, r0 | |
00000050: 0BE7 lsrs r7, r4, #0xf | |
00000052: 0000 movs r0, r0 | |
00000054: 0BE7 lsrs r7, r4, #0xf | |
00000056: 0000 movs r0, r0 | |
00000058: 0BE7 lsrs r7, r4, #0xf | |
0000005a: 0000 movs r0, r0 | |
0000005c: 0BE7 lsrs r7, r4, #0xf | |
0000005e: 0000 movs r0, r0 | |
00000060: 0BE7 lsrs r7, r4, #0xf | |
00000062: 0000 movs r0, r0 | |
00000064: 0BE7 lsrs r7, r4, #0xf | |
00000066: 0000 movs r0, r0 | |
00000068: 0BE7 lsrs r7, r4, #0xf | |
0000006a: 0000 movs r0, r0 | |
0000006c: 0BE7 lsrs r7, r4, #0xf | |
0000006e: 0000 movs r0, r0 | |
00000070: 0BE7 lsrs r7, r4, #0xf | |
00000072: 0000 movs r0, r0 | |
00000074: 0BE7 lsrs r7, r4, #0xf | |
00000076: 0000 movs r0, r0 | |
00000078: 0BE7 lsrs r7, r4, #0xf | |
0000007a: 0000 movs r0, r0 | |
0000007c: 0BE7 lsrs r7, r4, #0xf | |
0000007e: 0000 movs r0, r0 | |
00000080: 0BE7 lsrs r7, r4, #0xf | |
00000082: 0000 movs r0, r0 | |
00000084: 0BE7 lsrs r7, r4, #0xf | |
00000086: 0000 movs r0, r0 | |
00000088: 0BE7 lsrs r7, r4, #0xf | |
0000008a: 0000 movs r0, r0 | |
0000008c: 0BE7 lsrs r7, r4, #0xf | |
0000008e: 0000 movs r0, r0 | |
00000090: 0BE7 lsrs r7, r4, #0xf | |
00000092: 0000 movs r0, r0 | |
00000094: 0BE7 lsrs r7, r4, #0xf | |
00000096: 0000 movs r0, r0 | |
00000098: 0BE7 lsrs r7, r4, #0xf | |
0000009a: 0000 movs r0, r0 | |
0000009c: 0C09 lsrs r1, r1, #0x10 | |
0000009e: 0000 movs r0, r0 | |
000000a0: 0BE7 lsrs r7, r4, #0xf | |
000000a2: 0000 movs r0, r0 | |
000000a4: 0BE7 lsrs r7, r4, #0xf | |
000000a6: 0000 movs r0, r0 | |
000000a8: 0BE7 lsrs r7, r4, #0xf | |
000000aa: 0000 movs r0, r0 | |
000000ac: 0BE7 lsrs r7, r4, #0xf | |
000000ae: 0000 movs r0, r0 | |
000000b0: 0BE7 lsrs r7, r4, #0xf | |
000000b2: 0000 movs r0, r0 | |
000000b4: 0BE7 lsrs r7, r4, #0xf | |
000000b6: 0000 movs r0, r0 | |
000000b8: 0BE7 lsrs r7, r4, #0xf | |
000000ba: 0000 movs r0, r0 | |
000000bc: 0BE7 lsrs r7, r4, #0xf | |
000000be: 0000 movs r0, r0 | |
000000c0: 0BE7 lsrs r7, r4, #0xf | |
000000c2: 0000 movs r0, r0 | |
000000c4: 0BE7 lsrs r7, r4, #0xf | |
000000c6: 0000 movs r0, r0 | |
000000c8: 0BE7 lsrs r7, r4, #0xf | |
000000ca: 0000 movs r0, r0 | |
000000cc: 0BE7 lsrs r7, r4, #0xf | |
000000ce: 0000 movs r0, r0 | |
000000d0: 0BE7 lsrs r7, r4, #0xf | |
000000d2: 0000 movs r0, r0 | |
000000d4: 0BE7 lsrs r7, r4, #0xf | |
000000d6: 0000 movs r0, r0 | |
000000d8: 0BE7 lsrs r7, r4, #0xf | |
000000da: 0000 movs r0, r0 | |
000000dc: 0BE7 lsrs r7, r4, #0xf | |
000000de: 0000 movs r0, r0 | |
000000e0: 0BE7 lsrs r7, r4, #0xf | |
000000e2: 0000 movs r0, r0 | |
000000e4: 0BE7 lsrs r7, r4, #0xf | |
000000e6: 0000 movs r0, r0 | |
000000e8: 0BE7 lsrs r7, r4, #0xf | |
000000ea: 0000 movs r0, r0 | |
000000ec: 0BE7 lsrs r7, r4, #0xf | |
000000ee: 0000 movs r0, r0 | |
000000f0: 0BE7 lsrs r7, r4, #0xf | |
000000f2: 0000 movs r0, r0 | |
000000f4: 0BE7 lsrs r7, r4, #0xf | |
000000f6: 0000 movs r0, r0 | |
000000f8: 0BE7 lsrs r7, r4, #0xf | |
000000fa: 0000 movs r0, r0 | |
000000fc: 0BE7 lsrs r7, r4, #0xf | |
000000fe: 0000 movs r0, r0 | |
00000100: 0BE7 lsrs r7, r4, #0xf | |
00000102: 0000 movs r0, r0 | |
00000104: 0BE7 lsrs r7, r4, #0xf | |
00000106: 0000 movs r0, r0 | |
00000108: 0BE7 lsrs r7, r4, #0xf | |
0000010a: 0000 movs r0, r0 | |
0000010c: 0BE7 lsrs r7, r4, #0xf | |
0000010e: 0000 movs r0, r0 | |
00000110: 0BE7 lsrs r7, r4, #0xf | |
00000112: 0000 movs r0, r0 | |
00000114: 0BE7 lsrs r7, r4, #0xf | |
00000116: 0000 movs r0, r0 | |
00000118: 0BE7 lsrs r7, r4, #0xf | |
0000011a: 0000 movs r0, r0 | |
0000011c: 0BE7 lsrs r7, r4, #0xf | |
0000011e: 0000 movs r0, r0 | |
00000120: 0BE7 lsrs r7, r4, #0xf | |
00000122: 0000 movs r0, r0 | |
00000124: 0BE7 lsrs r7, r4, #0xf | |
00000126: 0000 movs r0, r0 | |
00000128: 0BE7 lsrs r7, r4, #0xf | |
0000012a: 0000 movs r0, r0 | |
0000012c: 0BE7 lsrs r7, r4, #0xf | |
0000012e: 0000 movs r0, r0 | |
00000130: 0BE7 lsrs r7, r4, #0xf | |
00000132: 0000 movs r0, r0 | |
00000134: 0BE7 lsrs r7, r4, #0xf | |
00000136: 0000 movs r0, r0 | |
00000138: 0BE7 lsrs r7, r4, #0xf | |
0000013a: 0000 movs r0, r0 | |
0000013c: 0BE7 lsrs r7, r4, #0xf | |
0000013e: 0000 movs r0, r0 | |
00000140: 0BE7 lsrs r7, r4, #0xf | |
00000142: 0000 movs r0, r0 | |
00000144: 0BE7 lsrs r7, r4, #0xf | |
00000146: 0000 movs r0, r0 | |
00000148: 0BE7 lsrs r7, r4, #0xf | |
0000014a: 0000 movs r0, r0 | |
0000014c: 0BE7 lsrs r7, r4, #0xf | |
0000014e: 0000 movs r0, r0 | |
00000150: 0000 movs r0, r0 | |
00000152: 0000 movs r0, r0 | |
00000154: 0000 movs r0, r0 | |
00000156: 0000 movs r0, r0 | |
00000158: 0BE7 lsrs r7, r4, #0xf | |
0000015a: 0000 movs r0, r0 | |
0000015c: 0BE7 lsrs r7, r4, #0xf | |
0000015e: 0000 movs r0, r0 | |
00000160: 0BE7 lsrs r7, r4, #0xf | |
00000162: 0000 movs r0, r0 | |
00000164: 0BE7 lsrs r7, r4, #0xf | |
00000166: 0000 movs r0, r0 | |
00000168: 0000 movs r0, r0 | |
0000016a: 0000 movs r0, r0 | |
0000016c: 0BE7 lsrs r7, r4, #0xf | |
0000016e: 0000 movs r0, r0 | |
00000170: 0BE7 lsrs r7, r4, #0xf | |
00000172: 0000 movs r0, r0 | |
00000174: 0BE7 lsrs r7, r4, #0xf | |
00000176: 0000 movs r0, r0 | |
00000178: 0BE7 lsrs r7, r4, #0xf | |
0000017a: 0000 movs r0, r0 | |
0000017c: 0BE7 lsrs r7, r4, #0xf | |
0000017e: 0000 movs r0, r0 | |
00000180: 0BE7 lsrs r7, r4, #0xf | |
00000182: 0000 movs r0, r0 | |
00000184: 0BE7 lsrs r7, r4, #0xf | |
00000186: 0000 movs r0, r0 | |
00000188: 0BE7 lsrs r7, r4, #0xf | |
0000018a: 0000 movs r0, r0 | |
0000018c: 0BE7 lsrs r7, r4, #0xf | |
0000018e: 0000 movs r0, r0 | |
00000190: 0BE7 lsrs r7, r4, #0xf | |
00000192: 0000 movs r0, r0 | |
00000194: 0BE7 lsrs r7, r4, #0xf | |
00000196: 0000 movs r0, r0 | |
00000198: 0BE7 lsrs r7, r4, #0xf | |
0000019a: 0000 movs r0, r0 | |
0000019c: 0BE7 lsrs r7, r4, #0xf | |
0000019e: 0000 movs r0, r0 | |
000001a0: 0BE7 lsrs r7, r4, #0xf | |
000001a2: 0000 movs r0, r0 | |
000001a4: 0BE7 lsrs r7, r4, #0xf | |
000001a6: 0000 movs r0, r0 | |
000001a8: 0BE7 lsrs r7, r4, #0xf | |
000001aa: 0000 movs r0, r0 | |
000001ac: 0BE7 lsrs r7, r4, #0xf | |
000001ae: 0000 movs r0, r0 | |
000001b0: 0BE7 lsrs r7, r4, #0xf | |
000001b2: 0000 movs r0, r0 | |
000001b4: 0BE7 lsrs r7, r4, #0xf | |
000001b6: 0000 movs r0, r0 | |
000001b8: 0BE7 lsrs r7, r4, #0xf | |
000001ba: 0000 movs r0, r0 | |
000001bc: 0BE7 lsrs r7, r4, #0xf | |
000001be: 0000 movs r0, r0 | |
000001c0: 0BE7 lsrs r7, r4, #0xf | |
000001c2: 0000 movs r0, r0 | |
000001c4: 0BE7 lsrs r7, r4, #0xf | |
000001c6: 0000 movs r0, r0 | |
000001c8: 0BE7 lsrs r7, r4, #0xf | |
000001ca: 0000 movs r0, r0 | |
000001cc: 0BE7 lsrs r7, r4, #0xf | |
000001ce: 0000 movs r0, r0 | |
000001d0: 0BE7 lsrs r7, r4, #0xf | |
000001d2: 0000 movs r0, r0 | |
000001d4: 0BE7 lsrs r7, r4, #0xf | |
000001d6: 0000 movs r0, r0 | |
000001d8: 0BE7 lsrs r7, r4, #0xf | |
000001da: 0000 movs r0, r0 | |
000001dc: 0BE7 lsrs r7, r4, #0xf | |
000001de: 0000 movs r0, r0 | |
000001e0: 0BE7 lsrs r7, r4, #0xf | |
000001e2: 0000 movs r0, r0 | |
000001e4: 0BE7 lsrs r7, r4, #0xf | |
000001e6: 0000 movs r0, r0 | |
000001e8: 0BE7 lsrs r7, r4, #0xf | |
000001ea: 0000 movs r0, r0 | |
000001ec: 0BE7 lsrs r7, r4, #0xf | |
000001ee: 0000 movs r0, r0 | |
000001f0: 0BE7 lsrs r7, r4, #0xf | |
000001f2: 0000 movs r0, r0 | |
000001f4: 0BE7 lsrs r7, r4, #0xf | |
000001f6: 0000 movs r0, r0 | |
000001f8: 0BE7 lsrs r7, r4, #0xf | |
000001fa: 0000 movs r0, r0 | |
000001fc: 0BE7 lsrs r7, r4, #0xf | |
000001fe: 0000 movs r0, r0 | |
00000200: 0BE7 lsrs r7, r4, #0xf | |
00000202: 0000 movs r0, r0 | |
00000204: 0000 movs r0, r0 | |
00000206: 0000 movs r0, r0 | |
67 { | |
PinoutSet(): | |
00000208: B5F8 push {r3, r4, r5, r6, r7, lr} | |
0000020a: 4606 mov r6, r0 | |
71 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); | |
0000020c: F04F7480 mov.w r4, #0x1000000 | |
00000210: 6C60 ldr r0, [r4, #0x44] | |
85 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ); | |
00000212: 4D73 ldr r5, [pc, #0x1cc] | |
71 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); | |
00000214: 6980 ldr r0, [r0, #0x18] | |
67 { | |
00000216: 460F mov r7, r1 | |
71 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); | |
00000218: 4601 mov r1, r0 | |
0000021a: 4628 mov r0, r5 | |
0000021c: 1E40 subs r0, r0, #1 | |
0000021e: 4788 blx r1 | |
72 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); | |
00000220: 6C60 ldr r0, [r4, #0x44] | |
00000222: 6980 ldr r0, [r0, #0x18] | |
00000224: 4601 mov r1, r0 | |
00000226: 4628 mov r0, r5 | |
00000228: 4788 blx r1 | |
73 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); | |
0000022a: 6C60 ldr r0, [r4, #0x44] | |
0000022c: 6980 ldr r0, [r0, #0x18] | |
0000022e: 4601 mov r1, r0 | |
00000230: 4628 mov r0, r5 | |
00000232: 1C40 adds r0, r0, #1 | |
00000234: 4788 blx r1 | |
74 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); | |
00000236: 6C60 ldr r0, [r4, #0x44] | |
00000238: 6980 ldr r0, [r0, #0x18] | |
0000023a: 4601 mov r1, r0 | |
0000023c: 4628 mov r0, r5 | |
0000023e: 1C80 adds r0, r0, #2 | |
00000240: 4788 blx r1 | |
75 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); | |
00000242: 6C60 ldr r0, [r4, #0x44] | |
00000244: 6980 ldr r0, [r0, #0x18] | |
00000246: 4601 mov r1, r0 | |
00000248: 4628 mov r0, r5 | |
0000024a: 1CC0 adds r0, r0, #3 | |
0000024c: 4788 blx r1 | |
76 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); | |
0000024e: 6C60 ldr r0, [r4, #0x44] | |
00000250: 6980 ldr r0, [r0, #0x18] | |
00000252: 4601 mov r1, r0 | |
00000254: 4628 mov r0, r5 | |
00000256: 1D00 adds r0, r0, #4 | |
00000258: 4788 blx r1 | |
77 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG); | |
0000025a: 6C60 ldr r0, [r4, #0x44] | |
0000025c: 6980 ldr r0, [r0, #0x18] | |
0000025e: 4601 mov r1, r0 | |
00000260: 4628 mov r0, r5 | |
00000262: 1D40 adds r0, r0, #5 | |
00000264: 4788 blx r1 | |
78 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH); | |
00000266: 6C60 ldr r0, [r4, #0x44] | |
00000268: 6980 ldr r0, [r0, #0x18] | |
0000026a: 4601 mov r1, r0 | |
0000026c: 4628 mov r0, r5 | |
0000026e: 1D80 adds r0, r0, #6 | |
00000270: 4788 blx r1 | |
79 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ); | |
00000272: 6C60 ldr r0, [r4, #0x44] | |
00000274: 6980 ldr r0, [r0, #0x18] | |
00000276: 4601 mov r1, r0 | |
00000278: 4628 mov r0, r5 | |
0000027a: 1DC0 adds r0, r0, #7 | |
0000027c: 4788 blx r1 | |
80 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK); | |
0000027e: 6C60 ldr r0, [r4, #0x44] | |
00000280: 6980 ldr r0, [r0, #0x18] | |
00000282: 4601 mov r1, r0 | |
00000284: 4628 mov r0, r5 | |
00000286: 3008 adds r0, #8 | |
00000288: 4788 blx r1 | |
81 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL); | |
0000028a: 6C60 ldr r0, [r4, #0x44] | |
0000028c: 6980 ldr r0, [r0, #0x18] | |
0000028e: 4601 mov r1, r0 | |
00000290: 4628 mov r0, r5 | |
00000292: 3009 adds r0, #9 | |
00000294: 4788 blx r1 | |
82 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM); | |
00000296: 6C60 ldr r0, [r4, #0x44] | |
00000298: 6980 ldr r0, [r0, #0x18] | |
0000029a: 4601 mov r1, r0 | |
0000029c: 4628 mov r0, r5 | |
0000029e: 300A adds r0, #0xa | |
000002a0: 4788 blx r1 | |
83 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION); | |
000002a2: 6C60 ldr r0, [r4, #0x44] | |
000002a4: 6980 ldr r0, [r0, #0x18] | |
000002a6: 4601 mov r1, r0 | |
000002a8: 4628 mov r0, r5 | |
000002aa: 300B adds r0, #0xb | |
000002ac: 4788 blx r1 | |
84 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP); | |
000002ae: 6C60 ldr r0, [r4, #0x44] | |
000002b0: 6980 ldr r0, [r0, #0x18] | |
000002b2: 4601 mov r1, r0 | |
000002b4: 4628 mov r0, r5 | |
000002b6: 300C adds r0, #0xc | |
000002b8: 4788 blx r1 | |
85 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ); | |
000002ba: 6C60 ldr r0, [r4, #0x44] | |
000002bc: 6980 ldr r0, [r0, #0x18] | |
000002be: 4601 mov r1, r0 | |
000002c0: 4628 mov r0, r5 | |
000002c2: 300D adds r0, #0xd | |
000002c4: 4788 blx r1 | |
90 ROM_GPIOPinConfigure(GPIO_PA0_U0RX); | |
000002c6: 6A20 ldr r0, [r4, #0x20] | |
000002c8: 6E80 ldr r0, [r0, #0x68] | |
000002ca: 4601 mov r1, r0 | |
000002cc: 2001 movs r0, #1 | |
000002ce: 4788 blx r1 | |
91 ROM_GPIOPinConfigure(GPIO_PA1_U0TX); | |
000002d0: 6A20 ldr r0, [r4, #0x20] | |
000002d2: 6E80 ldr r0, [r0, #0x68] | |
000002d4: 4601 mov r1, r0 | |
000002d6: F2404001 movw r0, #0x401 | |
000002da: 4788 blx r1 | |
92 ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); | |
000002dc: 6A20 ldr r0, [r4, #0x20] | |
000002de: 6D40 ldr r0, [r0, #0x54] | |
000002e0: 2103 movs r1, #3 | |
000002e2: 4602 mov r2, r0 | |
000002e4: F04F2040 mov.w r0, #0x40004000 | |
000002e8: 4790 blx r2 | |
105 ROM_GPIOPinTypeUSBDigital(GPIO_PORTD_BASE, GPIO_PIN_6); | |
000002ea: 4D3E ldr r5, [pc, #0xf8] | |
99 if(bUSB) | |
000002ec: 2F01 cmp r7, #1 | |
000002ee: D00C beq $C$L1 | |
115 ROM_GPIOPinTypeGPIOInput(GPIO_PORTD_BASE, GPIO_PIN_6); | |
000002f0: 6A20 ldr r0, [r4, #0x20] | |
000002f2: 6B80 ldr r0, [r0, #0x38] | |
000002f4: 2140 movs r1, #0x40 | |
000002f6: 4602 mov r2, r0 | |
000002f8: 4628 mov r0, r5 | |
000002fa: 4790 blx r2 | |
116 MAP_GPIOPadConfigSet(GPIO_PORTD_BASE, GPIO_PIN_6, GPIO_STRENGTH_2MA, | |
000002fc: 4628 mov r0, r5 | |
000002fe: 2140 movs r1, #0x40 | |
00000300: 2201 movs r2, #1 | |
00000302: 230C movs r3, #0xc | |
00000304: F000F984 bl #0x610 | |
00000308: E021 b $C$L2 | |
101 HWREG(GPIO_PORTD_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY; | |
$C$L1: | |
0000030a: 4837 ldr r0, [pc, #0xdc] | |
0000030c: 4A37 ldr r2, [pc, #0xdc] | |
0000030e: 6002 str r2, [r0] | |
102 HWREG(GPIO_PORTD_BASE + GPIO_O_CR) = 0xff; | |
00000310: 21FF movs r1, #0xff | |
00000312: 6041 str r1, [r0, #4] | |
103 ROM_GPIOPinConfigure(GPIO_PD6_USB0EPEN); | |
00000314: 6A20 ldr r0, [r4, #0x20] | |
00000316: 6E80 ldr r0, [r0, #0x68] | |
00000318: 4601 mov r1, r0 | |
0000031a: 4835 ldr r0, [pc, #0xd4] | |
0000031c: 4788 blx r1 | |
104 ROM_GPIOPinTypeUSBAnalog(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1); | |
0000031e: 6A20 ldr r0, [r4, #0x20] | |
00000320: 6F00 ldr r0, [r0, #0x70] | |
00000322: 4602 mov r2, r0 | |
00000324: 4833 ldr r0, [pc, #0xcc] | |
00000326: 2103 movs r1, #3 | |
00000328: 4790 blx r2 | |
105 ROM_GPIOPinTypeUSBDigital(GPIO_PORTD_BASE, GPIO_PIN_6); | |
0000032a: 6A20 ldr r0, [r4, #0x20] | |
0000032c: 6E00 ldr r0, [r0, #0x60] | |
0000032e: 2140 movs r1, #0x40 | |
00000330: 4602 mov r2, r0 | |
00000332: 4628 mov r0, r5 | |
00000334: 4790 blx r2 | |
106 ROM_GPIOPinTypeUSBAnalog(GPIO_PORTL_BASE, GPIO_PIN_6 | GPIO_PIN_7); | |
00000336: 6A20 ldr r0, [r4, #0x20] | |
00000338: 6F00 ldr r0, [r0, #0x70] | |
0000033a: 4602 mov r2, r0 | |
0000033c: 482E ldr r0, [pc, #0xb8] | |
0000033e: 21C0 movs r1, #0xc0 | |
00000340: 4790 blx r2 | |
107 ROM_GPIOPinTypeGPIOInput(GPIO_PORTQ_BASE, GPIO_PIN_4); | |
00000342: 6A20 ldr r0, [r4, #0x20] | |
00000344: 6B80 ldr r0, [r0, #0x38] | |
00000346: 4602 mov r2, r0 | |
00000348: 482C ldr r0, [pc, #0xb0] | |
0000034a: 2110 movs r1, #0x10 | |
0000034c: 4790 blx r2 | |
132 GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_4); | |
$C$L2: | |
0000034e: 4D2C ldr r5, [pc, #0xb0] | |
124 if(bEthernet) | |
00000350: 2E01 cmp r6, #1 | |
00000352: D013 beq $C$L3 | |
142 ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_4); | |
00000354: 6A20 ldr r0, [r4, #0x20] | |
00000356: 6BC0 ldr r0, [r0, #0x3c] | |
00000358: 2111 movs r1, #0x11 | |
0000035a: 4602 mov r2, r0 | |
0000035c: 4628 mov r0, r5 | |
0000035e: 4790 blx r2 | |
147 ROM_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_4, 0); | |
00000360: 6A20 ldr r0, [r4, #0x20] | |
00000362: 6800 ldr r0, [r0] | |
00000364: 2111 movs r1, #0x11 | |
00000366: 2200 movs r2, #0 | |
00000368: 4603 mov r3, r0 | |
0000036a: 4628 mov r0, r5 | |
0000036c: 4798 blx r3 | |
148 MAP_GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_4, | |
0000036e: 4628 mov r0, r5 | |
00000370: 2111 movs r1, #0x11 | |
00000372: 2277 movs r2, #0x77 | |
00000374: 2308 movs r3, #8 | |
00000376: F000F94B bl #0x610 | |
0000037a: E00E b $C$L4 | |
129 ROM_GPIOPinConfigure(GPIO_PF0_EN0LED0); | |
$C$L3: | |
0000037c: 6A20 ldr r0, [r4, #0x20] | |
0000037e: 6E80 ldr r0, [r0, #0x68] | |
00000380: 4601 mov r1, r0 | |
00000382: F04F1005 mov.w r0, #0x50005 | |
00000386: 4788 blx r1 | |
130 ROM_GPIOPinConfigure(GPIO_PF4_EN0LED1); | |
00000388: 6A20 ldr r0, [r4, #0x20] | |
0000038a: 6E80 ldr r0, [r0, #0x68] | |
0000038c: 4601 mov r1, r0 | |
0000038e: 481D ldr r0, [pc, #0x74] | |
00000390: 4788 blx r1 | |
132 GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_4); | |
00000392: 4628 mov r0, r5 | |
00000394: 2111 movs r1, #0x11 | |
00000396: F000FC67 bl #0xc68 | |
157 ROM_GPIOPinTypeGPIOInput(GPIO_PORTJ_BASE, GPIO_PIN_0 | GPIO_PIN_1); | |
$C$L4: | |
0000039a: 6A20 ldr r0, [r4, #0x20] | |
158 ROM_GPIOPinWrite(GPIO_PORTJ_BASE, GPIO_PIN_0 | GPIO_PIN_1, 0); | |
0000039c: 4D1A ldr r5, [pc, #0x68] | |
157 ROM_GPIOPinTypeGPIOInput(GPIO_PORTJ_BASE, GPIO_PIN_0 | GPIO_PIN_1); | |
0000039e: 6B80 ldr r0, [r0, #0x38] | |
000003a0: 2103 movs r1, #3 | |
000003a2: 4602 mov r2, r0 | |
000003a4: 4628 mov r0, r5 | |
000003a6: 4790 blx r2 | |
158 ROM_GPIOPinWrite(GPIO_PORTJ_BASE, GPIO_PIN_0 | GPIO_PIN_1, 0); | |
000003a8: 6A20 ldr r0, [r4, #0x20] | |
000003aa: 6800 ldr r0, [r0] | |
000003ac: 2103 movs r1, #3 | |
000003ae: 2200 movs r2, #0 | |
000003b0: 4603 mov r3, r0 | |
000003b2: 4628 mov r0, r5 | |
000003b4: 4798 blx r3 | |
163 ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_0 | GPIO_PIN_1); | |
000003b6: 6A20 ldr r0, [r4, #0x20] | |
170 ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0 | GPIO_PIN_1, 0); | |
000003b8: 4D14 ldr r5, [pc, #0x50] | |
163 ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_0 | GPIO_PIN_1); | |
000003ba: 6BC0 ldr r0, [r0, #0x3c] | |
000003bc: 2103 movs r1, #3 | |
000003be: 4602 mov r2, r0 | |
000003c0: 4628 mov r0, r5 | |
000003c2: 4790 blx r2 | |
164 MAP_GPIOPadConfigSet(GPIO_PORTN_BASE, GPIO_PIN_0 | GPIO_PIN_1, | |
000003c4: 2103 movs r1, #3 | |
000003c6: 2277 movs r2, #0x77 | |
000003c8: 2308 movs r3, #8 | |
000003ca: 4628 mov r0, r5 | |
000003cc: F000F920 bl #0x610 | |
170 ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0 | GPIO_PIN_1, 0); | |
000003d0: 6A20 ldr r0, [r4, #0x20] | |
000003d2: 6800 ldr r0, [r0] | |
000003d4: 2103 movs r1, #3 | |
000003d6: 2200 movs r2, #0 | |
000003d8: 4603 mov r3, r0 | |
000003da: 4628 mov r0, r5 | |
000003dc: 4798 blx r3 | |
000003de: BDF8 pop {r3, r4, r5, r6, r7, pc} | |
$C$CON2: | |
000003e0: 0801 lsrs r1, r0, #0x20 | |
000003e2: F0007000 and r0, r0, #0x2000000 | |
000003e6: 4000 ands r0, r0 | |
$C$CON17: | |
000003e8: 7520 strb r0, [r4, #0x14] | |
000003ea: 4000 ands r0, r0 | |
$C$CON18: | |
000003ec: 434B muls r3, r1, r3 | |
000003ee: 4C4F ldr r4, [pc, #0x13c] | |
$C$CON19: | |
000003f0: 1805 adds r5, r0, r0 | |
000003f2: 0003 movs r3, r0 | |
$C$CON20: | |
000003f4: 5000 str r0, [r0, r0] | |
000003f6: 4000 ands r0, r0 | |
$C$CON21: | |
000003f8: 2000 movs r0, #0 | |
000003fa: 4006 ands r6, r0 | |
$C$CON22: | |
000003fc: 6000 str r0, [r0] | |
000003fe: 4006 ands r6, r0 | |
$C$CON23: | |
00000400: 5000 str r0, [r0, r0] | |
00000402: 4002 ands r2, r0 | |
$C$CON24: | |
00000404: 1005 asrs r5, r0, #0x20 | |
00000406: 0005 movs r5, r0 | |
$C$CON25: | |
00000408: D000 beq $C$CON26 | |
0000040a: 4003 ands r3, r0 | |
$C$CON26: | |
0000040c: 4000 ands r0, r0 | |
0000040e: 4006 ands r6, r0 | |
2127 { | |
SysCtlClockFreqSet(): | |
00000410: E92D43F8 push.w {r3, r4, r5, r6, r7, r8, r9, lr} | |
00000414: 4605 mov r5, r0 | |
2136 if(CLASS_IS_TM4C123) | |
00000416: 4C7D ldr r4, [pc, #0x1f4] | |
00000418: 4A72 ldr r2, [pc, #0x1c8] | |
0000041a: 4873 ldr r0, [pc, #0x1cc] | |
2127 { | |
0000041c: 460F mov r7, r1 | |
2136 if(CLASS_IS_TM4C123) | |
0000041e: 3CB0 subs r4, #0xb0 | |
00000420: F8541CB0 ldr r1, [r4, #-0xb0] | |
00000424: 400A ands r2, r1 | |
00000426: 4290 cmp r0, r2 | |
00000428: D048 beq $C$L54 | |
2397 HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(16000000); | |
0000042a: 4871 ldr r0, [pc, #0x1c4] | |
2149 if((ui32Config & 0x38) == SYSCTL_OSC_INT) | |
0000042c: F0050138 and r1, r5, #0x38 | |
2144 i32XtalIdx = SysCtlXtalCfgToIndex(ui32Config); | |
00000430: F3C51884 ubfx r8, r5, #6, #5 | |
2149 if((ui32Config & 0x38) == SYSCTL_OSC_INT) | |
00000434: 2910 cmp r1, #0x10 | |
00000436: D035 beq $C$L52 | |
2164 else if((ui32Config & 0x38) == SYSCTL_OSC_INT30) | |
00000438: 2930 cmp r1, #0x30 | |
0000043a: D02E beq $C$L51 | |
2172 else if((ui32Config & 0x38) == (SYSCTL_OSC_EXT32 & 0x38)) | |
0000043c: 2938 cmp r1, #0x38 | |
0000043e: D027 beq $C$L50 | |
2180 else if((ui32Config & 0x38) == SYSCTL_OSC_MAIN) | |
00000440: F0150F38 tst.w r5, #0x38 | |
00000444: D120 bne $C$L49 | |
2187 if((i32XtalIdx > (SysCtlXtalCfgToIndex(SYSCTL_XTAL_25MHZ))) || | |
00000446: F1B80F1A cmp.w r8, #0x1a | |
0000044a: DC37 bgt $C$L54 | |
0000044c: F1B80F09 cmp.w r8, #9 | |
00000450: DB34 blt $C$L54 | |
2205 ui32MOSCCTL = HWREG(SYSCTL_MOSCCTL) & | |
00000452: F854CC34 ldr r12, [r4, #-0x34] | |
2193 ui32Osc = g_pui32Xtals[i32XtalIdx]; | |
00000456: 4A65 ldr r2, [pc, #0x194] | |
00000458: 0929 lsrs r1, r5, #4 | |
2199 ui32OscSelect |= SYSCTL_RSCLKCFG_PLLSRC_MOSC; | |
0000045a: F04F764C mov.w r6, #0x3300000 | |
2223 ui32Delay = 524288; | |
0000045e: F44F2300 mov.w r3, #0x80000 | |
2193 ui32Osc = g_pui32Xtals[i32XtalIdx]; | |
00000462: F001017C and r1, r1, #0x7c | |
2205 ui32MOSCCTL = HWREG(SYSCTL_MOSCCTL) & | |
00000466: F02C0C1C bic r12, r12, #0x1c | |
2205 ui32MOSCCTL = HWREG(SYSCTL_MOSCCTL) & | |
00000467: 1CF0 .word 0x00001cf0 | |
......... 4C0C .word 0x00004c0c | |
2218 HWREG(SYSCTL_MOSCCTL) = ui32MOSCCTL; | |
0000046a: F04C0C10 orr r12, r12, #0x10 | |
0000046b: 10F0 .word 0x000010f0 | |
......... 520C .word 0x0000520c | |
2193 ui32Osc = g_pui32Xtals[i32XtalIdx]; | |
0000046e: F8529001 ldr.w r9, [r2, r1] | |
2193 ui32Osc = g_pui32Xtals[i32XtalIdx]; | |
0000046f: 01F8 .word 0x000001f8 | |
......... 4490 .word 0x00004490 | |
2218 HWREG(SYSCTL_MOSCCTL) = ui32MOSCCTL; | |
00000472: F844CC34 str r12, [r4, #-0x34] | |
2218 HWREG(SYSCTL_MOSCCTL) = ui32MOSCCTL; | |
00000473: 34F8 .word 0x000034f8 | |
......... 54CC .word 0x000054cc | |
2225 while((HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS) == 0) | |
$C$L47: | |
00000476: F8541C60 ldr r1, [r4, #-0x60] | |
00000477: 60F8 .word 0x000060f8 | |
00000479: 491C .word 0x0000491c | |
0000047b: 020A .word 0x0000020a | |
......... 5BD2 .word 0x00005bd2 | |
2231 break; | |
0000047e: 1E5B subs r3, r3, #1 | |
0000047f: F91E1BD1 .word 0x1bd1f91e | |
00000483: 93E0 .word 0x000093e0 | |
00000485: 19B9 .word 0x000019b9 | |
2239 if(ui32Delay == 0) | |
00000487: 4FE0 .word 0x00004fe0 | |
2252 ui32Osc = 0; | |
00000489: 00F0 .word 0x000000f0 | |
0000048b: 4E09 .word 0x00004e09 | |
0000048d: 0D46 .word 0x00000d46 | |
2253 ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_PIOSC; | |
0000048f: 4FE0 .word 0x00004fe0 | |
2177 ui32Osc = 32768; | |
00000491: 00F4 .word 0x000000f4 | |
00000493: 4F49 .word 0x00004f49 | |
2178 ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_RTC; | |
00000495: 80F4 .word 0x000080f4 | |
00000497: 0806 .word 0x00000806 | |
2179 } | |
00000499: 47E0 .word 0x000047e0 | |
2169 ui32Osc = 30000; | |
0000049b: 30F2 .word 0x000030f2 | |
0000049d: 4F59 .word 0x00004f59 | |
2170 ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_LFIOSC; | |
0000049f: 00F4 .word 0x000000f4 | |
000004a1: 0316 .word 0x00000316 | |
2171 } | |
000004a3: 81E0 .word 0x000081e0 | |
2155 ui32Osc = 16000000; | |
000004a5: 0046 .word 0x00000046 | |
2156 ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_PIOSC; | |
000004a7: 4F26 .word 0x00004f26 | |
2162 i32XtalIdx = SysCtlXtalCfgToIndex(SYSCTL_XTAL_16MHZ); | |
000004a9: 15F0 .word 0x000015f0 | |
000004ab: 1508 .word 0x00001508 | |
2259 if((ui32Config & SYSCTL_USE_OSC) == SYSCTL_USE_PLL) | |
000004ad: 60F4 .word 0x000060f4 | |
000004af: 6C5F .word 0x00006c5f | |
000004b1: 15D1 .word 0x000015d1 | |
2264 if(((ui32Config & 0x38) != SYSCTL_OSC_MAIN) && | |
000004b3: 38F0 .word 0x000038f0 | |
000004b5: 0400 .word 0x00000400 | |
000004b7: 10D0 .word 0x000010d0 | |
000004b9: 0228 .word 0x00000228 | |
000004bb: 00D0 .word 0x000000d0 | |
2267 return(0); | |
000004bd: BD20 .word 0x0000bd20 | |
000004bf: F8E84C83 .word 0x4c83f8e8 | |
2285 HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(25000000); | |
000004c3: 0048 .word 0x00000048 | |
000004c5: 90F0 .word 0x000090f0 | |
000004c7: 20FB .word 0x000020fb | |
000004c9: 4B61 .word 0x00004b61 | |
2290 ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG) & | |
000004cb: 2148 .word 0x00002148 | |
000004cd: DF68 .word 0x0000df68 | |
2326 HWREG(SYSCTL_PLLFREQ1) = | |
000004cf: 2CF8 .word 0x00002cf8 | |
......... 08C1 .word 0x000008c1 | |
2290 ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG) & | |
000004d2: 4008 ands r0, r1 | |
2290 ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG) & | |
......... ... | |
2303 HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; | |
000004d4: F0404000 orr r0, r0, #0x80000000 | |
000004d8: 6020 str r0, [r4] | |
2320 HWREG(SYSCTL_RSCLKCFG) |= ui32OscSelect; | |
000004da: 6823 ldr r3, [r4] | |
000004dc: F1A80209 sub.w r2, r8, #9 | |
000004e0: F3C56102 ubfx r1, r5, #0x18, #3 | |
000004e4: 0048 lsls r0, r1, #1 | |
000004e6: EB001001 add.w r0, r0, r1, lsl #4 | |
000004ea: 1812 adds r2, r2, r0 | |
000004ec: 0090 lsls r0, r2, #2 | |
000004ee: EB0000C2 add.w r0, r0, r2, lsl #3 | |
2320 HWREG(SYSCTL_RSCLKCFG) |= ui32OscSelect; | |
000004f2: EA460203 orr.w r2, r6, r3 | |
2326 HWREG(SYSCTL_PLLFREQ1) = | |
000004f6: EB0C0100 add.w r1, r12, r0 | |
2328 HWREG(SYSCTL_PLLFREQ1) |= PLL_Q_TO_REG(ui32SysDiv); | |
000004fa: 0DAB lsrs r3, r5, #0x16 | |
2326 HWREG(SYSCTL_PLLFREQ1) = | |
000004fc: 6849 ldr r1, [r1, #4] | |
2328 HWREG(SYSCTL_PLLFREQ1) |= PLL_Q_TO_REG(ui32SysDiv); | |
000004fe: 4D40 ldr r5, [pc, #0x100] | |
2320 HWREG(SYSCTL_RSCLKCFG) |= ui32OscSelect; | |
00000500: 6022 str r2, [r4] | |
2328 HWREG(SYSCTL_PLLFREQ1) |= PLL_Q_TO_REG(ui32SysDiv); | |
00000502: F003031C and r3, r3, #0x1c | |
2326 HWREG(SYSCTL_PLLFREQ1) = | |
00000506: F8C410B4 str.w r1, [r4, #0xb4] | |
2328 HWREG(SYSCTL_PLLFREQ1) |= PLL_Q_TO_REG(ui32SysDiv); | |
0000050a: 58E9 ldr r1, [r5, r3] | |
0000050c: F8D420B4 ldr.w r2, [r4, #0xb4] | |
00000510: 1879 adds r1, r7, r1 | |
00000512: 1E49 subs r1, r1, #1 | |
00000514: FBB1F1F7 udiv r1, r1, r7 | |
00000518: 0209 lsls r1, r1, #8 | |
0000051a: F5A17180 sub.w r1, r1, #0x100 | |
0000051e: 4311 orrs r1, r2 | |
2329 HWREG(SYSCTL_PLLFREQ0) = | |
00000520: F85C2000 ldr.w r2, [r12, r0] | |
2328 HWREG(SYSCTL_PLLFREQ1) |= PLL_Q_TO_REG(ui32SysDiv); | |
00000524: F8C410B4 str.w r1, [r4, #0xb4] | |
2329 HWREG(SYSCTL_PLLFREQ0) = | |
00000528: F8D410B0 ldr.w r1, [r4, #0xb0] | |
0000052c: F4010000 and r0, r1, #0x800000 | |
00000530: 4310 orrs r0, r2 | |
00000532: F8C400B0 str.w r0, [r4, #0xb0] | |
2336 ui32SysClock = _SysCtlFrequencyGet(ui32Osc) / 2; | |
00000536: 4648 mov r0, r9 | |
00000538: F000FAD2 bl #0xae0 | |
0000053c: 0847 lsrs r7, r0, #1 | |
2341 HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(ui32SysClock); | |
0000053e: 4638 mov r0, r7 | |
00000540: F000FB52 bl #0xbe8 | |
00000544: 6120 str r0, [r4, #0x10] | |
2346 if(HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR) | |
00000546: F8D400B0 ldr.w r0, [r4, #0xb0] | |
00000547: B0F8 .word 0x0000b0f8 | |
00000549: 0000 .word 0x00000000 | |
0000054b: 060E .word 0x0000060e | |
......... D4D2 .word 0x0000d4d2 | |
2358 HWREG(SYSCTL_PLLFREQ0) |= SYSCTL_PLLFREQ0_PLLPWR; | |
0000054e: F8D400B0 ldr.w r0, [r4, #0xb0] | |
0000054f: B0F8 .word 0x0000b0f8 | |
00000551: 4000 .word 0x00004000 | |
00000553: 00F4 .word 0x000000f4 | |
00000555: C400 .word 0x0000c400 | |
00000557: B0F8 .word 0x0000b0f8 | |
00000559: 0300 .word 0x00000300 | |
......... 20E0 .word 0x000020e0 | |
2351 HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_NEWFREQ; | |
$C$L56: | |
0000055c: 6820 ldr r0, [r4] | |
0000055d: 4068 .word 0x00004068 | |
0000055f: 80F0 .word 0x000080f0 | |
00000561: 2040 .word 0x00002040 | |
00000563: 4F60 .word 0x00004f60 | |
2364 for(i32Timeout = 32768; i32Timeout > 0; i32Timeout--) | |
00000565: 00F4 .word 0x000000f4 | |
00000567: 0841 .word 0x00000841 | |
00000569: D446 .word 0x0000d446 | |
2368 break; | |
0000056b: B8F8 .word 0x0000b8f8 | |
0000056d: 5220 .word 0x00005220 | |
0000056f: 0308 .word 0x00000308 | |
00000571: 49D2 .word 0x000049d2 | |
2364 for(i32Timeout = 32768; i32Timeout > 0; i32Timeout--) | |
00000573: A01E .word 0x0000a01e | |
00000575: 01F1 .word 0x000001f1 | |
00000577: F70000D1 .word 0x00d1f700 | |
2375 if(i32Timeout) | |
0000057b: 0828 .word 0x00000828 | |
0000057d: 00BF .word 0x000000bf | |
2389 ui32SysClock = 0; | |
0000057f: 2927 .word 0x00002927 | |
00000581: 21D0 .word 0x000021d0 | |
2377 ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); | |
00000583: 1F68 .word 0x00001f68 | |
2378 ui32RSClkConfig |= (1 << SYSCTL_RSCLKCFG_PSYSDIV_S) | | |
00000585: 0E48 .word 0x00000e48 | |
00000587: 0643 .word 0x00000643 | |
00000589: 2343 .word 0x00002343 | |
2386 } | |
0000058b: 00E0 .word 0x000000e0 | |
2397 HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(16000000); | |
0000058d: 2CF0 .word 0x00002cf0 | |
0000058f: 20FB .word 0x000020fb | |
00000591: 1D61 .word 0x00001d61 | |
2408 ui32RSClkConfig &= ~(SYSCTL_RSCLKCFG_OSYSDIV_M | | |
00000593: D44D .word 0x0000d44d | |
2402 HWREG(SYSCTL_PLLFREQ0) &= ~SYSCTL_PLLFREQ0_PLLPWR; | |
00000595: B0F8 .word 0x0000b0f8 | |
00000597: 2000 .word 0x00002000 | |
00000599: 00F4 .word 0x000000f4 | |
0000059b: C400 .word 0x0000c400 | |
0000059d: B0F8 .word 0x0000b0f8 | |
0000059f: 2100 .word 0x00002100 | |
2407 ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); | |
000005a1: 0568 .word 0x00000568 | |
2408 ui32RSClkConfig &= ~(SYSCTL_RSCLKCFG_OSYSDIV_M | | |
000005a3: 01EA .word 0x000001ea | |
000005a5: 4000 .word 0x00004000 | |
000005a7: 00F0 .word 0x000000f0 | |
000005a9: 2040 .word 0x00002040 | |
2420 HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; | |
000005ab: 3F60 .word 0x00003f60 | |
......... B9B1 .word 0x0000b9b1 | |
2435 ui32SysDiv = ui32Osc / ui32SysClock; | |
000005ae: FBB9F5F7 udiv r5, r9, r7 | |
......... ... | |
000005b2: B105 cbz r5, #0x5b6 | |
2444 ui32SysDiv -= 1; | |
000005b4: 1E6D subs r5, r5, #1 | |
2450 ui32SysClock = ui32Osc / (ui32SysDiv + 1); | |
$C$L61: | |
000005b6: 1C68 adds r0, r5, #1 | |
000005b8: FBB9F7F0 udiv r7, r9, r0 | |
000005bc: E000 b $C$L63 | |
2427 ui32SysDiv = 0; | |
$C$L62: | |
000005be: 2500 movs r5, #0 | |
2456 HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(ui32SysClock); | |
$C$L63: | |
000005c0: 4638 mov r0, r7 | |
000005c2: F000FB11 bl #0xbe8 | |
000005c6: 6120 str r0, [r4, #0x10] | |
2461 ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); | |
000005c8: 6820 ldr r0, [r4] | |
2462 ui32RSClkConfig |= (ui32SysDiv << SYSCTL_RSCLKCFG_OSYSDIV_S) | | |
000005ca: EA402085 orr.w r0, r0, r5, lsl #10 | |
000005ce: 4306 orrs r6, r0 | |
000005d0: F0464600 orr r6, r6, #0x80000000 | |
2473 HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; | |
$C$L64: | |
000005d4: 6026 str r6, [r4] | |
2479 HWREG(SYSCTL_RSCLKCFG) &= ~(SYSCTL_RSCLKCFG_OSCSRC_M); | |
$C$L65: | |
000005d6: 6821 ldr r1, [r4] | |
2481 return(ui32SysClock); | |
000005d8: 4638 mov r0, r7 | |
2479 HWREG(SYSCTL_RSCLKCFG) &= ~(SYSCTL_RSCLKCFG_OSCSRC_M); | |
000005da: F4210170 bic r1, r1, #0xf00000 | |
000005de: 6021 str r1, [r4] | |
000005e0: E8BD83F8 pop.w {r3, r4, r5, r6, r7, r8, r9, pc} | |
$C$CON109: | |
000005e4: 0000 movs r0, r0 | |
000005e6: 70FF strb r7, [r7, #3] | |
$C$CON111: | |
000005e8: 0000 movs r0, r0 | |
000005ea: 1005 asrs r5, r0, #0x20 | |
$C$CON112: | |
000005ec: 0F08 lsrs r0, r1, #0x1c | |
000005ee: 0000 movs r0, r0 | |
$C$CON113: | |
000005f0: 2400 movs r4, #0 | |
000005f2: 00F4 lsls r4, r6, #3 | |
$C$CON114: | |
000005f4: 7840 ldrb r0, [r0, #1] | |
000005f6: 017D lsls r5, r7, #5 | |
$C$CON115: | |
000005f8: FC00E00F .word 0xe00ffc00 | |
$C$CON116: | |
000005fc: 0CE8 lsrs r0, r5, #0x13 | |
000005fe: 0000 movs r0, r0 | |
$C$CON117: | |
00000600: 0FA4 lsrs r4, r4, #0x1e | |
00000602: 0000 movs r0, r0 | |
$C$CON118: | |
00000604: 0001 movs r1, r0 | |
00000606: 9000 str r0, [sp] | |
$C$CON119: | |
00000608: 03FF lsls r7, r7, #0xf | |
0000060a: 6F00 ldr r0, [r0, #0x70] | |
$C$CON120: | |
0000060c: E160 b #0x8d0 | |
0000060e: 400F ands r7, r1 | |
554 { | |
GPIOPadConfigSet(): | |
00000610: B5F8 push {r3, r4, r5, r6, r7, lr} | |
00000612: 4684 mov r12, r0 | |
00000614: 461F mov r7, r3 | |
00000616: 2000 movs r0, #0 | |
585 if(ui8Pins & (1 << ui8Bit)) | |
00000618: F04F0E01 mov.w lr, #1 | |
587 HWREG(ui32Port + GPIO_O_PC) = (HWREG(ui32Port + GPIO_O_PC) & | |
0000061c: 2503 movs r5, #3 | |
585 if(ui8Pins & (1 << ui8Bit)) | |
$C$L1: | |
0000061e: FA0EF300 lsl.w r3, lr, r0 | |
585 if(ui8Pins & (1 << ui8Bit)) | |
00000621: 19F3 .word 0x000019f3 | |
00000623: 0F42 .word 0x00000f42 | |
00000625: DCD0 .word 0x0000dcd0 | |
587 HWREG(ui32Port + GPIO_O_PC) = (HWREG(ui32Port + GPIO_O_PC) & | |
00000626: F8DC3FC4 ldr.w r3, [r12, #0xfc4] | |
587 HWREG(ui32Port + GPIO_O_PC) = (HWREG(ui32Port + GPIO_O_PC) & | |
00000627: C4F8 .word 0x0000c4f8 | |
00000629: 463F .word 0x0000463f | |
0000062b: 0500 .word 0x00000500 | |
0000062d: 06FA .word 0x000006fa | |
0000062f: A3F4 .word 0x0000a3f4 | |
00000631: CC43 .word 0x0000cc43 | |
00000633: C4F8 .word 0x0000c4f8 | |
00000635: DC3F .word 0x0000dc3f | |
589 HWREG(ui32Port + GPIO_O_PC) |= (((ui32Strength >> 5) & 0x3) << | |
00000636: F8DC4FC4 ldr.w r4, [r12, #0xfc4] | |
00000637: C4F8 .word 0x0000c4f8 | |
00000639: C24F .word 0x0000c24f | |
0000063b: 41F3 .word 0x000041f3 | |
0000063d: B313 .word 0x0000b313 | |
0000063f: 2340 .word 0x00002340 | |
00000641: CC43 .word 0x0000cc43 | |
00000643: C4F8 .word 0x0000c4f8 | |
00000645: 403F .word 0x0000403f | |
583 for(ui8Bit = 0; ui8Bit < 8; ui8Bit++) | |
00000647: 081C .word 0x0000081c | |
00000649: E82850DB .word 0x50dbe828 | |
597 HWREG(ui32Port + GPIO_O_DR2R) = ((ui32Strength & 1) ? | |
0000064d: 2708 .word 0x00002708 | |
0000064f: DCBF .word 0x0000dcbf | |
00000651: 00F8 .word 0x000000f8 | |
00000653: 0805 .word 0x00000805 | |
00000655: DC43 .word 0x0000dc43 | |
00000657: 00F8 .word 0x000000f8 | |
00000659: 8805 .word 0x00008805 | |
0000065b: CC43 .word 0x0000cc43 | |
0000065d: 00F8 .word 0x000000f8 | |
0000065f: 9005 .word 0x00009005 | |
602 HWREG(ui32Port + GPIO_O_DR4R) = ((ui32Strength & 2) ? | |
00000661: 2708 .word 0x00002708 | |
00000663: DCBF .word 0x0000dcbf | |
00000665: 04F8 .word 0x000004f8 | |
00000667: 0805 .word 0x00000805 | |
00000669: DC43 .word 0x0000dc43 | |
0000066b: 04F8 .word 0x000004f8 | |
0000066d: 8805 .word 0x00008805 | |
0000066f: CC43 .word 0x0000cc43 | |
00000671: 04F8 .word 0x000004f8 | |
00000673: D005 .word 0x0000d005 | |
607 HWREG(ui32Port + GPIO_O_DR8R) = ((ui32Strength & 4) ? | |
00000675: 2708 .word 0x00002708 | |
00000677: DCBF .word 0x0000dcbf | |
00000679: 08F8 .word 0x000008f8 | |
0000067b: 0805 .word 0x00000805 | |
0000067d: DC43 .word 0x0000dc43 | |
0000067f: 08F8 .word 0x000008f8 | |
00000681: 8805 .word 0x00008805 | |
00000683: CC43 .word 0x0000cc43 | |
00000685: 08F8 .word 0x000008f8 | |
00000687: 1005 .word 0x00001005 | |
612 HWREG(ui32Port + GPIO_O_SLR) = ((ui32Strength & 8) ? | |
00000689: 2709 .word 0x00002709 | |
0000068b: DCBF .word 0x0000dcbf | |
0000068d: 18F8 .word 0x000018f8 | |
0000068f: 0805 .word 0x00000805 | |
00000691: DC43 .word 0x0000dc43 | |
00000693: 18F8 .word 0x000018f8 | |
00000695: 8805 .word 0x00008805 | |
00000697: CC43 .word 0x0000cc43 | |
00000699: 18F8 .word 0x000018f8 | |
0000069b: 5005 .word 0x00005005 | |
623 HWREG(ui32Port + GPIO_O_DR12R) = ((ui32Strength & 0x10) ? | |
......... 0950 lsrs r0, r2, #5 | |
0000069d: 2709 .word 0x00002709 | |
0000069f: DCBF .word 0x0000dcbf | |
000006a1: 3CF8 .word 0x00003cf8 | |
000006a3: 0805 .word 0x00000805 | |
000006a5: DC43 .word 0x0000dc43 | |
000006a7: 3CF8 .word 0x00003cf8 | |
000006a9: 8805 .word 0x00008805 | |
000006ab: CC43 .word 0x0000cc43 | |
000006ad: 3CF8 .word 0x00003cf8 | |
......... ... | |
632 HWREG(ui32Port + GPIO_O_ODR) = ((ui32PinType & 1) ? | |
000006b0: 0878 lsrs r0, r7, #1 | |
000006b2: BF27 ittee hs | |
000006b4: F8DC050C ldr.w r0, [r12, #0x50c] | |
000006b8: 4308 orrs r0, r1 | |
000006ba: F8DC050C ldr.w r0, [r12, #0x50c] | |
000006be: 4388 bics r0, r1 | |
000006c0: F8CC050C str.w r0, [r12, #0x50c] | |
635 HWREG(ui32Port + GPIO_O_PUR) = ((ui32PinType & 2) ? | |
000006c4: 08B8 lsrs r0, r7, #2 | |
000006c6: BF27 ittee hs | |
000006c8: F8DC0510 ldr.w r0, [r12, #0x510] | |
000006cc: 4308 orrs r0, r1 | |
000006ce: F8DC0510 ldr.w r0, [r12, #0x510] | |
000006d2: 4388 bics r0, r1 | |
000006d4: F8CC0510 str.w r0, [r12, #0x510] | |
638 HWREG(ui32Port + GPIO_O_PDR) = ((ui32PinType & 4) ? | |
000006d8: 08F8 lsrs r0, r7, #3 | |
000006da: BF27 ittee hs | |
000006dc: F8DC0514 ldr.w r0, [r12, #0x514] | |
000006e0: 4308 orrs r0, r1 | |
000006e2: F8DC0514 ldr.w r0, [r12, #0x514] | |
000006e6: 4388 bics r0, r1 | |
000006e8: F8CC0514 str.w r0, [r12, #0x514] | |
641 HWREG(ui32Port + GPIO_O_DEN) = ((ui32PinType & 8) ? | |
000006ec: 0938 lsrs r0, r7, #4 | |
000006ee: BF27 ittee hs | |
000006f0: F8DC051C ldr.w r0, [r12, #0x51c] | |
000006f4: 4308 orrs r0, r1 | |
000006f6: F8DC051C ldr.w r0, [r12, #0x51c] | |
000006fa: 4388 bics r0, r1 | |
000006fc: F8CC051C str.w r0, [r12, #0x51c] | |
650 HWREG(ui32Port + GPIO_O_WAKELVL) = ((ui32PinType & 0x200) ? | |
00000700: 0AB8 lsrs r0, r7, #0xa | |
00000702: BF27 ittee hs | |
00000704: F8DC0544 ldr.w r0, [r12, #0x544] | |
00000708: 4308 orrs r0, r1 | |
0000070a: F8DC0544 ldr.w r0, [r12, #0x544] | |
0000070e: 4388 bics r0, r1 | |
655 HWREG(ui32Port + GPIO_O_WAKEPEN) = ((ui32PinType & 0x300) ? | |
00000710: F4177F40 tst.w r7, #0x300 | |
650 HWREG(ui32Port + GPIO_O_WAKELVL) = ((ui32PinType & 0x200) ? | |
00000714: F8CC0544 str.w r0, [r12, #0x544] | |
00000718: BF19 ittee ne | |
655 HWREG(ui32Port + GPIO_O_WAKEPEN) = ((ui32PinType & 0x300) ? | |
0000071a: F8DC0540 ldr.w r0, [r12, #0x540] | |
0000071e: 4308 orrs r0, r1 | |
00000720: F8DC0540 ldr.w r0, [r12, #0x540] | |
00000724: 4388 bics r0, r1 | |
664 HWREG(ui32Port + GPIO_O_AMSEL) = | |
00000726: 2F00 cmp r7, #0 | |
655 HWREG(ui32Port + GPIO_O_WAKEPEN) = ((ui32PinType & 0x300) ? | |
00000728: F8CC0540 str.w r0, [r12, #0x540] | |
0000072c: BF19 ittee ne | |
664 HWREG(ui32Port + GPIO_O_AMSEL) = | |
0000072e: F8DC0528 ldr.w r0, [r12, #0x528] | |
00000732: EA200101 bic.w r1, r0, r1 | |
00000736: F8DC0528 ldr.w r0, [r12, #0x528] | |
0000073a: 4301 orrs r1, r0 | |
0000073c: F8CC1528 str.w r1, [r12, #0x528] | |
00000740: BDF8 pop {r3, r4, r5, r6, r7, pc} | |
69 CMP r2, #0 ; CHECK FOR n == 0 | |
__aeabi_memcpy(), __aeabi_memcpy4(), __aeabi_memcpy8(), memcpy(): | |
00000742: 2A00 cmp r2, #0 | |
70 BEQ _ret2_ ; | |
00000744: D04A beq _ret2_ | |
72 MOVS r12, r0 ; SAVE RETURN VALUE | |
00000746: EA5F0C00 movs.w r12, r0 | |
74 LSLS r3, r1, #30 ; CHECK ADDRESS ALIGNMENT | |
0000074a: 078B lsls r3, r1, #0x1e | |
75 BNE _unaln ; IF NOT WORD ALIGNED, HANDLE SPECIALLY | |
0000074c: D11C bne _unaln | |
76 LSLS r3, r0, #30 ; | |
0000074e: 0783 lsls r3, r0, #0x1e | |
77 BNE _saln ; | |
00000750: D122 bne _saln | |
79 _aln: CMP r2, #16 ; ADDRESSES AND LENGTH ARE WORD ALIGNED | |
_aln: | |
00000752: 2A10 cmp r2, #0x10 | |
80 BCC _udr16 ; IF n < 16, SKIP 16 BYTE COPY CODE | |
00000754: D308 blo _udr16 | |
82 _ovr16: PUSH {r4 - r6} ; COPYING 16 BYTES OR MORE. | |
_ovr16: | |
00000756: B470 push {r4, r5, r6} | |
83 SUBS r2, #16 ; | |
00000758: 3A10 subs r2, #0x10 | |
84 _lp16: LDMIA r1!, {r3 - r6} ; | |
_lp16: | |
0000075a: C978 ldm r1!, {r3, r4, r5, r6} | |
85 STMIA r0!, {r3 - r6} ; | |
0000075c: C078 stm r0!, {r3, r4, r5, r6} | |
86 SUBS r2, #16 ; | |
0000075e: 3A10 subs r2, #0x10 | |
87 BCS _lp16 ; | |
00000760: D2FB bhs _lp16 | |
88 POP {r4 - r6} ; RESTORE THE SAVED REGISTERS AND | |
00000762: BC70 pop {r4, r5, r6} | |
89 ADDS r2, #16 ; CONTINUE THE COPY IF THE REMAINDER | |
00000764: 3210 adds r2, #0x10 | |
90 BEQ _ret_ ; IS NONZERO. | |
00000766: D038 beq _ret_ | |
92 _udr16: CMP r2, #4 ; IF UNDER 16, THEN COMPUTE | |
_udr16: | |
00000768: 2A04 cmp r2, #4 | |
93 BCC _off1 ; THE COPY CODE TO EXECUTE, AND | |
0000076a: D32C blo _off1 | |
94 CMP r2, #8 ; GO THERE | |
0000076c: 2A08 cmp r2, #8 | |
95 BCC _c4 ; | |
0000076e: D305 blo _c4 | |
96 CMP r2, #12 ; | |
00000770: 2A0C cmp r2, #0xc | |
97 ITT CS | |
00000772: BF24 itt hs | |
98 _c12: LDMIACS r1!, {r3} ; COPY 12 BYTES | |
_c12: | |
00000774: C908 ldm r1!, {r3} | |
99 STMIACS r0!, {r3} ; | |
00000776: C008 stm r0!, {r3} | |
100 _c8: LDMIA r1!, {r3} ; COPY 8 BYTES | |
_c8: | |
00000778: C908 ldm r1!, {r3} | |
101 STMIA r0!, {r3} ; | |
0000077a: C008 stm r0!, {r3} | |
102 _c4: LDMIA r1!, {r3} ; COPY 4 BYTES | |
_c4: | |
0000077c: C908 ldm r1!, {r3} | |
103 STMIA r0!, {r3} ; | |
0000077e: C008 stm r0!, {r3} | |
105 _oddsz: LSLS r2, r2, #30 ; HANDLE THE TRAILING BYTES | |
_oddsz: | |
00000780: 0792 lsls r2, r2, #0x1e | |
106 BEQ _ret_ ; | |
00000782: D02A beq _ret_ | |
107 LSRS r2, r2, #30 ; | |
00000784: 0F92 lsrs r2, r2, #0x1e | |
108 B _lp1 ; | |
00000786: E022 b _lp1 | |
110 _unaln: LDRB r3, [r1] ; THE ADDRESSES ARE NOT WORD ALIGNED. | |
_unaln: | |
00000788: 780B ldrb r3, [r1] | |
111 STRB r3, [r0] ; COPY BYTES UNTIL THE SOURCE IS | |
0000078a: 7003 strb r3, [r0] | |
112 ADDS r1, r1, #1 ; | |
0000078c: 1C49 adds r1, r1, #1 | |
113 ADDS r0, r0, #1 ; | |
0000078e: 1C40 adds r0, r0, #1 | |
114 SUBS r2, r2, #1 ; WORD ALIGNED OR THE COPY SIZE | |
00000790: 1E52 subs r2, r2, #1 | |
115 BEQ _ret_ ; BECOMES ZERO | |
00000792: D022 beq _ret_ | |
116 LSLS r3, r1, #30 ; | |
00000794: 078B lsls r3, r1, #0x1e | |
117 BNE _unaln ; | |
00000796: D1F7 bne _unaln | |
119 _saln: LSLS r3, r0, #31 ; IF THE ADDRESSES ARE OFF BY 1 BYTE | |
_saln: | |
00000798: 07C3 lsls r3, r0, #0x1f | |
120 BNE _off1 ; JUST BYTE COPY | |
0000079a: D114 bne _off1 | |
122 LSLS r3, r0, #30 ; IF THE ADDRESSES ARE NOW WORD ALIGNED | |
0000079c: 0783 lsls r3, r0, #0x1e | |
123 BEQ _aln ; GO COPY. ELSE THEY ARE OFF BY 2, SO | |
0000079e: D0D8 beq _aln | |
126 _off2: SUBS r2, r2, #4 ; COPY 2 BYTES AT A TIME... | |
_off2: | |
000007a0: 1F12 subs r2, r2, #4 | |
127 BCC _oddb ; | |
000007a2: D312 blo _oddb | |
128 _cp4s: LDMIA r1!, {r3} ; LOAD IN CHUNKS OF 4 | |
_cp4s: | |
000007a4: C908 ldm r1!, {r3} | |
134 STRH r3, [r0] ; | |
000007a6: 8003 strh r3, [r0] | |
135 LSRS r3, r3, #16 ; | |
000007a8: 0C1B lsrs r3, r3, #0x10 | |
136 STRH r3, [r0, #2] ; | |
000007aa: 8043 strh r3, [r0, #2] | |
138 ADDS r0, r0, #4 ; | |
000007ac: 1D00 adds r0, r0, #4 | |
139 SUBS r2, r2, #4 ; | |
000007ae: 1F12 subs r2, r2, #4 | |
140 BCS _cp4s ; | |
000007b0: D2F8 bhs _cp4s | |
141 B _oddb ; | |
000007b2: E00A b _oddb | |
143 _cp4: LDMIA r1!, {r3} ; COPY 1 BYTE AT A TIME, IN CHUNKS OF 4 | |
_cp4: | |
000007b4: C908 ldm r1!, {r3} | |
153 STRB r3, [r0] ; | |
000007b6: 7003 strb r3, [r0] | |
154 LSRS r3, r3, #8 ; | |
000007b8: 0A1B lsrs r3, r3, #8 | |
155 STRB r3, [r0, #1] ; | |
000007ba: 7043 strb r3, [r0, #1] | |
156 LSRS r3, r3, #8 ; | |
000007bc: 0A1B lsrs r3, r3, #8 | |
157 STRB r3, [r0, #2] ; | |
000007be: 7083 strb r3, [r0, #2] | |
158 LSRS r3, r3, #8 ; | |
000007c0: 0A1B lsrs r3, r3, #8 | |
159 STRB r3, [r0, #3] ; | |
000007c2: 70C3 strb r3, [r0, #3] | |
161 ADDS r0, r0, #4 ; | |
000007c4: 1D00 adds r0, r0, #4 | |
162 _off1: SUBS r2, r2, #4 ; | |
_off1: | |
000007c6: 1F12 subs r2, r2, #4 | |
163 BCS _cp4 ; | |
000007c8: D2F4 bhs _cp4 | |
165 _oddb: ADDS r2, r2, #4 ; THEN COPY THE ODD BYTES. | |
_oddb: | |
000007ca: 1D12 adds r2, r2, #4 | |
166 BEQ _ret_ ; | |
000007cc: D005 beq _ret_ | |
168 _lp1: LDRB r3, [r1] ; | |
_lp1: | |
000007ce: 780B ldrb r3, [r1] | |
169 STRB r3, [r0] ; | |
000007d0: 7003 strb r3, [r0] | |
170 ADDS r1, r1, #1 ; | |
000007d2: 1C49 adds r1, r1, #1 | |
171 ADDS r0, r0, #1 ; | |
000007d4: 1C40 adds r0, r0, #1 | |
172 SUBS r2, r2, #1 ; | |
000007d6: 1E52 subs r2, r2, #1 | |
173 BNE _lp1 ; | |
000007d8: D1F9 bne _lp1 | |
174 _ret_: MOV r0, r12 ; | |
_ret_: | |
000007da: 4660 mov r0, r12 | |
175 _ret2_: BX lr | |
_ret2_: | |
000007dc: 4770 bx lr | |
254 while(1) | |
$C$L2, FaultISR(): | |
000007de: E7FE b FaultISR | |
51 { | |
__TI_auto_init(): | |
000007e0: 4814 ldr r0, [pc, #0x50] | |
000007e2: B5B0 push {r4, r5, r7, lr} | |
000007e4: F1B03FFF cmp.w r0, #-1 | |
000007e8: D001 beq $C$L1 | |
118 copy_in((COPY_TABLE *)__binit__); | |
000007ea: F000F953 bl #0xa94 | |
140 if (__TI_Handler_Table_Base != __TI_Handler_Table_Limit) | |
$C$L1: | |
000007ee: 4D12 ldr r5, [pc, #0x48] | |
000007f0: 4812 ldr r0, [pc, #0x48] | |
000007f2: 42A8 cmp r0, r5 | |
000007f4: D010 beq $C$L3 | |
145 while (table_ptr != table_limit) | |
000007f6: 4812 ldr r0, [pc, #0x48] | |
000007f8: 4C12 ldr r4, [pc, #0x48] | |
000007fa: 42A0 cmp r0, r4 | |
000007fc: D00C beq $C$L3 | |
147 char const *load_addr = *table_ptr++; | |
000007fe: 1B00 subs r0, r0, r4 | |
00000800: 3C08 subs r4, #8 | |
00000802: 10C7 asrs r7, r0, #3 | |
149 char handler_idx = *load_addr++; | |
$C$L2: | |
00000804: F8540F08 ldr r0, [r4, #8]! | |
00000808: 7801 ldrb r1, [r0] | |
0000080a: F8552021 ldr.w r2, [r5, r1, lsl #2] | |
0000080e: 6861 ldr r1, [r4, #4] | |
00000810: 1C40 adds r0, r0, #1 | |
00000812: 4790 blx r2 | |
00000814: 1E7F subs r7, r7, #1 | |
00000816: D1F5 bne $C$L2 | |
58 _system_post_cinit(); | |
$C$L3: | |
00000818: F000FA64 bl #0xce4 | |
197 if (PINIT_BASE != PINIT_LIMIT) | |
0000081c: 4D0A ldr r5, [pc, #0x28] | |
0000081e: 4C0B ldr r4, [pc, #0x2c] | |
00000820: 42A5 cmp r5, r4 | |
00000822: D005 beq $C$L6 | |
200 while (&(PINIT_BASE[i]) != PINIT_LIMIT) | |
00000824: E002 b $C$L5 | |
201 PINIT_BASE[i++](); | |
$C$L4: | |
00000826: F8540B04 ldr r0, [r4], #4 | |
0000082a: 4780 blx r0 | |
$C$L5: | |
0000082c: 42A5 cmp r5, r4 | |
0000082e: D1FA bne $C$L4 | |
$C$L6: | |
00000830: BDB0 pop {r4, r5, r7, pc} | |
00000832: 46C0 mov r8, r8 | |
$C$CON1: | |
00000834: FFFFFFFF .word 0xffffffff | |
$C$CON2: | |
00000838: 0FC8 lsrs r0, r1, #0x1f | |
0000083a: 0000 movs r0, r0 | |
$C$CON3: | |
0000083c: 0FD0 lsrs r0, r2, #0x1f | |
0000083e: 0000 movs r0, r0 | |
$C$CON4: | |
00000840: 0FD8 lsrs r0, r3, #0x1f | |
00000842: 0000 movs r0, r0 | |
$C$CON5: | |
00000844: 0FD0 lsrs r0, r2, #0x1f | |
00000846: 0000 movs r0, r0 | |
$C$CON6: | |
00000848: 0000 movs r0, r0 | |
0000084a: 0000 movs r0, r0 | |
$C$CON7: | |
0000084c: 0000 movs r0, r0 | |
0000084e: 0000 movs r0, r0 | |
57 MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | | |
main(): | |
00000850: 4919 ldr r1, [pc, #0x64] | |
00000852: 4815 ldr r0, [pc, #0x54] | |
00000854: B510 push {r4, lr} | |
00000856: 0089 lsls r1, r1, #2 | |
00000858: F7FFFDDA bl #0x410 | |
62 PinoutSet(false,false); // Library function that sets up UART and USB IO. | |
0000085c: 2000 movs r0, #0 | |
0000085e: 4601 mov r1, r0 | |
00000860: F7FFFCD2 bl #0x208 | |
64 InitTimers(); | |
00000864: F000F994 bl #0xb90 | |
65 InitIO(); | |
00000868: F000F95E bl #0xb28 | |
68 IntEnable(INT_TIMER2A); | |
0000086c: 2027 movs r0, #0x27 | |
0000086e: F000F825 bl #0x8bc | |
72 TimerEnable(TIMER2_BASE,TIMER_A); | |
00000872: 4C0E ldr r4, [pc, #0x38] | |
69 TimerIntEnable(TIMER2_BASE,TIMER_TIMA_TIMEOUT); | |
00000874: 2101 movs r1, #1 | |
00000876: 4620 mov r0, r4 | |
00000878: F000FA24 bl #0xcc4 | |
71 IntMasterEnable(); | |
0000087c: F000FA06 bl #0xc8c | |
72 TimerEnable(TIMER2_BASE,TIMER_A); | |
00000880: 21FF movs r1, #0xff | |
00000882: 4620 mov r0, r4 | |
00000884: F000FA0A bl #0xc9c | |
75 if (digit_blink) | |
00000888: 4C0A ldr r4, [pc, #0x28] | |
0000088a: E003 b $C$L2 | |
78 GPIOPinWrite(GPIO_PORTL_BASE, LED_2,0x0); // Write to LCD would be here | |
$C$L1: | |
0000088c: 2102 movs r1, #2 | |
0000088e: 2200 movs r2, #0 | |
00000890: F000FA1C bl #0xccc | |
75 if (digit_blink) | |
$C$L2: | |
00000894: 7821 ldrb r1, [r4] | |
76 GPIOPinWrite(GPIO_PORTL_BASE, LED_2,LED_2); // Write to LCD would be here | |
00000896: 4806 ldr r0, [pc, #0x18] | |
75 if (digit_blink) | |
00000898: 2900 cmp r1, #0 | |
0000089a: D0F7 beq $C$L1 | |
76 GPIOPinWrite(GPIO_PORTL_BASE, LED_2,LED_2); // Write to LCD would be here | |
0000089c: 2102 movs r1, #2 | |
0000089e: 460A mov r2, r1 | |
000008a0: F000FA14 bl #0xccc | |
000008a4: E7F6 b $C$L2 | |
000008a6: 46C0 mov r8, r8 | |
$C$CON7: | |
000008a8: 0680 lsls r0, r0, #0x1a | |
000008aa: F1002000 add.w r0, r0, #0 | |
000008ae: 4003 ands r3, r0 | |
$C$CON10: | |
000008b0: 2000 movs r0, #0 | |
000008b2: 4006 ands r6, r0 | |
$C$CON11: | |
000008b4: 0814 lsrs r4, r2, #0x20 | |
000008b6: 2000 movs r0, #0 | |
$C$CON12: | |
000008b8: C380 stm r3!, {r7} | |
000008ba: 01C9 lsls r1, r1, #7 | |
625 HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; | |
IntEnable(): | |
000008bc: 4917 ldr r1, [pc, #0x5c] | |
620 if(ui32Interrupt == FAULT_MPU) | |
000008be: 2804 cmp r0, #4 | |
000008c0: D024 beq $C$L29 | |
627 else if(ui32Interrupt == FAULT_BUS) | |
000008c2: 2805 cmp r0, #5 | |
000008c4: D01D beq $C$L28 | |
634 else if(ui32Interrupt == FAULT_USAGE) | |
000008c6: 2806 cmp r0, #6 | |
000008c8: D016 beq $C$L27 | |
641 else if(ui32Interrupt == FAULT_SYSTICK) | |
000008ca: 280F cmp r0, #0xf | |
000008cc: D00D beq $C$L26 | |
648 else if(ui32Interrupt >= 16) | |
000008ce: 280F cmp r0, #0xf | |
000008d0: D921 bls $C$L31 | |
653 HWREG(g_pui32EnRegs[(ui32Interrupt - 16) / 32]) = | |
000008d2: 4913 ldr r1, [pc, #0x4c] | |
000008d4: 3810 subs r0, #0x10 | |
000008d6: 0942 lsrs r2, r0, #5 | |
000008d8: F8512022 ldr.w r2, [r1, r2, lsl #2] | |
000008dc: 2301 movs r3, #1 | |
000008de: F000001F and r0, r0, #0x1f | |
000008e2: FA03F100 lsl.w r1, r3, r0 | |
$C$L25: | |
000008e6: 4610 mov r0, r2 | |
000008e8: E014 b $C$L30 | |
646 HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; | |
$C$L26: | |
000008ea: 490B ldr r1, [pc, #0x2c] | |
000008ec: 6808 ldr r0, [r1] | |
000008ee: 460A mov r2, r1 | |
000008f0: F0400002 orr r0, r0, #2 | |
000008f4: 4601 mov r1, r0 | |
647 } | |
000008f6: E7F6 b $C$L25 | |
639 HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; | |
$C$L27: | |
000008f8: 4608 mov r0, r1 | |
000008fa: 6801 ldr r1, [r0] | |
000008fc: F4412180 orr r1, r1, #0x40000 | |
640 } | |
00000900: E008 b $C$L30 | |
632 HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; | |
$C$L28: | |
00000902: 4608 mov r0, r1 | |
00000904: 6801 ldr r1, [r0] | |
00000906: F4413100 orr r1, r1, #0x20000 | |
633 } | |
0000090a: E003 b $C$L30 | |
625 HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; | |
$C$L29: | |
0000090c: 4608 mov r0, r1 | |
0000090e: 6801 ldr r1, [r0] | |
00000910: F4413180 orr r1, r1, #0x10000 | |
$C$L30: | |
00000914: 6001 str r1, [r0] | |
$C$L31: | |
00000916: 4770 bx lr | |
$C$CON25: | |
00000918: E010 b #0x93c | |
0000091a: E000 b #0x91e | |
$C$CON26: | |
0000091c: ED24E000 stc p0, c14, [r4, #-0]! | |
$C$CON27: | |
00000920: 0EB8 lsrs r0, r7, #0x1a | |
00000922: 0000 movs r0, r0 | |
118 { | |
__TI_decompress_lzss(): | |
00000924: B5F8 push {r3, r4, r5, r6, r7, lr} | |
00000926: 4684 mov r12, r0 | |
183 if (offset == LZSS_EOD) | |
00000928: F64074FF movw r4, #0xfff | |
121 flags_t flags = READ_CHAR_ADV(inbuf); | |
$C$L1: | |
0000092c: F81C3B01 ldrb r3, [r12], #1 | |
124 for (i=0; i<CHAR_BIT ; i++) | |
00000930: 2200 movs r2, #0 | |
00000932: E010 b $C$L6 | |
190 pointer_t pos = outbuf - offset - 1; | |
$C$L2: | |
00000934: 1B48 subs r0, r1, r5 | |
00000936: 1E40 subs r0, r0, #1 | |
192 WRITE_CHAR_ADV(outbuf, READ_CHAR_ADV(pos)); | |
$C$L3: | |
00000938: F8105B01 ldrb r5, [r0], #1 | |
191 for (j = 0; j < length; j++) | |
0000093c: 1E7F subs r7, r7, #1 | |
192 WRITE_CHAR_ADV(outbuf, READ_CHAR_ADV(pos)); | |
0000093e: F8015B01 strb r5, [r1], #1 | |
191 for (j = 0; j < length; j++) | |
00000942: D1F9 bne $C$L3 | |
00000944: E003 b $C$L5 | |
131 WRITE_CHAR_ADV(outbuf, READ_CHAR_ADV(inbuf)); | |
$C$L4: | |
00000946: F81C0B01 ldrb r0, [r12], #1 | |
0000094a: F8010B01 strb r0, [r1], #1 | |
124 for (i=0; i<CHAR_BIT ; i++) | |
$C$L5: | |
0000094e: 1C52 adds r2, r2, #1 | |
195 flags >>= 1; | |
00000950: 085B lsrs r3, r3, #1 | |
124 for (i=0; i<CHAR_BIT ; i++) | |
00000952: 2A08 cmp r2, #8 | |
00000954: DAEA bge $C$L1 | |
126 if (flags & 0x1) | |
$C$L6: | |
00000956: 0858 lsrs r0, r3, #1 | |
00000958: D2F5 bhs $C$L4 | |
142 offset = READ_CHAR_ADV(inbuf); | |
0000095a: F81C0B01 ldrb r0, [r12], #1 | |
143 length = READ_CHAR_ADV(inbuf); | |
0000095e: F81C5B01 ldrb r5, [r12], #1 | |
146 length = (length & 0x000F) + 3; | |
00000962: F005070F and r7, r5, #0xf | |
00000966: 1CFF adds r7, r7, #3 | |
144 offset <<= 4; | |
00000968: F3C51503 ubfx r5, r5, #4, #4 | |
146 length = (length & 0x000F) + 3; | |
0000096c: 2F12 cmp r7, #0x12 | |
144 offset <<= 4; | |
0000096e: EA451500 orr.w r5, r5, r0, lsl #4 | |
146 length = (length & 0x000F) + 3; | |
00000972: D108 bne $C$L7 | |
158 length_t length2 = READ_CHAR_ADV(inbuf); | |
00000974: F81C6B01 ldrb r6, [r12], #1 | |
159 if (length2 & 0x80) | |
00000978: 0A30 lsrs r0, r6, #8 | |
0000097a: BF24 itt hs | |
161 length_t length3 = READ_CHAR_ADV(inbuf); | |
0000097c: F81C0B01 ldrb r0, [r12], #1 | |
162 length2 = (length2 & 0x7f) | (length3 << 7); | |
00000980: F36016DF bfi r6, r0, #7, #0x19 | |
164 length += length2; | |
00000984: 19F7 adds r7, r6, r7 | |
183 if (offset == LZSS_EOD) | |
$C$L7: | |
00000986: 42AC cmp r4, r5 | |
00000988: D1D4 bne $C$L2 | |
0000098a: BDF8 pop {r3, r4, r5, r6, r7, pc} | |
349 { | |
TimerConfigure(): | |
0000098c: B510 push {r4, lr} | |
383 HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); | |
0000098e: 4A13 ldr r2, [pc, #0x4c] | |
00000990: 68C3 ldr r3, [r0, #0xc] | |
395 if(NEW_TIMER_CONFIGURATION) | |
00000992: 4C14 ldr r4, [pc, #0x50] | |
383 HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); | |
00000994: 401A ands r2, r3 | |
388 HWREG(ui32Base + TIMER_O_CFG) = ui32Config >> 24; | |
00000996: 0E0B lsrs r3, r1, #0x18 | |
383 HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); | |
00000998: 60C2 str r2, [r0, #0xc] | |
395 if(NEW_TIMER_CONFIGURATION) | |
0000099a: 4A11 ldr r2, [pc, #0x44] | |
388 HWREG(ui32Base + TIMER_O_CFG) = ui32Config >> 24; | |
0000099c: 6003 str r3, [r0] | |
395 if(NEW_TIMER_CONFIGURATION) | |
0000099e: 4B12 ldr r3, [pc, #0x48] | |
000009a0: 6824 ldr r4, [r4] | |
000009a2: 4022 ands r2, r4 | |
000009a4: 4293 cmp r3, r2 | |
000009a6: D005 beq $C$L12 | |
406 HWREG(ui32Base + TIMER_O_TAMR) = ((ui32Config & 0xff) | | |
000009a8: F00103FF and r3, r1, #0xff | |
408 HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config >> 8) & 0xff) | | |
000009ac: F3C12207 ubfx r2, r1, #8, #8 | |
000009b0: 4619 mov r1, r3 | |
000009b2: E00B b $C$L13 | |
400 HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config & 0x00f00000) >> 8) | | |
$C$L12: | |
000009b4: 0A0A lsrs r2, r1, #8 | |
397 HWREG(ui32Base + TIMER_O_TAMR) = (((ui32Config & 0x000f0000) >> 4) | | |
000009b6: 090B lsrs r3, r1, #4 | |
400 HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config & 0x00f00000) >> 8) | | |
000009b8: F4024470 and r4, r2, #0xf000 | |
397 HWREG(ui32Base + TIMER_O_TAMR) = (((ui32Config & 0x000f0000) >> 4) | | |
000009bc: F00101FF and r1, r1, #0xff | |
000009c0: F4034370 and r3, r3, #0xf000 | |
400 HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config & 0x00f00000) >> 8) | | |
000009c4: F00202FF and r2, r2, #0xff | |
397 HWREG(ui32Base + TIMER_O_TAMR) = (((ui32Config & 0x000f0000) >> 4) | | |
000009c8: 4319 orrs r1, r3 | |
400 HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config & 0x00f00000) >> 8) | | |
000009ca: 4322 orrs r2, r4 | |
397 HWREG(ui32Base + TIMER_O_TAMR) = (((ui32Config & 0x000f0000) >> 4) | | |
$C$L13: | |
000009cc: F4417100 orr r1, r1, #0x200 | |
000009d0: 6041 str r1, [r0, #4] | |
400 HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config & 0x00f00000) >> 8) | | |
000009d2: F4427200 orr r2, r2, #0x200 | |
000009d6: 6082 str r2, [r0, #8] | |
000009d8: BD10 pop {r4, pc} | |
000009da: 46C0 mov r8, r8 | |
$C$CON11: | |
000009dc: FEFEFFFF mrc2 p15, #7, apsr_nzcv, c14, c15, #7 | |
$C$CON12: | |
000009e0: 0000 movs r0, r0 | |
000009e2: 70FF strb r7, [r7, #3] | |
$C$CON13: | |
000009e4: E000 b $C$CON14 | |
000009e6: 400F ands r7, r1 | |
$C$CON14: | |
000009e8: 0000 movs r0, r0 | |
000009ea: 100A asrs r2, r1, #0x20 | |
149 MOVW r1, #cpacr & 0xFFFF | |
_c_int00(): | |
000009ec: F64E5188 movw r1, #0xed88 | |
150 MOVT r1, #cpacr >> 16 | |
000009f0: F2CE0100 movt r1, #0xe000 | |
151 LDR r0, [ r1 ] | |
000009f4: 6808 ldr r0, [r1] | |
152 MOV r3, #0xf0 | |
000009f6: F04F03F0 mov.w r3, #0xf0 | |
153 ORR r0,r0,r3, LSL #16 | |
000009fa: EA404003 orr.w r0, r0, r3, lsl #16 | |
154 STR r0, [ r1 ] | |
000009fe: 6008 str r0, [r1] | |
171 LDR r0, c_stack | |
00000a00: 480C ldr r0, [pc, #0x30] | |
172 MOV sp, r0 | |
00000a02: 4685 mov sp, r0 | |
173 LDR r0, c_STACK_SIZE | |
00000a04: 480C ldr r0, [pc, #0x30] | |
175 ADD sp, r0 | |
00000a06: 4485 add sp, r0 | |
181 MOV r7, sp | |
00000a08: 466F mov r7, sp | |
182 MOVS r0, #0x07 | |
00000a0a: 2007 movs r0, #7 | |
183 BICS r7, r0 ; Clear upper 3 bits for 64-bit alignment. | |
00000a0c: 4387 bics r7, r0 | |
184 MOV sp, r7 | |
00000a0e: 46BD mov sp, r7 | |
196 LDR r0, c_mf_sp | |
00000a10: 480A ldr r0, [pc, #0x28] | |
198 MOV r7, sp | |
00000a12: 466F mov r7, sp | |
199 STR r7, [r0] | |
00000a14: 6007 str r7, [r0] | |
204 BL __mpu_init | |
00000a16: F000F964 bl #0xce2 | |
213 BL PRE_INIT_RTN | |
00000a1a: F000F95F bl #0xcdc | |
214 CMP R0, #0 | |
00000a1e: 2800 cmp r0, #0 | |
215 BEQ bypass_auto_init | |
00000a20: D001 beq bypass_auto_init | |
216 BL AUTO_INIT_RTN | |
00000a22: F7FFFEDD bl #0x7e0 | |
222 BL ARGS_MAIN_RTN | |
bypass_auto_init: | |
00000a26: F000F909 bl #0xc3c | |
227 MOVS r0, #1 | |
00000a2a: 2001 movs r0, #1 | |
228 BL EXIT_RTN | |
00000a2c: F000F80E bl #0xa4c | |
233 L1: B L1 | |
L1: | |
00000a30: E7FE b L1 | |
00000a32: 46C0 mov r8, r8 | |
c_stack: | |
00000a34: 0000 movs r0, r0 | |
00000a36: 2000 movs r0, #0 | |
c_STACK_SIZE: | |
00000a38: 0800 lsrs r0, r0, #0x20 | |
00000a3a: 0000 movs r0, r0 | |
c_mf_sp: | |
00000a3c: 081C lsrs r4, r3, #0x20 | |
00000a3e: 2000 movs r0, #0 | |
55 { | |
C$$EXIT(), loader_exit(): | |
00000a40: BF00 nop | |
00000a42: 4770 bx lr | |
128 { | |
abort(): | |
00000a44: B508 push {r3, lr} | |
129 loader_exit(); | |
00000a46: F7FFFFFB bl #0xa40 | |
130 for (;;); /* SPINS FOREVER */ | |
$C$L1: | |
00000a4a: E7FE b $C$L1 | |
79 { | |
exit(): | |
00000a4c: B538 push {r3, r4, r5, lr} | |
83 if (__TI_enable_exit_profile_output && | |
00000a4e: 4C0D ldr r4, [pc, #0x34] | |
79 { | |
00000a50: 4605 mov r5, r0 | |
83 if (__TI_enable_exit_profile_output && | |
00000a52: 68A0 ldr r0, [r4, #8] | |
00000a54: B120 cbz r0, #0xa60 | |
00000a56: 480C ldr r0, [pc, #0x30] | |
00000a58: F1B03FFF cmp.w r0, #-1 | |
00000a5c: D000 beq $C$L2 | |
87 (ppfunc)(); | |
00000a5e: 4780 blx r0 | |
94 _lock(); | |
$C$L2: | |
00000a60: 480A ldr r0, [pc, #0x28] | |
00000a62: 6800 ldr r0, [r0] | |
00000a64: 4780 blx r0 | |
101 if (__TI_dtors_ptr) (*__TI_dtors_ptr)(status); | |
00000a66: 6860 ldr r0, [r4, #4] | |
00000a68: B110 cbz r0, #0xa70 | |
00000a6a: 4601 mov r1, r0 | |
00000a6c: 4628 mov r0, r5 | |
00000a6e: 4788 blx r1 | |
117 if (__TI_cleanup_ptr) (*__TI_cleanup_ptr)(); | |
$C$L3: | |
00000a70: 6820 ldr r0, [r4] | |
00000a72: B100 cbz r0, #0xa76 | |
00000a74: 4780 blx r0 | |
120 _unlock(); | |
$C$L4: | |
00000a76: 4806 ldr r0, [pc, #0x18] | |
00000a78: 6800 ldr r0, [r0] | |
00000a7a: 4780 blx r0 | |
121 abort(); | |
00000a7c: F7FFFFE2 bl #0xa44 | |
00000a80: BD38 pop {r3, r4, r5, pc} | |
00000a82: 46C0 mov r8, r8 | |
$C$CON1: | |
00000a84: 0800 lsrs r0, r0, #0x20 | |
00000a86: 2000 movs r0, #0 | |
$C$CON2: | |
00000a88: FFFFFFFF .word 0xffffffff | |
$C$CON3: | |
00000a8c: 080C lsrs r4, r1, #0x20 | |
00000a8e: 2000 movs r0, #0 | |
$C$CON4: | |
00000a90: 0810 lsrs r0, r2, #0x20 | |
00000a92: 2000 movs r0, #0 | |
50 { | |
copy_in(): | |
00000a94: B5F8 push {r3, r4, r5, r6, r7, lr} | |
00000a96: 4606 mov r6, r0 | |
68 else if (__TI_Handler_Table_Base != __TI_Handler_Table_Limit) | |
00000a98: 4D0F ldr r5, [pc, #0x3c] | |
00000a9a: 4F10 ldr r7, [pc, #0x40] | |
00000a9c: 8873 ldrh r3, [r6, #2] | |
53 for (i = 0; i < tp->num_recs; i++) | |
00000a9e: 2400 movs r4, #0 | |
00000aa0: E017 b $C$L5 | |
55 COPY_RECORD crp = tp->recs[i]; | |
$C$L1: | |
00000aa2: 00A0 lsls r0, r4, #2 | |
00000aa4: EB0000C4 add.w r0, r0, r4, lsl #3 | |
00000aa8: 1832 adds r2, r6, r0 | |
56 char *load_addr = (char*)crp.load_addr; | |
00000aaa: 6851 ldr r1, [r2, #4] | |
57 char *run_addr = (char *)crp.run_addr; | |
00000aac: 6890 ldr r0, [r2, #8] | |
55 COPY_RECORD crp = tp->recs[i]; | |
00000aae: 68D2 ldr r2, [r2, #0xc] | |
00000ab0: B952 cbnz r2, #0xac8 | |
68 else if (__TI_Handler_Table_Base != __TI_Handler_Table_Limit) | |
00000ab2: 42AF cmp r7, r5 | |
00000ab4: D00B beq $C$L4 | |
78 handler(load_addr, run_addr); | |
00000ab6: 780A ldrb r2, [r1] | |
00000ab8: F8552022 ldr.w r2, [r5, r2, lsl #2] | |
00000abc: 4603 mov r3, r0 | |
00000abe: 1C49 adds r1, r1, #1 | |
00000ac0: 4608 mov r0, r1 | |
00000ac2: 4619 mov r1, r3 | |
00000ac4: 4790 blx r2 | |
00000ac6: E001 b $C$L3 | |
65 memcpy(run_addr, load_addr, crp.size); | |
$C$L2: | |
00000ac8: F7FFFE3B bl #0x742 | |
$C$L3: | |
00000acc: 8873 ldrh r3, [r6, #2] | |
53 for (i = 0; i < tp->num_recs; i++) | |
$C$L4: | |
00000ace: 1C64 adds r4, r4, #1 | |
00000ad0: B2A4 uxth r4, r4 | |
$C$L5: | |
00000ad2: 42A3 cmp r3, r4 | |
00000ad4: DCE5 bgt $C$L1 | |
00000ad6: BDF8 pop {r3, r4, r5, r6, r7, pc} | |
$C$CON1: | |
00000ad8: 0FC8 lsrs r0, r1, #0x1f | |
00000ada: 0000 movs r0, r0 | |
$C$CON2: | |
00000adc: 0FD0 lsrs r0, r2, #0x1f | |
00000ade: 0000 movs r0, r0 | |
278 ui16PFract = ((HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_MFRAC_M) >> | |
_SysCtlFrequencyGet(): | |
00000ae0: 4A10 ldr r2, [pc, #0x40] | |
00000ae2: B570 push {r4, r5, r6, lr} | |
00000ae4: 6811 ldr r1, [r2] | |
280 ui16PInt = HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_MINT_M; | |
00000ae6: 6815 ldr r5, [r2] | |
281 ui8Q = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_Q_M) >> | |
00000ae8: 6854 ldr r4, [r2, #4] | |
283 ui8N = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_N_M) >> | |
00000aea: 6853 ldr r3, [r2, #4] | |
278 ui16PFract = ((HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_MFRAC_M) >> | |
00000aec: F3C12189 ubfx r1, r1, #0xa, #0xa | |
324 return(ui32Result); | |
00000af0: F021061F bic r6, r1, #0x1f | |
283 ui8N = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_N_M) >> | |
00000af4: F003031F and r3, r3, #0x1f | |
324 return(ui32Result); | |
00000af8: 094A lsrs r2, r1, #5 | |
283 ui8N = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_N_M) >> | |
00000afa: 1C5B adds r3, r3, #1 | |
289 ui32Xtal /= (uint32_t)ui8N; | |
00000afc: FBB0F3F3 udiv r3, r0, r3 | |
324 return(ui32Result); | |
00000b00: 1B89 subs r1, r1, r6 | |
00000b02: FB03F002 mul r0, r3, r2 | |
280 ui16PInt = HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_MINT_M; | |
00000b06: F3C50209 ubfx r2, r5, #0, #0xa | |
324 return(ui32Result); | |
00000b0a: 0940 lsrs r0, r0, #5 | |
00000b0c: FB03F501 mul r5, r3, r1 | |
281 ui8Q = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_Q_M) >> | |
00000b10: F3C42104 ubfx r1, r4, #8, #5 | |
324 return(ui32Result); | |
00000b14: EB002095 add.w r0, r0, r5, lsr #10 | |
281 ui8Q = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_Q_M) >> | |
00000b18: 1C49 adds r1, r1, #1 | |
324 return(ui32Result); | |
00000b1a: FB030002 mla r0, r3, r2, r0 | |
00000b1e: FBB0F0F1 udiv r0, r0, r1 | |
00000b22: BD70 pop {r4, r5, r6, pc} | |
$C$CON108: | |
00000b24: E160 b #0xde8 | |
00000b26: 400F ands r7, r1 | |
44 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL); // Front Panel LEDs | |
InitIO(): | |
00000b28: 480A ldr r0, [pc, #0x28] | |
00000b2a: B510 push {r4, lr} | |
00000b2c: F000F816 bl #0xb5c | |
49 GPIOPinWrite(GPIO_PORTL_BASE, LED_2 ,0); | |
00000b30: 4C09 ldr r4, [pc, #0x24] | |
47 GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, LED_2); | |
00000b32: 2102 movs r1, #2 | |
00000b34: 4620 mov r0, r4 | |
00000b36: F000F875 bl #0xc24 | |
48 GPIOPadConfigSet(GPIO_PORTL_BASE, LED_2,GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); //Set Output | |
00000b3a: 2102 movs r1, #2 | |
00000b3c: 2201 movs r2, #1 | |
00000b3e: 2308 movs r3, #8 | |
00000b40: 4620 mov r0, r4 | |
00000b42: F7FFFD65 bl #0x610 | |
49 GPIOPinWrite(GPIO_PORTL_BASE, LED_2 ,0); | |
00000b46: 2102 movs r1, #2 | |
00000b48: 2200 movs r2, #0 | |
00000b4a: 4620 mov r0, r4 | |
00000b4c: F000F8BE bl #0xccc | |
00000b50: BD10 pop {r4, pc} | |
00000b52: 46C0 mov r8, r8 | |
$C$CON5: | |
00000b54: 080A lsrs r2, r1, #0x20 | |
00000b56: F0002000 and r0, r0, #0 | |
00000b5a: 4006 ands r6, r0 | |
855 HWREGBITW(SYSCTL_RCGCBASE + ((ui32Peripheral & 0xff00) >> 8), | |
SysCtlPeripheralEnable(): | |
00000b5c: 4A0B ldr r2, [pc, #0x2c] | |
00000b5e: 08C1 lsrs r1, r0, #3 | |
00000b60: F3C02307 ubfx r3, r0, #8, #8 | |
00000b64: F40151FF and r1, r1, #0x1fe0 | |
00000b68: F00000FF and r0, r0, #0xff | |
00000b6c: F5A13150 sub.w r1, r1, #0x34000 | |
00000b70: 18D2 adds r2, r2, r3 | |
00000b72: F021417E bic r1, r1, #0xfe000000 | |
00000b76: 0F12 lsrs r2, r2, #0x1c | |
00000b78: EA417102 orr.w r1, r1, r2, lsl #28 | |
00000b7c: 2201 movs r2, #1 | |
00000b7e: EA410180 orr.w r1, r1, r0, lsl #2 | |
00000b82: F0417000 orr r0, r1, #0x2000000 | |
00000b86: 6002 str r2, [r0] | |
00000b88: 4770 bx lr | |
00000b8a: 46C0 mov r8, r8 | |
$C$CON34: | |
00000b8c: E600 b #0x790 | |
00000b8e: 400F ands r7, r1 | |
36 SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER2); | |
InitTimers(): | |
00000b90: 4807 ldr r0, [pc, #0x1c] | |
00000b92: B510 push {r4, lr} | |
00000b94: F7FFFFE2 bl #0xb5c | |
40 TimerLoadSet(TIMER2_BASE,TIMER_A,SYSCLOCK/4);//Period of 0.25 Seconds | |
00000b98: 4C06 ldr r4, [pc, #0x18] | |
39 TimerConfigure(TIMER2_BASE,TIMER_CFG_PERIODIC); | |
00000b9a: 2122 movs r1, #0x22 | |
00000b9c: 4620 mov r0, r4 | |
00000b9e: F7FFFEF5 bl #0x98c | |
40 TimerLoadSet(TIMER2_BASE,TIMER_A,SYSCLOCK/4);//Period of 0.25 Seconds | |
00000ba2: 4A05 ldr r2, [pc, #0x14] | |
00000ba4: 21FF movs r1, #0xff | |
00000ba6: 4620 mov r0, r4 | |
00000ba8: F000F867 bl #0xc7a | |
00000bac: BD10 pop {r4, pc} | |
00000bae: 46C0 mov r8, r8 | |
$C$CON2: | |
00000bb0: 0402 lsls r2, r0, #0x10 | |
00000bb2: F0002000 and r0, r0, #0 | |
00000bb6: 4003 ands r3, r0 | |
$C$CON4: | |
00000bb8: C380 stm r3!, {r7} | |
00000bba: 01C9 lsls r1, r1, #7 | |
314 HWREG(ui32Port + GPIO_O_DIR) = ((ui32PinIO & 1) ? | |
GPIODirModeSet(): | |
00000bbc: 0853 lsrs r3, r2, #1 | |
00000bbe: BF27 ittee hs | |
00000bc0: F8D03400 ldr.w r3, [r0, #0x400] | |
00000bc4: 430B orrs r3, r1 | |
00000bc6: F8D03400 ldr.w r3, [r0, #0x400] | |
00000bca: 438B bics r3, r1 | |
317 HWREG(ui32Port + GPIO_O_AFSEL) = ((ui32PinIO & 2) ? | |
00000bcc: 0892 lsrs r2, r2, #2 | |
314 HWREG(ui32Port + GPIO_O_DIR) = ((ui32PinIO & 1) ? | |
00000bce: F8C03400 str.w r3, [r0, #0x400] | |
00000bd2: BF27 ittee hs | |
317 HWREG(ui32Port + GPIO_O_AFSEL) = ((ui32PinIO & 2) ? | |
00000bd4: F8D02420 ldr.w r2, [r0, #0x420] | |
00000bd8: 430A orrs r2, r1 | |
00000bda: F8D02420 ldr.w r2, [r0, #0x420] | |
00000bde: 438A bics r2, r1 | |
00000be0: F8C02420 str.w r2, [r0, #0x420] | |
00000be4: 4770 bx lr | |
272 while(1) | |
$C$L3, IntDefaultHandler(): | |
00000be6: E7FE b IntDefaultHandler | |
230 { | |
_SysCtlMemTimingGet(): | |
00000be8: 4906 ldr r1, [pc, #0x18] | |
237 ui8Idx < (sizeof(g_sXTALtoMEMTIM) / sizeof(g_sXTALtoMEMTIM[0])); | |
00000bea: 2206 movs r2, #6 | |
00000bec: 3908 subs r1, #8 | |
244 if(ui32SysClock <= g_sXTALtoMEMTIM[ui8Idx].ui32Frequency) | |
$C$L45: | |
00000bee: F8513F08 ldr r3, [r1, #8]! | |
00000bf2: 4283 cmp r3, r0 | |
00000bf4: BF28 it hs | |
250 return(g_sXTALtoMEMTIM[ui8Idx].ui32MemTiming); | |
00000bf6: 6848 ldr r0, [r1, #4] | |
00000bf8: D202 bhs $C$L46 | |
237 ui8Idx < (sizeof(g_sXTALtoMEMTIM) / sizeof(g_sXTALtoMEMTIM[0])); | |
00000bfa: 1E52 subs r2, r2, #1 | |
00000bfc: D1F7 bne $C$L45 | |
258 return(0); | |
00000bfe: 2000 movs r0, #0 | |
$C$L46: | |
00000c00: 4770 bx lr | |
00000c02: 46C0 mov r8, r8 | |
$C$CON107: | |
00000c04: 0F74 lsrs r4, r6, #0x1d | |
00000c06: 0000 movs r0, r0 | |
84 digit_blink = !digit_blink; | |
Timer2IntHandler(): | |
00000c08: 4905 ldr r1, [pc, #0x14] | |
00000c0a: 7808 ldrb r0, [r1] | |
00000c0c: F0800001 eor r0, r0, #1 | |
00000c10: 7008 strb r0, [r1] | |
86 TimerIntClear(TIMER2_BASE, TIMER_TIMA_TIMEOUT); | |
00000c12: 4802 ldr r0, [pc, #8] | |
00000c14: 2101 movs r1, #1 | |
00000c16: F000B85F b.w TimerIntClear | |
00000c1a: 46C0 mov r8, r8 | |
$C$CON14: | |
00000c1c: 2000 movs r0, #0 | |
00000c1e: 4003 ands r3, r0 | |
$C$CON15: | |
00000c20: 0814 lsrs r4, r2, #0x20 | |
00000c22: 2000 movs r0, #0 | |
1599 { | |
GPIOPinTypeGPIOOutput(): | |
00000c24: B538 push {r3, r4, r5, lr} | |
1608 GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); | |
00000c26: 2201 movs r2, #1 | |
1599 { | |
00000c28: 460C mov r4, r1 | |
00000c2a: 4605 mov r5, r0 | |
1608 GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); | |
00000c2c: 2308 movs r3, #8 | |
00000c2e: F7FFFCEF bl #0x610 | |
1613 GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_OUT); | |
00000c32: 4621 mov r1, r4 | |
00000c34: 4628 mov r0, r5 | |
00000c36: F7FFFFC1 bl #0xbbc | |
00000c3a: BD38 pop {r3, r4, r5, pc} | |
78 if (_symval(&__c_args__) != NO_C_ARGS) | |
_args_main(): | |
00000c3c: 4904 ldr r1, [pc, #0x10] | |
00000c3e: F1B13FFF cmp.w r1, #-1 | |
00000c42: BF07 ittee eq | |
76 register char **argv = 0; | |
00000c44: 2100 movs r1, #0 | |
00000c46: 1C08 adds r0, r1, #0 | |
79 { argc = pargs->argc; argv = pargs->argv; } | |
00000c48: 6808 ldr r0, [r1] | |
00000c4a: 1D09 adds r1, r1, #4 | |
81 return main(argc, argv); | |
00000c4c: F7FFBE00 b.w main | |
$C$CON1: | |
00000c50: FFFFFFFF .word 0xffffffff | |
56 _unlock = unlock; | |
_register_unlock(): | |
00000c54: 4903 ldr r1, [pc, #0xc] | |
00000c56: 6008 str r0, [r1] | |
00000c58: 4770 bx lr | |
51 _lock = lock; | |
_register_lock(): | |
00000c5a: 4902 ldr r1, [pc, #8] | |
00000c5c: 1F09 subs r1, r1, #4 | |
00000c5e: 6008 str r0, [r1] | |
00000c60: 4770 bx lr | |
40 { | |
_nop(): | |
00000c62: 4770 bx lr | |
$C$CON1: | |
00000c64: 0810 lsrs r0, r2, #0x20 | |
00000c66: 2000 movs r0, #0 | |
1459 { | |
GPIOPinTypeEthernetLED(): | |
00000c68: B510 push {r4, lr} | |
1468 GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); | |
00000c6a: 2202 movs r2, #2 | |
00000c6c: F7FFFFA6 bl #0xbbc | |
1473 GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); | |
00000c70: 2266 movs r2, #0x66 | |
00000c72: 2308 movs r3, #8 | |
00000c74: F7FFFCCC bl #0x610 | |
00000c78: BD10 pop {r4, pc} | |
984 if(ui32Timer & TIMER_A) | |
TimerLoadSet(): | |
00000c7a: F0110FFF tst.w r1, #0xff | |
00000c7e: BF18 it ne | |
986 HWREG(ui32Base + TIMER_O_TAILR) = ui32Value; | |
00000c80: 6282 str r2, [r0, #0x28] | |
992 if(ui32Timer & TIMER_B) | |
00000c82: F4114F7F tst.w r1, #0xff00 | |
00000c86: BF18 it ne | |
994 HWREG(ui32Base + TIMER_O_TBILR) = ui32Value; | |
00000c88: 62C2 str r2, [r0, #0x2c] | |
00000c8a: 4770 bx lr | |
212 { | |
IntMasterEnable(): | |
00000c8c: B508 push {r3, lr} | |
216 return(CPUcpsie()); | |
00000c8e: F000F813 bl #0xcb8 | |
00000c92: 2100 movs r1, #0 | |
00000c94: B100 cbz r0, #0xc98 | |
00000c96: 2101 movs r1, #1 | |
$C$L18: | |
00000c98: 4608 mov r0, r1 | |
00000c9a: BD08 pop {r3, pc} | |
223 HWREG(ui32Base + TIMER_O_CTL) |= ui32Timer & (TIMER_CTL_TAEN | | |
TimerEnable(): | |
00000c9c: 68C3 ldr r3, [r0, #0xc] | |
00000c9e: F2401201 movw r2, #0x101 | |
00000ca2: 4011 ands r1, r2 | |
00000ca4: 4319 orrs r1, r3 | |
00000ca6: 60C1 str r1, [r0, #0xc] | |
00000ca8: 4770 bx lr | |
101 memcpy(outbuf, (const unsigned char*)count_p, count); | |
__TI_decompress_none(): | |
00000caa: F8D02003 ldr.w r2, [r0, #3] | |
98 pointer_t count_p = (pointer_t)inbuf + (__alignof__(recordsize_t) - 1); | |
00000cae: 1DC3 adds r3, r0, #7 | |
101 memcpy(outbuf, (const unsigned char*)count_p, count); | |
00000cb0: 4608 mov r0, r1 | |
00000cb2: 4619 mov r1, r3 | |
00000cb4: F7FFBD45 b.w memcpy | |
267 { | |
CPUcpsie(): | |
00000cb8: F3EF8010 mrs r0, primask | |
00000cbc: B662 cpsie i | |
00000cbe: 4770 bx lr | |
282 return(0); | |
00000cc0: 2000 movs r0, #0 | |
00000cc2: 4770 bx lr | |
1477 HWREG(ui32Base + TIMER_O_IMR) |= ui32IntFlags; | |
TimerIntEnable(): | |
00000cc4: 6982 ldr r2, [r0, #0x18] | |
00000cc6: 4311 orrs r1, r2 | |
00000cc8: 6181 str r1, [r0, #0x18] | |
00000cca: 4770 bx lr | |
1147 HWREG(ui32Port + (GPIO_O_DATA + (ui8Pins << 2))) = ui8Val; | |
GPIOPinWrite(): | |
00000ccc: F8402021 str.w r2, [r0, r1, lsl #2] | |
00000cd0: 4770 bx lr | |
214 { | |
ResetISR(): | |
00000cd2: F7FFBE8B b.w _c_int00 | |
00000cd6: 4770 bx lr | |
1581 HWREG(ui32Base + TIMER_O_ICR) = ui32IntFlags; | |
TimerIntClear(): | |
00000cd8: 6241 str r1, [r0, #0x24] | |
00000cda: 4770 bx lr | |
58 return 1; | |
_system_pre_init(): | |
00000cdc: 2001 movs r0, #1 | |
00000cde: 4770 bx lr | |
236 while(1) | |
$C$L1, NmiSR(): | |
00000ce0: E7FE b NmiSR | |
51 { | |
__mpu_init(): | |
00000ce2: 4770 bx lr | |
50 { | |
_system_post_cinit(): | |
00000ce4: 4770 bx lr | |
00000ce6: 0000 movs r0, r0 | |
00000ce8: 0040 lsls r0, r0, #1 | |
00000cea: 0000 movs r0, r0 | |
00000cec: 0000 movs r0, r0 | |
00000cee: 0000 movs r0, r0 | |
00000cf0: 0100 lsls r0, r0, #4 | |
00000cf2: 0000 movs r0, r0 | |
00000cf4: 003E movs r6, r7 | |
00000cf6: 0008 movs r0, r1 | |
00000cf8: 0000 movs r0, r0 | |
00000cfa: 0000 movs r0, r0 | |
00000cfc: 0100 lsls r0, r0, #4 | |
00000cfe: 0000 movs r0, r0 | |
00000d00: 00A0 lsls r0, r4, #2 | |
00000d02: 0000 movs r0, r0 | |
00000d04: 0002 movs r2, r0 | |
00000d06: 0000 movs r0, r0 | |
00000d08: 0100 lsls r0, r0, #4 | |
00000d0a: 0000 movs r0, r0 | |
00000d0c: 5434 strb r4, [r6, r0] | |
00000d0e: 0001 movs r1, r0 | |
00000d10: 0000 movs r0, r0 | |
00000d12: 0000 movs r0, r0 | |
00000d14: 0100 lsls r0, r0, #4 | |
00000d16: 0000 movs r0, r0 | |
00000d18: 702B strb r3, [r5] | |
00000d1a: 0006 movs r6, r0 | |
00000d1c: 0000 movs r0, r0 | |
00000d1e: 0000 movs r0, r0 | |
00000d20: 0100 lsls r0, r0, #4 | |
00000d22: 0000 movs r0, r0 | |
00000d24: 0028 movs r0, r5 | |
00000d26: 0000 movs r0, r0 | |
00000d28: 0000 movs r0, r0 | |
00000d2a: 0000 movs r0, r0 | |
00000d2c: 0100 lsls r0, r0, #4 | |
00000d2e: 0000 movs r0, r0 | |
00000d30: 0027 movs r7, r4 | |
00000d32: 0001 movs r1, r0 | |
00000d34: 0000 movs r0, r0 | |
00000d36: 0000 movs r0, r0 | |
00000d38: 0100 lsls r0, r0, #4 | |
00000d3a: 0000 movs r0, r0 | |
00000d3c: 0020 movs r0, r4 | |
00000d3e: 0000 movs r0, r0 | |
00000d40: 0000 movs r0, r0 | |
00000d42: 0000 movs r0, r0 | |
00000d44: 0100 lsls r0, r0, #4 | |
00000d46: 0000 movs r0, r0 | |
00000d48: 0050 lsls r0, r2, #1 | |
00000d4a: 0000 movs r0, r0 | |
00000d4c: 0002 movs r2, r0 | |
00000d4e: 0000 movs r0, r0 | |
00000d50: 0100 lsls r0, r0, #4 | |
00000d52: 0000 movs r0, r0 | |
00000d54: AC1A add r4, sp, #0x68 | |
00000d56: 0000 movs r0, r0 | |
00000d58: 0000 movs r0, r0 | |
00000d5a: 0000 movs r0, r0 | |
00000d5c: 0100 lsls r0, r0, #4 | |
00000d5e: 0000 movs r0, r0 | |
00000d60: 9417 str r4, [sp, #0x5c] | |
00000d62: 0009 movs r1, r1 | |
00000d64: 0000 movs r0, r0 | |
00000d66: 0000 movs r0, r0 | |
00000d68: 0100 lsls r0, r0, #4 | |
00000d6a: 0000 movs r0, r0 | |
00000d6c: 9816 ldr r0, [sp, #0x58] | |
00000d6e: 0005 movs r5, r0 | |
00000d70: 0000 movs r0, r0 | |
00000d72: 0000 movs r0, r0 | |
00000d74: 0100 lsls r0, r0, #4 | |
00000d76: 0000 movs r0, r0 | |
00000d78: 0014 movs r4, r2 | |
00000d7a: 0000 movs r0, r0 | |
00000d7c: 0000 movs r0, r0 | |
00000d7e: 0000 movs r0, r0 | |
00000d80: 0100 lsls r0, r0, #4 | |
00000d82: 0000 movs r0, r0 | |
00000d84: 8013 strh r3, [r2] | |
00000d86: 0008 movs r0, r1 | |
00000d88: 0000 movs r0, r0 | |
00000d8a: 0000 movs r0, r0 | |
00000d8c: 0100 lsls r0, r0, #4 | |
00000d8e: 0000 movs r0, r0 | |
00000d90: 00A0 lsls r0, r4, #2 | |
00000d92: 0000 movs r0, r0 | |
00000d94: 0008 movs r0, r1 | |
00000d96: 0000 movs r0, r0 | |
00000d98: 0100 lsls r0, r0, #4 | |
00000d9a: 0000 movs r0, r0 | |
00000d9c: 0010 movs r0, r2 | |
00000d9e: 0000 movs r0, r0 | |
00000da0: 0000 movs r0, r0 | |
00000da2: 0000 movs r0, r0 | |
00000da4: 0100 lsls r0, r0, #4 | |
00000da6: 0000 movs r0, r0 | |
00000da8: 0028 movs r0, r5 | |
00000daa: 0000 movs r0, r0 | |
00000dac: 0002 movs r2, r0 | |
00000dae: 0000 movs r0, r0 | |
00000db0: 0100 lsls r0, r0, #4 | |
00000db2: 0000 movs r0, r0 | |
00000db4: 0040 lsls r0, r0, #1 | |
00000db6: 0000 movs r0, r0 | |
00000db8: 0004 movs r4, r0 | |
00000dba: 0000 movs r0, r0 | |
00000dbc: 0100 lsls r0, r0, #4 | |
00000dbe: 0000 movs r0, r0 | |
00000dc0: 0060 lsls r0, r4, #1 | |
00000dc2: 0000 movs r0, r0 | |
00000dc4: 0000 movs r0, r0 | |
00000dc6: 0000 movs r0, r0 | |
00000dc8: 0100 lsls r0, r0, #4 | |
00000dca: 0000 movs r0, r0 | |
00000dcc: 005D lsls r5, r3, #1 | |
00000dce: 000C movs r4, r1 | |
00000dd0: 0000 movs r0, r0 | |
00000dd2: 0000 movs r0, r0 | |
00000dd4: 0100 lsls r0, r0, #4 | |
00000dd6: 0000 movs r0, r0 | |
00000dd8: 0050 lsls r0, r2, #1 | |
00000dda: 0000 movs r0, r0 | |
00000ddc: 0000 movs r0, r0 | |
00000dde: 0000 movs r0, r0 | |
00000de0: 0100 lsls r0, r0, #4 | |
00000de2: 0000 movs r0, r0 | |
00000de4: 004E lsls r6, r1, #1 | |
00000de6: 0002 movs r2, r0 | |
00000de8: 0000 movs r0, r0 | |
00000dea: 0000 movs r0, r0 | |
00000dec: 0100 lsls r0, r0, #4 | |
00000dee: 0000 movs r0, r0 | |
00000df0: AC41 add r4, sp, #0x104 | |
00000df2: 0001 movs r1, r0 | |
00000df4: 0000 movs r0, r0 | |
00000df6: 0000 movs r0, r0 | |
00000df8: 0100 lsls r0, r0, #4 | |
00000dfa: 0000 movs r0, r0 | |
00000dfc: 003C movs r4, r7 | |
00000dfe: 0000 movs r0, r0 | |
00000e00: 0000 movs r0, r0 | |
00000e02: 0000 movs r0, r0 | |
00000e04: 0100 lsls r0, r0, #4 | |
00000e06: 0000 movs r0, r0 | |
00000e08: 803A strh r2, [r7] | |
00000e0a: 0009 movs r1, r1 | |
00000e0c: 0000 movs r0, r0 | |
00000e0e: 0000 movs r0, r0 | |
00000e10: 0100 lsls r0, r0, #4 | |
00000e12: 0000 movs r0, r0 | |
00000e14: 0030 movs r0, r6 | |
00000e16: 0000 movs r0, r0 | |
00000e18: 0000 movs r0, r0 | |
00000e1a: 0000 movs r0, r0 | |
00000e1c: 0100 lsls r0, r0, #4 | |
00000e1e: 0000 movs r0, r0 | |
00000e20: 0028 movs r0, r5 | |
00000e22: 0000 movs r0, r0 | |
00000e24: 0000 movs r0, r0 | |
00000e26: 0000 movs r0, r0 | |
00000e28: 0100 lsls r0, r0, #4 | |
00000e2a: 0000 movs r0, r0 | |
00000e2c: 0027 movs r7, r4 | |
00000e2e: 0001 movs r1, r0 | |
00000e30: 0000 movs r0, r0 | |
00000e32: 0000 movs r0, r0 | |
00000e34: 0100 lsls r0, r0, #4 | |
00000e36: 0000 movs r0, r0 | |
00000e38: 6023 str r3, [r4] | |
00000e3a: 0006 movs r6, r0 | |
00000e3c: 0000 movs r0, r0 | |
00000e3e: 0000 movs r0, r0 | |
00000e40: 0100 lsls r0, r0, #4 | |
00000e42: 0000 movs r0, r0 | |
00000e44: 6021 str r1, [r4] | |
00000e46: 0008 movs r0, r1 | |
00000e48: 0000 movs r0, r0 | |
00000e4a: 0000 movs r0, r0 | |
00000e4c: 0100 lsls r0, r0, #4 | |
00000e4e: 0000 movs r0, r0 | |
00000e50: 001E movs r6, r3 | |
00000e52: 0000 movs r0, r0 | |
00000e54: 0000 movs r0, r0 | |
00000e56: 0000 movs r0, r0 | |
00000e58: 0100 lsls r0, r0, #4 | |
00000e5a: 0000 movs r0, r0 | |
00000e5c: C01D stm r0!, {r0, r2, r3, r4} | |
00000e5e: 0004 movs r4, r0 | |
00000e60: 0000 movs r0, r0 | |
00000e62: 0000 movs r0, r0 | |
00000e64: 0100 lsls r0, r0, #4 | |
00000e66: 0000 movs r0, r0 | |
00000e68: 0050 lsls r0, r2, #1 | |
00000e6a: 0000 movs r0, r0 | |
00000e6c: 0002 movs r2, r0 | |
00000e6e: 0000 movs r0, r0 | |
00000e70: 0100 lsls r0, r0, #4 | |
00000e72: 0000 movs r0, r0 | |
00000e74: 0018 movs r0, r3 | |
00000e76: 0000 movs r0, r0 | |
00000e78: 0000 movs r0, r0 | |
00000e7a: 0000 movs r0, r0 | |
00000e7c: 0100 lsls r0, r0, #4 | |
00000e7e: 0000 movs r0, r0 | |
00000e80: 0014 movs r4, r2 | |
00000e82: 0000 movs r0, r0 | |
00000e84: 0000 movs r0, r0 | |
00000e86: 0000 movs r0, r0 | |
00000e88: 0100 lsls r0, r0, #4 | |
00000e8a: 0000 movs r0, r0 | |
00000e8c: 0060 lsls r0, r4, #1 | |
00000e8e: 0000 movs r0, r0 | |
00000e90: 0004 movs r4, r0 | |
00000e92: 0000 movs r0, r0 | |
00000e94: 0100 lsls r0, r0, #4 | |
00000e96: 0000 movs r0, r0 | |
00000e98: 0700 lsls r0, r0, #0x1c | |
00000e9a: 0000 movs r0, r0 | |
00000e9c: 0600 lsls r0, r0, #0x18 | |
00000e9e: 0000 movs r0, r0 | |
00000ea0: 0500 lsls r0, r0, #0x14 | |
00000ea2: 0000 movs r0, r0 | |
00000ea4: 0400 lsls r0, r0, #0x10 | |
00000ea6: 0000 movs r0, r0 | |
00000ea8: 0300 lsls r0, r0, #0xc | |
00000eaa: 0000 movs r0, r0 | |
00000eac: 0200 lsls r0, r0, #8 | |
00000eae: 0000 movs r0, r0 | |
00000eb0: 0100 lsls r0, r0, #4 | |
00000eb2: 0000 movs r0, r0 | |
00000eb4: 0000 movs r0, r0 | |
00000eb6: 0000 movs r0, r0 | |
00000eb8: E100 b #0x10bc | |
00000eba: E000 b #0xebe | |
00000ebc: E104 b #0x10c8 | |
00000ebe: E000 b #0xec2 | |
00000ec0: E108 b #0x10d4 | |
00000ec2: E000 b #0xec6 | |
00000ec4: E10C b #0x10e0 | |
00000ec6: E000 b #0xeca | |
00000ec8: E110 b #0x10ec | |
00000eca: E000 b #0xece | |
00000ecc: E180 b #0x11d0 | |
00000ece: E000 b #0xed2 | |
00000ed0: E184 b #0x11dc | |
00000ed2: E000 b #0xed6 | |
00000ed4: E188 b #0x11e8 | |
00000ed6: E000 b #0xeda | |
00000ed8: E18C b #0x11f4 | |
00000eda: E000 b #0xede | |
00000edc: E190 b #0x1200 | |
00000ede: E000 b #0xee2 | |
00000ee0: E200 b #0x12e4 | |
00000ee2: E000 b #0xee6 | |
00000ee4: E204 b #0x12f0 | |
00000ee6: E000 b #0xeea | |
00000ee8: E208 b #0x12fc | |
00000eea: E000 b #0xeee | |
00000eec: E20C b #0x1308 | |
00000eee: E000 b #0xef2 | |
00000ef0: E210 b #0x1314 | |
00000ef2: E000 b #0xef6 | |
00000ef4: E280 b #0x13f8 | |
00000ef6: E000 b #0xefa | |
00000ef8: E284 b #0x1404 | |
00000efa: E000 b #0xefe | |
00000efc: E288 b #0x1410 | |
00000efe: E000 b #0xf02 | |
00000f00: E28C b #0x141c | |
00000f02: E000 b #0xf06 | |
00000f04: E290 b #0x1428 | |
00000f06: E000 b #0xf0a | |
00000f08: 4240 rsbs r0, r0, #0 | |
00000f0a: 000F movs r7, r1 | |
00000f0c: 2000 movs r0, #0 | |
00000f0e: 001C movs r4, r3 | |
00000f10: 8480 strh r0, [r0, #0x24] | |
00000f12: 001E movs r6, r3 | |
00000f14: 8000 strh r0, [r0] | |
00000f16: 0025 movs r5, r4 | |
00000f18: 9E99 ldr r6, [sp, #0x264] | |
00000f1a: 0036 movs r6, r6 | |
00000f1c: 4000 ands r0, r0 | |
00000f1e: 0038 movs r0, r7 | |
00000f20: 0900 lsrs r0, r0, #4 | |
00000f22: 003D movs r5, r7 | |
00000f24: 8000 strh r0, [r0] | |
00000f26: 003E movs r6, r7 | |
00000f28: 0000 movs r0, r0 | |
00000f2a: 004B lsls r3, r1, #1 | |
00000f2c: 4B40 ldr r3, [pc, #0x100] | |
00000f2e: 004C lsls r4, r1, #1 | |
00000f30: 2000 movs r0, #0 | |
00000f32: 004E lsls r6, r1, #1 | |
00000f34: 8D80 ldrh r0, [r0, #0x2c] | |
00000f36: 005B lsls r3, r3, #1 | |
00000f38: C000 .word 0x0000c000 | |
00000f3a: 005D lsls r5, r3, #1 | |
00000f3c: 8000 strh r0, [r0] | |
00000f3e: 0070 lsls r0, r6, #1 | |
00000f40: 1200 asrs r0, r0, #8 | |
00000f42: 007A lsls r2, r7, #1 | |
00000f44: 0000 movs r0, r0 | |
00000f46: 007D lsls r5, r7, #1 | |
00000f48: 9680 str r6, [sp, #0x200] | |
00000f4a: 0098 lsls r0, r3, #2 | |
00000f4c: 1B00 subs r0, r0, r4 | |
00000f4e: 00B7 lsls r7, r6, #2 | |
00000f50: 8000 strh r0, [r0] | |
00000f52: 00BB lsls r3, r7, #2 | |
00000f54: E8C000CE .word 0x00cee8c0 | |
00000f58: 7A64 ldrb r4, [r4, #9] | |
00000f5a: 00DA lsls r2, r3, #3 | |
00000f5c: 2400 movs r4, #0 | |
00000f5e: 00F4 lsls r4, r6, #3 | |
00000f60: 0000 movs r0, r0 | |
00000f62: 00FA lsls r2, r7, #3 | |
00000f64: A880 add r0, sp, #0x200 | |
00000f66: 0112 lsls r2, r2, #4 | |
00000f68: 2D00 cmp r5, #0 | |
00000f6a: 0131 lsls r1, r6, #4 | |
00000f6c: 3600 adds r6, #0 | |
00000f6e: 016E lsls r6, r5, #5 | |
00000f70: 7840 ldrb r0, [r0, #1] | |
00000f72: 017D lsls r5, r7, #5 | |
00000f74: 2400 movs r4, #0 | |
00000f76: 00F4 lsls r4, r6, #3 | |
00000f78: 0030 movs r0, r6 | |
00000f7a: 0030 movs r0, r6 | |
00000f7c: 5A00 ldrh r0, [r0, r0] | |
00000f7e: 0262 lsls r2, r4, #9 | |
00000f80: 0091 lsls r1, r2, #2 | |
00000f82: 0091 lsls r1, r2, #2 | |
00000f84: 8700 strh r0, [r0, #0x38] | |
00000f86: 0393 lsls r3, r2, #0xe | |
00000f88: 00D2 lsls r2, r2, #3 | |
00000f8a: 00D2 lsls r2, r2, #3 | |
00000f8c: B400 .word 0x0000b400 | |
00000f8e: 04C4 lsls r4, r0, #0x13 | |
00000f90: 0113 lsls r3, r2, #4 | |
00000f92: 0113 lsls r3, r2, #4 | |
00000f94: E100 b #0x1198 | |
00000f96: 05F5 lsls r5, r6, #0x17 | |
00000f98: 0154 lsls r4, r2, #5 | |
00000f9a: 0154 lsls r4, r2, #5 | |
00000f9c: 0E00 lsrs r0, r0, #0x18 | |
00000f9e: 0727 lsls r7, r4, #0x1c | |
00000fa0: 0195 lsls r5, r2, #6 | |
00000fa2: 0195 lsls r5, r2, #6 | |
00000fa4: 6800 ldr r0, [r0] | |
00000fa6: 0989 lsrs r1, r1, #6 | |
00000fa8: 1C00 adds r0, r0, #0 | |
00000faa: 0E4E lsrs r6, r1, #0x19 | |
00000fac: 0000 movs r0, r0 | |
00000fae: 0000 movs r0, r0 | |
00000fb0: B500 push {lr} | |
00000fb2: 0000 movs r0, r0 | |
00000fb4: 0104 lsls r4, r0, #4 | |
00000fb6: 8000 strh r0, [r0] | |
00000fb8: 0C63 lsrs r3, r4, #0x11 | |
00000fba: 3300 adds r3, #0 | |
00000fbc: 0700 lsls r0, r0, #0x1c | |
00000fbe: 46C0 mov r8, r8 | |
00000fc0: 01C0 lsls r0, r0, #7 | |
00000fc2: FF7500F0 .word 0x00f0ff75 | |
00000fc6: 0000 movs r0, r0 | |
00000fc8: 0925 lsrs r5, r4, #4 | |
00000fca: 0000 movs r0, r0 | |
00000fcc: 0CAB lsrs r3, r5, #0x12 | |
00000fce: 0000 movs r0, r0 | |
00000fd0: 0FB0 lsrs r0, r6, #0x1e | |
00000fd2: 0000 movs r0, r0 | |
00000fd4: 0800 lsrs r0, r0, #0x20 | |
00000fd6: 2000 movs r0, #0 | |
00000fd8: FFFFFFFF .word 0xffffffff |
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