invertor.v

module invertor(input  wire x,
                output wire y);
    assign y = ~x;
endmodule

module test_invertor();
    reg  x;
    wire y, z;
    invertor inv(x, y);
    invertor inv1(y, z);

    initial begin
        x = 0; #1;
        $display("x = %b, y = %b, z = %b", x, y, z);
        x = 1; #1;
        $display("x = %b, y = %b, z = %b", x, y, z);
    end
endmodule

s2.v

module implication(input  wire x, y,
                   output wire out);
    assign out = ~x | y;
endmodule

module equivalence(input  wire x, y,
                   output wire out);
    assign out = 1 ^ x ^ y;
endmodule

module bred(input  wire a, b,
            output wire out);
    wire t1, t2;
    implication imp(a, b, t1);
    equivalence equ(a, b, t2);

    assign out = ~(t1 ^ t2);
endmodule

module test_bred();
    reg [2:0] i;
    wire out;
    bred b(i[0], i[1], out);
    initial begin
        for (i = 0; i <= 3'b011 ; i = i + 1) begin
           #1;
           $display("x = %b, y = %b, out = %b", i[0], i[1], out);
        end
    end
endmodule

sum1.v

module sum1(input  wire cin, x, y,
            output wire cout, out);
    assign cout = (x | y) & (cin | x) & (cin | y),
           out  = cin & (~x & ~y | x & y) | ~cin & (~x & y | x & ~y);
endmodule

module test_sum1();
    reg [3:0] i;
    wire x, y, cin;
    wire out, cout;

    assign {cin, x, y} = i;
    sum1 s1(cin, x, y, cout, out);

    initial begin
        for (i = 0; i <= 'b111; i = i+1) begin
            #1;
            $display("cin = %b, x = %b, y = %b | cout = %b, out = %b",
                         cin, x, y, cout, out);
        end
    end
endmodule

sum4.v

module sum1(input  wire cin, x, y,
            output wire cout, out);
    assign cout = (x | y) & (cin | x) & (cin | y),
           out  = cin & (~x & ~y | x & y) | ~cin & (~x & y | x & ~y);
endmodule

module sum4(input  wire       cin,
            input  wire [3:0] x, y,
            output wire       cout,
            output wire [3:0] out);

    wire [2:0] t;
    sum1 ss [3:0] ({t, cin}, x, y, {cout, t}, out);
endmodule

module sum #(parameter N=4) (input  wire         cin,
                             input  wire [N-1:0] x, y,
                             output wire         cout,
                             output wire [N-1:0] out);

    wire [N-2:0] t;
    sum1 ss [N-1:0] ({t, cin}, x, y, {cout, t}, out);
endmodule

module sub #(parameter N=4) (input  wire [N-1:0] x, y,
                             output wire         cout,
                             output wire [N-1:0] out);
    sum #(N) s(1, x, ~y, cout, out);
endmodule

module sumsub #(parameter N=4) (
                             input  wire         mode,
                             input  wire [N-1:0] x, y,
                             output wire         cout,
                             output wire [N-1:0] out);
endmodule


module sum16(input  wire        cin,
             input  wire [15:0] x, y,
             output wire        cout,
             output wire [15:0] out);

    wire [2:0] t;
    sum4 s0(cin,  x[3:0],   y[3:0],   t[0], out[3:0]),
         s1(t[0], x[7:4],   y[7:4],   t[1], out[7:4]),
         s2(t[1], x[11:8],  y[11:8],  t[2], out[11:8]),
         s3(t[2], x[15:12], y[15:12], cout, out[15:12]);
endmodule

module test();

    sub #(64) s(585429, 238753, , );

    initial begin
        #1;
        $display("out = %d", s.out);
    end
endmodule