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February 12, 2018 18:33
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| tinymembench v0.4.9 (simple benchmark for memory throughput and latency) | |
| ========================================================================== | |
| == Memory bandwidth tests == | |
| == == | |
| == Note 1: 1MB = 1000000 bytes == | |
| == Note 2: Results for 'copy' tests show how many bytes can be == | |
| == copied per second (adding together read and writen == | |
| == bytes would have provided twice higher numbers) == | |
| == Note 3: 2-pass copy means that we are using a small temporary buffer == | |
| == to first fetch data into it, and only then write it to the == | |
| == destination (source -> L1 cache, L1 cache -> destination) == | |
| == Note 4: If sample standard deviation exceeds 0.1%, it is shown in == | |
| == brackets == | |
| ========================================================================== | |
| C copy backwards : 1325.3 MB/s (0.6%) | |
| C copy backwards (32 byte blocks) : 1343.1 MB/s (0.5%) | |
| C copy backwards (64 byte blocks) : 1341.9 MB/s (0.4%) | |
| C copy : 1420.2 MB/s (0.4%) | |
| C copy prefetched (32 bytes step) : 1040.1 MB/s | |
| C copy prefetched (64 bytes step) : 1148.1 MB/s | |
| C 2-pass copy : 1224.4 MB/s (0.1%) | |
| C 2-pass copy prefetched (32 bytes step) : 886.9 MB/s | |
| C 2-pass copy prefetched (64 bytes step) : 762.5 MB/s | |
| C fill : 4722.4 MB/s | |
| C fill (shuffle within 16 byte blocks) : 4718.1 MB/s | |
| C fill (shuffle within 32 byte blocks) : 4718.6 MB/s | |
| C fill (shuffle within 64 byte blocks) : 4717.9 MB/s | |
| --- | |
| standard memcpy : 1424.5 MB/s | |
| standard memset : 4722.8 MB/s | |
| --- | |
| NEON LDP/STP copy : 1459.0 MB/s (0.1%) | |
| NEON LDP/STP copy pldl2strm (32 bytes step) : 964.8 MB/s (0.6%) | |
| NEON LDP/STP copy pldl2strm (64 bytes step) : 1202.8 MB/s | |
| NEON LDP/STP copy pldl1keep (32 bytes step) : 1557.4 MB/s | |
| NEON LDP/STP copy pldl1keep (64 bytes step) : 1556.9 MB/s | |
| NEON LD1/ST1 copy : 1445.5 MB/s (0.2%) | |
| NEON STP fill : 4724.1 MB/s | |
| NEON STNP fill : 2797.9 MB/s | |
| ARM LDP/STP copy : 1454.6 MB/s | |
| ARM STP fill : 4721.7 MB/s | |
| ARM STNP fill : 2797.3 MB/s (1.5%) | |
| ========================================================================== | |
| == Framebuffer read tests. == | |
| == == | |
| == Many ARM devices use a part of the system memory as the framebuffer, == | |
| == typically mapped as uncached but with write-combining enabled. == | |
| == Writes to such framebuffers are quite fast, but reads are much == | |
| == slower and very sensitive to the alignment and the selection of == | |
| == CPU instructions which are used for accessing memory. == | |
| == == | |
| == Many x86 systems allocate the framebuffer in the GPU memory, == | |
| == accessible for the CPU via a relatively slow PCI-E bus. Moreover, == | |
| == PCI-E is asymmetric and handles reads a lot worse than writes. == | |
| == == | |
| == If uncached framebuffer reads are reasonably fast (at least 100 MB/s == | |
| == or preferably >300 MB/s), then using the shadow framebuffer layer == | |
| == is not necessary in Xorg DDX drivers, resulting in a nice overall == | |
| == performance improvement. For example, the xf86-video-fbturbo DDX == | |
| == uses this trick. == | |
| ========================================================================== | |
| NEON LDP/STP copy (from framebuffer) : 197.4 MB/s | |
| NEON LDP/STP 2-pass copy (from framebuffer) : 184.1 MB/s | |
| NEON LD1/ST1 copy (from framebuffer) : 48.4 MB/s | |
| NEON LD1/ST1 2-pass copy (from framebuffer) : 47.4 MB/s | |
| ARM LDP/STP copy (from framebuffer) : 97.3 MB/s | |
| ARM LDP/STP 2-pass copy (from framebuffer) : 94.3 MB/s | |
| ========================================================================== | |
| == Memory latency test == | |
| == == | |
| == Average time is measured for random memory accesses in the buffers == | |
| == of different sizes. The larger is the buffer, the more significant == | |
| == are relative contributions of TLB, L1/L2 cache misses and SDRAM == | |
| == accesses. For extremely large buffer sizes we are expecting to see == | |
| == page table walk with several requests to SDRAM for almost every == | |
| == memory access (though 64MiB is not nearly large enough to experience == | |
| == this effect to its fullest). == | |
| == == | |
| == Note 1: All the numbers are representing extra time, which needs to == | |
| == be added to L1 cache latency. The cycle timings for L1 cache == | |
| == latency can be usually found in the processor documentation. == | |
| == Note 2: Dual random read means that we are simultaneously performing == | |
| == two independent memory accesses at a time. In the case if == | |
| == the memory subsystem can't handle multiple outstanding == | |
| == requests, dual random read has the same timings as two == | |
| == single reads performed one after another. == | |
| ========================================================================== | |
| block size : single random read / dual random read | |
| 1024 : 0.0 ns / 0.0 ns | |
| 2048 : 0.0 ns / 0.0 ns | |
| 4096 : 0.0 ns / 0.0 ns | |
| 8192 : 0.0 ns / 0.0 ns | |
| 16384 : 0.0 ns / 0.0 ns | |
| 32768 : 0.1 ns / 0.1 ns | |
| 65536 : 4.9 ns / 8.2 ns | |
| 131072 : 7.5 ns / 11.4 ns | |
| 262144 : 8.9 ns / 12.6 ns | |
| 524288 : 19.9 ns / 28.6 ns | |
| 1048576 : 109.3 ns / 160.7 ns | |
| 2097152 : 152.4 ns / 194.4 ns | |
| 4194304 : 176.7 ns / 211.6 ns | |
| 8388608 : 189.6 ns / 220.5 ns | |
| 16777216 : 196.8 ns / 226.2 ns | |
| 33554432 : 200.8 ns / 230.9 ns | |
| 67108864 : 204.5 ns / 235.9 ns |
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