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April 26, 2016 13:54
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red pitaya FPGA synthesis output
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| *** Running vivado | |
| with args -log red_pitaya_top.vds -m64 -mode batch -messageDb vivado.pb -notrace -source red_pitaya_top.tcl | |
| ****** Vivado v2016.1 (64-bit) | |
| **** SW Build 1538259 on Fri Apr 8 15:45:23 MDT 2016 | |
| **** IP Build 1537824 on Fri Apr 8 04:28:57 MDT 2016 | |
| ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. | |
| source red_pitaya_top.tcl -notrace | |
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |
| INFO: [IP_Flow 19-1704] No user IP repositories specified | |
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/jurek/data/Xilinx/Vivado/2016.1/data/ip'. | |
| Command: synth_design -top red_pitaya_top -part xc7z010clg400-1 | |
| Starting synth_design | |
| Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' | |
| INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' | |
| INFO: Launching helper process for spawning children vivado processes | |
| INFO: Helper process launched with PID 14788 | |
| --------------------------------------------------------------------------------- | |
| Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1048.902 ; gain = 158.082 ; free physical = 8955 ; free virtual = 29239 | |
| --------------------------------------------------------------------------------- | |
| INFO: [Synth 8-638] synthesizing module 'red_pitaya_top' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_top.v:64] | |
| INFO: [Synth 8-638] synthesizing module 'red_pitaya_ps' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_ps.v:43] | |
| INFO: [Synth 8-638] synthesizing module 'axi_master' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_master.v:13] | |
| Parameter DW bound to: 64 - type: integer | |
| Parameter AW bound to: 32 - type: integer | |
| Parameter ID bound to: 0 - type: integer | |
| Parameter IW bound to: 6 - type: integer | |
| Parameter LW bound to: 4 - type: integer | |
| Parameter SW bound to: 8 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_master' (1#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_master.v:13] | |
| INFO: [Synth 8-638] synthesizing module 'axi_slave' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_slave.v:49] | |
| Parameter AXI_DW bound to: 32 - type: integer | |
| Parameter AXI_AW bound to: 32 - type: integer | |
| Parameter AXI_IW bound to: 12 - type: integer | |
| Parameter AXI_SW bound to: 4 - type: integer | |
| INFO: [Synth 8-4471] merging register 'axi_rvalid_o_reg' into 'axi_rlast_o_reg' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_slave.v:183] | |
| INFO: [Synth 8-256] done synthesizing module 'axi_slave' (2#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_slave.v:49] | |
| INFO: [Synth 8-638] synthesizing module 'BUFG' [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:607] | |
| INFO: [Synth 8-256] done synthesizing module 'BUFG' (3#1) [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:607] | |
| INFO: [Synth 8-638] synthesizing module 'system_wrapper' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/hdl/system_wrapper.v:12] | |
| INFO: [Synth 8-638] synthesizing module 'system' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/hdl/system.v:13] | |
| INFO: [Synth 8-638] synthesizing module 'system_axi_protocol_converter_0_0' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_axi_protocol_converter_0_0/synth/system_axi_protocol_converter_0_0.v:58] | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_axi_protocol_converter' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v:62] | |
| Parameter C_FAMILY bound to: zynq - type: string | |
| Parameter C_M_AXI_PROTOCOL bound to: 2 - type: integer | |
| Parameter C_S_AXI_PROTOCOL bound to: 1 - type: integer | |
| Parameter C_IGNORE_ID bound to: 0 - type: integer | |
| Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer | |
| Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer | |
| Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer | |
| Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer | |
| Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_TRANSLATION_MODE bound to: 2 - type: integer | |
| Parameter P_AXI4 bound to: 0 - type: integer | |
| Parameter P_AXI3 bound to: 1 - type: integer | |
| Parameter P_AXILITE bound to: 2 - type: integer | |
| Parameter P_AXILITE_SIZE bound to: 3'b010 | |
| Parameter P_INCR bound to: 2'b01 | |
| Parameter P_DECERR bound to: 2'b11 | |
| Parameter P_SLVERR bound to: 2'b10 | |
| Parameter P_PROTECTION bound to: 1 - type: integer | |
| Parameter P_CONVERSION bound to: 2 - type: integer | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_b2s' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v:39] | |
| Parameter C_S_AXI_PROTOCOL bound to: 1 - type: integer | |
| Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer | |
| Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer | |
| Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_b2s_aw_channel' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_aw_channel.v:5] | |
| Parameter C_ID_WIDTH bound to: 12 - type: integer | |
| Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_b2s_cmd_translator' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_cmd_translator.v:17] | |
| Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer | |
| Parameter P_AXBURST_FIXED bound to: 2'b00 | |
| Parameter P_AXBURST_INCR bound to: 2'b01 | |
| Parameter P_AXBURST_WRAP bound to: 2'b10 | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_b2s_incr_cmd' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_incr_cmd.v:11] | |
| Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer | |
| Parameter L_AXI_ADDR_LOW_BIT bound to: 12 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_b2s_incr_cmd' (4#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_incr_cmd.v:11] | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_b2s_wrap_cmd' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wrap_cmd.v:11] | |
| Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer | |
| Parameter L_AXI_ADDR_LOW_BIT bound to: 12 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_b2s_wrap_cmd' (5#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wrap_cmd.v:11] | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_b2s_cmd_translator' (6#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_cmd_translator.v:17] | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_b2s_wr_cmd_fsm' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v:10] | |
| Parameter SM_IDLE bound to: 2'b00 | |
| Parameter SM_CMD_EN bound to: 2'b01 | |
| Parameter SM_CMD_ACCEPTED bound to: 2'b10 | |
| Parameter SM_DONE_WAIT bound to: 2'b11 | |
| INFO: [Synth 8-226] default block is never used [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v:64] | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_b2s_wr_cmd_fsm' (7#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v:10] | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_b2s_aw_channel' (8#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_aw_channel.v:5] | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_b2s_b_channel' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v:10] | |
| Parameter C_ID_WIDTH bound to: 12 - type: integer | |
| Parameter LP_RESP_OKAY bound to: 2'b00 | |
| Parameter LP_RESP_EXOKAY bound to: 2'b01 | |
| Parameter LP_RESP_SLVERROR bound to: 2'b10 | |
| Parameter LP_RESP_DECERR bound to: 2'b11 | |
| Parameter P_WIDTH bound to: 20 - type: integer | |
| Parameter P_DEPTH bound to: 4 - type: integer | |
| Parameter P_AWIDTH bound to: 2 - type: integer | |
| Parameter P_RWIDTH bound to: 2 - type: integer | |
| Parameter P_RDEPTH bound to: 4 - type: integer | |
| Parameter P_RAWIDTH bound to: 2 - type: integer | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_b2s_simple_fifo' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9] | |
| Parameter C_WIDTH bound to: 20 - type: integer | |
| Parameter C_AWIDTH bound to: 2 - type: integer | |
| Parameter C_DEPTH bound to: 4 - type: integer | |
| Parameter C_EMPTY bound to: 2'b11 | |
| Parameter C_EMPTY_PRE bound to: 2'b00 | |
| Parameter C_FULL bound to: 2'b10 | |
| Parameter C_FULL_PRE bound to: 2'b01 | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_b2s_simple_fifo' (9#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9] | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_b2s_simple_fifo__parameterized0' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9] | |
| Parameter C_WIDTH bound to: 2 - type: integer | |
| Parameter C_AWIDTH bound to: 2 - type: integer | |
| Parameter C_DEPTH bound to: 4 - type: integer | |
| Parameter C_EMPTY bound to: 2'b11 | |
| Parameter C_EMPTY_PRE bound to: 2'b00 | |
| Parameter C_FULL bound to: 2'b10 | |
| Parameter C_FULL_PRE bound to: 2'b01 | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_b2s_simple_fifo__parameterized0' (9#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9] | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_b2s_b_channel' (10#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v:10] | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_b2s_ar_channel' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v:5] | |
| Parameter C_ID_WIDTH bound to: 12 - type: integer | |
| Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_b2s_rd_cmd_fsm' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v:10] | |
| Parameter SM_IDLE bound to: 2'b00 | |
| Parameter SM_CMD_EN bound to: 2'b01 | |
| Parameter SM_CMD_ACCEPTED bound to: 2'b10 | |
| Parameter SM_DONE bound to: 2'b11 | |
| INFO: [Synth 8-226] default block is never used [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v:72] | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_b2s_rd_cmd_fsm' (11#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v:10] | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_b2s_ar_channel' (12#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v:5] | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_b2s_r_channel' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_r_channel.v:21] | |
| Parameter C_ID_WIDTH bound to: 12 - type: integer | |
| Parameter C_DATA_WIDTH bound to: 32 - type: integer | |
| Parameter P_WIDTH bound to: 13 - type: integer | |
| Parameter P_DEPTH bound to: 32 - type: integer | |
| Parameter P_AWIDTH bound to: 5 - type: integer | |
| Parameter P_D_WIDTH bound to: 34 - type: integer | |
| Parameter P_D_DEPTH bound to: 32 - type: integer | |
| Parameter P_D_AWIDTH bound to: 5 - type: integer | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_b2s_simple_fifo__parameterized1' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9] | |
| Parameter C_WIDTH bound to: 34 - type: integer | |
| Parameter C_AWIDTH bound to: 5 - type: integer | |
| Parameter C_DEPTH bound to: 32 - type: integer | |
| Parameter C_EMPTY bound to: 5'b11111 | |
| Parameter C_EMPTY_PRE bound to: 5'b00000 | |
| Parameter C_FULL bound to: 5'b11110 | |
| Parameter C_FULL_PRE bound to: 5'b11010 | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_b2s_simple_fifo__parameterized1' (12#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9] | |
| INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_8_b2s_simple_fifo__parameterized2' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9] | |
| Parameter C_WIDTH bound to: 13 - type: integer | |
| Parameter C_AWIDTH bound to: 5 - type: integer | |
| Parameter C_DEPTH bound to: 32 - type: integer | |
| Parameter C_EMPTY bound to: 5'b11111 | |
| Parameter C_EMPTY_PRE bound to: 5'b00000 | |
| Parameter C_FULL bound to: 5'b11110 | |
| Parameter C_FULL_PRE bound to: 5'b11010 | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_b2s_simple_fifo__parameterized2' (12#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v:9] | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_b2s_r_channel' (13#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_r_channel.v:21] | |
| INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_8_axi_register_slice' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axi_register_slice.v:64] | |
| Parameter C_FAMILY bound to: virtex6 - type: string | |
| Parameter C_AXI_PROTOCOL bound to: 1 - type: integer | |
| Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer | |
| Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer | |
| Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_REG_CONFIG_AW bound to: 1 - type: integer | |
| Parameter C_REG_CONFIG_W bound to: 0 - type: integer | |
| Parameter C_REG_CONFIG_B bound to: 1 - type: integer | |
| Parameter C_REG_CONFIG_AR bound to: 1 - type: integer | |
| Parameter C_REG_CONFIG_R bound to: 1 - type: integer | |
| Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer | |
| Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer | |
| Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer | |
| Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer | |
| Parameter G_AXI_AWLEN_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_AWLOCK_INDEX bound to: 48 - type: integer | |
| Parameter G_AXI_AWLOCK_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_AWID_INDEX bound to: 50 - type: integer | |
| Parameter G_AXI_AWID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_AWQOS_INDEX bound to: 62 - type: integer | |
| Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_AWREGION_INDEX bound to: 66 - type: integer | |
| Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWUSER_INDEX bound to: 66 - type: integer | |
| Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 66 - type: integer | |
| Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer | |
| Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer | |
| Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer | |
| Parameter G_AXI_ARLEN_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_ARLOCK_INDEX bound to: 48 - type: integer | |
| Parameter G_AXI_ARLOCK_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_ARID_INDEX bound to: 50 - type: integer | |
| Parameter G_AXI_ARID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_ARQOS_INDEX bound to: 62 - type: integer | |
| Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_ARREGION_INDEX bound to: 66 - type: integer | |
| Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARUSER_INDEX bound to: 66 - type: integer | |
| Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 66 - type: integer | |
| Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer | |
| Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer | |
| Parameter G_AXI_WID_INDEX bound to: 37 - type: integer | |
| Parameter G_AXI_WID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_WUSER_INDEX bound to: 49 - type: integer | |
| Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_WPAYLOAD_WIDTH bound to: 49 - type: integer | |
| Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_BID_INDEX bound to: 2 - type: integer | |
| Parameter G_AXI_BID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_BUSER_INDEX bound to: 14 - type: integer | |
| Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_BPAYLOAD_WIDTH bound to: 14 - type: integer | |
| Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer | |
| Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer | |
| Parameter G_AXI_RID_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_RID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_RUSER_INDEX bound to: 47 - type: integer | |
| Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_RPAYLOAD_WIDTH bound to: 47 - type: integer | |
| INFO: [Synth 8-638] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_axi2vector.v:60] | |
| Parameter C_AXI_PROTOCOL bound to: 1 - type: integer | |
| Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer | |
| Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer | |
| Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer | |
| Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AWPAYLOAD_WIDTH bound to: 66 - type: integer | |
| Parameter C_WPAYLOAD_WIDTH bound to: 49 - type: integer | |
| Parameter C_BPAYLOAD_WIDTH bound to: 14 - type: integer | |
| Parameter C_ARPAYLOAD_WIDTH bound to: 66 - type: integer | |
| Parameter C_RPAYLOAD_WIDTH bound to: 47 - type: integer | |
| Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer | |
| Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer | |
| Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer | |
| Parameter G_AXI_AWLEN_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_AWLOCK_INDEX bound to: 48 - type: integer | |
| Parameter G_AXI_AWLOCK_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_AWID_INDEX bound to: 50 - type: integer | |
| Parameter G_AXI_AWID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_AWQOS_INDEX bound to: 62 - type: integer | |
| Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_AWREGION_INDEX bound to: 66 - type: integer | |
| Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWUSER_INDEX bound to: 66 - type: integer | |
| Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 66 - type: integer | |
| Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer | |
| Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer | |
| Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer | |
| Parameter G_AXI_ARLEN_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_ARLOCK_INDEX bound to: 48 - type: integer | |
| Parameter G_AXI_ARLOCK_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_ARID_INDEX bound to: 50 - type: integer | |
| Parameter G_AXI_ARID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_ARQOS_INDEX bound to: 62 - type: integer | |
| Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_ARREGION_INDEX bound to: 66 - type: integer | |
| Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARUSER_INDEX bound to: 66 - type: integer | |
| Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 66 - type: integer | |
| Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer | |
| Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer | |
| Parameter G_AXI_WID_INDEX bound to: 37 - type: integer | |
| Parameter G_AXI_WID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_WUSER_INDEX bound to: 49 - type: integer | |
| Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_WPAYLOAD_WIDTH bound to: 49 - type: integer | |
| Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_BID_INDEX bound to: 2 - type: integer | |
| Parameter G_AXI_BID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_BUSER_INDEX bound to: 14 - type: integer | |
| Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_BPAYLOAD_WIDTH bound to: 14 - type: integer | |
| Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer | |
| Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer | |
| Parameter G_AXI_RID_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_RID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_RUSER_INDEX bound to: 47 - type: integer | |
| Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_RPAYLOAD_WIDTH bound to: 47 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (14#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_axi2vector.v:60] | |
| INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| Parameter C_FAMILY bound to: virtex6 - type: string | |
| Parameter C_DATA_WIDTH bound to: 66 - type: integer | |
| Parameter C_REG_CONFIG bound to: 1 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice' (15#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized0' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| Parameter C_FAMILY bound to: virtex6 - type: string | |
| Parameter C_DATA_WIDTH bound to: 49 - type: integer | |
| Parameter C_REG_CONFIG bound to: 0 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized0' (15#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized1' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| Parameter C_FAMILY bound to: virtex6 - type: string | |
| Parameter C_DATA_WIDTH bound to: 14 - type: integer | |
| Parameter C_REG_CONFIG bound to: 1 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized1' (15#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized2' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| Parameter C_FAMILY bound to: virtex6 - type: string | |
| Parameter C_DATA_WIDTH bound to: 47 - type: integer | |
| Parameter C_REG_CONFIG bound to: 1 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized2' (15#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| INFO: [Synth 8-638] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_vector2axi.v:60] | |
| Parameter C_AXI_PROTOCOL bound to: 1 - type: integer | |
| Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer | |
| Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer | |
| Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer | |
| Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AWPAYLOAD_WIDTH bound to: 66 - type: integer | |
| Parameter C_WPAYLOAD_WIDTH bound to: 49 - type: integer | |
| Parameter C_BPAYLOAD_WIDTH bound to: 14 - type: integer | |
| Parameter C_ARPAYLOAD_WIDTH bound to: 66 - type: integer | |
| Parameter C_RPAYLOAD_WIDTH bound to: 47 - type: integer | |
| Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer | |
| Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer | |
| Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer | |
| Parameter G_AXI_AWLEN_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_AWLOCK_INDEX bound to: 48 - type: integer | |
| Parameter G_AXI_AWLOCK_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_AWID_INDEX bound to: 50 - type: integer | |
| Parameter G_AXI_AWID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_AWQOS_INDEX bound to: 62 - type: integer | |
| Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_AWREGION_INDEX bound to: 66 - type: integer | |
| Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWUSER_INDEX bound to: 66 - type: integer | |
| Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 66 - type: integer | |
| Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer | |
| Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer | |
| Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer | |
| Parameter G_AXI_ARLEN_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_ARLOCK_INDEX bound to: 48 - type: integer | |
| Parameter G_AXI_ARLOCK_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_ARID_INDEX bound to: 50 - type: integer | |
| Parameter G_AXI_ARID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_ARQOS_INDEX bound to: 62 - type: integer | |
| Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_ARREGION_INDEX bound to: 66 - type: integer | |
| Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARUSER_INDEX bound to: 66 - type: integer | |
| Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 66 - type: integer | |
| Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer | |
| Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer | |
| Parameter G_AXI_WID_INDEX bound to: 37 - type: integer | |
| Parameter G_AXI_WID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_WUSER_INDEX bound to: 49 - type: integer | |
| Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_WPAYLOAD_WIDTH bound to: 49 - type: integer | |
| Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_BID_INDEX bound to: 2 - type: integer | |
| Parameter G_AXI_BID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_BUSER_INDEX bound to: 14 - type: integer | |
| Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_BPAYLOAD_WIDTH bound to: 14 - type: integer | |
| Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer | |
| Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer | |
| Parameter G_AXI_RID_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_RID_WIDTH bound to: 12 - type: integer | |
| Parameter G_AXI_RUSER_INDEX bound to: 47 - type: integer | |
| Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_RPAYLOAD_WIDTH bound to: 47 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (16#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_vector2axi.v:60] | |
| INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_8_axi_register_slice' (17#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axi_register_slice.v:64] | |
| INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_8_axi_register_slice__parameterized0' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axi_register_slice.v:64] | |
| Parameter C_FAMILY bound to: virtex6 - type: string | |
| Parameter C_AXI_PROTOCOL bound to: 2 - type: integer | |
| Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer | |
| Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_REG_CONFIG_AW bound to: 0 - type: integer | |
| Parameter C_REG_CONFIG_W bound to: 0 - type: integer | |
| Parameter C_REG_CONFIG_B bound to: 0 - type: integer | |
| Parameter C_REG_CONFIG_AR bound to: 0 - type: integer | |
| Parameter C_REG_CONFIG_R bound to: 0 - type: integer | |
| Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer | |
| Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer | |
| Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer | |
| Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer | |
| Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_WID_INDEX bound to: 36 - type: integer | |
| Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer | |
| Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer | |
| Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_BID_INDEX bound to: 2 - type: integer | |
| Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer | |
| Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer | |
| Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_RID_INDEX bound to: 34 - type: integer | |
| Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer | |
| Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer | |
| INFO: [Synth 8-638] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_axi2vector.v:60] | |
| Parameter C_AXI_PROTOCOL bound to: 2 - type: integer | |
| Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer | |
| Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer | |
| Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AWPAYLOAD_WIDTH bound to: 35 - type: integer | |
| Parameter C_WPAYLOAD_WIDTH bound to: 36 - type: integer | |
| Parameter C_BPAYLOAD_WIDTH bound to: 2 - type: integer | |
| Parameter C_ARPAYLOAD_WIDTH bound to: 35 - type: integer | |
| Parameter C_RPAYLOAD_WIDTH bound to: 34 - type: integer | |
| Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer | |
| Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer | |
| Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer | |
| Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_WID_INDEX bound to: 36 - type: integer | |
| Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer | |
| Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer | |
| Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_BID_INDEX bound to: 2 - type: integer | |
| Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer | |
| Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer | |
| Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_RID_INDEX bound to: 34 - type: integer | |
| Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer | |
| Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (17#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_axi2vector.v:60] | |
| INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized3' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| Parameter C_FAMILY bound to: virtex6 - type: string | |
| Parameter C_DATA_WIDTH bound to: 35 - type: integer | |
| Parameter C_REG_CONFIG bound to: 0 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized3' (17#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized4' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| Parameter C_FAMILY bound to: virtex6 - type: string | |
| Parameter C_DATA_WIDTH bound to: 36 - type: integer | |
| Parameter C_REG_CONFIG bound to: 0 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized4' (17#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized5' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| Parameter C_FAMILY bound to: virtex6 - type: string | |
| Parameter C_DATA_WIDTH bound to: 2 - type: integer | |
| Parameter C_REG_CONFIG bound to: 0 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized5' (17#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized6' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| Parameter C_FAMILY bound to: virtex6 - type: string | |
| Parameter C_DATA_WIDTH bound to: 35 - type: integer | |
| Parameter C_REG_CONFIG bound to: 0 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized6' (17#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| INFO: [Synth 8-638] synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized7' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| Parameter C_FAMILY bound to: virtex6 - type: string | |
| Parameter C_DATA_WIDTH bound to: 34 - type: integer | |
| Parameter C_REG_CONFIG bound to: 0 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_8_axic_register_slice__parameterized7' (17#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:62] | |
| INFO: [Synth 8-638] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_vector2axi.v:60] | |
| Parameter C_AXI_PROTOCOL bound to: 2 - type: integer | |
| Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer | |
| Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer | |
| Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer | |
| Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer | |
| Parameter C_AWPAYLOAD_WIDTH bound to: 35 - type: integer | |
| Parameter C_WPAYLOAD_WIDTH bound to: 36 - type: integer | |
| Parameter C_BPAYLOAD_WIDTH bound to: 2 - type: integer | |
| Parameter C_ARPAYLOAD_WIDTH bound to: 35 - type: integer | |
| Parameter C_RPAYLOAD_WIDTH bound to: 34 - type: integer | |
| Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer | |
| Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer | |
| Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer | |
| Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer | |
| Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer | |
| Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer | |
| Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_WID_INDEX bound to: 36 - type: integer | |
| Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer | |
| Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer | |
| Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_BID_INDEX bound to: 2 - type: integer | |
| Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer | |
| Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer | |
| Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer | |
| Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer | |
| Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer | |
| Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer | |
| Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_RID_INDEX bound to: 34 - type: integer | |
| Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer | |
| Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer | |
| Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (17#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_vector2axi.v:60] | |
| INFO: [Synth 8-256] done synthesizing module 'axi_register_slice_v2_1_8_axi_register_slice__parameterized0' (17#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axi_register_slice.v:64] | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_b2s' (18#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v:39] | |
| INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_8_axi_protocol_converter' (19#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v:62] | |
| INFO: [Synth 8-256] done synthesizing module 'system_axi_protocol_converter_0_0' (20#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_axi_protocol_converter_0_0/synth/system_axi_protocol_converter_0_0.v:58] | |
| WARNING: [Synth 8-350] instance 'axi_protocol_converter_0' of module 'system_axi_protocol_converter_0_0' requires 59 connections, but only 57 given [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/hdl/system.v:678] | |
| INFO: [Synth 8-638] synthesizing module 'system_proc_sys_reset_0' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_proc_sys_reset_0/synth/system_proc_sys_reset_0.vhd:71] | |
| Parameter C_FAMILY bound to: zynq - type: string | |
| Parameter C_EXT_RST_WIDTH bound to: 1 - type: integer | |
| Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer | |
| Parameter C_EXT_RESET_HIGH bound to: 1'b0 | |
| Parameter C_AUX_RESET_HIGH bound to: 1'b0 | |
| Parameter C_NUM_BUS_RST bound to: 1 - type: integer | |
| Parameter C_NUM_PERP_RST bound to: 1 - type: integer | |
| Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer | |
| Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer | |
| INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd:140' bound to instance 'U0' of component 'proc_sys_reset' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_proc_sys_reset_0/synth/system_proc_sys_reset_0.vhd:116] | |
| INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd:199] | |
| Parameter C_FAMILY bound to: zynq - type: string | |
| Parameter C_EXT_RST_WIDTH bound to: 1 - type: integer | |
| Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer | |
| Parameter C_EXT_RESET_HIGH bound to: 1'b0 | |
| Parameter C_AUX_RESET_HIGH bound to: 1'b0 | |
| Parameter C_NUM_BUS_RST bound to: 1 - type: integer | |
| Parameter C_NUM_PERP_RST bound to: 1 - type: integer | |
| Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer | |
| Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer | |
| INFO: [Synth 8-638] synthesizing module 'lpf' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd:138] | |
| Parameter C_EXT_RST_WIDTH bound to: 1 - type: integer | |
| Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer | |
| Parameter C_EXT_RESET_HIGH bound to: 1'b0 | |
| Parameter C_AUX_RESET_HIGH bound to: 1'b0 | |
| INFO: [Synth 8-3491] module 'SRL16' declared at '/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:43294' bound to instance 'POR_SRL_I' of component 'SRL16' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd:190] | |
| INFO: [Synth 8-638] synthesizing module 'SRL16' [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:43294] | |
| Parameter INIT bound to: 16'b0000000000000000 | |
| INFO: [Synth 8-256] done synthesizing module 'SRL16' (21#1) [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:43294] | |
| INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:106] | |
| Parameter C_CDC_TYPE bound to: 1 - type: integer | |
| Parameter C_RESET_STATE bound to: 0 - type: integer | |
| Parameter C_SINGLE_BIT bound to: 1 - type: integer | |
| Parameter C_FLOP_INPUT bound to: 0 - type: integer | |
| Parameter C_VECTOR_WIDTH bound to: 2 - type: integer | |
| Parameter C_MTBF_STAGES bound to: 4 - type: integer | |
| Parameter INIT bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:514] | |
| Parameter INIT bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:545] | |
| Parameter INIT bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:554] | |
| Parameter INIT bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:564] | |
| Parameter INIT bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:574] | |
| Parameter INIT bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:584] | |
| INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (22#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:106] | |
| INFO: [Synth 8-256] done synthesizing module 'lpf' (23#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd:138] | |
| INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/sequence_psr.vhd:146] | |
| INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd:125] | |
| Parameter C_SIZE bound to: 6 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (24#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd:125] | |
| INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (25#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/sequence_psr.vhd:146] | |
| INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (26#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd:199] | |
| INFO: [Synth 8-256] done synthesizing module 'system_proc_sys_reset_0' (27#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_proc_sys_reset_0/synth/system_proc_sys_reset_0.vhd:71] | |
| WARNING: [Synth 8-350] instance 'proc_sys_reset' of module 'system_proc_sys_reset_0' requires 10 connections, but only 7 given [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/hdl/system.v:736] | |
| INFO: [Synth 8-638] synthesizing module 'system_processing_system7_0' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_processing_system7_0/synth/system_processing_system7_0.v:59] | |
| INFO: [Synth 8-638] synthesizing module 'processing_system7_v5_5_processing_system7' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_processing_system7_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:156] | |
| Parameter C_USE_DEFAULT_ACP_USER_VAL bound to: 0 - type: integer | |
| Parameter C_S_AXI_ACP_ARUSER_VAL bound to: 31 - type: integer | |
| Parameter C_S_AXI_ACP_AWUSER_VAL bound to: 31 - type: integer | |
| Parameter C_M_AXI_GP0_THREAD_ID_WIDTH bound to: 12 - type: integer | |
| Parameter C_M_AXI_GP1_THREAD_ID_WIDTH bound to: 12 - type: integer | |
| Parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP bound to: 0 - type: integer | |
| Parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP bound to: 0 - type: integer | |
| Parameter C_M_AXI_GP0_ID_WIDTH bound to: 12 - type: integer | |
| Parameter C_M_AXI_GP1_ID_WIDTH bound to: 12 - type: integer | |
| Parameter C_S_AXI_GP0_ID_WIDTH bound to: 6 - type: integer | |
| Parameter C_S_AXI_GP1_ID_WIDTH bound to: 6 - type: integer | |
| Parameter C_S_AXI_HP0_ID_WIDTH bound to: 6 - type: integer | |
| Parameter C_S_AXI_HP1_ID_WIDTH bound to: 6 - type: integer | |
| Parameter C_S_AXI_HP2_ID_WIDTH bound to: 6 - type: integer | |
| Parameter C_S_AXI_HP3_ID_WIDTH bound to: 6 - type: integer | |
| Parameter C_S_AXI_ACP_ID_WIDTH bound to: 3 - type: integer | |
| Parameter C_S_AXI_HP0_DATA_WIDTH bound to: 64 - type: integer | |
| Parameter C_S_AXI_HP1_DATA_WIDTH bound to: 64 - type: integer | |
| Parameter C_S_AXI_HP2_DATA_WIDTH bound to: 64 - type: integer | |
| Parameter C_S_AXI_HP3_DATA_WIDTH bound to: 64 - type: integer | |
| Parameter C_INCLUDE_ACP_TRANS_CHECK bound to: 0 - type: integer | |
| Parameter C_NUM_F2P_INTR_INPUTS bound to: 1 - type: integer | |
| Parameter C_FCLK_CLK0_BUF bound to: true - type: string | |
| Parameter C_FCLK_CLK1_BUF bound to: true - type: string | |
| Parameter C_FCLK_CLK2_BUF bound to: true - type: string | |
| Parameter C_FCLK_CLK3_BUF bound to: true - type: string | |
| Parameter C_EMIO_GPIO_WIDTH bound to: 64 - type: integer | |
| Parameter C_INCLUDE_TRACE_BUFFER bound to: 0 - type: integer | |
| Parameter C_TRACE_BUFFER_FIFO_SIZE bound to: 128 - type: integer | |
| Parameter C_TRACE_BUFFER_CLOCK_DELAY bound to: 12 - type: integer | |
| Parameter USE_TRACE_DATA_EDGE_DETECTOR bound to: 0 - type: integer | |
| Parameter C_TRACE_PIPELINE_WIDTH bound to: 8 - type: integer | |
| Parameter C_PS7_SI_REV bound to: PRODUCTION - type: string | |
| Parameter C_EN_EMIO_ENET0 bound to: 0 - type: integer | |
| Parameter C_EN_EMIO_ENET1 bound to: 0 - type: integer | |
| Parameter C_EN_EMIO_TRACE bound to: 0 - type: integer | |
| Parameter C_DQ_WIDTH bound to: 32 - type: integer | |
| Parameter C_DQS_WIDTH bound to: 4 - type: integer | |
| Parameter C_DM_WIDTH bound to: 4 - type: integer | |
| Parameter C_MIO_PRIMITIVE bound to: 54 - type: integer | |
| Parameter C_PACKAGE_NAME bound to: clg400 - type: string | |
| Parameter C_IRQ_F2P_MODE bound to: DIRECT - type: string | |
| Parameter C_TRACE_INTERNAL_WIDTH bound to: 2 - type: integer | |
| Parameter C_EN_EMIO_PJTAG bound to: 0 - type: integer | |
| Parameter C_USE_AXI_NONSECURE bound to: 0 - type: integer | |
| Parameter C_USE_S_AXI_HP0 bound to: 1 - type: integer | |
| Parameter C_USE_S_AXI_HP1 bound to: 1 - type: integer | |
| Parameter C_USE_S_AXI_HP2 bound to: 0 - type: integer | |
| Parameter C_USE_S_AXI_HP3 bound to: 0 - type: integer | |
| Parameter C_USE_M_AXI_GP0 bound to: 1 - type: integer | |
| Parameter C_USE_M_AXI_GP1 bound to: 1 - type: integer | |
| Parameter C_USE_S_AXI_GP0 bound to: 0 - type: integer | |
| Parameter C_USE_S_AXI_GP1 bound to: 0 - type: integer | |
| Parameter C_USE_S_AXI_ACP bound to: 0 - type: integer | |
| INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_processing_system7_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:1338] | |
| INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_processing_system7_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:1339] | |
| INFO: [Synth 8-638] synthesizing module 'BIBUF' [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:268] | |
| INFO: [Synth 8-256] done synthesizing module 'BIBUF' (28#1) [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:268] | |
| INFO: [Synth 8-638] synthesizing module 'PS7' [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:33164] | |
| INFO: [Synth 8-256] done synthesizing module 'PS7' (29#1) [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:33164] | |
| INFO: [Synth 8-256] done synthesizing module 'processing_system7_v5_5_processing_system7' (30#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_processing_system7_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:156] | |
| WARNING: [Synth 8-350] instance 'inst' of module 'processing_system7_v5_5_processing_system7' requires 685 connections, but only 672 given [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_processing_system7_0/synth/system_processing_system7_0.v:726] | |
| INFO: [Synth 8-256] done synthesizing module 'system_processing_system7_0' (31#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_processing_system7_0/synth/system_processing_system7_0.v:59] | |
| WARNING: [Synth 8-350] instance 'processing_system7' of module 'system_processing_system7_0' requires 204 connections, but only 191 given [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/hdl/system.v:744] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/system_xadc_0.v:52] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_axi_xadc' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/system_xadc_0_axi_xadc.vhd:245] | |
| Parameter C_INSTANCE bound to: system_xadc_0_axi_xadc - type: string | |
| Parameter C_FAMILY bound to: virtex7 - type: string | |
| Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer | |
| Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer | |
| Parameter C_INCLUDE_INTR bound to: 1 - type: integer | |
| Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string | |
| INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/system_xadc_0_axi_xadc.vhd:162] | |
| INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/system_xadc_0_axi_xadc.vhd:163] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_axi_lite_ipif' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_axi_lite_ipif.vhd:241] | |
| Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer | |
| Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer | |
| Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000001111111111 | |
| Parameter C_USE_WSTRB bound to: 1 - type: integer | |
| Parameter C_DPHASE_TIMEOUT bound to: 64 - type: integer | |
| Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001111111111 | |
| Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000001 | |
| Parameter C_FAMILY bound to: virtex7 - type: string | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_slave_attachment' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_slave_attachment.vhd:227] | |
| Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001111111111 | |
| Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000001 | |
| Parameter C_IPIF_ABUS_WIDTH bound to: 11 - type: integer | |
| Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer | |
| Parameter C_S_AXI_MIN_SIZE bound to: 1023 - type: integer | |
| Parameter C_USE_WSTRB bound to: 1 - type: integer | |
| Parameter C_DPHASE_TIMEOUT bound to: 64 - type: integer | |
| Parameter C_FAMILY bound to: virtex7 - type: string | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_address_decoder' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:176] | |
| Parameter C_BUS_AWIDTH bound to: 10 - type: integer | |
| Parameter C_S_AXI_MIN_SIZE bound to: 1023 - type: integer | |
| Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001111111111 | |
| Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000001 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 5 - type: integer | |
| Parameter C_AW bound to: 10 - type: integer | |
| Parameter C_BAR bound to: 10'b0000000000 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized0' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 3 - type: integer | |
| Parameter C_AW bound to: 3 - type: integer | |
| Parameter C_BAR bound to: 3'b000 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized0' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized1' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 3 - type: integer | |
| Parameter C_AW bound to: 3 - type: integer | |
| Parameter C_BAR bound to: 3'b001 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized1' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized2' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 3 - type: integer | |
| Parameter C_AW bound to: 3 - type: integer | |
| Parameter C_BAR bound to: 3'b010 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized2' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized3' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 3 - type: integer | |
| Parameter C_AW bound to: 3 - type: integer | |
| Parameter C_BAR bound to: 3'b011 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized3' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized4' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 3 - type: integer | |
| Parameter C_AW bound to: 3 - type: integer | |
| Parameter C_BAR bound to: 3'b100 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized4' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized5' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 3 - type: integer | |
| Parameter C_AW bound to: 3 - type: integer | |
| Parameter C_BAR bound to: 3'b101 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized5' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized6' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 3 - type: integer | |
| Parameter C_AW bound to: 3 - type: integer | |
| Parameter C_BAR bound to: 3'b110 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized6' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized7' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 3 - type: integer | |
| Parameter C_AW bound to: 3 - type: integer | |
| Parameter C_BAR bound to: 3'b111 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized7' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized8' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 10 - type: integer | |
| Parameter C_BAR bound to: 10'b0001000000 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized8' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized9' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b0000 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized9' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized10' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b0001 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized10' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized11' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b0010 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized11' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized12' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b0011 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized12' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized13' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b0100 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized13' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized14' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b0101 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized14' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized15' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b0110 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized15' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized16' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b0111 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized16' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized17' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b1000 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized17' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized18' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b1001 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized18' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized19' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b1010 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized19' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized20' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b1011 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized20' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized21' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b1100 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized21' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized22' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b1101 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized22' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized23' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b1110 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized23' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:419] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized24' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 4 - type: integer | |
| Parameter C_AW bound to: 4 - type: integer | |
| Parameter C_BAR bound to: 4'b1111 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized24' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_pselect_f__parameterized25' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| Parameter C_AB bound to: 1 - type: integer | |
| Parameter C_AW bound to: 10 - type: integer | |
| Parameter C_BAR bound to: 10'b1000000000 | |
| Parameter C_FAMILY bound to: nofamily - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_pselect_f__parameterized25' (32#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_pselect_f.vhd:167] | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_address_decoder' (33#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_address_decoder.vhd:176] | |
| INFO: [Synth 8-226] default block is never used [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_slave_attachment.vhd:381] | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_slave_attachment' (34#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_slave_attachment.vhd:227] | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_axi_lite_ipif' (35#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_0_axi_lite_ipif.vhd:241] | |
| Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer | |
| Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer | |
| Parameter C_FAMILY bound to: virtex7 - type: string | |
| Parameter CE_NUMBERS bound to: 9 - type: integer | |
| Parameter IP_INTR_NUM bound to: 17 - type: integer | |
| Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string | |
| Parameter MUX_ADDR_NO bound to: 5 - type: integer | |
| INFO: [Synth 8-3491] module 'system_xadc_0_xadc_core_drp' declared at '/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/system_xadc_0_xadc_core_drp.vhd:140' bound to instance 'AXI_XADC_CORE_I' of component 'system_xadc_0_xadc_core_drp' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/system_xadc_0_axi_xadc.vhd:707] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_xadc_core_drp' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/system_xadc_0_xadc_core_drp.vhd:193] | |
| Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer | |
| Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer | |
| Parameter C_FAMILY bound to: virtex7 - type: string | |
| Parameter CE_NUMBERS bound to: 9 - type: integer | |
| Parameter IP_INTR_NUM bound to: 17 - type: integer | |
| Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string | |
| Parameter MUX_ADDR_NO bound to: 5 - type: integer | |
| Parameter INIT_40 bound to: 16'b0000000000000000 | |
| Parameter INIT_41 bound to: 16'b1000000100000000 | |
| Parameter INIT_42 bound to: 16'b0000010000000000 | |
| Parameter INIT_43 bound to: 16'b0000000000000000 | |
| Parameter INIT_44 bound to: 16'b0000000000000000 | |
| Parameter INIT_45 bound to: 16'b0000000000000000 | |
| Parameter INIT_46 bound to: 16'b0000000000000000 | |
| Parameter INIT_47 bound to: 16'b0000000000000000 | |
| Parameter INIT_48 bound to: 16'b0000100000000000 | |
| Parameter INIT_49 bound to: 16'b0000001100000011 | |
| Parameter INIT_4A bound to: 16'b0000000000000000 | |
| Parameter INIT_4B bound to: 16'b0000000000000000 | |
| Parameter INIT_4C bound to: 16'b0000000000000000 | |
| Parameter INIT_4D bound to: 16'b0000000000000000 | |
| Parameter INIT_4E bound to: 16'b0000000000000000 | |
| Parameter INIT_4F bound to: 16'b0000000000000000 | |
| Parameter INIT_50 bound to: 16'b1011010111101101 | |
| Parameter INIT_51 bound to: 16'b0101011111100100 | |
| Parameter INIT_52 bound to: 16'b1010000101000111 | |
| Parameter INIT_53 bound to: 16'b1100101000110011 | |
| Parameter INIT_54 bound to: 16'b1010100100111010 | |
| Parameter INIT_55 bound to: 16'b0101001011000110 | |
| Parameter INIT_56 bound to: 16'b1001010101010101 | |
| Parameter INIT_57 bound to: 16'b1010111001001110 | |
| Parameter INIT_58 bound to: 16'b0101100110011001 | |
| Parameter INIT_59 bound to: 16'b0101010101010101 | |
| Parameter INIT_5A bound to: 16'b1001100110011001 | |
| Parameter INIT_5B bound to: 16'b0110101010101010 | |
| Parameter INIT_5C bound to: 16'b0101000100010001 | |
| Parameter INIT_5D bound to: 16'b0101000100010001 | |
| Parameter INIT_5E bound to: 16'b1001000111101011 | |
| Parameter INIT_5F bound to: 16'b0110011001100110 | |
| Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 | |
| Parameter IS_DCLK_INVERTED bound to: 1'b0 | |
| Parameter SIM_DEVICE bound to: ZYNQ - type: string | |
| Parameter SIM_MONITOR_FILE bound to: design.txt - type: string | |
| INFO: [Synth 8-113] binding component instance 'XADC_INST' to cell 'XADC' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/system_xadc_0_xadc_core_drp.vhd:976] | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_xadc_core_drp' (36#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/system_xadc_0_xadc_core_drp.vhd:193] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_soft_reset' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:142] | |
| Parameter C_SIPIF_DWIDTH bound to: 32 - type: integer | |
| Parameter C_RESET_WIDTH bound to: 16 - type: integer | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:273] | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_CE_INVERTED bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D_INVERTED bound to: 1'b0 | |
| Parameter IS_R_INVERTED bound to: 1'b0 | |
| Parameter IS_S_INVERTED bound to: 1'b0 | |
| INFO: [Synth 8-113] binding component instance 'FF_WRACK' to cell 'FDRSE' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:296] | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_soft_reset' (37#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_0_soft_reset.vhd:142] | |
| INFO: [Synth 8-638] synthesizing module 'system_xadc_0_interrupt_control' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:240] | |
| Parameter C_NUM_CE bound to: 16 - type: integer | |
| Parameter C_NUM_IPIF_IRPT_SRC bound to: 1 - type: integer | |
| Parameter C_IP_INTR_MODE_ARRAY bound to: 544'b0000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101 | |
| Parameter C_INCLUDE_DEV_PENCODER bound to: 0 - type: bool | |
| Parameter C_INCLUDE_DEV_ISC bound to: 0 - type: bool | |
| Parameter C_IPIF_DWIDTH bound to: 32 - type: integer | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| WARNING: [Synth 8-5827] expecting unsigned expression [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:310] | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_interrupt_control' (38#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:240] | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0_axi_xadc' (39#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/system_xadc_0_axi_xadc.vhd:245] | |
| INFO: [Synth 8-256] done synthesizing module 'system_xadc_0' (40#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/system_xadc_0.v:52] | |
| WARNING: [Synth 8-350] instance 'xadc' of module 'system_xadc_0' requires 42 connections, but only 30 given [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/hdl/system.v:936] | |
| INFO: [Synth 8-638] synthesizing module 'system_xlconstant_0' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xlconstant_0/sim/system_xlconstant_0.v:56] | |
| INFO: [Synth 8-638] synthesizing module 'xlconstant' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/xlconstant_v1_1/xlconstant.v:23] | |
| Parameter CONST_VAL bound to: 1'b1 | |
| Parameter CONST_WIDTH bound to: 1 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'xlconstant' (41#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/xlconstant_v1_1/xlconstant.v:23] | |
| INFO: [Synth 8-256] done synthesizing module 'system_xlconstant_0' (42#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xlconstant_0/sim/system_xlconstant_0.v:56] | |
| INFO: [Synth 8-256] done synthesizing module 'system' (43#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/hdl/system.v:13] | |
| INFO: [Synth 8-256] done synthesizing module 'system_wrapper' (44#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/hdl/system_wrapper.v:12] | |
| INFO: [Synth 8-256] done synthesizing module 'red_pitaya_ps' (45#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_ps.v:43] | |
| INFO: [Synth 8-638] synthesizing module 'IBUFDS' [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:14160] | |
| Parameter CAPACITANCE bound to: DONT_CARE - type: string | |
| Parameter DIFF_TERM bound to: FALSE - type: string | |
| Parameter DQS_BIAS bound to: FALSE - type: string | |
| Parameter IBUF_DELAY_VALUE bound to: 0 - type: string | |
| Parameter IBUF_LOW_PWR bound to: TRUE - type: string | |
| Parameter IFD_DELAY_VALUE bound to: AUTO - type: string | |
| Parameter IOSTANDARD bound to: DEFAULT - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'IBUFDS' (46#1) [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:14160] | |
| INFO: [Synth 8-638] synthesizing module 'red_pitaya_pll' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pll.sv:13] | |
| INFO: [Synth 8-638] synthesizing module 'PLLE2_ADV' [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:32656] | |
| Parameter BANDWIDTH bound to: OPTIMIZED - type: string | |
| Parameter CLKFBOUT_MULT bound to: 8 - type: integer | |
| Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float | |
| Parameter CLKIN1_PERIOD bound to: 8.000000 - type: float | |
| Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float | |
| Parameter CLKOUT0_DIVIDE bound to: 8 - type: integer | |
| Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float | |
| Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float | |
| Parameter CLKOUT1_DIVIDE bound to: 8 - type: integer | |
| Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float | |
| Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float | |
| Parameter CLKOUT2_DIVIDE bound to: 4 - type: integer | |
| Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float | |
| Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float | |
| Parameter CLKOUT3_DIVIDE bound to: 4 - type: integer | |
| Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float | |
| Parameter CLKOUT3_PHASE bound to: -45.000000 - type: float | |
| Parameter CLKOUT4_DIVIDE bound to: 4 - type: integer | |
| Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float | |
| Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float | |
| Parameter CLKOUT5_DIVIDE bound to: 4 - type: integer | |
| Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float | |
| Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float | |
| Parameter COMPENSATION bound to: ZHOLD - type: string | |
| Parameter DIVCLK_DIVIDE bound to: 1 - type: integer | |
| Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 | |
| Parameter IS_PWRDWN_INVERTED bound to: 1'b0 | |
| Parameter IS_RST_INVERTED bound to: 1'b0 | |
| Parameter REF_JITTER1 bound to: 0.010000 - type: float | |
| Parameter REF_JITTER2 bound to: 0.010000 - type: float | |
| Parameter STARTUP_WAIT bound to: FALSE - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'PLLE2_ADV' (47#1) [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:32656] | |
| INFO: [Synth 8-256] done synthesizing module 'red_pitaya_pll' (48#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pll.sv:13] | |
| INFO: [Synth 8-638] synthesizing module 'ODDR' [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:25287] | |
| Parameter DDR_CLK_EDGE bound to: OPPOSITE_EDGE - type: string | |
| Parameter INIT bound to: 1'b0 | |
| Parameter IS_C_INVERTED bound to: 1'b0 | |
| Parameter IS_D1_INVERTED bound to: 1'b0 | |
| Parameter IS_D2_INVERTED bound to: 1'b0 | |
| Parameter SRTYPE bound to: SYNC - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'ODDR' (49#1) [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:25287] | |
| INFO: [Synth 8-638] synthesizing module 'red_pitaya_hk' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_hk.v:29] | |
| Parameter DWL bound to: 8 - type: integer | |
| Parameter DWE bound to: 8 - type: integer | |
| Parameter DNA bound to: 57'b010000010001101000101011001111000100110101011110011011110 | |
| INFO: [Synth 8-638] synthesizing module 'DNA_PORT' [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:3033] | |
| Parameter SIM_DNA_VALUE bound to: 57'b010000010001101000101011001111000100110101011110011011110 | |
| INFO: [Synth 8-256] done synthesizing module 'DNA_PORT' (50#1) [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:3033] | |
| INFO: [Synth 8-256] done synthesizing module 'red_pitaya_hk' (51#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_hk.v:29] | |
| INFO: [Synth 8-638] synthesizing module 'IOBUF' [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:17333] | |
| Parameter DRIVE bound to: 12 - type: integer | |
| Parameter IBUF_LOW_PWR bound to: TRUE - type: string | |
| Parameter IOSTANDARD bound to: DEFAULT - type: string | |
| Parameter SLEW bound to: SLOW - type: string | |
| INFO: [Synth 8-256] done synthesizing module 'IOBUF' (52#1) [/home/jurek/data/Xilinx/Vivado/2016.1/scripts/rt/data/unisim_comp.v:17333] | |
| INFO: [Synth 8-638] synthesizing module 'red_pitaya_scope' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_scope.v:50] | |
| Parameter RSZ bound to: 14 - type: integer | |
| INFO: [Synth 8-638] synthesizing module 'red_pitaya_dfilt1' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_dfilt1.v:22] | |
| INFO: [Synth 8-5534] Detected attribute (* use_dsp48 = "yes" *) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_dfilt1.v:85] | |
| INFO: [Synth 8-256] done synthesizing module 'red_pitaya_dfilt1' (53#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_dfilt1.v:22] | |
| INFO: [Synth 8-638] synthesizing module 'axi_wr_fifo' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_wr_fifo.v:13] | |
| Parameter DW bound to: 64 - type: integer | |
| Parameter AW bound to: 32 - type: integer | |
| Parameter FW bound to: 8 - type: integer | |
| Parameter SW bound to: 8 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'axi_wr_fifo' (54#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_wr_fifo.v:13] | |
| INFO: [Synth 8-4471] merging register 'adc_b_raddr_reg[13:0]' into 'adc_a_raddr_reg[13:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_scope.v:284] | |
| INFO: [Synth 8-256] done synthesizing module 'red_pitaya_scope' (55#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_scope.v:50] | |
| INFO: [Synth 8-638] synthesizing module 'red_pitaya_asg' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_asg.v:51] | |
| Parameter RSZ bound to: 14 - type: integer | |
| INFO: [Synth 8-638] synthesizing module 'red_pitaya_asg_ch' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_asg_ch.v:37] | |
| Parameter RSZ bound to: 14 - type: integer | |
| INFO: [Synth 8-4471] merging register 'dac_rp_reg[13:0]' into 'buf_rpnt_o_reg[13:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_asg_ch.v:92] | |
| INFO: [Synth 8-256] done synthesizing module 'red_pitaya_asg_ch' (56#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_asg_ch.v:37] | |
| INFO: [Synth 8-4471] merging register 'buf_b_addr_reg[13:0]' into 'buf_a_addr_reg[13:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_asg.v:111] | |
| INFO: [Synth 8-256] done synthesizing module 'red_pitaya_asg' (57#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_asg.v:51] | |
| INFO: [Synth 8-638] synthesizing module 'red_pitaya_pid' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid.v:52] | |
| Parameter PSR bound to: 12 - type: integer | |
| Parameter ISR bound to: 18 - type: integer | |
| Parameter DSR bound to: 10 - type: integer | |
| INFO: [Synth 8-638] synthesizing module 'red_pitaya_pid_block' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid_block.v:49] | |
| Parameter PSR bound to: 12 - type: integer | |
| Parameter ISR bound to: 18 - type: integer | |
| Parameter DSR bound to: 10 - type: integer | |
| INFO: [Synth 8-256] done synthesizing module 'red_pitaya_pid_block' (58#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid_block.v:49] | |
| INFO: [Synth 8-256] done synthesizing module 'red_pitaya_pid' (59#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid.v:52] | |
| INFO: [Synth 8-638] synthesizing module 'red_pitaya_ams' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_ams.v:41] | |
| INFO: [Synth 8-256] done synthesizing module 'red_pitaya_ams' (60#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_ams.v:41] | |
| INFO: [Synth 8-638] synthesizing module 'red_pitaya_pwm' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pwm.sv:13] | |
| Parameter CCW bound to: 32'b00000000000000000000000000011000 | |
| Parameter FULL bound to: 8'b10011100 | |
| INFO: [Synth 8-256] done synthesizing module 'red_pitaya_pwm' (61#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pwm.sv:13] | |
| INFO: [Synth 8-256] done synthesizing module 'red_pitaya_top' (62#1) [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_top.v:64] | |
| WARNING: [Synth 8-3917] design red_pitaya_top has port adc_clk_o[1] driven by constant 1 | |
| WARNING: [Synth 8-3917] design red_pitaya_top has port adc_clk_o[0] driven by constant 0 | |
| WARNING: [Synth 8-3917] design red_pitaya_top has port adc_cdcs_o driven by constant 1 | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_addr[31] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_addr[30] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_addr[29] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_addr[28] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_addr[27] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_addr[26] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_addr[25] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_addr[24] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_addr[23] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_addr[22] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_addr[21] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_addr[20] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_wdata[31] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_wdata[30] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_wdata[29] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_wdata[28] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_wdata[27] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_wdata[26] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_wdata[25] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_wdata[24] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_sel[3] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_sel[2] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_sel[1] | |
| WARNING: [Synth 8-3331] design red_pitaya_ams has unconnected port sys_sel[0] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_addr[31] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_addr[30] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_addr[29] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_addr[28] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_addr[27] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_addr[26] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_addr[25] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_addr[24] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_addr[23] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_addr[22] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_addr[21] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_addr[20] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[31] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[30] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[29] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[28] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[27] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[26] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[25] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[24] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[23] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[22] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[21] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[20] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[19] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[18] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[17] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[16] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[15] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_wdata[14] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_sel[3] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_sel[2] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_sel[1] | |
| WARNING: [Synth 8-3331] design red_pitaya_pid has unconnected port sys_sel[0] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg_ch has unconnected port set_once_i | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_addr[31] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_addr[30] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_addr[29] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_addr[28] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_addr[27] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_addr[26] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_addr[25] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_addr[24] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_addr[23] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_addr[22] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_addr[21] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_addr[20] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_sel[3] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_sel[2] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_sel[1] | |
| WARNING: [Synth 8-3331] design red_pitaya_asg has unconnected port sys_sel[0] | |
| WARNING: [Synth 8-3331] design axi_wr_fifo has unconnected port axi_werr_i | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_addr[31] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_addr[30] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_addr[29] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_addr[28] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_addr[27] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_addr[26] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_addr[25] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_addr[24] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_addr[23] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_addr[22] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_addr[21] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_addr[20] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_sel[3] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_sel[2] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_sel[1] | |
| WARNING: [Synth 8-3331] design red_pitaya_scope has unconnected port sys_sel[0] | |
| WARNING: [Synth 8-3331] design red_pitaya_hk has unconnected port sys_addr[31] | |
| WARNING: [Synth 8-3331] design red_pitaya_hk has unconnected port sys_addr[30] | |
| WARNING: [Synth 8-3331] design red_pitaya_hk has unconnected port sys_addr[29] | |
| WARNING: [Synth 8-3331] design red_pitaya_hk has unconnected port sys_addr[28] | |
| WARNING: [Synth 8-3331] design red_pitaya_hk has unconnected port sys_addr[27] | |
| WARNING: [Synth 8-3331] design red_pitaya_hk has unconnected port sys_addr[26] | |
| WARNING: [Synth 8-3331] design red_pitaya_hk has unconnected port sys_addr[25] | |
| WARNING: [Synth 8-3331] design red_pitaya_hk has unconnected port sys_addr[24] | |
| INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. | |
| --------------------------------------------------------------------------------- | |
| Finished RTL Elaboration : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 1228.844 ; gain = 338.023 ; free physical = 8763 ; free virtual = 29051 | |
| --------------------------------------------------------------------------------- | |
| Report Check Netlist: | |
| +------+------------------+-------+---------+-------+------------------+ | |
| | |Item |Errors |Warnings |Status |Description | | |
| +------+------------------+-------+---------+-------+------------------+ | |
| |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | | |
| +------+------------------+-------+---------+-------+------------------+ | |
| --------------------------------------------------------------------------------- | |
| Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 1228.844 ; gain = 338.023 ; free physical = 8762 ; free virtual = 29050 | |
| --------------------------------------------------------------------------------- | |
| INFO: [Netlist 29-17] Analyzing 67 Unisim elements for replacement | |
| INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds | |
| INFO: [Device 21-403] Loading part xc7z010clg400-1 | |
| INFO: [Project 1-570] Preparing netlist for logic optimization | |
| Processing XDC Constraints | |
| Initializing timing engine | |
| Parsing XDC File [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_proc_sys_reset_0/system_proc_sys_reset_0_board.xdc] for cell 'i_ps/system_i/system_i/proc_sys_reset/U0' | |
| Finished Parsing XDC File [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_proc_sys_reset_0/system_proc_sys_reset_0_board.xdc] for cell 'i_ps/system_i/system_i/proc_sys_reset/U0' | |
| Parsing XDC File [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_proc_sys_reset_0/system_proc_sys_reset_0.xdc] for cell 'i_ps/system_i/system_i/proc_sys_reset/U0' | |
| Finished Parsing XDC File [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_proc_sys_reset_0/system_proc_sys_reset_0.xdc] for cell 'i_ps/system_i/system_i/proc_sys_reset/U0' | |
| Parsing XDC File [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_processing_system7_0/system_processing_system7_0.xdc] for cell 'i_ps/system_i/system_i/processing_system7/inst' | |
| Finished Parsing XDC File [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_processing_system7_0/system_processing_system7_0.xdc] for cell 'i_ps/system_i/system_i/processing_system7/inst' | |
| INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_processing_system7_0/system_processing_system7_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/red_pitaya_top_propImpl.xdc]. | |
| Resolution: To avoid this warning, move constraints listed in [.Xil/red_pitaya_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. | |
| Parsing XDC File [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/system_xadc_0.xdc] for cell 'i_ps/system_i/system_i/xadc/inst' | |
| Finished Parsing XDC File [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/system_xadc_0.xdc] for cell 'i_ps/system_i/system_i/xadc/inst' | |
| Parsing XDC File [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc] | |
| INFO: [Timing 38-2] Deriving generated clocks [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:215] | |
| WARNING: [Vivado 12-627] No clocks matched 'dac_clk_out'. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:215] | |
| INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:215] | |
| CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_clocks dac_clk_out]'. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:215] | |
| Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. | |
| WARNING: [Vivado 12-627] No clocks matched 'ser_clk_out'. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:216] | |
| INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:216] | |
| CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_clocks ser_clk_out]'. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:216] | |
| Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. | |
| WARNING: [Vivado 12-627] No clocks matched 'dac_2clk_out'. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:217] | |
| INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:217] | |
| CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_clocks dac_2clk_out]'. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:217] | |
| Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. | |
| WARNING: [Vivado 12-627] No clocks matched 'par_clk'. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:219] | |
| INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:219] | |
| CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_clocks par_clk]'. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:219] | |
| Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. | |
| WARNING: [Vivado 12-627] No clocks matched 'dac_clk_out'. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:220] | |
| INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:220] | |
| WARNING: [Vivado 12-627] No clocks matched 'dac_2clk_out'. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:220] | |
| INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:220] | |
| CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_clocks dac_clk_out]'. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:220] | |
| Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. | |
| WARNING: [Vivado 12-627] No clocks matched 'dac_clk_out'. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:221] | |
| INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:221] | |
| WARNING: [Vivado 12-627] No clocks matched 'dac_2ph_out'. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:221] | |
| INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:221] | |
| CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_clocks dac_clk_out]'. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc:221] | |
| Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. | |
| Finished Parsing XDC File [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc] | |
| INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/red_pitaya_top_propImpl.xdc]. | |
| Resolution: To avoid this warning, move constraints listed in [.Xil/red_pitaya_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. | |
| Parsing XDC File [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.runs/synth_1/dont_touch.xdc] | |
| Finished Parsing XDC File [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.runs/synth_1/dont_touch.xdc] | |
| INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/red_pitaya_top_propImpl.xdc]. | |
| Resolution: To avoid this warning, move constraints listed in [.Xil/red_pitaya_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. | |
| Completed Processing XDC Constraints | |
| INFO: [Project 1-111] Unisim Transformation Summary: | |
| A total of 46 instances were transformed. | |
| FDR => FDRE: 12 instances | |
| FDRSE => FDRSE (FDRE, LUT4, VCC): 17 instances | |
| IOBUF => IOBUF (IBUF, OBUFT): 16 instances | |
| SRL16 => SRL16E: 1 instances | |
| Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1436.305 ; gain = 0.000 ; free physical = 8643 ; free virtual = 28952 | |
| --------------------------------------------------------------------------------- | |
| Finished Constraint Validation : Time (s): cpu = 00:00:51 ; elapsed = 00:00:53 . Memory (MB): peak = 1436.309 ; gain = 545.488 ; free physical = 8641 ; free virtual = 28950 | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Loading Part and Timing Information | |
| --------------------------------------------------------------------------------- | |
| Loading part: xc7z010clg400-1 | |
| --------------------------------------------------------------------------------- | |
| Finished Loading Part and Timing Information : Time (s): cpu = 00:00:51 ; elapsed = 00:00:53 . Memory (MB): peak = 1436.309 ; gain = 545.488 ; free physical = 8641 ; free virtual = 28950 | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Applying 'set_property' XDC Constraints | |
| --------------------------------------------------------------------------------- | |
| Applied set_property DONT_TOUCH = true for i_ps/system_i/system_i/proc_sys_reset/U0. (constraint file /media/data/gitrepo/RedPitaya/fpga/project/redpitaya.runs/synth_1/dont_touch.xdc, line 27). | |
| Applied set_property DONT_TOUCH = true for i_ps/system_i/system_i/processing_system7/inst. (constraint file /media/data/gitrepo/RedPitaya/fpga/project/redpitaya.runs/synth_1/dont_touch.xdc, line 35). | |
| Applied set_property DONT_TOUCH = true for i_ps/system_i/system_i/xadc/inst. (constraint file /media/data/gitrepo/RedPitaya/fpga/project/redpitaya.runs/synth_1/dont_touch.xdc, line 40). | |
| Applied set_property DONT_TOUCH = true for i_ps/system_i/system_i. (constraint file auto generated constraint, line ). | |
| Applied set_property DONT_TOUCH = true for i_ps/system_i/system_i/axi_protocol_converter_0. (constraint file auto generated constraint, line ). | |
| Applied set_property DONT_TOUCH = true for i_ps/system_i/system_i/proc_sys_reset. (constraint file auto generated constraint, line ). | |
| Applied set_property DONT_TOUCH = true for i_ps/system_i/system_i/processing_system7. (constraint file auto generated constraint, line ). | |
| Applied set_property DONT_TOUCH = true for i_ps/system_i/system_i/xadc. (constraint file auto generated constraint, line ). | |
| Applied set_property DONT_TOUCH = true for i_ps/system_i/system_i/xlconstant. (constraint file auto generated constraint, line ). | |
| --------------------------------------------------------------------------------- | |
| Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:52 ; elapsed = 00:00:53 . Memory (MB): peak = 1436.309 ; gain = 545.488 ; free physical = 8639 ; free virtual = 28948 | |
| --------------------------------------------------------------------------------- | |
| INFO: [Synth 8-4471] merging register 'awdata_in_reg_reg' into 'axi_awvalid_o_reg' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_master.v:117] | |
| INFO: [Synth 8-4471] merging register 'wdata_in_reg_reg' into 'axi_wvalid_o_reg' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_master.v:191] | |
| INFO: [Synth 8-4471] merging register 'rdata_in_reg_reg' into 'sys_rrdy_o_reg' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_master.v:356] | |
| INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_master.v:233] | |
| INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_master.v:161] | |
| INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_master.v:401] | |
| INFO: [Synth 8-4471] merging register 'seq_cnt_en_reg' into 'from_sys_reg' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/sequence_psr.vhd:222] | |
| INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) | |
| INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) | |
| INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) | |
| INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) | |
| INFO: [Synth 8-5546] ROM "led_o" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "exp_p_dat_o" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "exp_p_dir_o" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "exp_n_dat_o" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "exp_n_dir_o" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "digital_loop" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_wr_fifo.v:216] | |
| INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/axi_wr_fifo.v:145] | |
| INFO: [Synth 8-5546] ROM "ext_trig_dp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "ext_trig_dn" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "asg_trig_dp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "asg_trig_dn" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "adc_we_keep" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_tresh" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_tresh" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_dly" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_dec" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_hyst" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_hyst" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_avg_en" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_filt_aa" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_filt_bb" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_filt_kk" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_filt_pp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_filt_aa" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_filt_bb" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_filt_kk" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_filt_pp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_deb_len" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_axi_en" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_axi_en" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_axi_start" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_axi_stop" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_axi_dly" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_axi_start" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_axi_stop" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_axi_dly" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "ext_trig_dp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "ext_trig_dn" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_amp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_zero" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_size" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_ofs" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_step" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_ncyc" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_rnum" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_rdly" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_amp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_size" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_ofs" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_step" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_ncyc" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_rnum" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_rdly" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_11_sp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_11_kp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_11_ki" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_11_kd" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_11_irst" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_12_sp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_12_kp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_12_ki" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_12_kd" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_21_sp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_21_kp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_21_ki" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_21_kd" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_22_sp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_22_kp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_22_ki" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_22_kd" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "dac_a_o" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "dac_b_o" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "dac_c_o" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "dac_d_o" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "bcnt" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5544] ROM "v0" won't be mapped to Block RAM because address size (4) smaller than threshold (5) | |
| --------------------------------------------------------------------------------- | |
| Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:56 ; elapsed = 00:00:58 . Memory (MB): peak = 1436.309 ; gain = 545.488 ; free physical = 8627 ; free virtual = 28936 | |
| --------------------------------------------------------------------------------- | |
| Report RTL Partitions: | |
| +-+--------------+------------+----------+ | |
| | |RTL Partition |Replication |Instances | | |
| +-+--------------+------------+----------+ | |
| +-+--------------+------------+----------+ | |
| --------------------------------------------------------------------------------- | |
| Start RTL Component Statistics | |
| --------------------------------------------------------------------------------- | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 4 Input 34 Bit Adders := 2 | |
| 3 Input 33 Bit Adders := 6 | |
| 2 Input 33 Bit Adders := 6 | |
| 4 Input 33 Bit Adders := 2 | |
| 2 Input 31 Bit Adders := 2 | |
| 3 Input 31 Bit Adders := 2 | |
| 2 Input 20 Bit Adders := 4 | |
| 3 Input 20 Bit Adders := 4 | |
| 2 Input 17 Bit Adders := 1 | |
| 2 Input 16 Bit Adders := 2 | |
| 2 Input 15 Bit Adders := 8 | |
| 3 Input 14 Bit Adders := 2 | |
| 2 Input 14 Bit Adders := 2 | |
| 2 Input 12 Bit Adders := 6 | |
| 2 Input 10 Bit Adders := 2 | |
| 2 Input 9 Bit Adders := 7 | |
| 2 Input 8 Bit Adders := 17 | |
| 2 Input 7 Bit Adders := 1 | |
| 2 Input 6 Bit Adders := 4 | |
| 2 Input 5 Bit Adders := 4 | |
| 2 Input 4 Bit Adders := 32 | |
| 3 Input 4 Bit Adders := 2 | |
| 2 Input 2 Bit Adders := 4 | |
| +---XORs : | |
| 2 Input 1 Bit XORs := 17 | |
| +---XORs : | |
| 2 Bit Wide XORs := 4 | |
| +---Registers : | |
| 66 Bit Registers := 4 | |
| 64 Bit Registers := 8 | |
| 57 Bit Registers := 1 | |
| 48 Bit Registers := 2 | |
| 47 Bit Registers := 2 | |
| 33 Bit Registers := 4 | |
| 32 Bit Registers := 46 | |
| 30 Bit Registers := 10 | |
| 28 Bit Registers := 2 | |
| 25 Bit Registers := 10 | |
| 24 Bit Registers := 4 | |
| 23 Bit Registers := 2 | |
| 20 Bit Registers := 9 | |
| 19 Bit Registers := 8 | |
| 18 Bit Registers := 4 | |
| 17 Bit Registers := 7 | |
| 16 Bit Registers := 11 | |
| 15 Bit Registers := 14 | |
| 14 Bit Registers := 58 | |
| 12 Bit Registers := 9 | |
| 11 Bit Registers := 1 | |
| 9 Bit Registers := 6 | |
| 8 Bit Registers := 33 | |
| 7 Bit Registers := 1 | |
| 6 Bit Registers := 2 | |
| 5 Bit Registers := 4 | |
| 4 Bit Registers := 41 | |
| 3 Bit Registers := 10 | |
| 2 Bit Registers := 32 | |
| 1 Bit Registers := 284 | |
| +---RAMs : | |
| 224K Bit RAMs := 4 | |
| 16K Bit RAMs := 2 | |
| +---Muxes : | |
| 2 Input 66 Bit Muxes := 4 | |
| 2 Input 64 Bit Muxes := 4 | |
| 2 Input 47 Bit Muxes := 2 | |
| 2 Input 33 Bit Muxes := 4 | |
| 2 Input 32 Bit Muxes := 40 | |
| 36 Input 32 Bit Muxes := 1 | |
| 20 Input 32 Bit Muxes := 1 | |
| 18 Input 32 Bit Muxes := 1 | |
| 2 Input 30 Bit Muxes := 6 | |
| 2 Input 24 Bit Muxes := 1 | |
| 3 Input 20 Bit Muxes := 4 | |
| 4 Input 18 Bit Muxes := 1 | |
| 3 Input 17 Bit Muxes := 1 | |
| 2 Input 16 Bit Muxes := 24 | |
| 2 Input 14 Bit Muxes := 32 | |
| 7 Input 14 Bit Muxes := 2 | |
| 2 Input 12 Bit Muxes := 4 | |
| 2 Input 10 Bit Muxes := 1 | |
| 2 Input 9 Bit Muxes := 4 | |
| 2 Input 8 Bit Muxes := 4 | |
| 4 Input 6 Bit Muxes := 1 | |
| 2 Input 6 Bit Muxes := 5 | |
| 2 Input 5 Bit Muxes := 4 | |
| 2 Input 4 Bit Muxes := 30 | |
| 8 Input 3 Bit Muxes := 2 | |
| 2 Input 2 Bit Muxes := 21 | |
| 4 Input 2 Bit Muxes := 1 | |
| 5 Input 2 Bit Muxes := 2 | |
| 7 Input 2 Bit Muxes := 1 | |
| 2 Input 1 Bit Muxes := 249 | |
| 3 Input 1 Bit Muxes := 1 | |
| 36 Input 1 Bit Muxes := 1 | |
| 4 Input 1 Bit Muxes := 2 | |
| 20 Input 1 Bit Muxes := 1 | |
| --------------------------------------------------------------------------------- | |
| Finished RTL Component Statistics | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start RTL Hierarchical Component Statistics | |
| --------------------------------------------------------------------------------- | |
| Hierarchical RTL Component report | |
| Module red_pitaya_top | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 15 Bit Adders := 2 | |
| +---XORs : | |
| 2 Bit Wide XORs := 2 | |
| +---Registers : | |
| 14 Bit Registers := 4 | |
| 1 Bit Registers := 3 | |
| +---Muxes : | |
| 2 Input 14 Bit Muxes := 4 | |
| Module axi_slave | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 6 Bit Adders := 1 | |
| +---Registers : | |
| 32 Bit Registers := 4 | |
| 12 Bit Registers := 2 | |
| 6 Bit Registers := 1 | |
| 4 Bit Registers := 1 | |
| 2 Bit Registers := 2 | |
| 1 Bit Registers := 8 | |
| +---Muxes : | |
| 2 Input 32 Bit Muxes := 1 | |
| 4 Input 6 Bit Muxes := 1 | |
| 2 Input 6 Bit Muxes := 4 | |
| 2 Input 2 Bit Muxes := 1 | |
| 2 Input 1 Bit Muxes := 2 | |
| Module axi_protocol_converter_v2_1_8_b2s_incr_cmd | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 12 Bit Adders := 2 | |
| 2 Input 10 Bit Adders := 1 | |
| 2 Input 9 Bit Adders := 1 | |
| +---Registers : | |
| 9 Bit Registers := 1 | |
| 1 Bit Registers := 2 | |
| +---Muxes : | |
| 2 Input 32 Bit Muxes := 1 | |
| 2 Input 9 Bit Muxes := 2 | |
| 2 Input 4 Bit Muxes := 1 | |
| 2 Input 1 Bit Muxes := 4 | |
| Module axi_protocol_converter_v2_1_8_b2s_wrap_cmd | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 12 Bit Adders := 1 | |
| 2 Input 6 Bit Adders := 1 | |
| 2 Input 5 Bit Adders := 1 | |
| 2 Input 4 Bit Adders := 2 | |
| +---Registers : | |
| 12 Bit Registers := 2 | |
| 5 Bit Registers := 1 | |
| 4 Bit Registers := 3 | |
| 1 Bit Registers := 2 | |
| +---Muxes : | |
| 2 Input 32 Bit Muxes := 1 | |
| 2 Input 12 Bit Muxes := 2 | |
| 2 Input 5 Bit Muxes := 2 | |
| 2 Input 4 Bit Muxes := 8 | |
| 2 Input 1 Bit Muxes := 4 | |
| Module axi_protocol_converter_v2_1_8_b2s_cmd_translator | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 1 Bit Registers := 3 | |
| +---Muxes : | |
| 2 Input 32 Bit Muxes := 2 | |
| 2 Input 1 Bit Muxes := 4 | |
| Module axi_protocol_converter_v2_1_8_b2s_wr_cmd_fsm | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 2 Bit Registers := 1 | |
| +---Muxes : | |
| 2 Input 2 Bit Muxes := 2 | |
| 4 Input 2 Bit Muxes := 1 | |
| Module axi_protocol_converter_v2_1_8_b2s_aw_channel | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 12 Bit Registers := 1 | |
| 8 Bit Registers := 1 | |
| Module axi_protocol_converter_v2_1_8_b2s_simple_fifo | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 2 Bit Adders := 1 | |
| +---Registers : | |
| 2 Bit Registers := 1 | |
| +---Muxes : | |
| 2 Input 2 Bit Muxes := 1 | |
| Module axi_protocol_converter_v2_1_8_b2s_simple_fifo__parameterized0 | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 2 Bit Adders := 1 | |
| +---Registers : | |
| 2 Bit Registers := 1 | |
| +---Muxes : | |
| 2 Input 2 Bit Muxes := 1 | |
| Module axi_protocol_converter_v2_1_8_b2s_b_channel | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 8 Bit Adders := 1 | |
| +---Registers : | |
| 8 Bit Registers := 1 | |
| 2 Bit Registers := 1 | |
| 1 Bit Registers := 3 | |
| Module axi_protocol_converter_v2_1_8_b2s_rd_cmd_fsm | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 2 Bit Registers := 1 | |
| +---Muxes : | |
| 5 Input 2 Bit Muxes := 2 | |
| 2 Input 2 Bit Muxes := 2 | |
| Module axi_protocol_converter_v2_1_8_b2s_ar_channel | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 12 Bit Registers := 1 | |
| Module axi_protocol_converter_v2_1_8_b2s_simple_fifo__parameterized1 | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 5 Bit Adders := 1 | |
| +---Registers : | |
| 5 Bit Registers := 1 | |
| +---Muxes : | |
| 2 Input 2 Bit Muxes := 1 | |
| Module axi_protocol_converter_v2_1_8_b2s_simple_fifo__parameterized2 | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 5 Bit Adders := 1 | |
| +---Registers : | |
| 5 Bit Registers := 1 | |
| +---Muxes : | |
| 2 Input 2 Bit Muxes := 1 | |
| Module axi_protocol_converter_v2_1_8_b2s_r_channel | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 12 Bit Registers := 1 | |
| 1 Bit Registers := 2 | |
| Module axi_register_slice_v2_1_8_axic_register_slice | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 66 Bit Registers := 2 | |
| 2 Bit Registers := 1 | |
| 1 Bit Registers := 2 | |
| +---Muxes : | |
| 2 Input 66 Bit Muxes := 2 | |
| Module axi_register_slice_v2_1_8_axic_register_slice__parameterized1 | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 14 Bit Registers := 2 | |
| 2 Bit Registers := 1 | |
| 1 Bit Registers := 2 | |
| +---Muxes : | |
| 2 Input 14 Bit Muxes := 2 | |
| Module axi_register_slice_v2_1_8_axic_register_slice__parameterized2 | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 47 Bit Registers := 2 | |
| 2 Bit Registers := 1 | |
| 1 Bit Registers := 2 | |
| +---Muxes : | |
| 2 Input 47 Bit Muxes := 2 | |
| Module axi_protocol_converter_v2_1_8_b2s | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 1 Bit Registers := 1 | |
| Module lpf | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 1 Bit Registers := 3 | |
| Module upcnt_n | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 6 Bit Adders := 1 | |
| +---Registers : | |
| 6 Bit Registers := 1 | |
| +---Muxes : | |
| 2 Input 6 Bit Muxes := 1 | |
| 2 Input 1 Bit Muxes := 1 | |
| Module sequence_psr | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 3 Bit Registers := 3 | |
| 1 Bit Registers := 5 | |
| Module proc_sys_reset | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 1 Bit Registers := 5 | |
| Module system_xadc_0_pselect_f | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized8 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized0 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized1 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized2 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized3 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized4 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized5 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized6 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized7 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized9 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized10 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized11 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized12 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized13 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized14 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized15 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized16 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized17 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized18 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized19 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized20 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized21 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized22 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized23 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_pselect_f__parameterized24 | |
| Detailed RTL Component Info : | |
| +---Muxes : | |
| 2 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_address_decoder | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 1 Bit Registers := 29 | |
| Module system_xadc_0_slave_attachment | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 7 Bit Adders := 1 | |
| +---Registers : | |
| 32 Bit Registers := 1 | |
| 7 Bit Registers := 1 | |
| 2 Bit Registers := 3 | |
| 1 Bit Registers := 3 | |
| +---Muxes : | |
| 2 Input 10 Bit Muxes := 1 | |
| 2 Input 4 Bit Muxes := 1 | |
| 7 Input 2 Bit Muxes := 1 | |
| 2 Input 2 Bit Muxes := 2 | |
| 2 Input 1 Bit Muxes := 7 | |
| Module system_xadc_0_xadc_core_drp | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 16 Bit Registers := 1 | |
| 11 Bit Registers := 1 | |
| 9 Bit Registers := 1 | |
| 1 Bit Registers := 20 | |
| +---Muxes : | |
| 4 Input 18 Bit Muxes := 1 | |
| 2 Input 1 Bit Muxes := 5 | |
| 3 Input 1 Bit Muxes := 1 | |
| Module system_xadc_0_soft_reset | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 1 Bit Registers := 2 | |
| Module system_xadc_0_interrupt_control | |
| Detailed RTL Component Info : | |
| +---XORs : | |
| 2 Input 1 Bit XORs := 17 | |
| +---Registers : | |
| 17 Bit Registers := 1 | |
| 1 Bit Registers := 56 | |
| +---Muxes : | |
| 2 Input 32 Bit Muxes := 3 | |
| 2 Input 1 Bit Muxes := 19 | |
| Module system_xadc_0_axi_xadc | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 32 Bit Registers := 1 | |
| 1 Bit Registers := 14 | |
| Module axi_master | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 4 Bit Adders := 10 | |
| +---Registers : | |
| 64 Bit Registers := 2 | |
| 32 Bit Registers := 2 | |
| 8 Bit Registers := 1 | |
| 4 Bit Registers := 12 | |
| 2 Bit Registers := 2 | |
| 1 Bit Registers := 10 | |
| +---Muxes : | |
| 2 Input 4 Bit Muxes := 1 | |
| 2 Input 2 Bit Muxes := 4 | |
| 2 Input 1 Bit Muxes := 8 | |
| Module red_pitaya_ps | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 1 Bit Registers := 1 | |
| Module red_pitaya_hk | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 9 Bit Adders := 1 | |
| +---Registers : | |
| 57 Bit Registers := 1 | |
| 32 Bit Registers := 1 | |
| 9 Bit Registers := 1 | |
| 8 Bit Registers := 5 | |
| 1 Bit Registers := 7 | |
| +---Muxes : | |
| 2 Input 32 Bit Muxes := 1 | |
| 2 Input 1 Bit Muxes := 6 | |
| Module red_pitaya_dfilt1 | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 3 Input 33 Bit Adders := 1 | |
| 2 Input 33 Bit Adders := 1 | |
| 2 Input 15 Bit Adders := 1 | |
| +---Registers : | |
| 48 Bit Registers := 1 | |
| 33 Bit Registers := 1 | |
| 32 Bit Registers := 1 | |
| 28 Bit Registers := 1 | |
| 25 Bit Registers := 2 | |
| 23 Bit Registers := 1 | |
| 18 Bit Registers := 1 | |
| 15 Bit Registers := 2 | |
| 14 Bit Registers := 1 | |
| +---Muxes : | |
| 2 Input 32 Bit Muxes := 1 | |
| 2 Input 14 Bit Muxes := 3 | |
| Module axi_wr_fifo | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 4 Input 34 Bit Adders := 1 | |
| 2 Input 33 Bit Adders := 2 | |
| 4 Input 33 Bit Adders := 1 | |
| 2 Input 9 Bit Adders := 2 | |
| 2 Input 8 Bit Adders := 3 | |
| 3 Input 4 Bit Adders := 1 | |
| 2 Input 4 Bit Adders := 2 | |
| +---Registers : | |
| 64 Bit Registers := 1 | |
| 33 Bit Registers := 1 | |
| 32 Bit Registers := 3 | |
| 9 Bit Registers := 1 | |
| 8 Bit Registers := 3 | |
| 4 Bit Registers := 2 | |
| 1 Bit Registers := 10 | |
| +---RAMs : | |
| 16K Bit RAMs := 1 | |
| +---Muxes : | |
| 2 Input 33 Bit Muxes := 2 | |
| 2 Input 32 Bit Muxes := 2 | |
| 2 Input 4 Bit Muxes := 4 | |
| 2 Input 2 Bit Muxes := 1 | |
| 2 Input 1 Bit Muxes := 10 | |
| Module red_pitaya_scope | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 17 Bit Adders := 1 | |
| 3 Input 14 Bit Adders := 2 | |
| 2 Input 14 Bit Adders := 2 | |
| 2 Input 2 Bit Adders := 2 | |
| +---Registers : | |
| 64 Bit Registers := 2 | |
| 32 Bit Registers := 12 | |
| 25 Bit Registers := 6 | |
| 20 Bit Registers := 1 | |
| 18 Bit Registers := 2 | |
| 17 Bit Registers := 2 | |
| 14 Bit Registers := 13 | |
| 4 Bit Registers := 2 | |
| 3 Bit Registers := 2 | |
| 2 Bit Registers := 10 | |
| 1 Bit Registers := 23 | |
| +---RAMs : | |
| 224K Bit RAMs := 2 | |
| +---Muxes : | |
| 2 Input 64 Bit Muxes := 4 | |
| 2 Input 32 Bit Muxes := 4 | |
| 36 Input 32 Bit Muxes := 1 | |
| 3 Input 17 Bit Muxes := 1 | |
| 2 Input 16 Bit Muxes := 16 | |
| 7 Input 14 Bit Muxes := 2 | |
| 2 Input 4 Bit Muxes := 1 | |
| 8 Input 3 Bit Muxes := 2 | |
| 2 Input 1 Bit Muxes := 53 | |
| 36 Input 1 Bit Muxes := 1 | |
| Module red_pitaya_asg_ch | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 31 Bit Adders := 1 | |
| 3 Input 31 Bit Adders := 1 | |
| 2 Input 20 Bit Adders := 2 | |
| 2 Input 16 Bit Adders := 1 | |
| 2 Input 15 Bit Adders := 1 | |
| 2 Input 8 Bit Adders := 1 | |
| +---XORs : | |
| 2 Bit Wide XORs := 1 | |
| +---Registers : | |
| 30 Bit Registers := 2 | |
| 20 Bit Registers := 2 | |
| 16 Bit Registers := 1 | |
| 15 Bit Registers := 1 | |
| 14 Bit Registers := 5 | |
| 8 Bit Registers := 1 | |
| 3 Bit Registers := 1 | |
| 2 Bit Registers := 2 | |
| 1 Bit Registers := 4 | |
| +---RAMs : | |
| 224K Bit RAMs := 1 | |
| +---Muxes : | |
| 2 Input 30 Bit Muxes := 3 | |
| 3 Input 20 Bit Muxes := 2 | |
| 2 Input 16 Bit Muxes := 2 | |
| 2 Input 14 Bit Muxes := 1 | |
| 2 Input 1 Bit Muxes := 11 | |
| 4 Input 1 Bit Muxes := 1 | |
| Module red_pitaya_asg | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 32 Bit Registers := 5 | |
| 30 Bit Registers := 6 | |
| 16 Bit Registers := 4 | |
| 14 Bit Registers := 5 | |
| 3 Bit Registers := 3 | |
| 1 Bit Registers := 17 | |
| +---Muxes : | |
| 20 Input 32 Bit Muxes := 1 | |
| 2 Input 1 Bit Muxes := 15 | |
| 20 Input 1 Bit Muxes := 1 | |
| Module red_pitaya_pid_block | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 3 Input 33 Bit Adders := 1 | |
| 3 Input 20 Bit Adders := 1 | |
| +---Registers : | |
| 32 Bit Registers := 2 | |
| 20 Bit Registers := 1 | |
| 19 Bit Registers := 2 | |
| 17 Bit Registers := 1 | |
| 15 Bit Registers := 2 | |
| 14 Bit Registers := 1 | |
| +---Muxes : | |
| 2 Input 32 Bit Muxes := 4 | |
| 2 Input 14 Bit Muxes := 3 | |
| Module red_pitaya_pid | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 15 Bit Adders := 2 | |
| +---Registers : | |
| 32 Bit Registers := 1 | |
| 14 Bit Registers := 18 | |
| 1 Bit Registers := 6 | |
| +---Muxes : | |
| 18 Input 32 Bit Muxes := 1 | |
| 2 Input 32 Bit Muxes := 1 | |
| 2 Input 14 Bit Muxes := 6 | |
| 2 Input 1 Bit Muxes := 17 | |
| Module red_pitaya_ams | |
| Detailed RTL Component Info : | |
| +---Registers : | |
| 32 Bit Registers := 1 | |
| 24 Bit Registers := 4 | |
| 1 Bit Registers := 2 | |
| +---Muxes : | |
| 2 Input 24 Bit Muxes := 1 | |
| 2 Input 1 Bit Muxes := 4 | |
| Module red_pitaya_pwm | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 8 Bit Adders := 2 | |
| 2 Input 4 Bit Adders := 1 | |
| +---Registers : | |
| 16 Bit Registers := 1 | |
| 8 Bit Registers := 4 | |
| 4 Bit Registers := 1 | |
| 1 Bit Registers := 1 | |
| +---Muxes : | |
| 2 Input 16 Bit Muxes := 1 | |
| 2 Input 8 Bit Muxes := 1 | |
| 2 Input 1 Bit Muxes := 3 | |
| --------------------------------------------------------------------------------- | |
| Finished RTL Hierarchical Component Statistics | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Part Resource Summary | |
| --------------------------------------------------------------------------------- | |
| Part Resources: | |
| DSPs: 80 (col length:40) | |
| BRAMs: 120 (col length: RAMB18 40 RAMB36 20) | |
| --------------------------------------------------------------------------------- | |
| Finished Part Resource Summary | |
| --------------------------------------------------------------------------------- | |
| Start Parallel Synthesis Optimization : Time (s): cpu = 00:00:56 ; elapsed = 00:00:58 . Memory (MB): peak = 1436.309 ; gain = 545.488 ; free physical = 8627 ; free virtual = 28937 | |
| --------------------------------------------------------------------------------- | |
| Start Cross Boundary Optimization | |
| --------------------------------------------------------------------------------- | |
| INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:121] | |
| INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v:121] | |
| INFO: [Synth 8-4471] merging register 'INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I/DO_IRPT_INPUT[15].GEN_POS_EDGE_DETECT.irpt_dly1_reg' into 'INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I/DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly1_reg' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:638] | |
| INFO: [Synth 8-4471] merging register 'INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I/DO_IRPT_INPUT[15].GEN_POS_EDGE_DETECT.irpt_dly2_reg' into 'INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I/DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly2_reg' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:639] | |
| INFO: [Synth 8-4471] merging register 'INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I/DO_IRPT_INPUT[16].GEN_POS_EDGE_DETECT.irpt_dly1_reg' into 'INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I/DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly1_reg' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:638] | |
| INFO: [Synth 8-4471] merging register 'INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I/DO_IRPT_INPUT[16].GEN_POS_EDGE_DETECT.irpt_dly2_reg' into 'INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I/DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly2_reg' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_0_interrupt_control.vhd:639] | |
| INFO: [Synth 8-4471] merging register 'bus2ip_reset_active_high_reg' into 'AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/bd/system/ip/system_xadc_0/system_xadc_0_axi_xadc.vhd:655] | |
| INFO: [Synth 8-5546] ROM "led_o" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "digital_loop" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "exp_p_dat_o" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "exp_p_dir_o" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "exp_n_dat_o" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "exp_n_dir_o" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-4471] merging register 'r3_reg_reg[22:0]' into 'r3_reg_reg[22:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_dfilt1.v:88] | |
| DSP Report: Generating DSP bb_mult, operation Mode is: A2*B. | |
| DSP Report: register cfg_bb_r_reg is absorbed into DSP bb_mult. | |
| DSP Report: operator bb_mult is absorbed into DSP bb_mult. | |
| DSP Report: Generating DSP r3_sum, operation Mode is: C'-A2*B2. | |
| DSP Report: register cfg_aa_r_reg is absorbed into DSP r3_sum. | |
| DSP Report: register r3_reg_reg is absorbed into DSP r3_sum. | |
| DSP Report: register C is absorbed into DSP r3_sum. | |
| DSP Report: operator r3_sum is absorbed into DSP r3_sum. | |
| DSP Report: operator aa_mult is absorbed into DSP r3_sum. | |
| DSP Report: Generating DSP r3_sum, operation Mode is: PCIN+A2:B2. | |
| DSP Report: register C is absorbed into DSP r3_sum. | |
| DSP Report: register A is absorbed into DSP r3_sum. | |
| DSP Report: operator r3_sum is absorbed into DSP r3_sum. | |
| DSP Report: Generating DSP pp_mult, operation Mode is: A2*B2. | |
| DSP Report: register r4_reg_reg is absorbed into DSP pp_mult. | |
| DSP Report: register cfg_pp_r_reg is absorbed into DSP pp_mult. | |
| DSP Report: operator pp_mult is absorbed into DSP pp_mult. | |
| DSP Report: Generating DSP kk_mult, operation Mode is: A2*BCIN''. | |
| DSP Report: register cfg_kk_r_reg is absorbed into DSP kk_mult. | |
| DSP Report: register r4_reg_r_reg is absorbed into DSP kk_mult. | |
| DSP Report: register r4_reg_rr_reg is absorbed into DSP kk_mult. | |
| DSP Report: operator kk_mult is absorbed into DSP kk_mult. | |
| INFO: [Synth 8-4471] merging register 'r3_reg_reg[22:0]' into 'r3_reg_reg[22:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_dfilt1.v:88] | |
| DSP Report: Generating DSP bb_mult, operation Mode is: A2*B. | |
| DSP Report: register cfg_bb_r_reg is absorbed into DSP bb_mult. | |
| DSP Report: operator bb_mult is absorbed into DSP bb_mult. | |
| DSP Report: Generating DSP r3_sum, operation Mode is: C'-A2*B2. | |
| DSP Report: register cfg_aa_r_reg is absorbed into DSP r3_sum. | |
| DSP Report: register r3_reg_reg is absorbed into DSP r3_sum. | |
| DSP Report: register C is absorbed into DSP r3_sum. | |
| DSP Report: operator r3_sum is absorbed into DSP r3_sum. | |
| DSP Report: operator aa_mult is absorbed into DSP r3_sum. | |
| DSP Report: Generating DSP r3_sum, operation Mode is: PCIN+A2:B2. | |
| DSP Report: register B is absorbed into DSP r3_sum. | |
| DSP Report: register A is absorbed into DSP r3_sum. | |
| DSP Report: operator r3_sum is absorbed into DSP r3_sum. | |
| DSP Report: Generating DSP pp_mult, operation Mode is: A2*B2. | |
| DSP Report: register r4_reg_reg is absorbed into DSP pp_mult. | |
| DSP Report: register cfg_pp_r_reg is absorbed into DSP pp_mult. | |
| DSP Report: operator pp_mult is absorbed into DSP pp_mult. | |
| DSP Report: Generating DSP kk_mult, operation Mode is: A2*BCIN''. | |
| DSP Report: register cfg_kk_r_reg is absorbed into DSP kk_mult. | |
| DSP Report: register r4_reg_r_reg is absorbed into DSP kk_mult. | |
| DSP Report: register r4_reg_rr_reg is absorbed into DSP kk_mult. | |
| DSP Report: operator kk_mult is absorbed into DSP kk_mult. | |
| INFO: [Synth 8-5546] ROM "adc_we_keep" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_dec" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_tresh" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_hyst" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_tresh" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_hyst" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_deb_len" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "ext_trig_dp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "ext_trig_dn" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "asg_trig_dp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "asg_trig_dn" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_dly" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_avg_en" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_filt_aa" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_filt_bb" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_filt_kk" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_a_filt_pp" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_filt_aa" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_filt_bb" won't be mapped to RAM because it is too sparse | |
| INFO: [Synth 8-5546] ROM "set_b_filt_kk" won't be mapped to RAM because it is too sparse | |
| INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. | |
| DSP Report: Generating DSP ch[1]/dac_mult_reg, operation Mode is: (A*B'')'. | |
| DSP Report: register ch[1]/dac_rd_reg is absorbed into DSP ch[1]/dac_mult_reg. | |
| DSP Report: register ch[1]/dac_rdat_reg is absorbed into DSP ch[1]/dac_mult_reg. | |
| DSP Report: register ch[1]/dac_mult_reg is absorbed into DSP ch[1]/dac_mult_reg. | |
| DSP Report: operator ch[1]/dac_mult0 is absorbed into DSP ch[1]/dac_mult_reg. | |
| DSP Report: Generating DSP ch[0]/dac_mult_reg, operation Mode is: (A*B'')'. | |
| DSP Report: register ch[0]/dac_rd_reg is absorbed into DSP ch[0]/dac_mult_reg. | |
| DSP Report: register ch[0]/dac_rdat_reg is absorbed into DSP ch[0]/dac_mult_reg. | |
| DSP Report: register ch[0]/dac_mult_reg is absorbed into DSP ch[0]/dac_mult_reg. | |
| DSP Report: operator ch[0]/dac_mult0 is absorbed into DSP ch[0]/dac_mult_reg. | |
| INFO: [Synth 8-4471] merging register 'i_pid11/int_reg_reg[31:0]' into 'i_pid11/int_reg_reg[31:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid_block.v:128] | |
| INFO: [Synth 8-4471] merging register 'i_pid21/int_reg_reg[31:0]' into 'i_pid21/int_reg_reg[31:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid_block.v:128] | |
| INFO: [Synth 8-4471] merging register 'i_pid12/int_reg_reg[31:0]' into 'i_pid12/int_reg_reg[31:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid_block.v:128] | |
| INFO: [Synth 8-4471] merging register 'i_pid22/int_reg_reg[31:0]' into 'i_pid22/int_reg_reg[31:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid_block.v:128] | |
| INFO: [Synth 8-4471] merging register 'i_pid11/error_reg[14:0]' into 'i_pid11/error_reg[14:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid_block.v:79] | |
| INFO: [Synth 8-4471] merging register 'i_pid21/error_reg[14:0]' into 'i_pid21/error_reg[14:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid_block.v:79] | |
| INFO: [Synth 8-4471] merging register 'i_pid12/error_reg[14:0]' into 'i_pid12/error_reg[14:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid_block.v:79] | |
| INFO: [Synth 8-4471] merging register 'i_pid22/error_reg[14:0]' into 'i_pid22/error_reg[14:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid_block.v:79] | |
| INFO: [Synth 8-4471] merging register 'i_pid11/error_reg[14:0]' into 'i_pid11/error_reg[14:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid_block.v:79] | |
| INFO: [Synth 8-4471] merging register 'i_pid21/error_reg[14:0]' into 'i_pid21/error_reg[14:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid_block.v:79] | |
| INFO: [Synth 8-4471] merging register 'i_pid12/error_reg[14:0]' into 'i_pid12/error_reg[14:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid_block.v:79] | |
| INFO: [Synth 8-4471] merging register 'i_pid22/error_reg[14:0]' into 'i_pid22/error_reg[14:0]' [/media/data/gitrepo/RedPitaya/fpga/project/redpitaya.srcs/sources_1/imports/rtl/red_pitaya_pid_block.v:79] | |
| DSP Report: Generating DSP i_pid12/int_sum, operation Mode is: C'+((D'-A)*B2)'. | |
| DSP Report: register set_12_sp_reg is absorbed into DSP i_pid12/int_sum. | |
| DSP Report: register set_12_ki_reg is absorbed into DSP i_pid12/int_sum. | |
| DSP Report: register i_pid12/int_reg_reg is absorbed into DSP i_pid12/int_sum. | |
| DSP Report: register i_pid12/ki_mult_reg is absorbed into DSP i_pid12/int_sum. | |
| DSP Report: register i_pid12/error_reg is absorbed into DSP i_pid12/int_sum. | |
| DSP Report: operator i_pid12/ki_mult0 is absorbed into DSP i_pid12/int_sum. | |
| DSP Report: operator i_pid12/error0 is absorbed into DSP i_pid12/int_sum. | |
| DSP Report: operator i_pid12/int_sum is absorbed into DSP i_pid12/int_sum. | |
| DSP Report: Generating DSP i_pid12/kd_mult, operation Mode is: (D'-A)*B2. | |
| DSP Report: register set_12_sp_reg is absorbed into DSP i_pid12/kd_mult. | |
| DSP Report: register set_12_kd_reg is absorbed into DSP i_pid12/kd_mult. | |
| DSP Report: register i_pid12/error_reg is absorbed into DSP i_pid12/kd_mult. | |
| DSP Report: operator i_pid12/error0 is absorbed into DSP i_pid12/kd_mult. | |
| DSP Report: operator i_pid12/kd_mult is absorbed into DSP i_pid12/kd_mult. | |
| DSP Report: Generating DSP i_pid12/kp_mult, operation Mode is: (D'-A)*B2. | |
| DSP Report: register set_12_sp_reg is absorbed into DSP i_pid12/kp_mult. | |
| DSP Report: register set_12_kp_reg is absorbed into DSP i_pid12/kp_mult. | |
| DSP Report: register i_pid12/error_reg is absorbed into DSP i_pid12/kp_mult. | |
| DSP Report: operator i_pid12/error0 is absorbed into DSP i_pid12/kp_mult. | |
| DSP Report: operator i_pid12/kp_mult is absorbed into DSP i_pid12/kp_mult. | |
| DSP Report: Generating DSP i_pid11/int_sum, operation Mode is: C'+((D'-A)*B2)'. | |
| DSP Report: register set_11_sp_reg is absorbed into DSP i_pid11/int_sum. | |
| DSP Report: register set_11_ki_reg is absorbed into DSP i_pid11/int_sum. | |
| DSP Report: register i_pid11/int_reg_reg is absorbed into DSP i_pid11/int_sum. | |
| DSP Report: register i_pid11/ki_mult_reg is absorbed into DSP i_pid11/int_sum. | |
| DSP Report: register i_pid11/error_reg is absorbed into DSP i_pid11/int_sum. | |
| DSP Report: operator i_pid11/ki_mult0 is absorbed into DSP i_pid11/int_sum. | |
| DSP Report: operator i_pid11/error0 is absorbed into DSP i_pid11/int_sum. | |
| DSP Report: operator i_pid11/int_sum is absorbed into DSP i_pid11/int_sum. | |
| DSP Report: Generating DSP i_pid11/kd_mult, operation Mode is: (D'-A)*B2. | |
| DSP Report: register set_11_sp_reg is absorbed into DSP i_pid11/kd_mult. | |
| DSP Report: register set_11_kd_reg is absorbed into DSP i_pid11/kd_mult. | |
| DSP Report: register i_pid11/error_reg is absorbed into DSP i_pid11/kd_mult. | |
| DSP Report: operator i_pid11/error0 is absorbed into DSP i_pid11/kd_mult. | |
| DSP Report: operator i_pid11/kd_mult is absorbed into DSP i_pid11/kd_mult. | |
| DSP Report: Generating DSP i_pid11/kp_mult, operation Mode is: (D'-A)*B2. | |
| DSP Report: register set_11_sp_reg is absorbed into DSP i_pid11/kp_mult. | |
| DSP Report: register set_11_kp_reg is absorbed into DSP i_pid11/kp_mult. | |
| DSP Report: register i_pid11/error_reg is absorbed into DSP i_pid11/kp_mult. | |
| DSP Report: operator i_pid11/error0 is absorbed into DSP i_pid11/kp_mult. | |
| DSP Report: operator i_pid11/kp_mult is absorbed into DSP i_pid11/kp_mult. | |
| DSP Report: Generating DSP i_pid21/int_sum, operation Mode is: C'+((D'-A)*B2)'. | |
| DSP Report: register set_21_sp_reg is absorbed into DSP i_pid21/int_sum. | |
| DSP Report: register set_21_ki_reg is absorbed into DSP i_pid21/int_sum. | |
| DSP Report: register i_pid21/int_reg_reg is absorbed into DSP i_pid21/int_sum. | |
| DSP Report: register i_pid21/ki_mult_reg is absorbed into DSP i_pid21/int_sum. | |
| DSP Report: register i_pid21/error_reg is absorbed into DSP i_pid21/int_sum. | |
| DSP Report: operator i_pid21/ki_mult0 is absorbed into DSP i_pid21/int_sum. | |
| DSP Report: operator i_pid21/error0 is absorbed into DSP i_pid21/int_sum. | |
| DSP Report: operator i_pid21/int_sum is absorbed into DSP i_pid21/int_sum. | |
| DSP Report: Generating DSP i_pid21/kd_mult, operation Mode is: (D'-A)*B2. | |
| DSP Report: register set_21_sp_reg is absorbed into DSP i_pid21/kd_mult. | |
| DSP Report: register set_21_kd_reg is absorbed into DSP i_pid21/kd_mult. | |
| DSP Report: register i_pid21/error_reg is absorbed into DSP i_pid21/kd_mult. | |
| DSP Report: operator i_pid21/error0 is absorbed into DSP i_pid21/kd_mult. | |
| DSP Report: operator i_pid21/kd_mult is absorbed into DSP i_pid21/kd_mult. | |
| DSP Report: Generating DSP i_pid21/kp_mult, operation Mode is: (D'-A)*B2. | |
| DSP Report: register set_21_sp_reg is absorbed into DSP i_pid21/kp_mult. | |
| DSP Report: register set_21_kp_reg is absorbed into DSP i_pid21/kp_mult. | |
| DSP Report: register i_pid21/error_reg is absorbed into DSP i_pid21/kp_mult. | |
| DSP Report: operator i_pid21/error0 is absorbed into DSP i_pid21/kp_mult. | |
| DSP Report: operator i_pid21/kp_mult is absorbed into DSP i_pid21/kp_mult. | |
| DSP Report: Generating DSP i_pid22/int_sum, operation Mode is: C'+((D'-A)*B2)'. | |
| DSP Report: register set_22_sp_reg is absorbed into DSP i_pid22/int_sum. | |
| DSP Report: register set_22_ki_reg is absorbed into DSP i_pid22/int_sum. | |
| DSP Report: register i_pid22/int_reg_reg is absorbed into DSP i_pid22/int_sum. | |
| DSP Report: register i_pid22/ki_mult_reg is absorbed into DSP i_pid22/int_sum. | |
| DSP Report: register i_pid22/error_reg is absorbed into DSP i_pid22/int_sum. | |
| DSP Report: operator i_pid22/ki_mult0 is absorbed into DSP i_pid22/int_sum. | |
| DSP Report: operator i_pid22/error0 is absorbed into DSP i_pid22/int_sum. | |
| DSP Report: operator i_pid22/int_sum is absorbed into DSP i_pid22/int_sum. | |
| DSP Report: Generating DSP i_pid22/kd_mult, operation Mode is: (D'-A)*B2. | |
| DSP Report: register set_22_sp_reg is absorbed into DSP i_pid22/kd_mult. | |
| DSP Report: register set_22_kd_reg is absorbed into DSP i_pid22/kd_mult. | |
| DSP Report: register i_pid22/error_reg is absorbed into DSP i_pid22/kd_mult. | |
| DSP Report: operator i_pid22/error0 is absorbed into DSP i_pid22/kd_mult. | |
| DSP Report: operator i_pid22/kd_mult is absorbed into DSP i_pid22/kd_mult. | |
| DSP Report: Generating DSP i_pid22/kp_mult, operation Mode is: (D'-A)*B2. | |
| DSP Report: register set_22_sp_reg is absorbed into DSP i_pid22/kp_mult. | |
| DSP Report: register set_22_kp_reg is absorbed into DSP i_pid22/kp_mult. | |
| DSP Report: register i_pid22/error_reg is absorbed into DSP i_pid22/kp_mult. | |
| DSP Report: operator i_pid22/error0 is absorbed into DSP i_pid22/kp_mult. | |
| DSP Report: operator i_pid22/kp_mult is absorbed into DSP i_pid22/kp_mult. | |
| WARNING: [Synth 8-3917] design red_pitaya_top has port adc_clk_o[1] driven by constant 1 | |
| WARNING: [Synth 8-3917] design red_pitaya_top has port adc_clk_o[0] driven by constant 0 | |
| WARNING: [Synth 8-3917] design red_pitaya_top has port adc_cdcs_o driven by constant 1 | |
| WARNING: [Synth 8-3917] design red_pitaya_top has port daisy_p_o[1] driven by constant 0 | |
| WARNING: [Synth 8-3917] design red_pitaya_top has port daisy_n_o[1] driven by constant 0 | |
| --------------------------------------------------------------------------------- | |
| Finished Cross Boundary Optimization : Time (s): cpu = 00:01:02 ; elapsed = 00:01:04 . Memory (MB): peak = 1436.309 ; gain = 545.488 ; free physical = 8627 ; free virtual = 28937 | |
| --------------------------------------------------------------------------------- | |
| Finished Parallel Reinference : Time (s): cpu = 00:01:02 ; elapsed = 00:01:04 . Memory (MB): peak = 1436.309 ; gain = 545.488 ; free physical = 8627 ; free virtual = 28937 | |
| Report RTL Partitions: | |
| +-+--------------+------------+----------+ | |
| | |RTL Partition |Replication |Instances | | |
| +-+--------------+------------+----------+ | |
| +-+--------------+------------+----------+ | |
| --------------------------------------------------------------------------------- | |
| Start ROM, RAM, DSP and Shift Register Reporting | |
| --------------------------------------------------------------------------------- | |
| Block RAM: Preliminary Mapping Report (see note below) | |
| +------------------+---------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ | |
| |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | | |
| +------------------+---------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ | |
| |axi_wr_fifo | fifo_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | | |
| |red_pitaya_scope | adc_a_buf_reg | 16 K x 14(READ_FIRST) | W | | 16 K x 14(WRITE_FIRST) | | R | Port A and B | 0 | 7 | | |
| |red_pitaya_scope | adc_b_buf_reg | 16 K x 14(READ_FIRST) | W | | 16 K x 14(WRITE_FIRST) | | R | Port A and B | 0 | 7 | | |
| |red_pitaya_asg_ch | dac_buf_reg | 16 K x 14(READ_FIRST) | W | R | 16 K x 14(WRITE_FIRST) | | R | Port A and B | 0 | 7 | | |
| |red_pitaya_asg_ch | dac_buf_reg | 16 K x 14(READ_FIRST) | W | R | 16 K x 14(WRITE_FIRST) | | R | Port A and B | 0 | 7 | | |
| +------------------+---------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ | |
| Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. | |
| Distributed RAM: Preliminary Mapping Report (see note below) | |
| +--------------+------------------------------+----------------+----------------------+---------------+ | |
| |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | | |
| +--------------+------------------------------+----------------+----------------------+---------------+ | |
| |red_pitaya_ps | axi_master[1]/axi_awfifo_reg | User Attribute | 16 x 37 | RAM32M x 7 | | |
| |red_pitaya_ps | axi_master[1]/axi_wfifo_reg | User Attribute | 16 x 73 | RAM32M x 13 | | |
| |red_pitaya_ps | axi_master[0]/axi_awfifo_reg | User Attribute | 16 x 37 | RAM32M x 7 | | |
| |red_pitaya_ps | axi_master[0]/axi_wfifo_reg | User Attribute | 16 x 73 | RAM32M x 13 | | |
| +--------------+------------------------------+----------------+----------------------+---------------+ | |
| Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. | |
| DSP: Preliminary Mapping Report (see note below) | |
| +------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ | |
| |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | | |
| +------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ | |
| |red_pitaya_dfilt1 | A2*B | 25 | 14 | - | - | 39 | 1 | 0 | - | - | - | 0 | 0 | | |
| |red_pitaya_dfilt1 | C'-A2*B2 | 23 | 18 | 48 | - | 48 | 1 | 1 | 1 | - | - | 0 | 0 | | |
| |red_pitaya_dfilt1 | PCIN+A2:B2 | 30 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | | |
| |red_pitaya_dfilt1 | A2*B2 | 25 | 15 | - | - | 40 | 1 | 1 | - | - | - | 0 | 0 | | |
| |red_pitaya_dfilt1 | A2*BCIN'' | 25 | 15 | - | - | 40 | 1 | 2 | - | - | - | 0 | 0 | | |
| |red_pitaya_dfilt1 | A2*B | 25 | 14 | - | - | 39 | 1 | 0 | - | - | - | 0 | 0 | | |
| |red_pitaya_dfilt1 | C'-A2*B2 | 23 | 18 | 48 | - | 48 | 1 | 1 | 1 | - | - | 0 | 0 | | |
| |red_pitaya_dfilt1 | PCIN+A2:B2 | 30 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | | |
| |red_pitaya_dfilt1 | A2*B2 | 25 | 15 | - | - | 40 | 1 | 1 | - | - | - | 0 | 0 | | |
| |red_pitaya_dfilt1 | A2*BCIN'' | 25 | 15 | - | - | 40 | 1 | 2 | - | - | - | 0 | 0 | | |
| |red_pitaya_asg_ch | (A*B'')' | 15 | 14 | - | - | 29 | 0 | 2 | - | - | - | 1 | 0 | | |
| |red_pitaya_asg_ch | (A*B'')' | 15 | 14 | - | - | 29 | 0 | 2 | - | - | - | 1 | 0 | | |
| |red_pitaya_pid | C'+((D'-A)*B2)' | 14 | 14 | 32 | 14 | 33 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | | |
| |red_pitaya_pid | (D'-A)*B2 | 14 | 14 | - | 14 | 29 | 0 | 1 | - | 1 | 1 | 0 | 0 | | |
| |red_pitaya_pid | (D'-A)*B2 | 14 | 14 | - | 14 | 29 | 0 | 1 | - | 1 | 1 | 0 | 0 | | |
| |red_pitaya_pid | C'+((D'-A)*B2)' | 14 | 14 | 32 | 14 | 33 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | | |
| |red_pitaya_pid | (D'-A)*B2 | 14 | 14 | - | 14 | 29 | 0 | 1 | - | 1 | 1 | 0 | 0 | | |
| |red_pitaya_pid | (D'-A)*B2 | 14 | 14 | - | 14 | 29 | 0 | 1 | - | 1 | 1 | 0 | 0 | | |
| |red_pitaya_pid | C'+((D'-A)*B2)' | 14 | 14 | 32 | 14 | 33 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | | |
| |red_pitaya_pid | (D'-A)*B2 | 14 | 14 | - | 14 | 29 | 0 | 1 | - | 1 | 1 | 0 | 0 | | |
| |red_pitaya_pid | (D'-A)*B2 | 14 | 14 | - | 14 | 29 | 0 | 1 | - | 1 | 1 | 0 | 0 | | |
| |red_pitaya_pid | C'+((D'-A)*B2)' | 14 | 14 | 32 | 14 | 33 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | | |
| |red_pitaya_pid | (D'-A)*B2 | 14 | 14 | - | 14 | 29 | 0 | 1 | - | 1 | 1 | 0 | 0 | | |
| |red_pitaya_pid | (D'-A)*B2 | 14 | 14 | - | 14 | 29 | 0 | 1 | - | 1 | 1 | 0 | 0 | | |
| +------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ | |
| Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. | |
| --------------------------------------------------------------------------------- | |
| Finished ROM, RAM, DSP and Shift Register Reporting | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Area Optimization | |
| --------------------------------------------------------------------------------- | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[0]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[1]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[2]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[3]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[4]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[5]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[6]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[7]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[8]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[9]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[10]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[11]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[12]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[13]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[14]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[15]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'red_pitaya_dfilt1:/r01_reg_reg[16]' (FDR) to 'red_pitaya_dfilt1:/r01_reg_reg[17]' | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (red_pitaya_dfilt1:/\r01_reg_reg[17] ) | |
| INFO: [Synth 8-3886] merging instance 'i_asg/ch[0]/ext_trig_in_reg[0]' (FDR) to 'i_asg/ch[1]/ext_trig_in_reg[0]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/ch[0]/ext_trig_in_reg[1]' (FDR) to 'i_asg/ch[1]/ext_trig_in_reg[1]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_b_dat_reg[13]' (FDE) to 'i_scope/axi_b_dat_reg[14]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_b_dat_reg[14]' (FDE) to 'i_scope/axi_b_dat_reg[15]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_b_dat_reg[29]' (FDE) to 'i_scope/axi_b_dat_reg[30]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_b_dat_reg[30]' (FDE) to 'i_scope/axi_b_dat_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_b_dat_reg[45]' (FDE) to 'i_scope/axi_b_dat_reg[46]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_b_dat_reg[46]' (FDE) to 'i_scope/axi_b_dat_reg[47]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_b_dat_reg[61]' (FDE) to 'i_scope/axi_b_dat_reg[62]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_b_dat_reg[62]' (FDE) to 'i_scope/axi_b_dat_reg[63]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_a_dat_reg[13]' (FDE) to 'i_scope/axi_a_dat_reg[14]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_a_dat_reg[14]' (FDE) to 'i_scope/axi_a_dat_reg[15]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_a_dat_reg[29]' (FDE) to 'i_scope/axi_a_dat_reg[30]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_a_dat_reg[30]' (FDE) to 'i_scope/axi_a_dat_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_a_dat_reg[45]' (FDE) to 'i_scope/axi_a_dat_reg[46]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_a_dat_reg[46]' (FDE) to 'i_scope/axi_a_dat_reg[47]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_a_dat_reg[61]' (FDE) to 'i_scope/axi_a_dat_reg[62]' | |
| INFO: [Synth 8-3886] merging instance 'i_scope/axi_a_dat_reg[62]' (FDE) to 'i_scope/axi_a_dat_reg[63]' | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (axi_wr_fifo:/axi_wfixed_o_reg) | |
| INFO: [Synth 8-3886] merging instance 'axi_wr_fifo:/axi_wsel_o_reg[0]' (FDSE) to 'axi_wr_fifo:/axi_wsel_o_reg[1]' | |
| INFO: [Synth 8-3886] merging instance 'axi_wr_fifo:/axi_wsel_o_reg[1]' (FDSE) to 'axi_wr_fifo:/axi_wsel_o_reg[2]' | |
| INFO: [Synth 8-3886] merging instance 'axi_wr_fifo:/axi_wsel_o_reg[2]' (FDSE) to 'axi_wr_fifo:/axi_wsel_o_reg[3]' | |
| INFO: [Synth 8-3886] merging instance 'axi_wr_fifo:/axi_wsel_o_reg[3]' (FDSE) to 'axi_wr_fifo:/axi_wsel_o_reg[4]' | |
| INFO: [Synth 8-3886] merging instance 'axi_wr_fifo:/axi_wsel_o_reg[4]' (FDSE) to 'axi_wr_fifo:/axi_wsel_o_reg[5]' | |
| INFO: [Synth 8-3886] merging instance 'axi_wr_fifo:/axi_wsel_o_reg[5]' (FDSE) to 'axi_wr_fifo:/axi_wsel_o_reg[6]' | |
| INFO: [Synth 8-3886] merging instance 'axi_wr_fifo:/axi_wsel_o_reg[6]' (FDSE) to 'axi_wr_fifo:/axi_wsel_o_reg[7]' | |
| INFO: [Synth 8-3333] propagating constant 1 across sequential element (axi_wr_fifo:/\axi_wsel_o_reg[7] ) | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[0]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[1]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[0]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[1]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[1]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[16]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[1]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[16]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[16]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[16]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[17]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[17]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[18]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[17]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[18]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[18]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[19]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[18]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[19]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[19]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[20]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[19]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[20]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[20]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[21]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[20]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[21]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[21]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[22]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[21]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[22]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[22]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[23]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[22]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[23]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[23]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[24]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[23]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[24]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[24]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[25]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[24]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[25]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[25]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[26]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[25]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[26]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[26]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[27]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[26]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[27]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[27]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[28]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[27]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[28]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[28]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[29]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[28]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[29]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[29]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[30]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[29]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[30]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[30]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[30]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_b_rpnt_rd_reg[30]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_asg/buf_a_rpnt_rd_reg[31]' (FDE) to 'i_asg/buf_b_rpnt_rd_reg[31]' | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_asg/\buf_b_rpnt_rd_reg[31] ) | |
| INFO: [Synth 8-3886] merging instance 'i_ps/axi_master[1]/nxt_burst_rdy_reg__0' (FDSE) to 'i_ps/axi_master[0]/nxt_burst_rdy_reg__0' | |
| INFO: [Synth 8-3333] propagating constant 1 across sequential element (i_ps/\axi_master[0]/nxt_burst_rdy_reg__0 ) | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[14]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[15]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[16]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[17]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[18]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[19]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[20]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[21]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[22]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[23]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[24]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_ams/sys_rdata_reg[24]' (FDE) to 'i_ams/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[25]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_ams/sys_rdata_reg[25]' (FDE) to 'i_ams/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[26]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_ams/sys_rdata_reg[26]' (FDE) to 'i_ams/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[27]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_ams/sys_rdata_reg[27]' (FDE) to 'i_ams/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[28]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_ams/sys_rdata_reg[28]' (FDE) to 'i_ams/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_pid/sys_rdata_reg[29]' (FDE) to 'i_pid/sys_rdata_reg[31]' | |
| INFO: [Synth 8-3886] merging instance 'i_ams/sys_rdata_reg[29]' (FDE) to 'i_ams/sys_rdata_reg[31]' | |
| INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_pid/\sys_rdata_reg[31] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_ams/\sys_rdata_reg[31] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_ps/\axi_master[1]/axi_awburst_o_reg[1] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_ps/\axi_master[1]/axi_arvalid_o_reg ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_ps/\axi_master[0]/axi_awburst_o_reg[1] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_ps/\axi_master[0]/axi_arvalid_o_reg ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_ps/\axi_master[0]/axi_arburst_o_reg[0] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_ps/\axi_master[0]/axi_arburst_o_reg[1] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_ps/\axi_master[0]/axi_araddr_o_reg[31] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_ps/\axi_slave_gp0/axi_bresp_o_reg[0] ) | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/wr_awaddr_reg[31]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/wr_awaddr_reg[30]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/wr_awaddr_reg[29]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/wr_awaddr_reg[28]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/wr_awaddr_reg[27]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/wr_awaddr_reg[26]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/wr_awaddr_reg[25]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/wr_awaddr_reg[24]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/wr_awaddr_reg[23]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/rd_araddr_reg[31]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/rd_araddr_reg[30]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/rd_araddr_reg[29]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/rd_araddr_reg[28]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/rd_araddr_reg[27]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/rd_araddr_reg[26]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/rd_araddr_reg[25]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/rd_araddr_reg[24]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/rd_araddr_reg[23]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_slave_gp0/sys_sel_o_reg[0]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_awburst_o_reg[1]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_arvalid_o_reg) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/sys_werr_o_reg) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_awburst_o_reg[1]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_arvalid_o_reg) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/sys_werr_o_reg) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/nxt_burst_rdy_reg__0) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/nxt_burst_rdy_reg__0) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[31]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_arlen_o_reg[0]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_arlen_o_reg[1]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_arlen_o_reg[2]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_arlen_o_reg[3]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_arburst_o_reg[0]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_arburst_o_reg[0]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_arburst_o_reg[1]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_arburst_o_reg[1]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[0]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[1]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[2]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[3]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[4]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[5]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[6]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[7]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[8]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[9]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[10]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[11]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[12]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[13]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[14]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[15]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[16]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[17]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[18]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[19]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[20]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[21]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[22]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[23]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[24]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[25]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[26]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[27]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[28]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[29]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[1]/axi_araddr_o_reg[30]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_arlen_o_reg[3]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_arlen_o_reg[0]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_arlen_o_reg[1]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_arlen_o_reg[2]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[0]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[1]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[2]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[3]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[4]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[5]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[6]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[7]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[8]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[9]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[10]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[11]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[12]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[13]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[14]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[15]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[16]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[17]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[18]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[19]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[20]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[21]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[22]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[23]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[24]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[25]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[26]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[27]) is unused and will be removed from module red_pitaya_ps. | |
| WARNING: [Synth 8-3332] Sequential element (axi_master[0]/axi_araddr_o_reg[28]) is unused and will be removed from module red_pitaya_ps. | |
| INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_ps/\system_i/system_i /xadc/inst/\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[1] ) | |
| INFO: [Synth 8-3333] propagating constant 1 across sequential element (i_scope/i_wr1/\sys_trig_size_r_reg[3] ) | |
| INFO: [Synth 8-3333] propagating constant 1 across sequential element (i_scope/i_wr0/\sys_trig_size_r_reg[3] ) | |
| --------------------------------------------------------------------------------- | |
| Finished Area Optimization : Time (s): cpu = 00:01:27 ; elapsed = 00:01:29 . Memory (MB): peak = 1436.312 ; gain = 545.492 ; free physical = 8580 ; free virtual = 28892 | |
| --------------------------------------------------------------------------------- | |
| Finished Parallel Area Optimization : Time (s): cpu = 00:01:27 ; elapsed = 00:01:29 . Memory (MB): peak = 1436.312 ; gain = 545.492 ; free physical = 8580 ; free virtual = 28892 | |
| Report RTL Partitions: | |
| +-+--------------+------------+----------+ | |
| | |RTL Partition |Replication |Instances | | |
| +-+--------------+------------+----------+ | |
| +-+--------------+------------+----------+ | |
| --------------------------------------------------------------------------------- | |
| Start Timing Optimization | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Applying XDC Timing Constraints | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:38 ; elapsed = 00:01:41 . Memory (MB): peak = 1716.305 ; gain = 825.484 ; free physical = 8279 ; free virtual = 28598 | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Timing Optimization : Time (s): cpu = 00:01:43 ; elapsed = 00:01:46 . Memory (MB): peak = 1757.328 ; gain = 866.508 ; free physical = 8235 ; free virtual = 28554 | |
| --------------------------------------------------------------------------------- | |
| Report RTL Partitions: | |
| +-+--------------+------------+----------+ | |
| | |RTL Partition |Replication |Instances | | |
| +-+--------------+------------+----------+ | |
| +-+--------------+------------+----------+ | |
| --------------------------------------------------------------------------------- | |
| Start Technology Mapping | |
| --------------------------------------------------------------------------------- | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/i_wr0/fifo_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/i_wr1/fifo_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/adc_a_buf_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/adc_a_buf_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/adc_a_buf_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/adc_a_buf_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/adc_a_buf_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/adc_a_buf_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/adc_a_buf_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/adc_b_buf_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/adc_b_buf_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/adc_b_buf_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/adc_b_buf_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/adc_b_buf_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/adc_b_buf_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_scope/adc_b_buf_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_asg/ch[1]/dac_buf_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_asg/ch[1]/dac_buf_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_asg/ch[1]/dac_buf_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_asg/ch[1]/dac_buf_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_asg/ch[1]/dac_buf_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_asg/ch[1]/dac_buf_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_asg/ch[1]/dac_buf_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_asg/ch[0]/dac_buf_reg_0 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_asg/ch[0]/dac_buf_reg_1 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_asg/ch[0]/dac_buf_reg_2 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_asg/ch[0]/dac_buf_reg_3 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_asg/ch[0]/dac_buf_reg_4 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_asg/ch[0]/dac_buf_reg_5 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| INFO: [Synth 8-4480] The timing for the instance i_asg/ch[0]/dac_buf_reg_6 (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. | |
| --------------------------------------------------------------------------------- | |
| Finished Technology Mapping : Time (s): cpu = 00:01:53 ; elapsed = 00:01:55 . Memory (MB): peak = 1816.312 ; gain = 925.492 ; free physical = 8175 ; free virtual = 28494 | |
| --------------------------------------------------------------------------------- | |
| Finished Parallel Technology Mapping Optimization : Time (s): cpu = 00:01:53 ; elapsed = 00:01:55 . Memory (MB): peak = 1816.312 ; gain = 925.492 ; free physical = 8175 ; free virtual = 28494 | |
| Report RTL Partitions: | |
| +-+--------------+------------+----------+ | |
| | |RTL Partition |Replication |Instances | | |
| +-+--------------+------------+----------+ | |
| +-+--------------+------------+----------+ | |
| Finished Parallel Synthesis Optimization : Time (s): cpu = 00:01:53 ; elapsed = 00:01:55 . Memory (MB): peak = 1816.312 ; gain = 925.492 ; free physical = 8175 ; free virtual = 28494 | |
| --------------------------------------------------------------------------------- | |
| Start IO Insertion | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Flattening Before IO Insertion | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Flattening Before IO Insertion | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Final Netlist Cleanup | |
| --------------------------------------------------------------------------------- | |
| INFO: [Synth 8-5365] Flop inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/aresetn_d_reg[1] is being inverted and renamed to inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar_pipe/aresetn_d_reg[1]_inv. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 10 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/cnt_read [0]. Fanout reduced from 21 to 7 by creating 3 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 10 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/cnt_read [1]. Fanout reduced from 20 to 7 by creating 2 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 10 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/cnt_read [2]. Fanout reduced from 18 to 7 by creating 2 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 10 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/cnt_read [3]. Fanout reduced from 17 to 7 by creating 2 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 10 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/cnt_read [4]. Fanout reduced from 16 to 7 by creating 2 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 10 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/cnt_read [1]. Fanout reduced from 27 to 7 by creating 3 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 10 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/cnt_read [0]. Fanout reduced from 28 to 10 by creating 2 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 10 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/cnt_read [0]. Fanout reduced from 44 to 9 by creating 5 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 10 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/cnt_read [2]. Fanout reduced from 41 to 9 by creating 4 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 10 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/cnt_read [1]. Fanout reduced from 43 to 9 by creating 4 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 10 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/cnt_read [3]. Fanout reduced from 40 to 9 by creating 4 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 10 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/cnt_read [4]. Fanout reduced from 39 to 9 by creating 4 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 20 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/state [1]. Fanout reduced from 25 to 13 by creating 1 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 20 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/state [0]. Fanout reduced from 25 to 13 by creating 1 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 20 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/state [1]. Fanout reduced from 23 to 12 by creating 1 replicas. | |
| INFO: [Synth 8-4618] Found max_fanout attribute set to 20 on net \inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/state [0]. Fanout reduced from 23 to 12 by creating 1 replicas. | |
| --------------------------------------------------------------------------------- | |
| Finished Final Netlist Cleanup | |
| --------------------------------------------------------------------------------- | |
| INFO: [Synth 8-4560] design has 9 instantiated BUFGs while the available bufg limit from the part is 8 | |
| --------------------------------------------------------------------------------- | |
| Finished IO Insertion : Time (s): cpu = 00:01:55 ; elapsed = 00:01:58 . Memory (MB): peak = 1816.312 ; gain = 925.492 ; free physical = 8175 ; free virtual = 28494 | |
| --------------------------------------------------------------------------------- | |
| Report Check Netlist: | |
| +------+------------------+-------+---------+-------+------------------+ | |
| | |Item |Errors |Warnings |Status |Description | | |
| +------+------------------+-------+---------+-------+------------------+ | |
| |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | | |
| +------+------------------+-------+---------+-------+------------------+ | |
| --------------------------------------------------------------------------------- | |
| Start Renaming Generated Instances | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Renaming Generated Instances : Time (s): cpu = 00:01:56 ; elapsed = 00:01:58 . Memory (MB): peak = 1816.312 ; gain = 925.492 ; free physical = 8175 ; free virtual = 28494 | |
| --------------------------------------------------------------------------------- | |
| Report RTL Partitions: | |
| +-+--------------+------------+----------+ | |
| | |RTL Partition |Replication |Instances | | |
| +-+--------------+------------+----------+ | |
| +-+--------------+------------+----------+ | |
| --------------------------------------------------------------------------------- | |
| Start Rebuilding User Hierarchy | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:58 ; elapsed = 00:02:00 . Memory (MB): peak = 1816.312 ; gain = 925.492 ; free physical = 8174 ; free virtual = 28493 | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Renaming Generated Ports | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Renaming Generated Ports : Time (s): cpu = 00:01:58 ; elapsed = 00:02:00 . Memory (MB): peak = 1816.312 ; gain = 925.492 ; free physical = 8174 ; free virtual = 28493 | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Handling Custom Attributes | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Handling Custom Attributes : Time (s): cpu = 00:01:58 ; elapsed = 00:02:01 . Memory (MB): peak = 1816.312 ; gain = 925.492 ; free physical = 8174 ; free virtual = 28493 | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Renaming Generated Nets | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Renaming Generated Nets : Time (s): cpu = 00:01:58 ; elapsed = 00:02:01 . Memory (MB): peak = 1816.312 ; gain = 925.492 ; free physical = 8174 ; free virtual = 28493 | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start ROM, RAM, DSP and Shift Register Reporting | |
| --------------------------------------------------------------------------------- | |
| Static Shift Register Report: | |
| +---------------+-------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ | |
| |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | | |
| +---------------+-------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ | |
| |red_pitaya_top | i_scope/adc_rval_reg[3] | 4 | 1 | YES | NO | YES | 1 | 0 | | |
| +---------------+-------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ | |
| Dynamic Shift Register Report: | |
| +------------+----------------+--------+------------+--------+---------+--------+--------+--------+ | |
| |Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | | |
| +------------+----------------+--------+------------+--------+---------+--------+--------+--------+ | |
| |dsrl | memory_reg[3] | 4 | 20 | 20 | 0 | 0 | 0 | 0 | | |
| |dsrl__1 | memory_reg[3] | 4 | 2 | 2 | 0 | 0 | 0 | 0 | | |
| |dsrl__2 | memory_reg[31] | 32 | 34 | 0 | 34 | 0 | 0 | 0 | | |
| |dsrl__3 | memory_reg[31] | 32 | 13 | 0 | 13 | 0 | 0 | 0 | | |
| +------------+----------------+--------+------------+--------+---------+--------+--------+--------+ | |
| --------------------------------------------------------------------------------- | |
| Finished ROM, RAM, DSP and Shift Register Reporting | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Writing Synthesis Report | |
| --------------------------------------------------------------------------------- | |
| Report BlackBoxes: | |
| +-+--------------+----------+ | |
| | |BlackBox name |Instances | | |
| +-+--------------+----------+ | |
| +-+--------------+----------+ | |
| Report Cell Usage: | |
| +------+-----------+------+ | |
| | |Cell |Count | | |
| +------+-----------+------+ | |
| |1 |BIBUF | 130| | |
| |2 |BUFG | 14| | |
| |3 |CARRY4 | 425| | |
| |4 |DNA_PORT | 1| | |
| |5 |DSP48E1_1 | 4| | |
| |6 |DSP48E1_10 | 2| | |
| |7 |DSP48E1_2 | 2| | |
| |8 |DSP48E1_3 | 2| | |
| |9 |DSP48E1_5 | 3| | |
| |10 |DSP48E1_7 | 1| | |
| |11 |DSP48E1_8 | 8| | |
| |12 |DSP48E1_9 | 2| | |
| |13 |LUT1 | 572| | |
| |14 |LUT2 | 876| | |
| |15 |LUT3 | 1064| | |
| |16 |LUT4 | 915| | |
| |17 |LUT5 | 990| | |
| |18 |LUT6 | 1480| | |
| |19 |MUXF7 | 36| | |
| |20 |ODDR | 18| | |
| |21 |PLLE2_ADV | 1| | |
| |22 |PS7 | 1| | |
| |23 |RAM32M | 40| | |
| |24 |RAMB36E1 | 2| | |
| |25 |RAMB36E1_1 | 28| | |
| |26 |SRL16 | 1| | |
| |27 |SRL16E | 23| | |
| |28 |SRLC32E | 47| | |
| |29 |XADC | 1| | |
| |30 |FDR | 8| | |
| |31 |FDRE | 4801| | |
| |32 |FDSE | 245| | |
| |33 |IBUF | 36| | |
| |34 |IBUFDS | 1| | |
| |35 |IOBUF | 16| | |
| |36 |OBUF | 35| | |
| |37 |OBUFT | 2| | |
| +------+-----------+------+ | |
| Report Instance Areas: | |
| +------+---------------------------------------------------+--------------------------------------------------------------+------+ | |
| | |Instance |Module |Cells | | |
| +------+---------------------------------------------------+--------------------------------------------------------------+------+ | |
| |1 |top | | 11833| | |
| |2 | i_ams |red_pitaya_ams | 145| | |
| |3 | \pwm[0] |red_pitaya_pwm | 104| | |
| |4 | \pwm[1] |red_pitaya_pwm_0 | 105| | |
| |5 | \pwm[2] |red_pitaya_pwm_1 | 104| | |
| |6 | \pwm[3] |red_pitaya_pwm_2 | 104| | |
| |7 | i_asg |red_pitaya_asg | 2086| | |
| |8 | \ch[0] |red_pitaya_asg_ch | 752| | |
| |9 | \ch[1] |red_pitaya_asg_ch_14 | 754| | |
| |10 | i_hk |red_pitaya_hk | 243| | |
| |11 | i_pid |red_pitaya_pid | 1223| | |
| |12 | i_pid11 |red_pitaya_pid_block | 220| | |
| |13 | i_pid12 |red_pitaya_pid_block_11 | 201| | |
| |14 | i_pid21 |red_pitaya_pid_block_12 | 201| | |
| |15 | i_pid22 |red_pitaya_pid_block_13 | 220| | |
| |16 | i_ps |red_pitaya_ps | 3372| | |
| |17 | \axi_master[0] |axi_master | 225| | |
| |18 | \axi_master[1] |axi_master_5 | 225| | |
| |19 | axi_slave_gp0 |axi_slave | 971| | |
| |20 | system_i |system_wrapper | 1946| | |
| |21 | system_i |system | 1933| | |
| |22 | axi_protocol_converter_0 |system_axi_protocol_converter_0_0 | 1191| | |
| |23 | inst |axi_protocol_converter_v2_1_8_axi_protocol_converter | 1191| | |
| |24 | \gen_axilite.gen_b2s_conv.axilite_b2s |axi_protocol_converter_v2_1_8_b2s | 1191| | |
| |25 | \RD.ar_channel_0 |axi_protocol_converter_v2_1_8_b2s_ar_channel | 181| | |
| |26 | ar_cmd_fsm_0 |axi_protocol_converter_v2_1_8_b2s_rd_cmd_fsm | 27| | |
| |27 | cmd_translator_0 |axi_protocol_converter_v2_1_8_b2s_cmd_translator_8 | 142| | |
| |28 | incr_cmd_0 |axi_protocol_converter_v2_1_8_b2s_incr_cmd_9 | 48| | |
| |29 | wrap_cmd_0 |axi_protocol_converter_v2_1_8_b2s_wrap_cmd_10 | 89| | |
| |30 | \RD.r_channel_0 |axi_protocol_converter_v2_1_8_b2s_r_channel | 124| | |
| |31 | rd_data_fifo_0 |axi_protocol_converter_v2_1_8_b2s_simple_fifo__parameterized1 | 72| | |
| |32 | transaction_fifo_0 |axi_protocol_converter_v2_1_8_b2s_simple_fifo__parameterized2 | 38| | |
| |33 | SI_REG |axi_register_slice_v2_1_8_axi_register_slice | 627| | |
| |34 | ar_pipe |axi_register_slice_v2_1_8_axic_register_slice | 217| | |
| |35 | aw_pipe |axi_register_slice_v2_1_8_axic_register_slice_7 | 216| | |
| |36 | b_pipe |axi_register_slice_v2_1_8_axic_register_slice__parameterized1 | 48| | |
| |37 | r_pipe |axi_register_slice_v2_1_8_axic_register_slice__parameterized2 | 146| | |
| |38 | \WR.aw_channel_0 |axi_protocol_converter_v2_1_8_b2s_aw_channel | 187| | |
| |39 | aw_cmd_fsm_0 |axi_protocol_converter_v2_1_8_b2s_wr_cmd_fsm | 33| | |
| |40 | cmd_translator_0 |axi_protocol_converter_v2_1_8_b2s_cmd_translator | 138| | |
| |41 | incr_cmd_0 |axi_protocol_converter_v2_1_8_b2s_incr_cmd | 46| | |
| |42 | wrap_cmd_0 |axi_protocol_converter_v2_1_8_b2s_wrap_cmd | 88| | |
| |43 | \WR.b_channel_0 |axi_protocol_converter_v2_1_8_b2s_b_channel | 70| | |
| |44 | bid_fifo_0 |axi_protocol_converter_v2_1_8_b2s_simple_fifo | 38| | |
| |45 | bresp_fifo_0 |axi_protocol_converter_v2_1_8_b2s_simple_fifo__parameterized0 | 8| | |
| |46 | proc_sys_reset |system_proc_sys_reset_0 | 62| | |
| |47 | U0 |proc_sys_reset | 62| | |
| |48 | EXT_LPF |lpf | 19| | |
| |49 | \ACTIVE_LOW_AUX.ACT_LO_AUX |cdc_sync | 6| | |
| |50 | \ACTIVE_LOW_EXT.ACT_LO_EXT |cdc_sync_6 | 5| | |
| |51 | SEQ |sequence_psr | 38| | |
| |52 | SEQ_COUNTER |upcnt_n | 13| | |
| |53 | processing_system7 |system_processing_system7_0 | 247| | |
| |54 | inst |processing_system7_v5_5_processing_system7 | 247| | |
| |55 | xadc |system_xadc_0 | 433| | |
| |56 | inst |system_xadc_0_axi_xadc | 433| | |
| |57 | AXI_LITE_IPIF_I |system_xadc_0_axi_lite_ipif | 189| | |
| |58 | I_SLAVE_ATTACHMENT |system_xadc_0_slave_attachment | 189| | |
| |59 | I_DECODER |system_xadc_0_address_decoder | 132| | |
| |60 | AXI_XADC_CORE_I |system_xadc_0_xadc_core_drp | 77| | |
| |61 | \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I |system_xadc_0_interrupt_control | 98| | |
| |62 | SOFT_RESET_I |system_xadc_0_soft_reset | 36| | |
| |63 | xlconstant |system_xlconstant_0 | 0| | |
| |64 | i_scope |red_pitaya_scope | 4142| | |
| |65 | i_dfilt1_cha |red_pitaya_dfilt1 | 269| | |
| |66 | i_dfilt1_chb |red_pitaya_dfilt1_3 | 270| | |
| |67 | i_wr0 |axi_wr_fifo | 621| | |
| |68 | i_wr1 |axi_wr_fifo_4 | 621| | |
| |69 | pll |red_pitaya_pll | 2| | |
| +------+---------------------------------------------------+--------------------------------------------------------------+------+ | |
| --------------------------------------------------------------------------------- | |
| Finished Writing Synthesis Report : Time (s): cpu = 00:01:58 ; elapsed = 00:02:01 . Memory (MB): peak = 1816.312 ; gain = 925.492 ; free physical = 8174 ; free virtual = 28493 | |
| --------------------------------------------------------------------------------- | |
| Synthesis finished with 0 errors, 0 critical warnings and 664 warnings. | |
| Synthesis Optimization Runtime : Time (s): cpu = 00:01:47 ; elapsed = 00:01:49 . Memory (MB): peak = 1816.312 ; gain = 626.949 ; free physical = 8174 ; free virtual = 28493 | |
| Synthesis Optimization Complete : Time (s): cpu = 00:01:58 ; elapsed = 00:02:01 . Memory (MB): peak = 1816.320 ; gain = 925.500 ; free physical = 8175 ; free virtual = 28495 | |
| INFO: [Project 1-571] Translating synthesized netlist | |
| INFO: [Netlist 29-17] Analyzing 601 Unisim elements for replacement | |
| INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds | |
| INFO: [Project 1-570] Preparing netlist for logic optimization | |
| INFO: [Opt 31-140] Inserted 2 IBUFs to IO ports without IO buffers. | |
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |
| INFO: [Project 1-111] Unisim Transformation Summary: | |
| A total of 65 instances were transformed. | |
| FDR => FDRE: 8 instances | |
| IOBUF => IOBUF (IBUF, OBUFT): 16 instances | |
| RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 40 instances | |
| SRL16 => SRL16E: 1 instances | |
| INFO: [Common 17-83] Releasing license: Synthesis | |
| 577 Infos, 261 Warnings, 6 Critical Warnings and 0 Errors encountered. | |
| synth_design completed successfully | |
| synth_design: Time (s): cpu = 00:02:01 ; elapsed = 00:02:03 . Memory (MB): peak = 1816.320 ; gain = 847.000 ; free physical = 8173 ; free virtual = 28494 | |
| report_utilization: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1848.332 ; gain = 0.000 ; free physical = 8169 ; free virtual = 28492 | |
| INFO: [Common 17-206] Exiting Vivado at Sun Apr 24 22:03:48 2016... |
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