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Created Sep 3, 2014
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>>> Opening project: /home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom/u2plus.xise
Changed current working directory to the project directory:
"/home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom"
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core 'fifo_xlnx_32x36_2clk' do
not match the ISE project settings.
Family mismatch "Spartan3" vs. "Spartan-3A DSP"
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
'fifo_xlnx_512x36_2clk_36to18' do not match the ISE project settings.
Family mismatch "Spartan3" vs. "Spartan-3A DSP"
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
'fifo_xlnx_512x36_2clk_18to36' do not match the ISE project settings.
Family mismatch "Spartan3" vs. "Spartan-3A DSP"
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:692 - The device settings for core
'fifo_xlnx_512x36_2clk_prog_full' do not match the ISE project settings.
Family mismatch "Spartan3" vs. "Spartan-3A DSP"
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/CRC16_D16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/atr_controller16.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/bin2gray.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/bootram.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/dbsm.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/dcache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/decoder_3_8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/double_buffer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/dpram32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/fifo_to_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/gpio_atr.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/gray2bin.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/gray_send.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/icache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/longfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/medfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/mux4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/mux8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/nsgpio16LE.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/oneshot_2clk.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/pic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/priority_enc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/quad_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_2port.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harv_cache.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_harvard2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/ram_loader.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/reset_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/s3a_icap_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/sd_spi_wb.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/setting_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_16LE.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_bus_crossclock.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/settings_fifo_ctrl.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_i2c_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_spi_core.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/simple_uart_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/srl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/system_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/user_settings.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_1master.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_bridge_16_32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/control_lib/wb_readback_mux_16LE.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/ext_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_fifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/nobl_if.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/extramfifo/refill_randomizer.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/add_routing_header.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/buffer_int2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/buffer_pool.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/crossbar36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/dsp_framer36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_pad.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo19_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_demux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_mux.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo36_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_2clock_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_cascade.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_long.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_pacer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/fifo_short.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/ll8_shortfifo.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo19.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/ll8_to_fifo36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x3.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_dispatcher36_x4.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_generator32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_padder36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_router.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/packet_verifier32.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/splitter36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/fifo/valve36.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/decode_8b10b.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/8b10b/encode_8b10b.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v\"
into library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
file
"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
line 131
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v\
" into library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
file
"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
line 73
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v' in
file "/home/usrp/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v"
line 77
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v" line 41
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v" line 45
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v\" into
library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v' in file
"/home/usrp/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v" line 46
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_config.vhd" into library
work
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpupkg.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd" into
library work
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd" into
library work
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd" into
library work
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/acc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_and_round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/add2_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_dec_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_decim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_int_shifter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cic_strober.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/clip_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_stage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/cordic_z24.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/ddc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dsp_tx_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_16to8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/dspengine_8to16.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/duc_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/hb_interp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipectrl.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/pipestage.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/round.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_reg.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/round_sd.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_dcoffset.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/rx_frontend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/sign_extend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_dec.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/small_hb_int.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/sdr_lib/tx_frontend.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes_fc_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/serdes/serdes_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/address_filter_promisc.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/crc.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/delay_line.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethrx_realign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/ethtx_realign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/flow_ctrl_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/ll8_to_txmac.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_clockgen.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_miim.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/rxmac_to_ll8.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_rx.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_tx.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wb.v\" into library
work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v\" into
library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/simple_timer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_64bit.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_compare.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_receiver.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_sender.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/time_sync.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/timing/timer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/top/N2x0/capture_ddrlvds.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v\" into library work
INFO:ProjectMgmt - Include file found:
'/home/usrp/uhd/fpga/usrp2/top/N2x0/bootloader.rmi' in file
"/home/usrp/uhd/fpga/usrp2/top/N2x0/u2plus_core.v" line 356
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/udp/add_onescomp.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/udp/fifo19_rxrealign.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/udp/prot_eng_tx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/udp/udp_wrapper.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/gen_context_pkt.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/trigger_context_pkt.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_pkt_gen.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_engine_glue.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_rx_framer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_chain.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_control.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_deframer.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/custom/custom_dsp_rx.v\" into library work
INFO:HDLCompiler:1574 - Analyzing Verilog file
\"/home/usrp/uhd/fpga/usrp2/vrt/vita_tx_engine_glue.v\" into library work
INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit
'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'ila' found in library 'work'
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco" line
0 (active)
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
line 0 (active)
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
36
>>> Running Process: Generate Programming File
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x40_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_16x19_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_2Kx36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_32x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v" line 36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_18to36'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_512x36_2clk_36to18'
found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco" line 0
(active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit
'fifo_xlnx_512x36_2clk_prog_full' found in library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco" line
0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'fifo_xlnx_64x36_2clk' found in
library 'work'
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco" line 0 (active)
WARNING:ProjectMgmt:495 -
"/home/usrp/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v" line 40
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'ila' found in library 'work'
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.xco" line
0 (active)
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/ila.v" line
36
WARNING:ProjectMgmt:565 - Duplicate Design Unit 'icon' found in library 'work'
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.xco"
line 0 (active)
WARNING:ProjectMgmt:495 - "/home/usrp/uhd/fpga/usrp2/extramfifo/icon.v" line
36
Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "/home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom/u2plus.xst" -ofn "/home/usrp/uhd/fpga/usrp2/top/N2x0/build-custom/u2plus.syr"
Reading design: u2plus.prj
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "../../../custom/custom_dsp_rx.v" in library work
Compiling verilog file "../../../sdr_lib/clip.v" in library work
Module <custom_dsp_rx> compiled
Compiling verilog file "../../../sdr_lib/pipestage.v" in library work
Module <clip> compiled
Compiling verilog file "../../../sdr_lib/add2_and_clip.v" in library work
Module <pipestage> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_64x36_2clk.v" in library work
Module <add2_and_clip> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_512x36_2clk.v" in library work
Module <fifo_xlnx_64x36_2clk> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_2Kx36_2clk.v" in library work
Module <fifo_xlnx_512x36_2clk> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_16x19_2clk.v" in library work
Module <fifo_xlnx_2Kx36_2clk> compiled
Compiling verilog file "../../../control_lib/ram_2port.v" in library work
Module <fifo_xlnx_16x19_2clk> compiled
Compiling verilog file "../../../simple_gemac/miim/eth_shiftreg.v" in library work
Module <ram_2port> compiled
Compiling verilog file "../../../simple_gemac/miim/eth_outputcontrol.v" in library work
Module <eth_shiftreg> compiled
Compiling verilog file "../../../simple_gemac/miim/eth_clockgen.v" in library work
Module <eth_outputcontrol> compiled
Compiling verilog file "../../../simple_gemac/delay_line.v" in library work
Module <eth_clockgen> compiled
Compiling verilog file "../../../simple_gemac/crc.v" in library work
Module <delay_line> compiled
Compiling verilog file "../../../simple_gemac/address_filter_promisc.v" in library work
Module <crc> compiled
Compiling verilog file "../../../simple_gemac/address_filter.v" in library work
Module <address_filter_promisc> compiled
Compiling verilog file "../../../sdr_lib/sign_extend.v" in library work
Module <address_filter> compiled
Compiling verilog file "../../../sdr_lib/round.v" in library work
Module <sign_extend> compiled
Compiling verilog file "../../../sdr_lib/pipectrl.v" in library work
Module <round> compiled
Compiling verilog file "../../../sdr_lib/clip_reg.v" in library work
Module <pipectrl> compiled
Compiling verilog file "../../../sdr_lib/add2_and_round.v" in library work
Module <clip_reg> compiled
Compiling verilog file "../../../sdr_lib/add2_and_clip_reg.v" in library work
Module <add2_and_round> compiled
Compiling verilog file "../../../sdr_lib/add2.v" in library work
Module <add2_and_clip_reg> compiled
Compiling verilog file "../../../fifo/fifo_short.v" in library work
Module <add2> compiled
Compiling verilog file "../../../fifo/fifo_long.v" in library work
Module <fifo_short> compiled
Compiling verilog file "../../../fifo/fifo_2clock.v" in library work
Module <fifo_long> compiled
Compiling verilog file "../../../control_lib/shortfifo.v" in library work
Module <fifo_2clock> compiled
Compiling verilog file "../../../control_lib/setting_reg.v" in library work
Module <shortfifo> compiled
Compiling verilog file "../../../control_lib/bin2gray.v" in library work
Module <setting_reg> compiled
Compiling verilog file "../../../udp/add_onescomp.v" in library work
Module <bin2gray> compiled
Compiling verilog file "../../../timing/time_compare.v" in library work
Module <add_onescomp> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac_tx.v" in library work
Module <time_compare> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac_rx.v" in library work
Module <simple_gemac_tx> compiled
Compiling verilog file "../../../simple_gemac/miim/eth_miim.v" in library work
Module <simple_gemac_rx> compiled
Compiling verilog file "../../../simple_gemac/flow_ctrl_tx.v" in library work
Module <eth_miim> compiled
Compiling verilog file "../../../sdr_lib/round_sd.v" in library work
Module <flow_ctrl_tx> compiled
Compiling verilog file "../../../sdr_lib/round_reg.v" in library work
Module <round_sd> compiled
Compiling verilog file "../../../sdr_lib/dspengine_8to16.v" in library work
Module <round_reg> compiled
Compiling verilog file "../../../sdr_lib/dspengine_16to8.v" in library work
Module <dspengine_8to16> compiled
Compiling verilog file "../../../sdr_lib/cordic_stage.v" in library work
Module <dspengine_16to8> compiled
Compiling verilog file "../../../sdr_lib/cic_int_shifter.v" in library work
Module <cordic_stage> compiled
Compiling verilog file "../../../sdr_lib/cic_dec_shifter.v" in library work
Module <cic_int_shifter> compiled
Compiling verilog file "../../../sdr_lib/add2_reg.v" in library work
Module <cic_dec_shifter> compiled
Compiling verilog file "../../../sdr_lib/add2_and_round_reg.v" in library work
Module <add2_reg> compiled
Compiling verilog file "../../../sdr_lib/acc.v" in library work
Module <add2_and_round_reg> compiled
Compiling verilog file "../../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" in library work
Compiling verilog include file "../../../opencores/i2c/rtl/verilog/i2c_master_defines.v"
Module <acc> compiled
Compiling verilog file "../../../opencores/8b10b/encode_8b10b.v" in library work
Module <i2c_master_bit_ctrl> compiled
Compiling verilog file "../../../opencores/8b10b/decode_8b10b.v" in library work
Module <encode_8b10b> compiled
Compiling verilog file "../../../fifo/splitter36.v" in library work
Module <decode_8b10b> compiled
Compiling verilog file "../../../fifo/ll8_shortfifo.v" in library work
Module <splitter36> compiled
Compiling verilog file "../../../fifo/fifo_cascade.v" in library work
Module <ll8_shortfifo> compiled
Compiling verilog file "../../../fifo/fifo_2clock_cascade.v" in library work
Module <fifo_cascade> compiled
Compiling verilog file "../../../fifo/fifo36_mux.v" in library work
Module <fifo_2clock_cascade> compiled
Compiling verilog file "../../../extramfifo/nobl_if.v" in library work
Module <fifo36_mux> compiled
Compiling verilog file "../../../control_lib/srl.v" in library work
Module <nobl_if> compiled
Compiling verilog file "../../../control_lib/reset_sync.v" in library work
Module <srl> compiled
Compiling verilog file "../../../control_lib/oneshot_2clk.v" in library work
Module <reset_sync> compiled
Compiling verilog file "../../../control_lib/medfifo.v" in library work
Module <oneshot_2clk> compiled
Compiling verilog file "../../../control_lib/dbsm.v" in library work
Module <medfifo> compiled
Module <dbsm> compiled
Compiling verilog file "../../../control_lib/CRC16_D16.v" in library work
Module <buff_sm> compiled
Compiling verilog file "../../../vrt/vita_tx_engine_glue.v" in library work
Module <CRC16_D16> compiled
Compiling verilog file "../../../vrt/vita_tx_deframer.v" in library work
Module <vita_tx_engine_glue> compiled
Compiling verilog file "../../../vrt/vita_tx_control.v" in library work
Module <vita_tx_deframer> compiled
Compiling verilog file "../../../vrt/vita_rx_framer.v" in library work
Module <vita_tx_control> compiled
Compiling verilog file "../../../vrt/vita_rx_engine_glue.v" in library work
Module <vita_rx_framer> compiled
Compiling verilog file "../../../vrt/vita_rx_control.v" in library work
Module <vita_rx_engine_glue> compiled
Compiling verilog file "../../../vrt/trigger_context_pkt.v" in library work
Module <vita_rx_control> compiled
Compiling verilog file "../../../vrt/gen_context_pkt.v" in library work
Module <trigger_context_pkt> compiled
Compiling verilog file "../../../udp/prot_eng_tx.v" in library work
Module <gen_context_pkt> compiled
Compiling verilog file "../../../udp/fifo19_rxrealign.v" in library work
Module <prot_eng_tx> compiled
Compiling verilog file "../../../timing/time_sender.v" in library work
Module <fifo19_rxrealign> compiled
Compiling verilog file "../../../timing/time_receiver.v" in library work
Module <time_sender> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac_wb.v" in library work
Module <time_receiver> compiled
Module <wb_reg> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac.v" in library work
Module <simple_gemac_wb> compiled
Compiling verilog file "../../../simple_gemac/rxmac_to_ll8.v" in library work
Module <simple_gemac> compiled
Compiling verilog file "../../../simple_gemac/ll8_to_txmac.v" in library work
Module <rxmac_to_ll8> compiled
Compiling verilog file "../../../simple_gemac/flow_ctrl_rx.v" in library work
Module <ll8_to_txmac> compiled
Compiling verilog file "../../../simple_gemac/ethtx_realign.v" in library work
Module <flow_ctrl_rx> compiled
Compiling verilog file "../../../serdes/serdes_tx.v" in library work
Module <ethtx_realign> compiled
Compiling verilog file "../../../serdes/serdes_rx.v" in library work
Module <serdes_tx> compiled
Compiling verilog file "../../../serdes/serdes_fc_tx.v" in library work
Module <serdes_rx> compiled
Compiling verilog file "../../../serdes/serdes_fc_rx.v" in library work
Module <serdes_fc_tx> compiled
Compiling verilog file "../../../sdr_lib/small_hb_int.v" in library work
Module <serdes_fc_rx> compiled
Compiling verilog file "../../../sdr_lib/small_hb_dec.v" in library work
Module <small_hb_int> compiled
Compiling verilog file "../../../sdr_lib/rx_dcoffset.v" in library work
Module <small_hb_dec> compiled
Compiling verilog file "../../../sdr_lib/hb_interp.v" in library work
Module <rx_dcoffset> compiled
Compiling verilog file "../../../sdr_lib/hb_dec.v" in library work
Module <hb_interp> compiled
Compiling verilog file "../../../sdr_lib/dsp_tx_glue.v" in library work
Module <hb_dec> compiled
Compiling verilog file "../../../sdr_lib/dsp_rx_glue.v" in library work
Module <dsp_tx_glue> compiled
Compiling verilog file "../../../sdr_lib/cordic_z24.v" in library work
Module <dsp_rx_glue> compiled
Compiling verilog file "../../../sdr_lib/cic_strober.v" in library work
Module <cordic_z24> compiled
Compiling verilog file "../../../sdr_lib/cic_interp.v" in library work
Module <cic_strober> compiled
Compiling verilog file "../../../sdr_lib/cic_decim.v" in library work
Module <cic_interp> compiled
Compiling verilog file "../../../opencores/spi/rtl/verilog/spi_shift.v" in library work
Compiling verilog include file "../../../opencores/spi/rtl/verilog/spi_defines.v"
Module <cic_decim> compiled
Compiling verilog file "../../../opencores/spi/rtl/verilog/spi_clgen.v" in library work
Compiling verilog include file "../../../opencores/spi/rtl/verilog/spi_defines.v"
Module <spi_shift> compiled
Compiling verilog file "../../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" in library work
Compiling verilog include file "../../../opencores/i2c/rtl/verilog/i2c_master_defines.v"
Module <spi_clgen> compiled
Compiling verilog file "../../../fifo/valve36.v" in library work
Module <i2c_master_byte_ctrl> compiled
Compiling verilog file "../../../fifo/packet_dispatcher36_x4.v" in library work
Module <valve36> compiled
Compiling verilog file "../../../fifo/ll8_to_fifo19.v" in library work
Module <packet_dispatcher36_x4> compiled
Compiling verilog file "../../../fifo/fifo36_to_ll8.v" in library work
Module <ll8_to_fifo19> compiled
Compiling verilog file "../../../fifo/fifo19_to_fifo36.v" in library work
Module <fifo36_to_ll8> compiled
Compiling verilog file "../../../fifo/crossbar36.v" in library work
Module <fifo19_to_fifo36> compiled
Compiling verilog file "../../../fifo/buffer_int2.v" in library work
Module <crossbar36> compiled
Compiling verilog file "../../../fifo/add_routing_header.v" in library work
Module <buffer_int2> compiled
Compiling verilog file "../../../extramfifo/refill_randomizer.v" in library work
Module <add_routing_header> compiled
Compiling verilog file "../../../extramfifo/nobl_fifo.v" in library work
Module <refill_randomizer> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_512x36_2clk_prog_full.v" in library work
Module <nobl_fifo> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_512x36_2clk_36to18.v" in library work
Module <fifo_xlnx_512x36_2clk_prog_full> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_512x36_2clk_18to36.v" in library work
Module <fifo_xlnx_512x36_2clk_36to18> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_32x36_2clk.v" in library work
Module <fifo_xlnx_512x36_2clk_18to36> compiled
Compiling verilog file "../../../coregen/fifo_xlnx_16x40_2clk.v" in library work
Module <fifo_xlnx_32x36_2clk> compiled
Compiling verilog file "../../../control_lib/simple_uart_tx.v" in library work
Module <fifo_xlnx_16x40_2clk> compiled
Compiling verilog file "../../../control_lib/simple_uart_rx.v" in library work
Module <simple_uart_tx> compiled
Compiling verilog file "../../../control_lib/priority_enc.v" in library work
Module <simple_uart_rx> compiled
Compiling verilog file "../../../control_lib/double_buffer.v" in library work
Module <priority_enc> compiled
Compiling verilog file "../../../vrt/vita_tx_chain.v" in library work
Module <double_buffer> compiled
Compiling verilog file "../../../vrt/vita_rx_chain.v" in library work
Module <vita_tx_chain> compiled
Compiling verilog file "../../../timing/time_64bit.v" in library work
Module <vita_rx_chain> compiled
Compiling verilog file "../../../simple_gemac/simple_gemac_wrapper.v" in library work
Module <time_64bit> compiled
Compiling verilog file "../../../serdes/serdes.v" in library work
Module <simple_gemac_wrapper> compiled
Compiling verilog file "../../../sdr_lib/tx_frontend.v" in library work
Module <serdes> compiled
Compiling verilog file "../../../sdr_lib/rx_frontend.v" in library work
Module <tx_frontend> compiled
Compiling verilog file "../../../sdr_lib/duc_chain.v" in library work
Module <rx_frontend> compiled
Compiling verilog file "../../../sdr_lib/ddc_chain.v" in library work
Module <duc_chain> compiled
Compiling verilog file "../../../opencores/spi/rtl/verilog/spi_top.v" in library work
Compiling verilog include file "../../../opencores/spi/rtl/verilog/spi_defines.v"
Module <ddc_chain> compiled
Compiling verilog file "../../../opencores/i2c/rtl/verilog/i2c_master_top.v" in library work
Compiling verilog include file "../../../opencores/i2c/rtl/verilog/i2c_master_defines.v"
Module <spi_top> compiled
Compiling verilog file "../../../fifo/packet_router.v" in library work
Module <i2c_master_top> compiled
Compiling verilog file "../../../extramfifo/ext_fifo.v" in library work
Module <packet_router> compiled
Compiling verilog file "../../../control_lib/wb_readback_mux.v" in library work
Module <ext_fifo> compiled
Compiling verilog file "../../../control_lib/wb_1master.v" in library work
Module <wb_readback_mux> compiled
Compiling verilog file "../../../control_lib/user_settings.v" in library work
Module <wb_1master> compiled
Compiling verilog file "../../../control_lib/system_control.v" in library work
Module <user_settings> compiled
Compiling verilog file "../../../control_lib/simple_spi_core.v" in library work
Module <system_control> compiled
Compiling verilog file "../../../control_lib/settings_fifo_ctrl.v" in library work
Module <simple_spi_core> compiled
Compiling verilog file "../../../control_lib/settings_bus_crossclock.v" in library work
Module <settings_fifo_ctrl> compiled
Compiling verilog file "../../../control_lib/settings_bus.v" in library work
Module <settings_bus_crossclock> compiled
Compiling verilog file "../../../control_lib/s3a_icap_wb.v" in library work
Module <settings_bus> compiled
Compiling verilog file "../../../control_lib/ram_harvard2.v" in library work
Module <s3a_icap_wb> compiled
Compiling verilog file "../../../control_lib/quad_uart.v" in library work
Module <ram_harvard2> compiled
Compiling verilog file "../../../control_lib/pic.v" in library work
Module <quad_uart> compiled
Compiling verilog file "../../../control_lib/gpio_atr.v" in library work
Module <pic> compiled
Compiling verilog file "../../../control_lib/bootram.v" in library work
Module <gpio_atr> compiled
Compiling verilog file "../u2plus_core.v" in library work
Module <bootram> compiled
Compiling verilog include file "../bootloader.rmi"
Compiling verilog file "../capture_ddrlvds.v" in library work
Module <u2plus_core> compiled
Compiling verilog file "../u2plus.v" in library work
Module <capture_ddrlvds> compiled
Module <u2plus> compiled
No errors in compilation
Analysis of file <"u2plus.prj"> succeeded.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_config.vhd" in Library work.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpupkg.vhd" in Library work.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd" in Library work.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd" in Library work.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd" in Library work.
Architecture behave of Entity zpu_core is up to date.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd" in Library work.
Architecture behave of Entity zpu_wb_bridge is up to date.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd" in Library work.
Architecture behave of Entity zpu_system is up to date.
Compiling vhdl file "/home/usrp/uhd/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd" in Library work.
Architecture syn of Entity zpu_wb_top is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <u2plus> in library <work>.
Analyzing hierarchy for module <capture_ddrlvds> in library <work> with parameters.
WIDTH = "00000000000000000000000000001110"
Analyzing hierarchy for module <u2plus_core> in library <work> with parameters.
CPU_BLDR_CTRL_DONE = "00000000000000000000000000000001"
CPU_BLDR_CTRL_WAIT = "00000000000000000000000000000000"
DSP_RX_FIFOSIZE = "00000000000000000000000000001010"
DSP_TX_FIFOSIZE = "00000000000000000000000000001010"
ETH_RX_FIFOSIZE = "00000000000000000000000000001011"
ETH_TX_FIFOSIZE = "00000000000000000000000000001001"
SERDES_RX_FIFOSIZE = "00000000000000000000000000001001"
SERDES_TX_FIFOSIZE = "00000000000000000000000000001001"
SR_BUF_POOL = "00000000000000000000000000010000"
SR_GPIO = "00000000000000000000000010111000"
SR_MISC = "00000000000000000000000000000000"
SR_RX_CTRL0 = "00000000000000000000000000100000"
SR_RX_CTRL1 = "00000000000000000000000001010000"
SR_RX_DSP0 = "00000000000000000000000000110000"
SR_RX_DSP1 = "00000000000000000000000001100000"
SR_RX_FRONT = "00000000000000000000000000011000"
SR_SPI_CORE = "00000000000000000000000000010100"
SR_TIME64 = "00000000000000000000000000001010"
SR_TX_CTRL = "00000000000000000000000010010000"
SR_TX_DSP = "00000000000000000000000010100000"
SR_TX_FRONT = "00000000000000000000000010000000"
SR_UDP_SM = "00000000000000000000000011000000"
SR_USER_REGS = "00000000000000000000000000001000"
aw = "00000000000000000000000000010000"
compat_num = "00000000000010100000000000000001"
dw = "00000000000000000000000000100000"
sw = "00000000000000000000000000000100"
Analyzing hierarchy for module <wb_1master> in library <work> with parameters.
aw = "00000000000000000000000000010000"
decode_w = "00000000000000000000000000001000"
dw = "00000000000000000000000000100000"
s0_addr = "00000000"
s0_mask = "11000000"
s1_addr = "01000000"
s1_mask = "11110000"
s2_addr = "01010000"
s2_mask = "11111100"
s3_addr = "01010100"
s3_mask = "11111100"
s4_addr = "01011000"
s4_mask = "11111100"
s5_addr = "01011100"
s5_mask = "11111100"
s6_addr = "01100000"
s6_mask = "11110000"
s7_addr = "01110000"
s7_mask = "11110000"
s8_addr = "10000000"
s8_mask = "11111100"
s9_addr = "10000100"
s9_mask = "11111100"
sa_addr = "10001000"
sa_mask = "11111100"
sb_addr = "10001100"
sb_mask = "11111100"
sc_addr = "10010000"
sc_mask = "11110000"
sd_addr = "10100000"
sd_mask = "11110000"
se_addr = "10110000"
se_mask = "11110000"
sf_addr = "11000000"
sf_mask = "11000000"
sw = "00000000000000000000000000000100"
Analyzing hierarchy for module <system_control> in library <work>.
Analyzing hierarchy for entity <zpu_wb_top> in library <work> (architecture <syn>) with generics.
adr_w = 16
dat_w = 32
sel_w = 4
Analyzing hierarchy for module <bootram> in library <work>.
Analyzing hierarchy for module <ram_harvard2> in library <work> with parameters.
AWIDTH = "00000000000000000000000000001110"
RAM_SIZE = "00000000000000000100000000000000"
Analyzing hierarchy for module <packet_router> in library <work> with parameters.
BUF_SIZE = "00000000000000000000000000001001"
CTRL_BASE = "00000000000000000000000000010000"
UDP_BASE = "00000000000000000000000011000000"
Analyzing hierarchy for module <simple_spi_core> in library <work> with parameters.
BASE = "00000000000000000000000000010100"
CLK_IDLE = "00000000000000000000000000000000"
CLK_INV = "00000000000000000000000000000011"
CLK_REG = "00000000000000000000000000000010"
IDLE_SEN = "00000000000000000000000000000101"
POST_IDLE = "00000000000000000000000000000100"
PRE_IDLE = "00000000000000000000000000000001"
SEN_IDLE = "111111111111111111111111"
WAIT_TRIG = "00000000000000000000000000000000"
WIDTH = "00000000000000000000000000001001"
Analyzing hierarchy for module <i2c_master_top> in library <work> with parameters.
ARST_LVL = "00000000000000000000000000000001"
Analyzing hierarchy for module <gpio_atr> in library <work> with parameters.
BASE = "00000000000000000000000010111000"
WIDTH = "00000000000000000000000000100000"
Analyzing hierarchy for module <wb_readback_mux> in library <work>.
Analyzing hierarchy for module <simple_gemac_wrapper> in library <work> with parameters.
RXFIFOSIZE = "00000000000000000000000000001011"
RX_FLOW_CTRL = "00000000000000000000000000000000"
TXFIFOSIZE = "00000000000000000000000000001001"
Analyzing hierarchy for module <settings_bus> in library <work> with parameters.
AWIDTH = "00000000000000000000000000010000"
DWIDTH = "00000000000000000000000000100000"
Analyzing hierarchy for module <settings_bus_crossclock> in library <work> with parameters.
FLOW_CTRL = "00000000000000000000000000000001"
Analyzing hierarchy for module <user_settings> in library <work> with parameters.
BASE = "00000000000000000000000000001000"
Analyzing hierarchy for module <settings_fifo_ctrl> in library <work> with parameters.
ACK_SID = "00000000000000000000000000000000"
EVENT_CMD = "00000000000000000000000000000001"
LOAD_CMD = "00000000000000000000000000000000"
PROT_DEST = "00000000000000000000000000000011"
PROT_HDR = "00000000000000000000000000000001"
READ_DATA = "00000000000000000000000000001001"
READ_HDR = "00000000000000000000000000001000"
READ_LINE0 = "00000000000000000000000000000000"
START_STATE = "00000000000000000000000000000000"
STORE_CMD = "00000000000000000000000000001011"
VITA_CID0 = "00000000000000000000000000000011"
VITA_CID1 = "00000000000000000000000000000100"
VITA_HDR = "00000000000000000000000000000001"
VITA_SID = "00000000000000000000000000000010"
VITA_TSF0 = "00000000000000000000000000000110"
VITA_TSF1 = "00000000000000000000000000000111"
VITA_TSI = "00000000000000000000000000000101"
WAIT_EOF = "00000000000000000000000000001010"
WRITE_PKT_HDR = "00000000000000000000000000000000"
WRITE_PROT_HDR = "00000000000000000000000000000000"
WRITE_RB_DATA = "00000000000000000000000000000100"
WRITE_RB_HDR = "00000000000000000000000000000011"
WRITE_VRT_HDR = "00000000000000000000000000000001"
WRITE_VRT_SID = "00000000000000000000000000000010"
XPORT_HDR = "00000000000000000000000000000001"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000010001"
width = "00000000000000000000000000000001"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000000000"
width = "00000000000000000000000000001000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000000001"
width = "00000000000000000000000000001000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000000010"
width = "00000000000000000000000000001000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000000100"
width = "00000000000000000000000000000001"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000000101"
width = "00000000000000000000000000000001"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000000011"
width = "00000000000000000000000000001000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00011110"
my_addr = "00000000000000000000000000000110"
width = "00000000000000000000000000001000"
Analyzing hierarchy for module <pic> in library <work>.
Analyzing hierarchy for module <quad_uart> in library <work> with parameters.
RXDEPTH = "00000000000000000000000000000011"
SUART_CLKDIV = "00000000000000000000000000000000"
SUART_RXCHAR = "00000000000000000000000000000100"
SUART_RXLEVEL = "00000000000000000000000000000010"
SUART_TXCHAR = "00000000000000000000000000000011"
SUART_TXLEVEL = "00000000000000000000000000000001"
TXDEPTH = "00000000000000000000000000000011"
Analyzing hierarchy for module <s3a_icap_wb> in library <work> with parameters.
ICAP_IDLE = "00000000000000000000000000000000"
ICAP_RD0 = "00000000000000000000000000000010"
ICAP_RD1 = "00000000000000000000000000000011"
ICAP_WR0 = "00000000000000000000000000000001"
ICAP_WR1 = "00000000000000000000000000000101"
Analyzing hierarchy for module <spi_top> in library <work>.
Analyzing hierarchy for module <rx_frontend> in library <work> with parameters.
BASE = "00000000000000000000000000011000"
IQCOMP_EN = "00000000000000000000000000000001"
Analyzing hierarchy for module <ddc_chain> in library <work> with parameters.
BASE = "00000000000000000000000000110000"
DSPNO = "00000000000000000000000000000000"
WIDTH = "00000000000000000000000000011000"
cwidth = "00000000000000000000000000011001"
zwidth = "00000000000000000000000000011000"
Analyzing hierarchy for module <vita_rx_chain> in library <work> with parameters.
BASE = "00000000000000000000000000100000"
DSP_NUMBER = "00000000000000000000000000000000"
FIFOSIZE = "00000000000000000000000000001010"
PROT_ENG_FLAGS = "00000000000000000000000000000001"
UNIT = "00000000000000000000000000000000"
Analyzing hierarchy for module <ddc_chain> in library <work> with parameters.
BASE = "00000000000000000000000001100000"
DSPNO = "00000000000000000000000000000001"
WIDTH = "00000000000000000000000000011000"
cwidth = "00000000000000000000000000011001"
zwidth = "00000000000000000000000000011000"
Analyzing hierarchy for module <vita_rx_chain> in library <work> with parameters.
BASE = "00000000000000000000000001010000"
DSP_NUMBER = "00000000000000000000000000000001"
FIFOSIZE = "00000000000000000000000000001010"
PROT_ENG_FLAGS = "00000000000000000000000000000001"
UNIT = "00000000000000000000000000000010"
Analyzing hierarchy for module <ext_fifo> in library <work> with parameters.
EXT_WIDTH = "00000000000000000000000000100100"
FIFO_DEPTH = "00000000000000000000000000010010"
INT_WIDTH = "00000000000000000000000000100100"
RAM_DEPTH = "00000000000000000000000000010010"
Analyzing hierarchy for module <vita_tx_chain> in library <work> with parameters.
BASE = "00000000000000000000000010010000"
DO_FLOW_CONTROL = "00000000000000000000000000000001"
DSP_NUMBER = "00000000000000000000000000000000"
FIFOSIZE = "00000000000000000000000000001010"
FIFOWIDTH = "00000000000000000000000001110101"
MAXCHAN = "00000000000000000000000000000001"
POST_ENGINE_FIFOSIZE = "00000000000000000000000000001010"
PROT_ENG_FLAGS = "00000000000000000000000000000001"
REPORT_ERROR = "00000000000000000000000000000001"
USE_TRANS_HEADER = "00000000000000000000000000000001"
Analyzing hierarchy for module <duc_chain> in library <work> with parameters.
BASE = "00000000000000000000000010100000"
DSPNO = "00000000000000000000000000000000"
WIDTH = "00000000000000000000000000011000"
cwidth = "00000000000000000000000000011000"
zwidth = "00000000000000000000000000011000"
Analyzing hierarchy for module <tx_frontend> in library <work> with parameters.
BASE = "00000000000000000000000010000000"
IQCOMP_EN = "00000000000000000000000000000001"
WIDTH_OUT = "00000000000000000000000000010000"
Analyzing hierarchy for module <serdes> in library <work> with parameters.
RXFIFOSIZE = "00000000000000000000000000001001"
TXFIFOSIZE = "00000000000000000000000000001001"
Analyzing hierarchy for module <time_64bit> in library <work> with parameters.
BASE = "00000000000000000000000000001010"
MIMO_SYNC = "00000000000000000000000000000101"
NEXT_TICKS_HI = "00000000000000000000000000000000"
NEXT_TICKS_LO = "00000000000000000000000000000001"
PPS_IMM = "00000000000000000000000000000011"
PPS_POLSRC = "00000000000000000000000000000010"
Analyzing hierarchy for entity <zpu_system> in library <work> (architecture <behave>) with generics.
simulate = false
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000010000"
width = "00000000000000000000000000000001"
Analyzing hierarchy for module <valve36> in library <work>.
Analyzing hierarchy for module <crossbar36> in library <work>.
Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <fifo36_mux> in library <work> with parameters.
MUX_DATA0 = "00000000000000000000000000000001"
MUX_DATA1 = "00000000000000000000000000000011"
MUX_IDLE0 = "00000000000000000000000000000000"
MUX_IDLE1 = "00000000000000000000000000000010"
prio = "00000000000000000000000000000000"
Analyzing hierarchy for module <fifo36_mux> in library <work> with parameters.
MUX_DATA0 = "00000000000000000000000000000001"
MUX_DATA1 = "00000000000000000000000000000011"
MUX_IDLE0 = "00000000000000000000000000000000"
MUX_IDLE1 = "00000000000000000000000000000010"
prio = "00000000000000000000000000000001"
Analyzing hierarchy for module <buffer_int2> in library <work> with parameters.
BASE = "00000000000000000000000000010011"
BUF_SIZE = "00000000000000000000000000001001"
DONE = "101"
ERROR = "100"
IDLE = "000"
PRE_READ = "001"
READING = "010"
WRITING = "011"
Analyzing hierarchy for module <packet_dispatcher36_x4> in library <work> with parameters.
BASE = "00000000000000000000000000010001"
PD_DEST_BOF = "00000000000000000000000000000011"
PD_DEST_CPU = "00000000000000000000000000000010"
PD_DEST_CTL = "00000000000000000000000000000100"
PD_DEST_DSP = "00000000000000000000000000000000"
PD_DEST_EXT = "00000000000000000000000000000001"
PD_DREGS_DSP_OFFSET = "00000000000000000000000000001011"
PD_MAX_NUM_DREGS = "00000000000000000000000000001101"
PD_STATE_READ_COM = "00000000000000000000000000000001"
PD_STATE_READ_COM_PRE = "00000000000000000000000000000000"
PD_STATE_WRITE_LIVE = "00000000000000000000000000000011"
PD_STATE_WRITE_REGS = "00000000000000000000000000000010"
Analyzing hierarchy for module <fifo_cascade> in library <work> with parameters.
SIZE = "00000000000000000000000000001001"
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <prot_eng_tx> in library <work> with parameters.
BASE = "00000000000000000000000011000000"
Analyzing hierarchy for module <fifo36_mux> in library <work> with parameters.
MUX_DATA0 = "00000000000000000000000000000001"
MUX_DATA1 = "00000000000000000000000000000011"
MUX_IDLE0 = "00000000000000000000000000000000"
MUX_IDLE1 = "00000000000000000000000000000010"
prio = "00000000000000000000000000000000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000010100"
width = "00000000000000000000000000010000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000010101"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000010110"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <i2c_master_byte_ctrl> in library <work> with parameters.
ST_ACK = "01000"
ST_IDLE = "00000"
ST_READ = "00010"
ST_START = "00001"
ST_STOP = "10000"
ST_WRITE = "00100"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010111000"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010111001"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010111010"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010111011"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010111100"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <reset_sync> in library <work>.
Analyzing hierarchy for module <simple_gemac> in library <work> with parameters.
SGE_IFG = "00001100"
Analyzing hierarchy for module <simple_gemac_wb> in library <work>.
Analyzing hierarchy for module <rxmac_to_ll8> in library <work> with parameters.
XFER_ACTIVE = "00000000000000000000000000000001"
XFER_ERROR = "00000000000000000000000000000010"
XFER_ERROR2 = "00000000000000000000000000000011"
XFER_IDLE = "00000000000000000000000000000000"
XFER_OVERRUN = "00000000000000000000000000000100"
XFER_OVERRUN2 = "00000000000000000000000000000101"
Analyzing hierarchy for module <ll8_to_fifo19> in library <work> with parameters.
XFER_EMPTY = "00000000000000000000000000000000"
XFER_HALF = "00000000000000000000000000000001"
XFER_HALF_WRITE = "00000000000000000000000000000011"
Analyzing hierarchy for module <fifo19_rxrealign> in library <work> with parameters.
RXRE_DUMMY = "00000000000000000000000000000000"
RXRE_PKT = "00000000000000000000000000000001"
Analyzing hierarchy for module <fifo19_to_fifo36> in library <work> with parameters.
LE = "00000000000000000000000000000000"
Analyzing hierarchy for module <fifo_2clock_cascade> in library <work> with parameters.
SIZE = "00000000000000000000000000001011"
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <fifo_2clock_cascade> in library <work> with parameters.
SIZE = "00000000000000000000000000001001"
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <ethtx_realign> in library <work> with parameters.
RE_DONE = "00000000000000000000000000000010"
RE_HELD = "00000000000000000000000000000001"
RE_IDLE = "00000000000000000000000000000000"
Analyzing hierarchy for module <fifo36_to_ll8> in library <work>.
Analyzing hierarchy for module <ll8_to_txmac> in library <work> with parameters.
XFER_ACTIVE = "00000000000000000000000000000001"
XFER_DROP = "00000000000000000000000000000100"
XFER_IDLE = "00000000000000000000000000000000"
XFER_UNDERRUN = "00000000000000000000000000000011"
XFER_WAIT1 = "00000000000000000000000000000010"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000001000"
width = "00000000000000000000000000001000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000001001"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <shortfifo> in library <work> with parameters.
WIDTH = "00000000000000000000000010000001"
Analyzing hierarchy for module <shortfifo> in library <work> with parameters.
WIDTH = "00000000000000000000000001000000"
Analyzing hierarchy for module <time_compare> in library <work>.
Analyzing hierarchy for module <priority_enc> in library <work>.
Analyzing hierarchy for module <simple_uart_tx> in library <work> with parameters.
DEPTH = "00000000000000000000000000000011"
Analyzing hierarchy for module <simple_uart_rx> in library <work> with parameters.
DEPTH = "00000000000000000000000000000011"
Analyzing hierarchy for module <spi_clgen> in library <work>.
Analyzing hierarchy for module <spi_shift> in library <work>.
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000011000"
width = "00000000000000000000000000000001"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000011001"
width = "00000000000000000000000000010010"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000011010"
width = "00000000000000000000000000010010"
Analyzing hierarchy for module <rx_dcoffset> in library <work> with parameters.
ADDR = "00000000000000000000000000011011"
WIDTH = "00000000000000000000000000010010"
alpha_shift = "00000000000000000000000000010100"
int_width = "00000000000000000000000000100110"
Analyzing hierarchy for module <rx_dcoffset> in library <work> with parameters.
ADDR = "00000000000000000000000000011100"
WIDTH = "00000000000000000000000000010010"
alpha_shift = "00000000000000000000000000010100"
int_width = "00000000000000000000000000100110"
Analyzing hierarchy for module <add2_and_clip_reg> in library <work> with parameters.
WIDTH = "00000000000000000000000000011000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000110000"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000110001"
width = "00000000000000000000000000010010"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000110010"
width = "00000000000000000000000000001010"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000110011"
width = "00000000000000000000000000000010"
Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
bits_in = "00000000000000000000000000011000"
bits_out = "00000000000000000000000000011001"
Analyzing hierarchy for module <cordic_z24> in library <work> with parameters.
bitwidth = "00000000000000000000000000011001"
c00 = "01000000000000000000000"
c01 = "00100101110010000000101"
c02 = "00010011111101100111000"
c03 = "00001010001000100010010"
c04 = "00000101000101100001101"
c05 = "00000010100010111011000"
c06 = "00000001010001011110110"
c07 = "00000000101000101111100"
c08 = "00000000010100010111110"
c09 = "00000000001010001011111"
c10 = "00000000000101000110000"
c11 = "00000000000010100011000"
c12 = "00000000000001010001100"
c13 = "00000000000000101000110"
c14 = "00000000000000010100011"
c15 = "00000000000000001010001"
c16 = "00000000000000000101001"
c17 = "00000000000000000010100"
c18 = "00000000000000000001010"
c19 = "00000000000000000000101"
c20 = "00000000000000000000011"
c21 = "00000000000000000000001"
c22 = "00000000000000000000001"
c23 = "00000000000000000000000"
stages = "00000000000000000000000000010011"
zwidth = "00000000000000000000000000011000"
Analyzing hierarchy for module <clip_reg> in library <work> with parameters.
STROBED = "0"
bits_in = "00000000000000000000000000011001"
bits_out = "00000000000000000000000000011000"
Analyzing hierarchy for module <cic_strober> in library <work> with parameters.
WIDTH = "00000000000000000000000000001000"
Analyzing hierarchy for module <cic_decim> in library <work> with parameters.
N = "00000000000000000000000000000100"
bw = "00000000000000000000000000011000"
log2_of_max_rate = "00000000000000000000000000000111"
maxbitgain = "00000000000000000000000000011100"
Analyzing hierarchy for module <small_hb_dec> in library <work> with parameters.
ACCWIDTH = "00000000000000000000000000011110"
INTWIDTH = "00000000000000000000000000010001"
WIDTH = "00000000000000000000000000011000"
Analyzing hierarchy for module <hb_dec> in library <work> with parameters.
ACCWIDTH = "00000000000000000000000000011011"
INTWIDTH = "00000000000000000000000000010001"
SHIFT_FACTOR = "00000000000000000000000000000110"
WIDTH = "00000000000000000000000000011000"
Analyzing hierarchy for module <round_sd> in library <work> with parameters.
DISABLE_SD = "00000000000000000000000000000000"
ERR_WIDTH = "00000000000000000000000000001001"
WIDTH_IN = "00000000000000000000000000011000"
WIDTH_OUT = "00000000000000000000000000010000"
Analyzing hierarchy for module <dsp_rx_glue> in library <work> with parameters.
DSPNO = "00000000000000000000000000000000"
WIDTH = "00000000000000000000000000011000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000101000"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <vita_rx_control> in library <work> with parameters.
BASE = "00000000000000000000000000100000"
IBS_BROKENCHAIN = "00000000000000000000000000000101"
IBS_IDLE = "00000000000000000000000000000000"
IBS_LATECMD = "00000000000000000000000000000110"
IBS_OVERRUN = "00000000000000000000000000000100"
IBS_RUNNING = "00000000000000000000000000000010"
IBS_WAITING = "00000000000000000000000000000001"
IBS_ZEROLEN = "00000000000000000000000000000111"
WIDTH = "00000000000000000000000000100000"
Analyzing hierarchy for module <vita_rx_framer> in library <work> with parameters.
BASE = "00000000000000000000000000100000"
MAXCHAN = "00000000000000000000000000000001"
SAMP_WIDTH = "00000000000000000000000001100101"
VITA_ERR_HEADER = "00000000000000000000000000000111"
VITA_ERR_PAYLOAD = "00000000000000000000000000001011"
VITA_ERR_STREAMID = "00000000000000000000000000001000"
VITA_ERR_TICS = "00000000000000000000000000001001"
VITA_ERR_TICS2 = "00000000000000000000000000001010"
VITA_ERR_TRAILER = "00000000000000000000000000001100"
VITA_HEADER = "00000000000000000000000000000001"
VITA_IDLE = "00000000000000000000000000000000"
VITA_PAYLOAD = "00000000000000000000000000000101"
VITA_STREAMID = "00000000000000000000000000000010"
VITA_TICS = "00000000000000000000000000000011"
VITA_TICS2 = "00000000000000000000000000000100"
VITA_TRAILER = "00000000000000000000000000000110"
Analyzing hierarchy for module <double_buffer> in library <work> with parameters.
BUF_SIZE = "00000000000000000000000000001010"
IDLE = "00000000000000000000000000000000"
PRE_READ = "00000000000000000000000000000001"
READING = "00000000000000000000000000000010"
Analyzing hierarchy for module <vita_rx_engine_glue> in library <work> with parameters.
BUF_SIZE = "00000000000000000000000000001010"
DSPNO = "00000000000000000000000000000000"
MAIN_SETTINGS_BASE = "00000000000000000000000000100011"
Analyzing hierarchy for module <add_routing_header> in library <work> with parameters.
PORT_SEL = "00000000000000000000000000000000"
PROT_ENG_FLAGS = "00000000000000000000000000000001"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000001100000"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000001100001"
width = "00000000000000000000000000010010"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000001100010"
width = "00000000000000000000000000001010"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000001100011"
width = "00000000000000000000000000000010"
Analyzing hierarchy for module <dsp_rx_glue> in library <work> with parameters.
DSPNO = "00000000000000000000000000000001"
WIDTH = "00000000000000000000000000011000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000001011000"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <vita_rx_control> in library <work> with parameters.
BASE = "00000000000000000000000001010000"
IBS_BROKENCHAIN = "00000000000000000000000000000101"
IBS_IDLE = "00000000000000000000000000000000"
IBS_LATECMD = "00000000000000000000000000000110"
IBS_OVERRUN = "00000000000000000000000000000100"
IBS_RUNNING = "00000000000000000000000000000010"
IBS_WAITING = "00000000000000000000000000000001"
IBS_ZEROLEN = "00000000000000000000000000000111"
WIDTH = "00000000000000000000000000100000"
Analyzing hierarchy for module <vita_rx_framer> in library <work> with parameters.
BASE = "00000000000000000000000001010000"
MAXCHAN = "00000000000000000000000000000001"
SAMP_WIDTH = "00000000000000000000000001100101"
VITA_ERR_HEADER = "00000000000000000000000000000111"
VITA_ERR_PAYLOAD = "00000000000000000000000000001011"
VITA_ERR_STREAMID = "00000000000000000000000000001000"
VITA_ERR_TICS = "00000000000000000000000000001001"
VITA_ERR_TICS2 = "00000000000000000000000000001010"
VITA_ERR_TRAILER = "00000000000000000000000000001100"
VITA_HEADER = "00000000000000000000000000000001"
VITA_IDLE = "00000000000000000000000000000000"
VITA_PAYLOAD = "00000000000000000000000000000101"
VITA_STREAMID = "00000000000000000000000000000010"
VITA_TICS = "00000000000000000000000000000011"
VITA_TICS2 = "00000000000000000000000000000100"
VITA_TRAILER = "00000000000000000000000000000110"
Analyzing hierarchy for module <vita_rx_engine_glue> in library <work> with parameters.
BUF_SIZE = "00000000000000000000000000001010"
DSPNO = "00000000000000000000000000000001"
MAIN_SETTINGS_BASE = "00000000000000000000000001010011"
Analyzing hierarchy for module <add_routing_header> in library <work> with parameters.
PORT_SEL = "00000000000000000000000000000010"
PROT_ENG_FLAGS = "00000000000000000000000000000001"
Analyzing hierarchy for module <nobl_fifo> in library <work> with parameters.
FIFO_DEPTH = "00000000000000000000000000010010"
RAM_DEPTH = "00000000000000000000000000010010"
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <refill_randomizer> in library <work> with parameters.
BITS = "00000000000000000000000000000111"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010010000"
width = "00000000000000000000000000000001"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010010010"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <vita_tx_deframer> in library <work> with parameters.
BASE = "00000000000000000000000010010000"
FIFOWIDTH = "00000000000000000000000001110101"
MAXCHAN = "00000000000000000000000000000001"
USE_TRANS_HEADER = "00000000000000000000000000000001"
VITA_CLASSID = "00000000000000000000000000000011"
VITA_CLASSID2 = "00000000000000000000000000000100"
VITA_DUMP = "00000000000000000000000000001011"
VITA_HEADER = "00000000000000000000000000000001"
VITA_PAYLOAD = "00000000000000000000000000001000"
VITA_SECS = "00000000000000000000000000000101"
VITA_STREAMID = "00000000000000000000000000000010"
VITA_TICS = "00000000000000000000000000000110"
VITA_TICS2 = "00000000000000000000000000000111"
VITA_TRAILER = "00000000000000000000000000001010"
VITA_TRANS_HEADER = "00000000000000000000000000000000"
Analyzing hierarchy for module <vita_tx_control> in library <work> with parameters.
BASE = "00000000000000000000000010010000"
IBS_CONT_BURST = "00000000000000000000000000000010"
IBS_ERROR = "00000000000000000000000000000011"
IBS_ERROR_DONE = "00000000000000000000000000000100"
IBS_ERROR_WAIT = "00000000000000000000000000000101"
IBS_IDLE = "00000000000000000000000000000000"
IBS_RUN = "00000000000000000000000000000001"
MAX_IDLE = "00000000000011110100001001000000"
WIDTH = "00000000000000000000000000100000"
Analyzing hierarchy for module <gen_context_pkt> in library <work> with parameters.
CTXT_DONE = "00000000000000000000000000001000"
CTXT_FLOWCTRL = "00000000000000000000000000000111"
CTXT_HEADER = "00000000000000000000000000000010"
CTXT_IDLE = "00000000000000000000000000000000"
CTXT_MESSAGE = "00000000000000000000000000000110"
CTXT_PROT_ENG = "00000000000000000000000000000001"
CTXT_STREAMID = "00000000000000000000000000000011"
CTXT_TICS = "00000000000000000000000000000100"
CTXT_TICS2 = "00000000000000000000000000000101"
DSP_NUMBER = "00000000000000000000000000000000"
PROT_ENG_FLAGS = "00000000000000000000000000000001"
Analyzing hierarchy for module <trigger_context_pkt> in library <work> with parameters.
BASE = "00000000000000000000000010010000"
Analyzing hierarchy for module <vita_tx_engine_glue> in library <work> with parameters.
BUF_SIZE = "00000000000000000000000000001010"
DSPNO = "00000000000000000000000000000000"
HEADER_OFFSET = "00000000000000000000000000000001"
MAIN_SETTINGS_BASE = "00000000000000000000000010010001"
Analyzing hierarchy for module <fifo_cascade> in library <work> with parameters.
SIZE = "00000000000000000000000000001010"
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010100000"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010100001"
width = "00000000000000000000000000010010"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010100010"
width = "00000000000000000000000000001010"
Analyzing hierarchy for module <cic_strober> in library <work> with parameters.
WIDTH = "00000000000000000000000000001000"
Analyzing hierarchy for module <cic_strober> in library <work> with parameters.
WIDTH = "00000000000000000000000000000010"
Analyzing hierarchy for module <hb_interp> in library <work> with parameters.
ACCWIDTH = "00000000000000000000000000011000"
CWIDTH = "00000000000000000000000000010010"
IWIDTH = "00000000000000000000000000010010"
MWIDTH = "00000000000000000000000000010110"
OWIDTH = "00000000000000000000000000010010"
Analyzing hierarchy for module <small_hb_int> in library <work> with parameters.
MWIDTH = "00000000000000000000000000100100"
WIDTH = "00000000000000000000000000010010"
Analyzing hierarchy for module <cic_interp> in library <work> with parameters.
N = "00000000000000000000000000000100"
bw = "00000000000000000000000000010010"
log2_of_max_rate = "00000000000000000000000000000111"
maxbitgain = "00000000000000000000000000010101"
Analyzing hierarchy for module <cordic_z24> in library <work> with parameters.
bitwidth = "00000000000000000000000000011000"
c00 = "01000000000000000000000"
c01 = "00100101110010000000101"
c02 = "00010011111101100111000"
c03 = "00001010001000100010010"
c04 = "00000101000101100001101"
c05 = "00000010100010111011000"
c06 = "00000001010001011110110"
c07 = "00000000101000101111100"
c08 = "00000000010100010111110"
c09 = "00000000001010001011111"
c10 = "00000000000101000110000"
c11 = "00000000000010100011000"
c12 = "00000000000001010001100"
c13 = "00000000000000101000110"
c14 = "00000000000000010100011"
c15 = "00000000000000001010001"
c16 = "00000000000000000101001"
c17 = "00000000000000000010100"
c18 = "00000000000000000001010"
c19 = "00000000000000000000101"
c20 = "00000000000000000000011"
c21 = "00000000000000000000001"
c22 = "00000000000000000000001"
c23 = "00000000000000000000000"
stages = "00000000000000000000000000010011"
zwidth = "00000000000000000000000000011000"
Analyzing hierarchy for module <dsp_tx_glue> in library <work> with parameters.
DSPNO = "00000000000000000000000000000000"
WIDTH = "00000000000000000000000000011000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010000000"
width = "00000000000000000000000000011000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010000001"
width = "00000000000000000000000000011000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010000010"
width = "00000000000000000000000000010010"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010000011"
width = "00000000000000000000000000010010"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010000100"
width = "00000000000000000000000000001000"
Analyzing hierarchy for module <serdes_tx> in library <work> with parameters.
DONE = "011"
D_56 = "11000101"
FIFOSIZE = "00000000000000000000000000001001"
IDLE = "000"
K_COMMA = "10111100"
K_ERROR = "00000000"
K_IDLE = "00111100"
K_LOS = "11111111"
K_PKT_END = "10011100"
K_PKT_START = "11011100"
K_XOFF = "01111100"
K_XON = "01011100"
RUN1 = "001"
RUN2 = "010"
SENDCRC = "100"
WAIT = "101"
Analyzing hierarchy for module <serdes_rx> in library <work> with parameters.
CRC_CHECK = "101"
DONE = "111"
D_56 = "11000101"
ERROR = "110"
FIFOSIZE = "00000000000000000000000000001001"
FIRSTLINE1 = "001"
FIRSTLINE2 = "010"
IDLE = "000"
K_COMMA = "10111100"
K_ERROR = "00000000"
K_IDLE = "00111100"
K_LOS = "11111111"
K_PKT_END = "10011100"
K_PKT_START = "11011100"
K_XOFF = "01111100"
K_XON = "01011100"
PKT1 = "011"
PKT2 = "100"
Analyzing hierarchy for module <serdes_fc_tx> in library <work>.
Analyzing hierarchy for module <serdes_fc_rx> in library <work> with parameters.
HWMARK = "00000000000000000000000010000000"
LWMARK = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000001011"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000001010"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000001100"
width = "00000000000000000000000000000010"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000001101"
width = "00000000000000000000000000000001"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000001111"
width = "00000000000000000000000000001001"
Analyzing hierarchy for module <time_sender> in library <work> with parameters.
COMMA = "10111100"
HEAD = "00111100"
SEND_HEAD = "00000000000000000000000000000001"
SEND_IDLE = "00000000000000000000000000000000"
SEND_T0 = "00000000000000000000000000000010"
SEND_T1 = "00000000000000000000000000000011"
SEND_T2 = "00000000000000000000000000000100"
SEND_T3 = "00000000000000000000000000000101"
SEND_T4 = "00000000000000000000000000000110"
SEND_T5 = "00000000000000000000000000000111"
SEND_T6 = "00000000000000000000000000001000"
SEND_T7 = "00000000000000000000000000001001"
SEND_TAIL = "00000000000000000000000000001010"
TAIL = "11110111"
Analyzing hierarchy for module <time_receiver> in library <work> with parameters.
COMMA_0 = "1010000011"
COMMA_1 = "0101111100"
HEAD = "100111100"
STATE_IDLE = "00000000000000000000000000000000"
STATE_T0 = "00000000000000000000000000000001"
STATE_T1 = "00000000000000000000000000000010"
STATE_T2 = "00000000000000000000000000000011"
STATE_T3 = "00000000000000000000000000000100"
STATE_T4 = "00000000000000000000000000000101"
STATE_T5 = "00000000000000000000000000000110"
STATE_T6 = "00000000000000000000000000000111"
STATE_T7 = "00000000000000000000000000001000"
STATE_TAIL = "00000000000000000000000000001001"
TAIL = "111110111"
Analyzing hierarchy for entity <zpu_core> in library <work> (architecture <behave>).
Analyzing hierarchy for entity <zpu_wb_bridge> in library <work> (architecture <behave>).
Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <ram_2port> in library <work> with parameters.
AWIDTH = "00000000000000000000000000001001"
DWIDTH = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000010011"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000010001"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000010010"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <splitter36> in library <work> with parameters.
STATE_COPY_BOTH = "00000000000000000000000000000000"
STATE_COPY_ONE = "00000000000000000000000000000010"
STATE_COPY_ZERO = "00000000000000000000000000000001"
Analyzing hierarchy for module <fifo36_mux> in library <work> with parameters.
MUX_DATA0 = "00000000000000000000000000000001"
MUX_DATA1 = "00000000000000000000000000000011"
MUX_IDLE0 = "00000000000000000000000000000000"
MUX_IDLE1 = "00000000000000000000000000000010"
prio = "00000000000000000000000000000000"
Analyzing hierarchy for module <fifo36_mux> in library <work> with parameters.
MUX_DATA0 = "00000000000000000000000000000001"
MUX_DATA1 = "00000000000000000000000000000011"
MUX_IDLE0 = "00000000000000000000000000000000"
MUX_IDLE1 = "00000000000000000000000000000010"
prio = "00000000000000000000000000000000"
Analyzing hierarchy for module <fifo_long> in library <work> with parameters.
EMPTY = "00000000000000000000000000000000"
NUMLINES = "00000000000000000000000111111110"
PRE_READ = "00000000000000000000000000000001"
READING = "00000000000000000000000000000010"
SIZE = "00000000000000000000000000001001"
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <add_onescomp> in library <work> with parameters.
WIDTH = "00000000000000000000000000010000"
Analyzing hierarchy for module <i2c_master_bit_ctrl> in library <work> with parameters.
idle = "00000000000000000"
rd_a = "00000001000000000"
rd_b = "00000010000000000"
rd_c = "00000100000000000"
rd_d = "00001000000000000"
start_a = "00000000000000001"
start_b = "00000000000000010"
start_c = "00000000000000100"
start_d = "00000000000001000"
start_e = "00000000000010000"
stop_a = "00000000000100000"
stop_b = "00000000001000000"
stop_c = "00000000010000000"
stop_d = "00000000100000000"
wr_a = "00010000000000000"
wr_b = "00100000000000000"
wr_c = "01000000000000000"
wr_d = "10000000000000000"
Analyzing hierarchy for module <reset_sync> in library <work>.
Analyzing hierarchy for module <simple_gemac_tx> in library <work> with parameters.
MAX_FRAME_LEN = "00000000000000000010000000000000"
MIN_FRAME_LEN = "00000000000000000000000001000100"
SGE_FLOW_CTRL_ADDR = "000000011000000011000010000000000000000000000001"
TX_CRC_0 = "00000000000000000000000000010000"
TX_CRC_1 = "00000000000000000000000000010001"
TX_CRC_2 = "00000000000000000000000000010010"
TX_CRC_3 = "00000000000000000000000000010011"
TX_ERROR = "00000000000000000000000000100000"
TX_FIRSTBYTE = "00000000000000000000000000001001"
TX_IDLE = "00000000000000000000000000000000"
TX_IN_FRAME = "00000000000000000000000000001010"
TX_IN_FRAME_2 = "00000000000000000000000000001011"
TX_PAD = "00000000000000000000000000001100"
TX_PAUSE = "00000000000000000000000000110111"
TX_PAUSE_END = "00000000000000000000000001010000"
TX_PAUSE_FIRST = "00000000000000000000000000111111"
TX_PAUSE_SOF = "00000000000000000000000000111110"
TX_PREAMBLE = "00000000000000000000000000000001"
TX_SOF_DEL = "00000000000000000000000000001000"
Analyzing hierarchy for module <simple_gemac_rx> in library <work> with parameters.
DELAY = "00000000000000000000000000000110"
MIN_PAUSE_LEN = "00000000000000000000000001000111"
RX_DO_PAUSE = "00000000000000000000000000000100"
RX_DROP = "00000000000000000000000000000110"
RX_ERROR = "00000000000000000000000000000101"
RX_FRAME = "00000000000000000000000000000010"
RX_GOODFRAME = "00000000000000000000000000000011"
RX_IDLE = "00000000000000000000000000000000"
RX_PAUSE = "00000000000000000000000000010000"
RX_PAUSE_CHK00 = "00000000000000000000000000010111"
RX_PAUSE_CHK01 = "00000000000000000000000000011000"
RX_PAUSE_CHK08 = "00000000000000000000000000010110"
RX_PAUSE_CHK88 = "00000000000000000000000000010101"
RX_PAUSE_STORE_LSB = "00000000000000000000000000011010"
RX_PAUSE_STORE_MSB = "00000000000000000000000000011001"
RX_PAUSE_WAIT_CRC = "00000000000000000000000000011011"
RX_PREAMBLE = "00000000000000000000000000000001"
Analyzing hierarchy for module <flow_ctrl_tx> in library <work>.
Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
ADDR = "00000000000000000000000000000000"
DEFAULT = "0111011"
WIDTH = "00000000000000000000000000000111"
Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
ADDR = "00000000000000000000000000000001"
DEFAULT = "00000000000000000000000000000000"
WIDTH = "00000000000000000000000000010000"
Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
ADDR = "00000000000000000000000000000010"
DEFAULT = "00000000000000000000000000000000"
WIDTH = "00000000000000000000000000100000"
Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
ADDR = "00000000000000000000000000000011"
DEFAULT = "00000000000000000000000000000000"
WIDTH = "00000000000000000000000000010000"
Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
ADDR = "00000000000000000000000000000100"
DEFAULT = "00000000000000000000000000000000"
WIDTH = "00000000000000000000000000100000"
Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
ADDR = "00000000000000000000000000000101"
DEFAULT = "00000000000000000000000000000000"
WIDTH = "00000000000000000000000000001001"
Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
ADDR = "00000000000000000000000000000110"
DEFAULT = "00000000000000000000000000000000"
WIDTH = "00000000000000000000000000001101"
Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
ADDR = "00000000000000000000000000000111"
DEFAULT = "00000000000000000000000000000000"
WIDTH = "00000000000000000000000000010000"
Analyzing hierarchy for module <eth_miim> in library <work>.
Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
ADDR = "00000000000000000000000000001011"
DEFAULT = "00000000000000000000000000000000"
WIDTH = "00000000000000000000000000010000"
Analyzing hierarchy for module <wb_reg> in library <work> with parameters.
ADDR = "00000000000000000000000000001100"
DEFAULT = "00000000000000000000000000000000"
WIDTH = "00000000000000000000000000010000"
Analyzing hierarchy for module <ll8_shortfifo> in library <work>.
Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
WIDTH = "00000000000000000000000000010011"
Analyzing hierarchy for module <fifo_2clock> in library <work> with parameters.
SIZE = "00000000000000000000000000001011"
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <fifo_2clock> in library <work> with parameters.
SIZE = "00000000000000000000000000001001"
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <medfifo> in library <work> with parameters.
DEPTH = "00000000000000000000000000000011"
NUM_FIFOS = "00000000000000000000000000001000"
WIDTH = "00000000000000000000000000001000"
Analyzing hierarchy for module <round_sd> in library <work> with parameters.
DISABLE_SD = "00000000000000000000000000000000"
ERR_WIDTH = "00000000000000000000000000010101"
WIDTH_IN = "00000000000000000000000000100110"
WIDTH_OUT = "00000000000000000000000000010010"
Analyzing hierarchy for module <add2_and_clip_reg> in library <work> with parameters.
WIDTH = "00000000000000000000000000010010"
Analyzing hierarchy for module <add2_and_clip> in library <work> with parameters.
WIDTH = "00000000000000000000000000011000"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000000000"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000000001"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000000010"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000000011"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000000100"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000000101"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000000110"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000000111"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000001000"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000001001"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000001010"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000001011"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000001100"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000001101"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000001110"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000001111"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000010000"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000010001"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000010010"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011011"
shift = "00000000000000000000000000010011"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <clip> in library <work> with parameters.
bits_in = "00000000000000000000000000011001"
bits_out = "00000000000000000000000000011000"
Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
bits_in = "00000000000000000000000000011000"
bits_out = "00000000000000000000000000110100"
Analyzing hierarchy for module <cic_dec_shifter> in library <work> with parameters.
bw = "00000000000000000000000000011000"
maxbitgain = "00000000000000000000000000011100"
Analyzing hierarchy for module <round_sd> in library <work> with parameters.
DISABLE_SD = "00000000000000000000000000000000"
ERR_WIDTH = "00000000000000000000000000001000"
WIDTH_IN = "00000000000000000000000000011000"
WIDTH_OUT = "00000000000000000000000000010001"
Analyzing hierarchy for module <round_sd> in library <work> with parameters.
DISABLE_SD = "00000000000000000000000000000000"
ERR_WIDTH = "00000000000000000000000000000110"
WIDTH_IN = "00000000000000000000000000011110"
WIDTH_OUT = "00000000000000000000000000011001"
Analyzing hierarchy for module <srl> in library <work> with parameters.
WIDTH = "00000000000000000000000000010001"
Analyzing hierarchy for module <acc> in library <work> with parameters.
IWIDTH = "00000000000000000000000000011001"
OWIDTH = "00000000000000000000000000011011"
Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
bits_in = "00000000000000000000000000010001"
bits_out = "00000000000000000000000000010101"
Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
bits_in = "00000000000000000000000000001001"
bits_out = "00000000000000000000000000011000"
Analyzing hierarchy for module <add2_and_clip_reg> in library <work> with parameters.
WIDTH = "00000000000000000000000000011000"
Analyzing hierarchy for module <round> in library <work> with parameters.
bits_in = "00000000000000000000000000011000"
bits_out = "00000000000000000000000000010000"
round_to_nearest = "00000000000000000000000000000001"
round_to_zero = "00000000000000000000000000000000"
trunc = "00000000000000000000000000000000"
Analyzing hierarchy for module <custom_dsp_rx> in library <work> with parameters.
WIDTH = "00000000000000000000000000011000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000100000"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000100001"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000100010"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
WIDTH = "00000000000000000000000001100000"
Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
WIDTH = "00000000000000000000000001100101"
Analyzing hierarchy for module <time_compare> in library <work>.
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000100100"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000100101"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000100110"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000100111"
width = "00000000000000000000000000010000"
Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
WIDTH = "00000000000000000000000000100010"
Analyzing hierarchy for module <dbsm> in library <work> with parameters.
BUFF_ACCESSIBLE = "00000000000000000000000000000001"
BUFF_ERROR = "00000000000000000000000000000011"
BUFF_READABLE = "00000000000000000000000000000010"
BUFF_WRITABLE = "00000000000000000000000000000000"
PORT_USE_0 = "00000000000000000000000000000001"
PORT_USE_1 = "00000000000000000000000000000011"
PORT_WAIT_0 = "00000000000000000000000000000000"
PORT_WAIT_1 = "00000000000000000000000000000010"
Analyzing hierarchy for module <ram_2port> in library <work> with parameters.
AWIDTH = "00000000000000000000000000001010"
DWIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <dspengine_16to8> in library <work> with parameters.
BASE = "00000000000000000000000000100011"
BUF_SIZE = "00000000000000000000000000001010"
DSP_CONVERT = "00000000000000000000000000000010"
DSP_CONVERT_DRAIN_PIPE = "00000000000000000000000000000011"
DSP_DONE = "00000000000000000000000000000111"
DSP_IDLE = "00000000000000000000000000000000"
DSP_PARSE_HEADER = "00000000000000000000000000000001"
DSP_READ_TRAILER = "00000000000000000000000000000100"
DSP_WRITE_HEADER = "00000000000000000000000000000110"
DSP_WRITE_TRAILER = "00000000000000000000000000000101"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000001010000"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000001010001"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000001010010"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000001010100"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000001010101"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000001010110"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000001010111"
width = "00000000000000000000000000010000"
Analyzing hierarchy for module <dspengine_16to8> in library <work> with parameters.
BASE = "00000000000000000000000001010011"
BUF_SIZE = "00000000000000000000000000001010"
DSP_CONVERT = "00000000000000000000000000000010"
DSP_CONVERT_DRAIN_PIPE = "00000000000000000000000000000011"
DSP_DONE = "00000000000000000000000000000111"
DSP_IDLE = "00000000000000000000000000000000"
DSP_PARSE_HEADER = "00000000000000000000000000000001"
DSP_READ_TRAILER = "00000000000000000000000000000100"
DSP_WRITE_HEADER = "00000000000000000000000000000110"
DSP_WRITE_TRAILER = "00000000000000000000000000000101"
Analyzing hierarchy for module <nobl_if> in library <work> with parameters.
DEPTH = "00000000000000000000000000010010"
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
WIDTH = "00000000000000000000000001110101"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010010011"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010010100"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010010101"
width = "00000000000000000000000000100000"
Analyzing hierarchy for module <dspengine_8to16> in library <work> with parameters.
BASE = "00000000000000000000000010010001"
BUF_SIZE = "00000000000000000000000000001010"
DSP_DONE = "00000000000000000000000000001010"
DSP_IDLE = "00000000000000000000000000000000"
DSP_IDLE_RD = "00000000000000000000000000000001"
DSP_PARSE_HEADER = "00000000000000000000000000000010"
DSP_READ = "00000000000000000000000000000011"
DSP_READ_TRAILER = "00000000000000000000000000000111"
DSP_READ_WAIT = "00000000000000000000000000000100"
DSP_WRITE_0 = "00000000000000000000000000000110"
DSP_WRITE_1 = "00000000000000000000000000000101"
DSP_WRITE_HEADER = "00000000000000000000000000001001"
DSP_WRITE_TRAILER = "00000000000000000000000000001000"
HEADER_OFFSET = "00000000000000000000000000000001"
Analyzing hierarchy for module <fifo_long> in library <work> with parameters.
EMPTY = "00000000000000000000000000000000"
NUMLINES = "00000000000000000000001111111110"
PRE_READ = "00000000000000000000000000000001"
READING = "00000000000000000000000000000010"
SIZE = "00000000000000000000000000001010"
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <srl> in library <work> with parameters.
WIDTH = "00000000000000000000000000010010"
Analyzing hierarchy for module <add2_reg> in library <work> with parameters.
WIDTH = "00000000000000000000000000010010"
Analyzing hierarchy for module <add2_and_round_reg> in library <work> with parameters.
WIDTH = "00000000000000000000000000010110"
Analyzing hierarchy for module <acc> in library <work> with parameters.
IWIDTH = "00000000000000000000000000010110"
OWIDTH = "00000000000000000000000000011000"
Analyzing hierarchy for module <clip> in library <work> with parameters.
bits_in = "00000000000000000000000000011000"
bits_out = "00000000000000000000000000010011"
Analyzing hierarchy for module <round> in library <work> with parameters.
bits_in = "00000000000000000000000000010011"
bits_out = "00000000000000000000000000010010"
round_to_nearest = "00000000000000000000000000000001"
round_to_zero = "00000000000000000000000000000000"
trunc = "00000000000000000000000000000000"
Analyzing hierarchy for module <add2_and_round_reg> in library <work> with parameters.
WIDTH = "00000000000000000000000000010010"
Analyzing hierarchy for module <acc> in library <work> with parameters.
IWIDTH = "00000000000000000000000000100100"
OWIDTH = "00000000000000000000000000100101"
Analyzing hierarchy for module <round_reg> in library <work> with parameters.
bits_in = "00000000000000000000000000100101"
bits_out = "00000000000000000000000000010101"
Analyzing hierarchy for module <clip_reg> in library <work> with parameters.
STROBED = "0"
bits_in = "00000000000000000000000000010101"
bits_out = "00000000000000000000000000010010"
Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
bits_in = "00000000000000000000000000010010"
bits_out = "00000000000000000000000000100111"
Analyzing hierarchy for module <cic_int_shifter> in library <work> with parameters.
bw = "00000000000000000000000000010010"
maxbitgain = "00000000000000000000000000010101"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000000000"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000000001"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000000010"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000000011"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000000100"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000000101"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000000110"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000000111"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000001000"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000001001"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000001010"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000001011"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000001100"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000001101"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000001110"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000001111"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000010000"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000010001"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000010010"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <cordic_stage> in library <work> with parameters.
bitwidth = "00000000000000000000000000011010"
shift = "00000000000000000000000000010011"
zwidth = "00000000000000000000000000010111"
Analyzing hierarchy for module <fifo_cascade> in library <work> with parameters.
SIZE = "00000000000000000000000000001001"
WIDTH = "00000000000000000000000000100010"
Analyzing hierarchy for module <CRC16_D16> in library <work>.
Analyzing hierarchy for module <oneshot_2clk> in library <work>.
Analyzing hierarchy for module <fifo_2clock_cascade> in library <work> with parameters.
SIZE = "00000000000000000000000000001001"
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <encode_8b10b> in library <work>.
Analyzing hierarchy for module <decode_8b10b> in library <work>.
Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <ram_2port> in library <work> with parameters.
AWIDTH = "00000000000000000000000000001001"
DWIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <crc> in library <work>.
Analyzing hierarchy for module <delay_line> in library <work> with parameters.
WIDTH = "00000000000000000000000000001010"
Analyzing hierarchy for module <address_filter> in library <work>.
Analyzing hierarchy for module <address_filter_promisc> in library <work>.
Analyzing hierarchy for module <eth_clockgen> in library <work>.
Analyzing hierarchy for module <eth_shiftreg> in library <work>.
Analyzing hierarchy for module <eth_outputcontrol> in library <work>.
Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
WIDTH = "00000000000000000000000000001011"
Analyzing hierarchy for module <shortfifo> in library <work> with parameters.
WIDTH = "00000000000000000000000000001000"
Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
bits_in = "00000000000000000000000000010101"
bits_out = "00000000000000000000000000100110"
Analyzing hierarchy for module <add2_and_clip_reg> in library <work> with parameters.
WIDTH = "00000000000000000000000000100110"
Analyzing hierarchy for module <round> in library <work> with parameters.
bits_in = "00000000000000000000000000100110"
bits_out = "00000000000000000000000000010010"
round_to_nearest = "00000000000000000000000000000001"
round_to_zero = "00000000000000000000000000000000"
trunc = "00000000000000000000000000000000"
Analyzing hierarchy for module <add2_and_clip> in library <work> with parameters.
WIDTH = "00000000000000000000000000010010"
Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
bits_in = "00000000000000000000000000001000"
bits_out = "00000000000000000000000000011000"
Analyzing hierarchy for module <round> in library <work> with parameters.
bits_in = "00000000000000000000000000011000"
bits_out = "00000000000000000000000000010001"
round_to_nearest = "00000000000000000000000000000001"
round_to_zero = "00000000000000000000000000000000"
trunc = "00000000000000000000000000000000"
Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
bits_in = "00000000000000000000000000000110"
bits_out = "00000000000000000000000000011110"
Analyzing hierarchy for module <add2_and_clip_reg> in library <work> with parameters.
WIDTH = "00000000000000000000000000011110"
Analyzing hierarchy for module <round> in library <work> with parameters.
bits_in = "00000000000000000000000000011110"
bits_out = "00000000000000000000000000011001"
round_to_nearest = "00000000000000000000000000000001"
round_to_zero = "00000000000000000000000000000000"
trunc = "00000000000000000000000000000000"
Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
bits_in = "00000000000000000000000000011001"
bits_out = "00000000000000000000000000011011"
Analyzing hierarchy for module <add2_and_clip> in library <work> with parameters.
WIDTH = "00000000000000000000000000011000"
Analyzing hierarchy for module <buff_sm> in library <work> with parameters.
BUFF_ACCESSIBLE = "00000000000000000000000000000001"
BUFF_ERROR = "00000000000000000000000000000011"
BUFF_READABLE = "00000000000000000000000000000010"
BUFF_WRITABLE = "00000000000000000000000000000000"
PORT_USE_FLAG = "00000000000000000000000000000001"
Analyzing hierarchy for module <buff_sm> in library <work> with parameters.
BUFF_ACCESSIBLE = "00000000000000000000000000000001"
BUFF_ERROR = "00000000000000000000000000000011"
BUFF_READABLE = "00000000000000000000000000000010"
BUFF_WRITABLE = "00000000000000000000000000000000"
PORT_USE_FLAG = "00000000000000000000000000000011"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000000100011"
width = "00000000000000000000000000000001"
Analyzing hierarchy for module <pipectrl> in library <work> with parameters.
STAGES = "00000000000000000000000000000010"
TAGWIDTH = "00000000000000000000000000000010"
Analyzing hierarchy for module <clip_reg> in library <work> with parameters.
STROBED = "00000000000000000000000000000001"
bits_in = "00000000000000000000000000010000"
bits_out = "00000000000000000000000000001000"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000001010011"
width = "00000000000000000000000000000001"
Analyzing hierarchy for module <bin2gray> in library <work> with parameters.
WIDTH = "00000000000000000000000000010010"
Analyzing hierarchy for module <setting_reg> in library <work> with parameters.
at_reset = "00000000000000000000000000000000"
my_addr = "00000000000000000000000010010001"
width = "00000000000000000000000000000001"
Analyzing hierarchy for module <ram_2port> in library <work> with parameters.
AWIDTH = "00000000000000000000000000001010"
DWIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <add2> in library <work> with parameters.
WIDTH = "00000000000000000000000000010010"
Analyzing hierarchy for module <add2_and_round> in library <work> with parameters.
WIDTH = "00000000000000000000000000010110"
Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
bits_in = "00000000000000000000000000010110"
bits_out = "00000000000000000000000000011000"
Analyzing hierarchy for module <add2_and_round> in library <work> with parameters.
WIDTH = "00000000000000000000000000010010"
Analyzing hierarchy for module <sign_extend> in library <work> with parameters.
bits_in = "00000000000000000000000000100100"
bits_out = "00000000000000000000000000100101"
Analyzing hierarchy for module <round> in library <work> with parameters.
bits_in = "00000000000000000000000000100101"
bits_out = "00000000000000000000000000010101"
round_to_nearest = "00000000000000000000000000000001"
round_to_zero = "00000000000000000000000000000000"
trunc = "00000000000000000000000000000000"
Analyzing hierarchy for module <clip> in library <work> with parameters.
bits_in = "00000000000000000000000000010101"
bits_out = "00000000000000000000000000010010"
Analyzing hierarchy for module <fifo_short> in library <work> with parameters.
WIDTH = "00000000000000000000000000100010"
Analyzing hierarchy for module <fifo_long> in library <work> with parameters.
EMPTY = "00000000000000000000000000000000"
NUMLINES = "00000000000000000000000111111110"
PRE_READ = "00000000000000000000000000000001"
READING = "00000000000000000000000000000010"
SIZE = "00000000000000000000000000001001"
WIDTH = "00000000000000000000000000100010"
Analyzing hierarchy for module <fifo_2clock> in library <work> with parameters.
SIZE = "00000000000000000000000000001001"
WIDTH = "00000000000000000000000000100100"
Analyzing hierarchy for module <add2_and_clip> in library <work> with parameters.
WIDTH = "00000000000000000000000000100110"
Analyzing hierarchy for module <clip> in library <work> with parameters.
bits_in = "00000000000000000000000000010011"
bits_out = "00000000000000000000000000010010"
Analyzing hierarchy for module <add2_and_clip> in library <work> with parameters.
WIDTH = "00000000000000000000000000011110"
Analyzing hierarchy for module <clip> in library <work> with parameters.
bits_in = "00000000000000000000000000011001"
bits_out = "00000000000000000000000000011000"
Analyzing hierarchy for module <pipestage> in library <work> with parameters.
TAGWIDTH = "00000000000000000000000000000010"
Analyzing hierarchy for module <clip> in library <work> with parameters.
bits_in = "00000000000000000000000000010000"
bits_out = "00000000000000000000000000001000"
Analyzing hierarchy for module <ram_2port> in library <work> with parameters.
AWIDTH = "00000000000000000000000000001001"
DWIDTH = "00000000000000000000000000100010"
Analyzing hierarchy for module <clip> in library <work> with parameters.
bits_in = "00000000000000000000000000100111"
bits_out = "00000000000000000000000000100110"
Analyzing hierarchy for module <clip> in library <work> with parameters.
bits_in = "00000000000000000000000000011111"
bits_out = "00000000000000000000000000011110"
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <u2plus>.
WARNING:Xst:863 - "../u2plus.v" line 64: Name conflict (<clk_func> and <CLK_FUNC>, renaming clk_func as clk_func_rnm0).
WARNING:Xst:852 - "../u2plus.v" line 375: Unconnected input port 'por' of instance 'u2p_c' is tied to GND.
Module <u2plus> is correct for synthesis.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <phyclk> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <phyclk> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <phyclk> in unit <u2plus>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <phyclk> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <clk_fpga_pin> in unit <u2plus>.
Set user-defined property "DIFF_TERM = FALSE" for instance <clk_fpga_pin> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <clk_fpga_pin> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <clk_fpga_pin> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVPECL_25" for instance <clk_fpga_pin> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <exp_time_in_pin> in unit <u2plus>.
Set user-defined property "DIFF_TERM = FALSE" for instance <exp_time_in_pin> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <exp_time_in_pin> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <exp_time_in_pin> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <exp_time_in_pin> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVDS_25" for instance <exp_time_in_pin> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <exp_time_out_pin> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVDS_25" for instance <exp_time_out_pin> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <exp_user_in_pin> in unit <u2plus>.
Set user-defined property "DIFF_TERM = FALSE" for instance <exp_user_in_pin> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <exp_user_in_pin> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <exp_user_in_pin> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <exp_user_in_pin> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVDS_25" for instance <exp_user_in_pin> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <exp_user_out_pin> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVDS_25" for instance <exp_user_out_pin> in unit <u2plus>.
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "CLKFX_DIVIDE = 1" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "CLKFX_MULTIPLY = 4" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "CLKIN_PERIOD = 10.000000" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "CLK_FEEDBACK = 1X" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "DSS_MODE = NONE" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "FACTORY_JF = 8080" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "PHASE_SHIFT = 0" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "SIM_MODE = SAFE" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "STARTUP_WAIT = FALSE" for instance <DCM_INST> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <scl_pin> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <scl_pin> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <scl_pin> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <scl_pin> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <scl_pin> in unit <u2plus>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <scl_pin> in unit <u2plus>.
Set user-defined property "SLEW = SLOW" for instance <scl_pin> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <sda_pin> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <sda_pin> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <sda_pin> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <sda_pin> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <sda_pin> in unit <u2plus>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <sda_pin> in unit <u2plus>.
Set user-defined property "SLEW = SLOW" for instance <sda_pin> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[0].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[0].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[0].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[0].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[0].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[0].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[0].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[1].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[1].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[1].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[1].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[1].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[1].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[1].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[2].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[2].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[2].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[2].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[2].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[2].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[2].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[3].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[3].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[3].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[3].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[3].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[3].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[3].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[4].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[4].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[4].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[4].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[4].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[4].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[4].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[5].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[5].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[5].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[5].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[5].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[5].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[5].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[6].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[6].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[6].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[6].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[6].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[6].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[6].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[7].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[7].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[7].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[7].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[7].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[7].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[7].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[8].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[8].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[8].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[8].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[8].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[8].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[8].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[9].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[9].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[9].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[9].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[9].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[9].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[9].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[10].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[10].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[10].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[10].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[10].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[10].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[10].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[11].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[11].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[11].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[11].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[11].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[11].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[11].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[12].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[12].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[12].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[12].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[12].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[12].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[12].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[13].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[13].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[13].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[13].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[13].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[13].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[13].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[14].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[14].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[14].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[14].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[14].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[14].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[14].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[15].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[15].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[15].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[15].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[15].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[15].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[15].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[16].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[16].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[16].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[16].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[16].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[16].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[16].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[17].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[17].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[17].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[17].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[17].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[17].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[17].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[18].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[18].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[18].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[18].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[18].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[18].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[18].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[19].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[19].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[19].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[19].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[19].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[19].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[19].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[20].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[20].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[20].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[20].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[20].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[20].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[20].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[21].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[21].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[21].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[21].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[21].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[21].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[21].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[22].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[22].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[22].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[22].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[22].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[22].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[22].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[23].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[23].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[23].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[23].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[23].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[23].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[23].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[24].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[24].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[24].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[24].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[24].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[24].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[24].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[25].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[25].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[25].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[25].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[25].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[25].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[25].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[26].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[26].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[26].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[26].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[26].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[26].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[26].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[27].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[27].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[27].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[27].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[27].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[27].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[27].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[28].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[28].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[28].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[28].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[28].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[28].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[28].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[29].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[29].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[29].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[29].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[29].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[29].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[29].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[30].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[30].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[30].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[30].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[30].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[30].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[30].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[31].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[31].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[31].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[31].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[31].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[31].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[31].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[32].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[32].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[32].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[32].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[32].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[32].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[32].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[33].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[33].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[33].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[33].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[33].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[33].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[33].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[34].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[34].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[34].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[34].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[34].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[34].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[34].RAM_D_i> in unit <u2plus>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_RAM_D_IO[35].RAM_D_i> in unit <u2plus>.
Set user-defined property "DRIVE = 12" for instance <gen_RAM_D_IO[35].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_RAM_D_IO[35].RAM_D_i> in unit <u2plus>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_RAM_D_IO[35].RAM_D_i> in unit <u2plus>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_RAM_D_IO[35].RAM_D_i> in unit <u2plus>.
Set user-defined property "IOSTANDARD = LVCMOS25" for instance <gen_RAM_D_IO[35].RAM_D_i> in unit <u2plus>.
Set user-defined property "SLEW = FAST" for instance <gen_RAM_D_IO[35].RAM_D_i> in unit <u2plus>.
Analyzing module <capture_ddrlvds> in library <work>.
WIDTH = 32'sb00000000000000000000000000001110
Module <capture_ddrlvds> is correct for synthesis.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <clkbuf> in unit <capture_ddrlvds>.
Set user-defined property "DIFF_TERM = TRUE" for instance <clkbuf> in unit <capture_ddrlvds>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <clkbuf> in unit <capture_ddrlvds>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <clkbuf> in unit <capture_ddrlvds>.
Set user-defined property "IOSTANDARD = LVDS_33" for instance <clkbuf> in unit <capture_ddrlvds>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_lvds_pins[0].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "DIFF_TERM = FALSE" for instance <gen_lvds_pins[0].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_lvds_pins[0].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_lvds_pins[0].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_lvds_pins[0].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IOSTANDARD = LVDS_33" for instance <gen_lvds_pins[0].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "DDR_ALIGNMENT = C1" for instance <gen_lvds_pins[0].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "INIT_Q0 = 0" for instance <gen_lvds_pins[0].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "INIT_Q1 = 0" for instance <gen_lvds_pins[0].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "SRTYPE = SYNC" for instance <gen_lvds_pins[0].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_lvds_pins[1].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "DIFF_TERM = FALSE" for instance <gen_lvds_pins[1].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_lvds_pins[1].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_lvds_pins[1].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_lvds_pins[1].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IOSTANDARD = LVDS_33" for instance <gen_lvds_pins[1].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "DDR_ALIGNMENT = C1" for instance <gen_lvds_pins[1].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "INIT_Q0 = 0" for instance <gen_lvds_pins[1].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "INIT_Q1 = 0" for instance <gen_lvds_pins[1].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "SRTYPE = SYNC" for instance <gen_lvds_pins[1].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_lvds_pins[2].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "DIFF_TERM = FALSE" for instance <gen_lvds_pins[2].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_lvds_pins[2].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_lvds_pins[2].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_lvds_pins[2].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IOSTANDARD = LVDS_33" for instance <gen_lvds_pins[2].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "DDR_ALIGNMENT = C1" for instance <gen_lvds_pins[2].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "INIT_Q0 = 0" for instance <gen_lvds_pins[2].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "INIT_Q1 = 0" for instance <gen_lvds_pins[2].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "SRTYPE = SYNC" for instance <gen_lvds_pins[2].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_lvds_pins[3].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "DIFF_TERM = FALSE" for instance <gen_lvds_pins[3].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_lvds_pins[3].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_lvds_pins[3].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_lvds_pins[3].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IOSTANDARD = LVDS_33" for instance <gen_lvds_pins[3].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "DDR_ALIGNMENT = C1" for instance <gen_lvds_pins[3].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "INIT_Q0 = 0" for instance <gen_lvds_pins[3].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "INIT_Q1 = 0" for instance <gen_lvds_pins[3].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "SRTYPE = SYNC" for instance <gen_lvds_pins[3].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_lvds_pins[4].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "DIFF_TERM = FALSE" for instance <gen_lvds_pins[4].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_lvds_pins[4].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <gen_lvds_pins[4].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <gen_lvds_pins[4].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IOSTANDARD = LVDS_33" for instance <gen_lvds_pins[4].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "DDR_ALIGNMENT = C1" for instance <gen_lvds_pins[4].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "INIT_Q0 = 0" for instance <gen_lvds_pins[4].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "INIT_Q1 = 0" for instance <gen_lvds_pins[4].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "SRTYPE = SYNC" for instance <gen_lvds_pins[4].iddr2> in unit <capture_ddrlvds>.
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <gen_lvds_pins[5].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "DIFF_TERM = FALSE" for instance <gen_lvds_pins[5].ibufds> in unit <capture_ddrlvds>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <gen_lvds_pins[5].ibufds> in unit <capture_ddrlvds>.