cpm22-XPBIOS.z80

	PROCESSOR	Z80
	ORG	0000H
	JP	XPCOLD

	ORG	0038H
	JP	INT0INT

;
; XXX: CP/M common part is included here
;

;
;**************************************************************
;*
;*        BIOS FOR HD647180 ON LUNA
;*
;**************************************************************
;
; The initialization part is based on Izumi Tsutsui's
;   a dumb SSG player for OMRON LUNA's "XP" processor HD647180 and YM2149
;
; Copyright (c) 2016 Izumi Tsutsui.  All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
; 1. Redistributions of source code must retain the above copyright
;    notice, this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright
;    notice, this list of conditions and the following disclaimer in the
;    documentation and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
; OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
; IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
; THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;

XPCOLD:
	; Disable interrupt
	DI

	; I/O control register
	; (3FH) = 00H
	;  - internal I/O address: 0000H - 003FH
	LD	A,00H
	DB	0EDH, 39H, 3FH		;OUT0	(3FH),A

	; DMA/WAIT control register
	; (32H) = 20H
	;  - no memory wait
	;  - 3 external I/O wait
	;  - disable DMA
	LD	A,20H
	DB	0EDH, 39H, 32H		;OUT0	(32H),A

	; refresh control register
	; (36H) = 03H
	;  - disable refresh controller (647180 on LUNAs uses SRAM)
	;  - cycle interval 80 states (recommended for 6.144MHz clock)
	LD	A,03H
	DB	0EDH, 39H, 36H		;OUT0	(36H),A

	; set MMU control registers
	; (3AH) = 00H
	;  - map 3port RAM first 64k to 0000H
	LD	A,00H
	DB	0EDH, 39H, 3AH		;OUT0	(3AH),A

	; (38H) = 00H
	;  - map 3port RAM first 64k to 0000H
	LD	A,00H
	DB	0EDH, 39H, 38H		;OUT0	(38H),A

	; (39H) = 00H
	;  - bank area disabled
	LD	A,00H
	DB	0EDH, 39H, 39H		;OUT0	(39H),A

	; set stack pointer XXX:CCPSTACK is enough?
	LD	SP,CCPSTACK

	; set Interrupt/TRAP control reg
	; (34H) = 00H
	;  - disable external interrupts ITE2, ITE1
	;  - enable external interrupt ITE0
	LD	A,01H
	DB	0EDH, 39H, 34H		;OUT0	(34H),A

	; set Interrupt Vector Low reg
	; (33H) = 00H
	;  - interrupt vectors of internal I/O: 00H - 10H
	LD	A,00H
	DB	0EDH, 39H, 33H		;OUT0	(33H),A

	; set interrupt register
	; I = 7EH
	;  - vector table is located at 7E00H - 7EFFH
	LD	A,7EH
	LD	I,A
	; use interrupt mode 1
	;  - note IM only affects external /INT0
	IM	1

	; Enable Timer Ch0   TCR (10H) = 01h
	LD	A,01H
	DB	0EDH, 39H, 10H		;OUT0	(10H),A

	; initialize ASCI0
	;
	; (02H) : ASCI Control Register B0
	;         PreScale = x10, Rate=16, Baud Rate=9600
	DB	0EDH, 38H, 02H		;IN0	A,(02H)
	RES	5, A			; PreScale = 0 (/10)
	RES	3, A			; Divide Ratio = 0 (/16)
	RES	2, A			;
	DB	0CBH, 0CFH ;	SET	1, A
	RES	0, A			;
	DB	0EDH, 39H, 02H		;OUT0	(02H),A

	; (00H) : ASCI Control Register A0
	;         enable receiver(bit 6) and transmitter(bit 5)
	;         /RTS0 (Request to Send) (bit 4)
	;         8bit, 1stop bit, no parity (bit 2-0)
	DB	0EDH, 38H, 00H		;IN0	A,(00H)
	DB	0CBH, 0F7H ;	SET	6, A
	DB	0CBH, 0EFH ;	SET	5, A
	RES	4, A			;/RTS0
	DB	0CBH, 0D7H ;	SET	2, A
	RES	1, A			; Start + 8bit + 1 Stop
	RES	0, A			;
	DB	0EDH, 39H, 00H		;OUT0	(00H),A

	; (04H) : ASCI Status Register 0
	;         receive interrupt enable(bit 3)
;	DB	0EDH, 38H, 04H		;IN0	A,(04H)
;	DB	0CBH, 0DFH ;	SET	3, A
;	DB	0EDH, 39H, 04H		;OUT0	(04H),A

	; format RAM DISK
	LD	HL, DISKTOP
	LD	BC, 8000H
	LD	A, (EMPTYFCB)
	LD	E, A
_FMT1
	LD	(HL), E
	INC	HL
	DEC	BC
	LD	A, B		; BC == 0 ?
	OR	C
	JR	NZ, _FMT1

	; say hello to the world
	LD	HL, MSG_BANNER
	CALL	PUTS0
	LD	HL, INBUFF + 2
	CALL	PUTS0

	; enable interrupt
	EI

	; jump to main
	JP	SETENTRY

STRAYINT:
	EI
	RET

ASCI0INT:
	PUSH	AF

	; read RDR0 (ASCI Receive Data Register)
	DB	0EDH, 38H, 08H		;IN0	A,(08H)
	CALL	PUTC0

	POP	AF
	EI
	RETI
;
; Put one character, wait until Transmitter flag is clear
;   Broken: none
;
PUTC0:
	PUSH	HL
	PUSH	AF
	LD	HL, XPTTY_TXFLAG
_PUTC00:
	LD	A, (HL)
	OR	A
	JR	NZ, _PUTC00		; if TXFLAG != 0, Tx buffer is not empty
	DEC	HL			; HL is XPTTY_TXBUF
	POP	AF
	LD	(HL), A
	INC	HL			; HL is XPTTY_TXFLAG
	LD	(HL), 0FFH		; set FLAG
	POP	HL
	DB	0EDH, 39H, 0A0H		;OUT0	(0A0H), A / send level5 intr.
	RET
;
; Put zero-terminated string that starts at (HL)
;   Broken: HL
;
PUTS0:
	PUSH	AF
_PUTS00:
	LD	A, (HL)
	INC	HL
	OR	A		; A == 0 ?
	JR	Z, _PUTS01	;
	CALL	PUTC0
	JR	_PUTS00
_PUTS01
	POP	AF
	RET
;
; Get one character, wait until Receive buffer is full
;   Broken: A
;
GETC0:
	PUSH	HL			; save HL
	LD	HL, XPTTY_RXFLAG
	LD	A, (HL)
	OR	A
	JR	NZ, _GETC01		; if RXFLAG != 0, Rx buffer has data
	XOR	A			; else return with A=0
	POP	HL			; restore HL
	RET
_GETC01:
	DEC	HL			; HL is XPTTY_RFBUF
	LD	A, (HL)			; A has the character
	INC	HL			; HL is XPTTY_RXFLAG
	LD	(HL), 0			; reset FLAG
	POP	HL			; restore HL
	DB	0EDH, 39H, 0A0H		;OUT0	(0A0H), A / send level5 intr.
	RET
;
; Get one character, wait until Receive buffer is full
;   Broken: A
;
INT0INT:
	DB	0EDH, 39H, 90H		;OUT0	(090H), A / clear intr. req.
	PUSH	HL			; save HL
	LD	HL, XPTTY_RXBUF
	LD	A, (HL)			; A has the character
	INC	HL			; HL is XPTTY_RXFLAG
	LD	(HL), 0			; reset FLAG
	POP	HL			; restore HL
	EI
	RETI
;
; Debug routine
;
XP_HEX1:
	PUSH	AF
	PUSH	AF
	AND	0F0H
	SRL	A
	SRL	A
	SRL	A
	SRL	A			; A has higher 4 bit value
	ADD	A, '0'
	CP	':'			; '9' + 1
	JR	C, _XP_HEX10
	ADD	A, 'a' - ':'
_XP_HEX10:
	CALL	PUTC0
	POP	AF
	AND	00FH
	ADD	A, '0'
	CP	':'			; '9' + 1
	JR	C, _XP_HEX20
	ADD	A, 'a' - ':'
_XP_HEX20:
	CALL	PUTC0
	POP	AF
	RET

MSG_BANNER:
	DB	0DH, 0AH, "LUNA XP(HD647180) CP/M 2.2", 0DH, 0AH, 00H

; ** DISK WORK AREA **
TRKADRS:
	DW	0
SCTADRS:
	DW	0
DMAADRS:
	DW	0
DRVNO:
	DB	0
CONSTDT:
	DB	0

org_7E00:
	DS	7E00H - org_7E00

	ORG	7E00H
IVECTBL:

VINT1:
	; +00
	DW	STRAYINT
VINT2:
	; +02
	DW	STRAYINT
VTMR0:
	; +04
	DW	STRAYINT
VTMR1:
	; +06
	DW	STRAYINT
VDMAC0:
	; +08
	DW	STRAYINT
VDMAC1:
	; +0A
	DW	STRAYINT
VCSIO:
	; +0C
	DW	STRAYINT
VASCI0:
	; +0E
	DW	ASCI0INT
VASCI1:
	; +10
	DW	STRAYINT

DIRBF:
	DS	128
CSV00:
	DB	0,0,0,0,0,0,0,0
ALV00:
	DB	0,0,0

; ** XPTTY I/F **

	ORG	7F00H
XPTTY_MAGIC:
	DB	"XPTY"		; 4 bytes

XPTTY_TXBUF:
	DS	1		; 1 bytes
XPTTY_TXFLAG:
	DS	1		; 1 bytes
	DS	2		; 2 bytes (padding)

XPTTY_RXBUF:
	DS	1		; 1 bytes
XPTTY_RXFLAG:
	DS	1		; 1 bytes
	DS	2		; 2 bytes (padding)

; ** RAM DISK **

	ORG	8000H
DISKTOP:
	DS	8000H

;*
;******************   E N D   O F   C P / M   *****************
;*
END