deskew.vhd

----------------------------------------------------------------------------------
-- Company:        apertus° Association
-- Engineer:       Apurva Nandan
-- 
-- Create Date:    00:22:57 08/05/2019 
-- Design Name: 
-- Module Name:    ft601_top
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description:    Dynamic Phase Alignment
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity deskew is
	port (
		sclk     : in  std_logic;
		rst      : in  std_logic;
		data_val : in  std_logic;
		data_fb  : in  std_logic_vector(9 downto 0);
		delay    : out std_logic_vector(4 downto 0) := (others => '0');
		done     : out std_logic := '0'
	);
end entity deskew;

architecture rtl of deskew is

	signal data_ref : std_logic_vector(9 downto 0) := (others => '0');
	signal dly_ind  : std_logic_vector(4 downto 0) := (others => '0');
	signal min_dly  : std_logic_vector(5 downto 0) := (others => '0');
	signal max_dly  : std_logic_vector(5 downto 0) := (others => '0');
	signal state    : std_logic_vector(2 downto 0) := (others => '0');
	signal avg_dly  : std_logic_vector(5 downto 0) := (others => '0');

begin

	delay   <= dly_ind;
	avg_dly <= min_dly + max_dly;
	done    <= state(2);

	process(sclk)
	begin
		if rising_edge(sclk) then
			if rst = '1' then
				data_ref <= (others => '0');
				dly_ind  <= (others => '0');
				min_dly  <= (others => '0');
				max_dly  <= (others => '0');
				state    <= (others => '0');

			else
				if data_val = '1' then
					if state = "000" then
						data_ref <= data_fb;
						state    <= "001";

					elsif state = "010" then
						data_ref <= data_fb;
						state    <= "011";

					else
						data_ref <= data_ref;
					end if;
						
					if (data_fb xor data_ref) /= "0000000000" and state = "001" then
						min_dly <= "0" & dly_ind;
						state   <= "010";
					end if;
						
					if (data_fb xor data_ref) /= "0000000000" and state = "011" then
						max_dly <= "0" & dly_ind;
						state   <= "100";
					end if;
						
					if state = "000" then
						dly_ind <= (others => '0');

					elsif state = "001" and dly_ind /= "11111" then
						dly_ind <= dly_ind + '1';

					elsif state = "010" then
						dly_ind <= (others => '1');

					elsif state = "011" and dly_ind /= "00000" then
						dly_ind <= dly_ind - '1';

					else
						dly_ind <= avg_dly(5 downto 1);
					end if;
				end if;
			end if;
		end if;
	end process;

end architecture rtl;