ddrunmodified.vhd

-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2
-- Module  Version: 5.8
--/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n unmodified -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 375 -gear 4 -clk eclk -aligned -del 8 

-- Mon Aug 26 03:11:20 2019


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library machxo2;
use machxo2.components.all;

entity unmodifiedrx_sync is
port(
  rstn :  in std_logic;
  clk :  in std_logic;
  init :  in std_logic;
  lock :  in std_logic;
  uddcntln :  out std_logic;
  freeze :  out std_logic;
  rx_stop :  out std_logic;
  rx_reset :  out std_logic;
  rx_start :  out std_logic);
end unmodifiedrx_sync;

architecture beh of unmodifiedrx_sync is
  signal CTRL_CNT : std_logic_vector(2 downto 0);
  signal STATE : std_logic_vector(5 downto 0);
  signal STATE_NS : std_logic_vector(1 downto 0);
  signal STATE_NS_I_1 : std_logic_vector(1 to 1);
  signal CTRL_CNTE_0 : std_logic_vector(2 to 2);
  signal STATE_NS_I_X1_1 : std_logic_vector(0 to 0);
  signal CTRL_CNT_FAST : std_logic_vector(2 to 2);
  signal CTRL_CNTE_0_FAST : std_logic_vector(2 to 2);
  signal STATE_NS_I_MB_1 : std_logic_vector(0 to 0);
  signal UDDCNTLN_3 : std_logic ;
  signal FREEZE_4 : std_logic ;
  signal RX_STOP_5 : std_logic ;
  signal RX_START_6 : std_logic ;
  signal LOCK_P1 : std_logic ;
  signal LOCK_P2 : std_logic ;
  signal CTRL_CNT_N0 : std_logic ;
  signal CTRL_CNT_N1 : std_logic ;
  signal N_118_LI : std_logic ;
  signal N_166 : std_logic ;
  signal N_137 : std_logic ;
  signal N_169_I : std_logic ;
  signal N_170_I : std_logic ;
  signal N_171_I : std_logic ;
  signal N_172_I : std_logic ;
  signal N_161_I : std_logic ;
  signal FREEZEE_0 : std_logic ;
  signal RX_STARTE_0 : std_logic ;
  signal RX_STOPE_0 : std_logic ;
  signal UDDCNTLNE_0 : std_logic ;
  signal FREEZE_RNO_0 : std_logic ;
  signal LOCK_P2_FAST : std_logic ;
  signal RX_START_FAST : std_logic ;
  signal RX_STARTE_0_FAST : std_logic ;
  signal N_169_I_SX : std_logic ;
  signal CTRL_CNT_N0_0_S_SX : std_logic ;
  signal CTRL_CNT_N1_0_S_0_X0 : std_logic ;
  signal CTRL_CNT_N1_0_S_0_X1 : std_logic ;
  signal G0_1_S_FAST_SX : std_logic ;
  signal G0_1_S_SX : std_logic ;
  signal RSTN_I : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
RSTN_RNIB582: INV port map (
    A => rstn,
    Z => RSTN_I);
UDDCNTLN_REG_Z104: FD1S3BX port map (
    D => UDDCNTLNE_0,
    CK => clk,
    PD => RSTN_I,
    Q => UDDCNTLN_3);
\STATE[0]_REG_Z106\: FD1S3BX port map (
    D => STATE_NS(0),
    CK => clk,
    PD => RSTN_I,
    Q => STATE(0));
\STATE[1]_REG_Z108\: FD1S3DX port map (
    D => STATE_NS(1),
    CK => clk,
    CD => RSTN_I,
    Q => STATE(1));
\STATE[2]_REG_Z110\: FD1S3DX port map (
    D => N_172_I,
    CK => clk,
    CD => RSTN_I,
    Q => STATE(2));
\STATE[3]_REG_Z112\: FD1S3DX port map (
    D => N_171_I,
    CK => clk,
    CD => RSTN_I,
    Q => STATE(3));
\STATE[4]_REG_Z114\: FD1S3DX port map (
    D => N_170_I,
    CK => clk,
    CD => RSTN_I,
    Q => STATE(4));
\STATE[5]_REG_Z116\: FD1S3DX port map (
    D => N_169_I,
    CK => clk,
    CD => RSTN_I,
    Q => STATE(5));
RX_STOP_REG_Z118: FD1S3DX port map (
    D => RX_STOPE_0,
    CK => clk,
    CD => RSTN_I,
    Q => RX_STOP_5);
RX_START_FAST_REG_Z120: FD1S3DX port map (
    D => RX_STARTE_0_FAST,
    CK => clk,
    CD => RSTN_I,
    Q => RX_START_FAST);
RX_START_REG_Z122: FD1S3DX port map (
    D => RX_STARTE_0,
    CK => clk,
    CD => RSTN_I,
    Q => RX_START_6);
RX_RESET_REG_Z124: FD1S3DX port map (
    D => STATE(2),
    CK => clk,
    CD => RSTN_I,
    Q => rx_reset);
LOCK_P2_FAST_REG_Z126: FD1S3DX port map (
    D => LOCK_P1,
    CK => clk,
    CD => RSTN_I,
    Q => LOCK_P2_FAST);
LOCK_P2_REG_Z128: FD1S3DX port map (
    D => LOCK_P1,
    CK => clk,
    CD => RSTN_I,
    Q => LOCK_P2);
LOCK_P1_REG_Z130: FD1S3DX port map (
    D => lock,
    CK => clk,
    CD => RSTN_I,
    Q => LOCK_P1);
FREEZE_REG_Z132: FD1S3DX port map (
    D => FREEZEE_0,
    CK => clk,
    CD => RSTN_I,
    Q => FREEZE_4);
\CTRL_CNT[0]_REG_Z134\: FD1P3DX port map (
    D => CTRL_CNT_N0,
    SP => N_161_I,
    CK => clk,
    CD => RSTN_I,
    Q => CTRL_CNT(0));
\CTRL_CNT[1]_REG_Z136\: FD1P3DX port map (
    D => CTRL_CNT_N1,
    SP => N_161_I,
    CK => clk,
    CD => RSTN_I,
    Q => CTRL_CNT(1));
\CTRL_CNT_FAST[2]_REG_Z138\: FD1S3DX port map (
    D => CTRL_CNTE_0_FAST(2),
    CK => clk,
    CD => RSTN_I,
    Q => CTRL_CNT_FAST(2));
\CTRL_CNT[2]_REG_Z140\: FD1S3DX port map (
    D => CTRL_CNTE_0(2),
    CK => clk,
    CD => RSTN_I,
    Q => CTRL_CNT(2));
N_118_LI <= not CTRL_CNT(0) and CTRL_CNT(1) and not CTRL_CNT_FAST(2);
N_166 <= (not LOCK_P2_FAST and RX_START_6) or 
	(not init and RX_START_6);
N_137 <= (not RX_START_6 and STATE(5)) or 
	(init and LOCK_P2 and STATE(5));
N_172_I <= (N_118_LI and STATE(1)) or 
	(not N_118_LI and not N_166 and STATE(2));
N_171_I <= (N_118_LI and STATE(2)) or 
	(not N_118_LI and not N_166 and STATE(3));
N_170_I <= (N_118_LI and STATE(3)) or 
	(not N_118_LI and not N_166 and STATE(4));
STATE_NS_I_1(1) <= (not LOCK_P2 and RX_START_6 and not STATE(0)) or 
	(not init and RX_START_6) or 
	(not init and STATE(0));
STATE_NS(1) <= (STATE(0) and not STATE_NS_I_1(1)) or 
	(not N_118_LI and STATE(1) and not STATE_NS_I_1(1));
RX_STOPE_0 <= (RX_STOP_5 and not STATE(4)) or 
	(STATE(2));
UDDCNTLNE_0 <= not STATE(2) and UDDCNTLN_3;
N_161_I <= (not CTRL_CNT_FAST(2)) or 
	(not CTRL_CNT(1)) or 
	(STATE(0));
FREEZE_RNO_0 <= not CTRL_CNT(0) and not CTRL_CNT(2) and STATE(4);
FREEZEE_0 <= (not CTRL_CNT(1) and FREEZE_4) or 
	(not FREEZE_RNO_0 and FREEZE_4) or 
	(STATE(1));
CTRL_CNTE_0(2) <= (CTRL_CNT(0) and CTRL_CNT(1) and not STATE(0)) or 
	(CTRL_CNT(2) and not STATE(0));
STATE_NS_I_X1_1(0) <= (not RX_START_FAST) or 
	(not CTRL_CNT_FAST(2) and not STATE(5));
CTRL_CNTE_0_FAST(2) <= (CTRL_CNT(0) and CTRL_CNT(1) and not STATE(0)) or 
	(CTRL_CNT_FAST(2) and not STATE(0));
N_169_I_SX <= not CTRL_CNT(0) and CTRL_CNT(1) and not CTRL_CNT(2) and STATE(4);
N_169_I <= (N_137) or 
	(N_169_I_SX);
CTRL_CNT_N0_0_S_SX <= (CTRL_CNT(0)) or 
	(STATE(0));
CTRL_CNT_N0 <= (not CTRL_CNT(1) and not CTRL_CNT_N0_0_S_SX) or 
	(CTRL_CNT(2) and not CTRL_CNT_N0_0_S_SX) or 
	(not CTRL_CNT_N0_0_S_SX and STATE(5));
CTRL_CNT_N1_0_S_0_X0 <= CTRL_CNT(0) and not STATE(0);
CTRL_CNT_N1_0_S_0_X1 <= (not CTRL_CNT(0) and CTRL_CNT(2) and not STATE(0)) or 
	(not CTRL_CNT(0) and not STATE(0) and STATE(5));
CTRL_CNT_N1_0_S_0: PFUMX port map (
    ALUT => CTRL_CNT_N1_0_S_0_X1,
    BLUT => CTRL_CNT_N1_0_S_0_X0,
    C0 => CTRL_CNT(1),
    Z => CTRL_CNT_N1);
G0_1_S_FAST_SX <= (not STATE(5)) or 
	(not LOCK_P2 and not RX_START_FAST) or 
	(not CTRL_CNT(2) and not RX_START_FAST);
RX_STARTE_0_FAST <= (not CTRL_CNT(0) and CTRL_CNT(1) and not G0_1_S_FAST_SX) or 
	(not G0_1_S_FAST_SX and RX_START_FAST);
G0_1_S_SX <= (not STATE(5)) or 
	(not LOCK_P2 and not RX_START_6) or 
	(not CTRL_CNT(2) and not RX_START_6);
RX_STARTE_0 <= (not CTRL_CNT(0) and CTRL_CNT(1) and not G0_1_S_SX) or 
	(not G0_1_S_SX and RX_START_6);
STATE_NS_I_MB_1(0) <= (not CTRL_CNT(1) and not RX_START_FAST) or 
	(CTRL_CNT(0) and not RX_START_FAST) or 
	(not RX_START_FAST and STATE_NS_I_X1_1(0)) or 
	(not CTRL_CNT(0) and CTRL_CNT(1) and STATE_NS_I_X1_1(0));
STATE_NS(0) <= (not LOCK_P2 and not STATE(0) and not STATE_NS_I_MB_1(0)) or 
	(not init and not STATE_NS_I_MB_1(0)) or 
	(not init and STATE(0));
NN_1 <= '0';
NN_2 <= '1';
uddcntln <= UDDCNTLN_3;
freeze <= FREEZE_4;
rx_stop <= RX_STOP_5;
rx_start <= RX_START_6;
end beh;


library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library MACHXO2;
use MACHXO2.components.all;
-- synopsys translate_on

entity unmodified is
    port (
        alignwd: in  std_logic; 
        clk: in  std_logic; 
        clk_s: in  std_logic; 
        dqsdll_reset: in  std_logic; 
        freeze: in  std_logic; 
        init: in  std_logic; 
        lock: out  std_logic; 
        reset: in  std_logic; 
        rx_ready: out  std_logic; 
        sclk: out  std_logic; 
        uddcntln: in  std_logic; 
        datain: in  std_logic_vector(4 downto 0); 
        q: out  std_logic_vector(39 downto 0));
end unmodified;

architecture Structure of unmodified is

    -- internal signal declarations
    signal q7_4: std_logic;
    signal q6_4: std_logic;
    signal q5_4: std_logic;
    signal q4_4: std_logic;
    signal q3_4: std_logic;
    signal q2_4: std_logic;
    signal q1_4: std_logic;
    signal q0_4: std_logic;
    signal q7_3: std_logic;
    signal q6_3: std_logic;
    signal q5_3: std_logic;
    signal q4_3: std_logic;
    signal q3_3: std_logic;
    signal q2_3: std_logic;
    signal q1_3: std_logic;
    signal q0_3: std_logic;
    signal q7_2: std_logic;
    signal q6_2: std_logic;
    signal q5_2: std_logic;
    signal q4_2: std_logic;
    signal q3_2: std_logic;
    signal q2_2: std_logic;
    signal q1_2: std_logic;
    signal q0_2: std_logic;
    signal q7_1: std_logic;
    signal q6_1: std_logic;
    signal q5_1: std_logic;
    signal q4_1: std_logic;
    signal q3_1: std_logic;
    signal q2_1: std_logic;
    signal q1_1: std_logic;
    signal q0_1: std_logic;
    signal q7_0: std_logic;
    signal q6_0: std_logic;
    signal q5_0: std_logic;
    signal q4_0: std_logic;
    signal q3_0: std_logic;
    signal q2_0: std_logic;
    signal q1_0: std_logic;
    signal q0_0: std_logic;
    signal sclk_t: std_logic;
    signal cdiv1: std_logic;
    signal rx_reset: std_logic;
    signal xstop: std_logic;
    signal freeze_i: std_logic;
    signal uddcntln_i: std_logic;
    signal reset_inv: std_logic;
    signal eclki: std_logic;
    signal dqsdel: std_logic;
    signal lock_chk: std_logic;
    signal freeze_t: std_logic;
    signal uddcntln_t: std_logic;
    signal eclko: std_logic;
    signal dataini_t4: std_logic;
    signal dataini_t3: std_logic;
    signal dataini_t2: std_logic;
    signal dataini_t1: std_logic;
    signal dataini_t0: std_logic;
    signal buf_clk: std_logic;
    signal buf_dataini4: std_logic;
    signal buf_dataini3: std_logic;
    signal buf_dataini2: std_logic;
    signal buf_dataini1: std_logic;
    signal buf_dataini0: std_logic;

    -- local component declarations
    component AND2
        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
    end component;
    component INV
        port (A: in  std_logic; Z: out  std_logic);
    end component;
    component OR2
        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
    end component;
    component IB
        port (I: in  std_logic; O: out  std_logic);
    end component;
    component IDDRX4B
        port (D: in  std_logic; ECLK: in  std_logic; SCLK: in  std_logic; 
            RST: in  std_logic; ALIGNWD: in  std_logic; 
            Q0: out  std_logic; Q1: out  std_logic; Q2: out  std_logic; 
            Q3: out  std_logic; Q4: out  std_logic; Q5: out  std_logic; 
            Q6: out  std_logic; Q7: out  std_logic);
    end component;
    component DQSDLLC
        generic (FORCE_MAX_DELAY : in String; FIN : in String; 
                LOCK_SENSITIVITY : in String);
        port (CLK: in  std_logic; RST: in  std_logic; 
            UDDCNTLN: in  std_logic; FREEZE: in  std_logic; 
            LOCK: out  std_logic; DQSDEL: out  std_logic);
    end component;
    component DELAYE
        generic (DEL_VALUE : in String; DEL_MODE : in String);
        port (A: in  std_logic; Z: out  std_logic);
    end component;
    component DLLDELC
        port (CLKI: in  std_logic; DQSDEL: in  std_logic; 
            CLKO: out  std_logic);
    end component;
    component CLKDIVC
        generic (DIV : in String);
        port (RST: in  std_logic; CLKI: in  std_logic; 
            ALIGNWD: in  std_logic; CDIV1: out  std_logic; 
            CDIVX: out  std_logic);
    end component;
    component ECLKSYNCA
        port (ECLKI: in  std_logic; STOP: in  std_logic; 
            ECLKO: out  std_logic);
    end component;
    component unmodifiedrx_sync
        port (rstn: in  std_logic; clk: in  std_logic; 
            init: in  std_logic; lock: in  std_logic; 
            uddcntln: out  std_logic; freeze: out  std_logic; 
            rx_stop: out  std_logic; rx_reset: out  std_logic; 
            rx_start: out  std_logic);
    end component;
    attribute IO_TYPE : string; 
    attribute IO_TYPE of Inst2_IB : label is "LVDS25";
    attribute IO_TYPE of Inst1_IB4 : label is "LVDS25";
    attribute IO_TYPE of Inst1_IB3 : label is "LVDS25";
    attribute IO_TYPE of Inst1_IB2 : label is "LVDS25";
    attribute IO_TYPE of Inst1_IB1 : label is "LVDS25";
    attribute IO_TYPE of Inst1_IB0 : label is "LVDS25";
    attribute syn_keep : boolean;
    attribute NGD_DRC_MASK : integer;
    attribute NGD_DRC_MASK of Structure : architecture is 1;

begin
    -- component instantiation statements
    INV_0: INV
        port map (A=>reset, Z=>reset_inv);

    AND2_t1: AND2
        port map (A=>uddcntln, B=>uddcntln_i, Z=>uddcntln_t);

    OR2_t0: OR2
        port map (A=>freeze, B=>freeze_i, Z=>freeze_t);

    Inst8_IDDRX4B4: IDDRX4B
        port map (D=>dataini_t4, ECLK=>eclko, SCLK=>sclk_t, RST=>reset, 
            ALIGNWD=>alignwd, Q0=>q0_4, Q1=>q1_4, Q2=>q2_4, Q3=>q3_4, 
            Q4=>q4_4, Q5=>q5_4, Q6=>q6_4, Q7=>q7_4);

    Inst8_IDDRX4B3: IDDRX4B
        port map (D=>dataini_t3, ECLK=>eclko, SCLK=>sclk_t, RST=>reset, 
            ALIGNWD=>alignwd, Q0=>q0_3, Q1=>q1_3, Q2=>q2_3, Q3=>q3_3, 
            Q4=>q4_3, Q5=>q5_3, Q6=>q6_3, Q7=>q7_3);

    Inst8_IDDRX4B2: IDDRX4B
        port map (D=>dataini_t2, ECLK=>eclko, SCLK=>sclk_t, RST=>reset, 
            ALIGNWD=>alignwd, Q0=>q0_2, Q1=>q1_2, Q2=>q2_2, Q3=>q3_2, 
            Q4=>q4_2, Q5=>q5_2, Q6=>q6_2, Q7=>q7_2);

    Inst8_IDDRX4B1: IDDRX4B
        port map (D=>dataini_t1, ECLK=>eclko, SCLK=>sclk_t, RST=>reset, 
            ALIGNWD=>alignwd, Q0=>q0_1, Q1=>q1_1, Q2=>q2_1, Q3=>q3_1, 
            Q4=>q4_1, Q5=>q5_1, Q6=>q6_1, Q7=>q7_1);

    Inst8_IDDRX4B0: IDDRX4B
        port map (D=>dataini_t0, ECLK=>eclko, SCLK=>sclk_t, RST=>reset, 
            ALIGNWD=>alignwd, Q0=>q0_0, Q1=>q1_0, Q2=>q2_0, Q3=>q3_0, 
            Q4=>q4_0, Q5=>q5_0, Q6=>q6_0, Q7=>q7_0);

    Inst7_CLKDIVC: CLKDIVC
        generic map (DIV=> "4.0")
        port map (RST=>reset, CLKI=>eclko, ALIGNWD=>alignwd, 
            CDIV1=>cdiv1, CDIVX=>sclk_t);

    Inst6_ECLKSYNCA: ECLKSYNCA
        port map (ECLKI=>eclki, STOP=>xstop, ECLKO=>eclko);

    Inst5_rx_sync: unmodifiedrx_sync
        port map (rstn=>reset_inv, clk=>clk_s, init=>init, 
            lock=>lock_chk, uddcntln=>uddcntln_i, freeze=>freeze_i, 
            rx_stop=>xstop, rx_reset=>rx_reset, rx_start=>rx_ready);

    Inst4_DLLDELC: DLLDELC
        port map (CLKI=>buf_clk, DQSDEL=>dqsdel, CLKO=>eclki);

    Inst3_DQSDLLC: DQSDLLC
        generic map (FORCE_MAX_DELAY=> "NO", FIN=> "375.0", 
        LOCK_SENSITIVITY=> "LOW")
        port map (CLK=>eclko, RST=>dqsdll_reset, UDDCNTLN=>uddcntln_t, 
            FREEZE=>freeze_t, LOCK=>lock_chk, DQSDEL=>dqsdel);

    udel_dataini4: DELAYE
        generic map (DEL_VALUE=> "DELAY8", DEL_MODE=> "USER_DEFINED")
        port map (A=>buf_dataini4, Z=>dataini_t4);

    udel_dataini3: DELAYE
        generic map (DEL_VALUE=> "DELAY8", DEL_MODE=> "USER_DEFINED")
        port map (A=>buf_dataini3, Z=>dataini_t3);

    udel_dataini2: DELAYE
        generic map (DEL_VALUE=> "DELAY8", DEL_MODE=> "USER_DEFINED")
        port map (A=>buf_dataini2, Z=>dataini_t2);

    udel_dataini1: DELAYE
        generic map (DEL_VALUE=> "DELAY8", DEL_MODE=> "USER_DEFINED")
        port map (A=>buf_dataini1, Z=>dataini_t1);

    udel_dataini0: DELAYE
        generic map (DEL_VALUE=> "DELAY8", DEL_MODE=> "USER_DEFINED")
        port map (A=>buf_dataini0, Z=>dataini_t0);

    Inst2_IB: IB
        port map (I=>clk, O=>buf_clk);

    Inst1_IB4: IB
        port map (I=>datain(4), O=>buf_dataini4);

    Inst1_IB3: IB
        port map (I=>datain(3), O=>buf_dataini3);

    Inst1_IB2: IB
        port map (I=>datain(2), O=>buf_dataini2);

    Inst1_IB1: IB
        port map (I=>datain(1), O=>buf_dataini1);

    Inst1_IB0: IB
        port map (I=>datain(0), O=>buf_dataini0);

    sclk <= sclk_t;
    q(39) <= q7_4;
    q(38) <= q7_3;
    q(37) <= q7_2;
    q(36) <= q7_1;
    q(35) <= q7_0;
    q(34) <= q6_4;
    q(33) <= q6_3;
    q(32) <= q6_2;
    q(31) <= q6_1;
    q(30) <= q6_0;
    q(29) <= q5_4;
    q(28) <= q5_3;
    q(27) <= q5_2;
    q(26) <= q5_1;
    q(25) <= q5_0;
    q(24) <= q4_4;
    q(23) <= q4_3;
    q(22) <= q4_2;
    q(21) <= q4_1;
    q(20) <= q4_0;
    q(19) <= q3_4;
    q(18) <= q3_3;
    q(17) <= q3_2;
    q(16) <= q3_1;
    q(15) <= q3_0;
    q(14) <= q2_4;
    q(13) <= q2_3;
    q(12) <= q2_2;
    q(11) <= q2_1;
    q(10) <= q2_0;
    q(9) <= q1_4;
    q(8) <= q1_3;
    q(7) <= q1_2;
    q(6) <= q1_1;
    q(5) <= q1_0;
    q(4) <= q0_4;
    q(3) <= q0_3;
    q(2) <= q0_2;
    q(1) <= q0_1;
    q(0) <= q0_0;
    lock <= lock_chk;
end Structure;

-- synopsys translate_off
library MACHXO2;
configuration Structure_CON of unmodified is
    for Structure
        for all:AND2 use entity MACHXO2.AND2(V); end for;
        for all:INV use entity MACHXO2.INV(V); end for;
        for all:OR2 use entity MACHXO2.OR2(V); end for;
        for all:IB use entity MACHXO2.IB(V); end for;
        for all:IDDRX4B use entity MACHXO2.IDDRX4B(V); end for;
        for all:DQSDLLC use entity MACHXO2.DQSDLLC(V); end for;
        for all:DELAYE use entity MACHXO2.DELAYE(V); end for;
        for all:DLLDELC use entity MACHXO2.DLLDELC(V); end for;
        for all:CLKDIVC use entity MACHXO2.CLKDIVC(V); end for;
        for all:ECLKSYNCA use entity MACHXO2.ECLKSYNCA(V); end for;
    end for;
end Structure_CON;

-- synopsys translate_on