ft601.vhd

----------------------------------------------------------------------------------
-- Company:        apertus° Association
-- Engineer:       Apurva Nandan
-- 
-- Create Date:    00:22:57 08/05/2019 
-- Design Name: 
-- Module Name:    ft601
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description:    FT601 Controller in FT245 mode
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ft601 is
    port (
        clk : in  std_logic;
        rst : in  std_logic;
        led : out std_logic;

        -- To FT601 chip
        ft601_data   : inout std_logic_vector(31 downto 0);
        ft601_be     : out   std_logic_vector(3 downto 0);
        ft601_rxf_n  : in    std_logic;
        ft601_txe_n  : in    std_logic;
        ft601_wr_n   : out   std_logic;
        ft601_siwu_n : out   std_logic;
        ft601_rd_n   : out   std_logic;
        ft601_oe_n   : out   std_logic;

        -- From Internal FIFOs
        data_in     : in  std_logic_vector(31 downto 0);
        req_data    : out std_logic;
        fifo_in_emp : in  std_logic;
        data_wr_en  : in  std_logic
    );

end entity ft601;


architecture rtl of ft601 is
    constant IDLE      : std_logic_vector(2 downto 0) := "000";
    constant INTMDT1   : std_logic_vector(2 downto 0) := "001";
    constant INTMDT2   : std_logic_vector(2 downto 0) := "010";
    constant INTMDT3   : std_logic_vector(2 downto 0) := "011";
    constant ACTIVE_TX : std_logic_vector(2 downto 0) := "101";

    --signal state     : std_logic_vector(2 downto 0) := IDLE;
    signal ft601_txe   : std_logic := '0';
    signal ft601_rxf   : std_logic := '0';
    --signal rd_en     : std_logic := '0';
    signal wr_en     : std_logic := '0';
    --signal dat_rdy   : std_logic := '0';
    signal dat_buf : std_logic_vector(31 downto 0);
    signal dat_o_buf : std_logic_vector(31 downto 0);

    signal tx_state  : std_logic_vector(2 downto 0) := IDLE;
    signal valid     : std_logic_vector(2 downto 0) := "000";
    signal pre_valid : std_logic_vector(2 downto 0) := "000";
    signal data      : std_logic_vector(95 downto 0);
    signal pre_data  : std_logic_vector(95 downto 0);

begin

    process(clk)
    begin
        if rising_edge(clk) then
            ft601_rxf   <= not ft601_rxf_n;
            ft601_txe   <= not ft601_txe_n;
            ft601_oe_n  <= '1';
            ft601_rd_n  <= '1';

        end if;
    end process;

    process(clk)
    begin
        if rising_edge(clk) then
            if rst = '1' then
                tx_state  <= IDLE;
                wr_en     <= '0';
                valid     <= "000";
                pre_valid <= "000";

            else
                if tx_state = IDLE then
                    if ft601_txe = '1' and (pre_valid(0) = '1' or fifo_in_emp = '0') then
                        tx_state  <= ACTIVE_TX;
                        dat_buf <= pre_data(31 downto 0);
                        valid(2)  <= pre_valid(0);
                        wr_en     <= pre_valid(0);
                        pre_valid <= "0" & pre_valid(2 downto 1);

                        data(95 downto 64)    <= pre_data(31 downto 0);
                        pre_data(63 downto 0) <= pre_data(95 downto 32);

                    end if;
                    
                elsif tx_state = ACTIVE_TX then
                    if ft601_txe = '0' or (pre_valid(1) = '0' and fifo_in_emp ='1') then
                         tx_state <= INTMDT1;

                    end if;

                    if pre_valid(0) = '1' then
                        data(95 downto 0)     <= pre_data(31 downto 0) & data(95 downto 32);
                        pre_data(63 downto 0) <= pre_data(95 downto 32);
                        dat_buf <= pre_data(31 downto 0);

                    else
                        data(95 downto 0)     <= data_in & data(95 downto 32);
                        pre_data(63 downto 0) <= pre_data(95 downto 32);
                        dat_buf <= data_in;

                    end if;
                    valid(2) <= pre_valid(0) or data_wr_en;
                    valid(1) <= valid(2);
                    valid(0) <= valid(1) and not ft601_txe;

                    wr_en     <= pre_valid(0) or data_wr_en;
                    pre_valid <= "0" & pre_valid(2 downto 1);

                elsif tx_state = INTMDT1 then
                    tx_state <= INTMDT2;
                    wr_en    <= '0';
                    valid(1) <= valid(1) and not ft601_txe;

                elsif tx_state = INTMDT2 then
                    tx_state <= INTMDT3;
                    valid(2) <= valid(2) and not ft601_txe;

                elsif tx_state = INTMDT3 then
                    valid <= valid(1 downto 0) & "0";
                    data(95 downto 32) <= data( 63 downto 0);

                    if valid(1 downto 0) = "00" then
                        tx_state <= IDLE;

                    end if;

                    if valid(2) = '1' then
                        pre_valid <= pre_valid(1 downto 0) & valid(2);
                        pre_data  <= pre_data(63 downto 0) & data(95 downto 64);

                    end if;
                end if;
            end if;
        end if;
    end process;

    ft601_data <= dat_buf(7 downto 0) & dat_buf(15 downto 8) & dat_buf(23 downto 16) & dat_buf(31 downto 24);

    req_data <= (not fifo_in_emp) and ft601_txe and (not pre_valid(1)) when (tx_state = IDLE or tx_state = ACTIVE_TX) else '0';
    ft601_be <= "1111";
    ft601_siwu_n <= '1';

    ft601_wr_n <= not wr_en;

    led <= not rst when tx_state /= IDLE else '0';

end architecture rtl;