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January 16, 2021 11:36
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| diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp | |
| index 6a7fe9d707a2..ad4b13a52300 100644 | |
| --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp | |
| +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp | |
| @@ -49,7 +49,7 @@ using namespace PatternMatch; | |
| /// FIXME: Enabled by default until the pattern is supported well. | |
| static cl::opt<bool> EnableUnsafeSelectTransform( | |
| - "instcombine-unsafe-select-transform", cl::init(true), | |
| + "instcombine-unsafe-select-transform", cl::init(false), | |
| cl::desc("Enable poison-unsafe select to and/or transform")); | |
| static Value *createMinMax(InstCombiner::BuilderTy &Builder, | |
| diff --git a/llvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll b/llvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll | |
| index 50657d744da1..cb0f5d82c088 100644 | |
| --- a/llvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll | |
| +++ b/llvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll | |
| @@ -33,7 +33,7 @@ define float @test_logical(float %x, x86_fp80 %y) nounwind readonly { | |
| ; CHECK-NEXT: entry: | |
| ; CHECK-NEXT: [[TMP67:%.*]] = fcmp uno x86_fp80 [[Y:%.*]], 0xK00000000000000000000 | |
| ; CHECK-NEXT: [[TMP71:%.*]] = fcmp uno float [[X:%.*]], 0.000000e+00 | |
| -; CHECK-NEXT: [[BOTHCOND:%.*]] = or i1 [[TMP67]], [[TMP71]] | |
| +; CHECK-NEXT: [[BOTHCOND:%.*]] = select i1 [[TMP67]], i1 true, i1 [[TMP71]] | |
| ; CHECK-NEXT: br i1 [[BOTHCOND]], label [[BB74:%.*]], label [[BB80:%.*]] | |
| ; CHECK: bb74: | |
| ; CHECK-NEXT: ret float 0.000000e+00 | |
| diff --git a/llvm/test/Transforms/InstCombine/2012-03-10-InstCombine.ll b/llvm/test/Transforms/InstCombine/2012-03-10-InstCombine.ll | |
| index d180560bfbcc..2574d52c5ce0 100644 | |
| --- a/llvm/test/Transforms/InstCombine/2012-03-10-InstCombine.ll | |
| +++ b/llvm/test/Transforms/InstCombine/2012-03-10-InstCombine.ll | |
| @@ -60,12 +60,12 @@ define i32 @func_logical(i8* %c, i8* %f) nounwind uwtable readnone noinline ssp | |
| ; CHECK: if.then: | |
| ; CHECK-NEXT: [[CMP2:%.*]] = icmp ule i8* [[D]], [[F:%.*]] | |
| ; CHECK-NEXT: [[NOT_CMP1:%.*]] = icmp uge i8* [[C]], [[F]] | |
| -; CHECK-NEXT: [[DOTCMP2:%.*]] = and i1 [[CMP2]], [[NOT_CMP1]] | |
| +; CHECK-NEXT: [[DOTCMP2:%.*]] = select i1 [[CMP2]], i1 [[NOT_CMP1]], i1 false | |
| ; CHECK-NEXT: br label [[RETURN:%.*]] | |
| ; CHECK: if.else: | |
| ; CHECK-NEXT: [[CMP5:%.*]] = icmp uge i8* [[D]], [[F]] | |
| ; CHECK-NEXT: [[NOT_CMP3:%.*]] = icmp ule i8* [[C]], [[F]] | |
| -; CHECK-NEXT: [[DOTCMP5:%.*]] = and i1 [[CMP5]], [[NOT_CMP3]] | |
| +; CHECK-NEXT: [[DOTCMP5:%.*]] = select i1 [[CMP5]], i1 [[NOT_CMP3]], i1 false | |
| ; CHECK-NEXT: br label [[RETURN]] | |
| ; CHECK: return: | |
| ; CHECK-NEXT: [[RETVAL_0_IN:%.*]] = phi i1 [ [[DOTCMP2]], [[IF_THEN]] ], [ [[DOTCMP5]], [[IF_ELSE]] ] | |
| diff --git a/llvm/test/Transforms/InstCombine/and-fcmp.ll b/llvm/test/Transforms/InstCombine/and-fcmp.ll | |
| index 18689c969bd0..bec51356eb1d 100644 | |
| --- a/llvm/test/Transforms/InstCombine/and-fcmp.ll | |
| +++ b/llvm/test/Transforms/InstCombine/and-fcmp.ll | |
| @@ -14,8 +14,10 @@ define i1 @PR1738(double %x, double %y) { | |
| define i1 @PR1738_logical(double %x, double %y) { | |
| ; CHECK-LABEL: @PR1738_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[X:%.*]], [[Y:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord double [[X:%.*]], 0.000000e+00 | |
| +; CHECK-NEXT: [[CMP2:%.*]] = fcmp ord double [[Y:%.*]], 0.000000e+00 | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[CMP1]], i1 [[CMP2]], i1 false | |
| +; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %cmp1 = fcmp ord double %x, 0.0 | |
| %cmp2 = fcmp ord double %y, 0.0 | |
| @@ -49,8 +51,10 @@ define i1 @PR41069(i1 %z, float %c, float %d) { | |
| define i1 @PR41069_logical(i1 %z, float %c, float %d) { | |
| ; CHECK-LABEL: @PR41069_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord float [[D:%.*]], [[C:%.*]] | |
| -; CHECK-NEXT: [[R:%.*]] = and i1 [[TMP1]], [[Z:%.*]] | |
| +; CHECK-NEXT: [[ORD1:%.*]] = fcmp arcp ord float [[C:%.*]], 0.000000e+00 | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[ORD1]], i1 [[Z:%.*]], i1 false | |
| +; CHECK-NEXT: [[ORD2:%.*]] = fcmp afn ord float [[D:%.*]], 0.000000e+00 | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[AND]], i1 [[ORD2]], i1 false | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %ord1 = fcmp arcp ord float %c, 0.0 | |
| @@ -75,8 +79,8 @@ define i1 @PR41069_commute(i1 %z, float %c, float %d) { | |
| define i1 @PR41069_commute_logical(i1 %z, float %c, float %d) { | |
| ; CHECK-LABEL: @PR41069_commute_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = fcmp ninf ord float [[D:%.*]], [[C:%.*]] | |
| -; CHECK-NEXT: [[R:%.*]] = and i1 [[TMP1]], [[Z:%.*]] | |
| +; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord float [[D:%.*]], [[C:%.*]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP1]], i1 [[Z:%.*]], i1 false | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %ord1 = fcmp ninf ord float %c, 0.0 | |
| @@ -135,7 +139,7 @@ define i1 @PR15737_logical(float %a, double %b) { | |
| ; CHECK-LABEL: @PR15737_logical( | |
| ; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[A:%.*]], 0.000000e+00 | |
| ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord double [[B:%.*]], 0.000000e+00 | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[CMP]], [[CMP1]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[CMP]], i1 [[CMP1]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %cmp = fcmp ord float %a, 0.000000e+00 | |
| @@ -170,8 +174,10 @@ define i1 @fcmp_ord_nonzero(float %x, float %y) { | |
| define i1 @fcmp_ord_nonzero_logical(float %x, float %y) { | |
| ; CHECK-LABEL: @fcmp_ord_nonzero_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord float [[X:%.*]], [[Y:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord float [[X:%.*]], 0.000000e+00 | |
| +; CHECK-NEXT: [[CMP2:%.*]] = fcmp ord float [[Y:%.*]], 0.000000e+00 | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[CMP1]], i1 [[CMP2]], i1 false | |
| +; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %cmp1 = fcmp ord float %x, 1.0 | |
| %cmp2 = fcmp ord float %y, 2.0 | |
| diff --git a/llvm/test/Transforms/InstCombine/and-or-icmp-nullptr.ll b/llvm/test/Transforms/InstCombine/and-or-icmp-nullptr.ll | |
| index b8a43c57bf58..fdbe40b8322c 100644 | |
| --- a/llvm/test/Transforms/InstCombine/and-or-icmp-nullptr.ll | |
| +++ b/llvm/test/Transforms/InstCombine/and-or-icmp-nullptr.ll | |
| @@ -705,7 +705,7 @@ define i1 @slt_and_min_logical(i8* %a, i8* %b) { | |
| ; CHECK-LABEL: @slt_and_min_logical( | |
| ; CHECK-NEXT: [[CMPEQ:%.*]] = icmp eq i8* [[A:%.*]], null | |
| ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i8* [[B:%.*]], null | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[CMPEQ]], [[TMP1]] | |
| +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[CMPEQ]], i1 [[TMP1]], i1 false | |
| ; CHECK-NEXT: ret i1 [[TMP2]] | |
| ; | |
| %cmpeq = icmp eq i8* %a, null | |
| diff --git a/llvm/test/Transforms/InstCombine/and-or-icmps.ll b/llvm/test/Transforms/InstCombine/and-or-icmps.ll | |
| index 0e8f0ca7bf96..0efe6e72f3ad 100644 | |
| --- a/llvm/test/Transforms/InstCombine/and-or-icmps.ll | |
| +++ b/llvm/test/Transforms/InstCombine/and-or-icmps.ll | |
| @@ -61,9 +61,10 @@ define i1 @PR2330(i32 %a, i32 %b) { | |
| define i1 @PR2330_logical(i32 %a, i32 %b) { | |
| ; CHECK-LABEL: @PR2330_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[B:%.*]], [[A:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 8 | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[A:%.*]], 8 | |
| +; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i32 [[B:%.*]], 8 | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[CMP2]], i1 [[CMP1]], i1 false | |
| +; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %cmp1 = icmp ult i32 %a, 8 | |
| %cmp2 = icmp ult i32 %b, 8 | |
| @@ -666,7 +667,7 @@ define i1 @substitute_constant_and_eq_eq_logical(i8 %x, i8 %y) { | |
| ; CHECK-LABEL: @substitute_constant_and_eq_eq_logical( | |
| ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42 | |
| ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[Y:%.*]], 42 | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]] | |
| +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[C1]], i1 [[TMP1]], i1 false | |
| ; CHECK-NEXT: ret i1 [[TMP2]] | |
| ; | |
| %c1 = icmp eq i8 %x, 42 | |
| @@ -905,7 +906,7 @@ define i1 @substitute_constant_or_ne_swap_sle_logical(i8 %x, i8 %y) { | |
| ; CHECK-LABEL: @substitute_constant_or_ne_swap_sle_logical( | |
| ; CHECK-NEXT: [[C1:%.*]] = icmp ne i8 [[X:%.*]], 42 | |
| ; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], 43 | |
| -; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[C1]], [[TMP1]] | |
| +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[C1]], i1 true, i1 [[TMP1]] | |
| ; CHECK-NEXT: ret i1 [[TMP2]] | |
| ; | |
| %c1 = icmp ne i8 %x, 42 | |
| @@ -972,7 +973,7 @@ define i1 @substitute_constant_or_eq_swap_ne_logical(i8 %x, i8 %y) { | |
| ; CHECK-LABEL: @substitute_constant_or_eq_swap_ne_logical( | |
| ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42 | |
| ; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[Y:%.*]], [[X]] | |
| -; CHECK-NEXT: [[R:%.*]] = or i1 [[C1]], [[C2]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[C1]], i1 true, i1 [[C2]] | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %c1 = icmp eq i8 %x, 42 | |
| diff --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll | |
| index 669cba88faba..9471d23c0b11 100644 | |
| --- a/llvm/test/Transforms/InstCombine/and.ll | |
| +++ b/llvm/test/Transforms/InstCombine/and.ll | |
| @@ -843,8 +843,10 @@ define i1 @and_orn_cmp_1(i32 %a, i32 %b, i32 %c) { | |
| define i1 @and_orn_cmp_1_logical(i32 %a, i32 %b, i32 %c) { | |
| ; CHECK-LABEL: @and_orn_cmp_1_logical( | |
| ; CHECK-NEXT: [[X:%.*]] = icmp sgt i32 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X_INV:%.*]] = icmp sle i32 [[A]], [[B]] | |
| ; CHECK-NEXT: [[Y:%.*]] = icmp ugt i32 [[C:%.*]], 42 | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[X]], [[Y]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[Y]], i1 true, i1 [[X_INV]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[X]], i1 [[OR]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %x = icmp sgt i32 %a, %b | |
| @@ -894,8 +896,10 @@ define i1 @and_orn_cmp_3(i72 %a, i72 %b, i72 %c) { | |
| define i1 @and_orn_cmp_3_logical(i72 %a, i72 %b, i72 %c) { | |
| ; CHECK-LABEL: @and_orn_cmp_3_logical( | |
| ; CHECK-NEXT: [[X:%.*]] = icmp ugt i72 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X_INV:%.*]] = icmp ule i72 [[A]], [[B]] | |
| ; CHECK-NEXT: [[Y:%.*]] = icmp ugt i72 [[C:%.*]], 42 | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[X]], [[Y]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[X_INV]], i1 true, i1 [[Y]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[X]], i1 [[OR]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %x = icmp ugt i72 %a, %b | |
| @@ -944,9 +948,11 @@ define i1 @andn_or_cmp_1(i37 %a, i37 %b, i37 %c) { | |
| define i1 @andn_or_cmp_1_logical(i37 %a, i37 %b, i37 %c) { | |
| ; CHECK-LABEL: @andn_or_cmp_1_logical( | |
| -; CHECK-NEXT: [[X_INV:%.*]] = icmp sle i37 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X:%.*]] = icmp sgt i37 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X_INV:%.*]] = icmp sle i37 [[A]], [[B]] | |
| ; CHECK-NEXT: [[Y:%.*]] = icmp ugt i37 [[C:%.*]], 42 | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[X_INV]], [[Y]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[Y]], i1 true, i1 [[X]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[X_INV]], i1 [[OR]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %x = icmp sgt i37 %a, %b | |
| @@ -977,9 +983,11 @@ define i1 @andn_or_cmp_2(i16 %a, i16 %b, i16 %c) { | |
| define i1 @andn_or_cmp_2_logical(i16 %a, i16 %b, i16 %c) { | |
| ; CHECK-LABEL: @andn_or_cmp_2_logical( | |
| -; CHECK-NEXT: [[X_INV:%.*]] = icmp slt i16 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X:%.*]] = icmp sge i16 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X_INV:%.*]] = icmp slt i16 [[A]], [[B]] | |
| ; CHECK-NEXT: [[Y:%.*]] = icmp ugt i16 [[C:%.*]], 42 | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[Y]], [[X_INV]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[Y]], i1 true, i1 [[X]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[OR]], i1 [[X_INV]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %x = icmp sge i16 %a, %b | |
| @@ -1028,9 +1036,11 @@ define i1 @andn_or_cmp_4(i32 %a, i32 %b, i32 %c) { | |
| define i1 @andn_or_cmp_4_logical(i32 %a, i32 %b, i32 %c) { | |
| ; CHECK-LABEL: @andn_or_cmp_4_logical( | |
| -; CHECK-NEXT: [[X_INV:%.*]] = icmp ne i32 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X_INV:%.*]] = icmp ne i32 [[A]], [[B]] | |
| ; CHECK-NEXT: [[Y:%.*]] = icmp ugt i32 [[C:%.*]], 42 | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[Y]], [[X_INV]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[X]], i1 true, i1 [[Y]] | |
| +; CHECK-NEXT: [[AND:%.*]] = and i1 [[OR]], [[X_INV]] | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %x = icmp eq i32 %a, %b | |
| diff --git a/llvm/test/Transforms/InstCombine/and2.ll b/llvm/test/Transforms/InstCombine/and2.ll | |
| index 6b12e26ab5f3..d8469a2fbed6 100644 | |
| --- a/llvm/test/Transforms/InstCombine/and2.ll | |
| +++ b/llvm/test/Transforms/InstCombine/and2.ll | |
| @@ -13,7 +13,7 @@ define i1 @test2(i1 %X, i1 %Y) { | |
| define i1 @test2_logical(i1 %X, i1 %Y) { | |
| ; CHECK-LABEL: @test2_logical( | |
| -; CHECK-NEXT: [[A:%.*]] = and i1 [[X:%.*]], [[Y:%.*]] | |
| +; CHECK-NEXT: [[A:%.*]] = select i1 [[X:%.*]], i1 [[Y:%.*]], i1 false | |
| ; CHECK-NEXT: ret i1 [[A]] | |
| ; | |
| %a = select i1 %X, i1 %Y, i1 false | |
| @@ -46,9 +46,11 @@ define i1 @test7(i32 %i, i1 %b) { | |
| define i1 @test7_logical(i32 %i, i1 %b) { | |
| ; CHECK-LABEL: @test7_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[I:%.*]], 0 | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[TMP1]], [[B:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[I:%.*]], 1 | |
| +; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[I]], -1 | |
| +; CHECK-NEXT: [[AND1:%.*]] = select i1 [[CMP1]], i1 [[B:%.*]], i1 false | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i1 [[AND1]], [[CMP2]] | |
| +; CHECK-NEXT: ret i1 [[AND2]] | |
| ; | |
| %cmp1 = icmp slt i32 %i, 1 | |
| %cmp2 = icmp sgt i32 %i, -1 | |
| diff --git a/llvm/test/Transforms/InstCombine/bit-checks.ll b/llvm/test/Transforms/InstCombine/bit-checks.ll | |
| index 28464c41ad49..e755e50833f4 100644 | |
| --- a/llvm/test/Transforms/InstCombine/bit-checks.ll | |
| +++ b/llvm/test/Transforms/InstCombine/bit-checks.ll | |
| @@ -153,10 +153,12 @@ define i32 @main3e_like(i32 %argc, i32 %argc2, i32 %argc3) { | |
| define i32 @main3e_like_logical(i32 %argc, i32 %argc2, i32 %argc3) { | |
| ; CHECK-LABEL: @main3e_like_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32 | |
| +; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND]], 0 | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], 0 | |
| +; CHECK-NEXT: [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %and = and i32 %argc, %argc2 | |
| @@ -252,10 +254,12 @@ define i32 @main3f_like(i32 %argc, i32 %argc2, i32 %argc3) { | |
| define i32 @main3f_like_logical(i32 %argc, i32 %argc2, i32 %argc3) { | |
| ; CHECK-LABEL: @main3f_like_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]] | |
| -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP2]], 0 | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[DOTNOT]] to i32 | |
| +; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[AND]], 0 | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp eq i32 [[AND2]], 0 | |
| +; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[TOBOOL]], i1 [[TOBOOL3]], i1 false | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %and = and i32 %argc, %argc2 | |
| @@ -351,10 +355,12 @@ define i32 @main4e_like(i32 %argc, i32 %argc2, i32 %argc3) { | |
| define i32 @main4e_like_logical(i32 %argc, i32 %argc2, i32 %argc3) { | |
| ; CHECK-LABEL: @main4e_like_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32 | |
| +; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND]], [[ARGC2]] | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[ARGC3]] | |
| +; CHECK-NEXT: [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %and = and i32 %argc, %argc2 | |
| @@ -450,10 +456,12 @@ define i32 @main4f_like(i32 %argc, i32 %argc2, i32 %argc3) { | |
| define i32 @main4f_like_logical(i32 %argc, i32 %argc2, i32 %argc3) { | |
| ; CHECK-LABEL: @main4f_like_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]] | |
| -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[DOTNOT]] to i32 | |
| +; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[AND]], [[ARGC2]] | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp eq i32 [[AND2]], [[ARGC3]] | |
| +; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[TOBOOL]], i1 [[TOBOOL3]], i1 false | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %and = and i32 %argc, %argc2 | |
| @@ -485,10 +493,12 @@ define i32 @main5_like(i32 %argc, i32 %argc2) { | |
| define i32 @main5_like_logical(i32 %argc, i32 %argc2) { | |
| ; CHECK-LABEL: @main5_like_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 7 | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 7 | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32 | |
| +; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], 7 | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND]], 7 | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC2:%.*]], 7 | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], 7 | |
| +; CHECK-NEXT: [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %and = and i32 %argc, 7 | |
| @@ -519,10 +529,12 @@ define i32 @main5e_like(i32 %argc, i32 %argc2, i32 %argc3) { | |
| define i32 @main5e_like_logical(i32 %argc, i32 %argc2, i32 %argc3) { | |
| ; CHECK-LABEL: @main5e_like_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC3:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[ARGC]] | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32 | |
| +; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND]], [[ARGC]] | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[ARGC]] | |
| +; CHECK-NEXT: [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %and = and i32 %argc, %argc2 | |
| @@ -554,10 +566,12 @@ define i32 @main5c_like(i32 %argc, i32 %argc2) { | |
| define i32 @main5c_like_logical(i32 %argc, i32 %argc2) { | |
| ; CHECK-LABEL: @main5c_like_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 7 | |
| -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP2]], 7 | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[DOTNOT]] to i32 | |
| +; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], 7 | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[AND]], 7 | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC2:%.*]], 7 | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp eq i32 [[AND2]], 7 | |
| +; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[TOBOOL]], i1 [[TOBOOL3]], i1 false | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %and = and i32 %argc, 7 | |
| @@ -588,10 +602,12 @@ define i32 @main5f_like(i32 %argc, i32 %argc2, i32 %argc3) { | |
| define i32 @main5f_like_logical(i32 %argc, i32 %argc2, i32 %argc3) { | |
| ; CHECK-LABEL: @main5f_like_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC3:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]] | |
| -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP2]], [[ARGC]] | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[DOTNOT]] to i32 | |
| +; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[AND]], [[ARGC]] | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp eq i32 [[AND2]], [[ARGC]] | |
| +; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[TOBOOL]], i1 [[TOBOOL3]], i1 false | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %and = and i32 %argc, %argc2 | |
| @@ -756,10 +772,12 @@ define i32 @main7a(i32 %argc, i32 %argc2, i32 %argc3) { | |
| define i32 @main7a_logical(i32 %argc, i32 %argc2, i32 %argc3) { | |
| ; CHECK-LABEL: @main7a_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32 | |
| +; CHECK-NEXT: [[AND1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[ARGC2]] | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC]] | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[ARGC3]] | |
| +; CHECK-NEXT: [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %and1 = and i32 %argc2, %argc | |
| @@ -791,10 +809,12 @@ define i32 @main7b(i32 %argc, i32 %argc2, i32 %argc3) { | |
| define i32 @main7b_logical(i32 %argc, i32 %argc2, i32 %argc3) { | |
| ; CHECK-LABEL: @main7b_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32 | |
| +; CHECK-NEXT: [[AND1:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[ARGC2]] | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[ARGC3]] | |
| +; CHECK-NEXT: [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %and1 = and i32 %argc, %argc2 | |
| @@ -826,10 +846,12 @@ define i32 @main7c(i32 %argc, i32 %argc2, i32 %argc3) { | |
| define i32 @main7c_logical(i32 %argc, i32 %argc2, i32 %argc3) { | |
| ; CHECK-LABEL: @main7c_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32 | |
| +; CHECK-NEXT: [[AND1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[ARGC2]] | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC]] | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[ARGC3]] | |
| +; CHECK-NEXT: [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %and1 = and i32 %argc2, %argc | |
| @@ -867,10 +889,12 @@ define i32 @main7d_logical(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %a | |
| ; CHECK-LABEL: @main7d_logical( | |
| ; CHECK-NEXT: [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]] | |
| ; CHECK-NEXT: [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[BC]], [[DE]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32 | |
| +; CHECK-NEXT: [[AND1:%.*]] = and i32 [[BC]], [[ARGC:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[BC]] | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[DE]], [[ARGC]] | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[DE]] | |
| +; CHECK-NEXT: [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %bc = and i32 %argc2, %argc4 | |
| @@ -910,10 +934,12 @@ define i32 @main7e_logical(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %a | |
| ; CHECK-LABEL: @main7e_logical( | |
| ; CHECK-NEXT: [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]] | |
| ; CHECK-NEXT: [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[BC]], [[DE]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32 | |
| +; CHECK-NEXT: [[AND1:%.*]] = and i32 [[BC]], [[ARGC:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[BC]] | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[DE]], [[ARGC]] | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[DE]] | |
| +; CHECK-NEXT: [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %bc = and i32 %argc2, %argc4 | |
| @@ -953,10 +979,12 @@ define i32 @main7f_logical(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %a | |
| ; CHECK-LABEL: @main7f_logical( | |
| ; CHECK-NEXT: [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]] | |
| ; CHECK-NEXT: [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[BC]], [[DE]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32 | |
| +; CHECK-NEXT: [[AND1:%.*]] = and i32 [[BC]], [[ARGC:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[BC]], [[AND1]] | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[DE]], [[ARGC]] | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[DE]], [[AND2]] | |
| +; CHECK-NEXT: [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %bc = and i32 %argc2, %argc4 | |
| @@ -996,10 +1024,12 @@ define i32 @main7g_logical(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %a | |
| ; CHECK-LABEL: @main7g_logical( | |
| ; CHECK-NEXT: [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]] | |
| ; CHECK-NEXT: [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[BC]], [[DE]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[TMP3]] to i32 | |
| +; CHECK-NEXT: [[AND1:%.*]] = and i32 [[BC]], [[ARGC:%.*]] | |
| +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[BC]], [[AND1]] | |
| +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[DE]], [[ARGC]] | |
| +; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[DE]], [[AND2]] | |
| +; CHECK-NEXT: [[AND_COND:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] | |
| +; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[STOREMERGE]] | |
| ; | |
| %bc = and i32 %argc2, %argc4 | |
| diff --git a/llvm/test/Transforms/InstCombine/demorgan.ll b/llvm/test/Transforms/InstCombine/demorgan.ll | |
| index 809c43d1a09d..f80254a64dff 100644 | |
| --- a/llvm/test/Transforms/InstCombine/demorgan.ll | |
| +++ b/llvm/test/Transforms/InstCombine/demorgan.ll | |
| @@ -475,8 +475,8 @@ define i32 @PR28476_logical(i32 %x, i32 %y) { | |
| ; CHECK-LABEL: @PR28476_logical( | |
| ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[X:%.*]], 0 | |
| ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[Y:%.*]], 0 | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i1 [[CMP0]], [[CMP1]] | |
| -; CHECK-NEXT: [[COND:%.*]] = zext i1 [[TMP1]] to i32 | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[CMP0]], i1 true, i1 [[CMP1]] | |
| +; CHECK-NEXT: [[COND:%.*]] = zext i1 [[AND]] to i32 | |
| ; CHECK-NEXT: ret i32 [[COND]] | |
| ; | |
| %cmp0 = icmp ne i32 %x, 0 | |
| diff --git a/llvm/test/Transforms/InstCombine/dont-distribute-phi.ll b/llvm/test/Transforms/InstCombine/dont-distribute-phi.ll | |
| index 98d91c9b048f..f7cf72851940 100644 | |
| --- a/llvm/test/Transforms/InstCombine/dont-distribute-phi.ll | |
| +++ b/llvm/test/Transforms/InstCombine/dont-distribute-phi.ll | |
| @@ -55,7 +55,7 @@ define zeroext i1 @foo_logical(i32 %arg) { | |
| ; CHECK: bb_exit: | |
| ; CHECK-NEXT: [[PHI1:%.*]] = phi i1 [ [[CMP2]], [[BB_ELSE]] ], [ undef, [[BB_THEN]] ] | |
| ; CHECK-NEXT: [[XOR1:%.*]] = xor i1 [[CMP1]], true | |
| -; CHECK-NEXT: [[AND1:%.*]] = and i1 [[PHI1]], [[XOR1]] | |
| +; CHECK-NEXT: [[AND1:%.*]] = select i1 [[PHI1]], i1 [[XOR1]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND1]] | |
| ; | |
| diff --git a/llvm/test/Transforms/InstCombine/icmp-logical.ll b/llvm/test/Transforms/InstCombine/icmp-logical.ll | |
| index cc23b114bd01..ceb9ca595189 100644 | |
| --- a/llvm/test/Transforms/InstCombine/icmp-logical.ll | |
| +++ b/llvm/test/Transforms/InstCombine/icmp-logical.ll | |
| @@ -129,9 +129,12 @@ define i1 @masked_and_notA(i32 %A) { | |
| define i1 @masked_and_notA_logical(i32 %A) { | |
| ; CHECK-LABEL: @masked_and_notA_logical( | |
| -; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A:%.*]], 78 | |
| +; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 14 | |
| +; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], [[A]] | |
| +; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A]], 78 | |
| ; CHECK-NEXT: [[TST2:%.*]] = icmp ne i32 [[MASK2]], [[A]] | |
| -; CHECK-NEXT: ret i1 [[TST2]] | |
| +; CHECK-NEXT: [[RES:%.*]] = select i1 [[TST1]], i1 [[TST2]], i1 false | |
| +; CHECK-NEXT: ret i1 [[RES]] | |
| ; | |
| %mask1 = and i32 %A, 14 | |
| %tst1 = icmp ne i32 %mask1, %A | |
| @@ -161,7 +164,7 @@ define i1 @masked_and_notA_slightly_optimized_logical(i32 %A) { | |
| ; CHECK-NEXT: [[T0:%.*]] = icmp ugt i32 [[A:%.*]], 7 | |
| ; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A]], 39 | |
| ; CHECK-NEXT: [[TST2:%.*]] = icmp ne i32 [[MASK2]], [[A]] | |
| -; CHECK-NEXT: [[RES:%.*]] = and i1 [[T0]], [[TST2]] | |
| +; CHECK-NEXT: [[RES:%.*]] = select i1 [[T0]], i1 [[TST2]], i1 false | |
| ; CHECK-NEXT: ret i1 [[RES]] | |
| ; | |
| %t0 = icmp uge i32 %A, 8 | |
| @@ -187,9 +190,12 @@ define i1 @masked_or_A(i32 %A) { | |
| define i1 @masked_or_A_logical(i32 %A) { | |
| ; CHECK-LABEL: @masked_or_A_logical( | |
| -; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A:%.*]], 78 | |
| +; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 14 | |
| +; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], [[A]] | |
| +; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A]], 78 | |
| ; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASK2]], [[A]] | |
| -; CHECK-NEXT: ret i1 [[TST2]] | |
| +; CHECK-NEXT: [[RES:%.*]] = select i1 [[TST1]], i1 true, i1 [[TST2]] | |
| +; CHECK-NEXT: ret i1 [[RES]] | |
| ; | |
| %mask1 = and i32 %A, 14 | |
| %tst1 = icmp eq i32 %mask1, %A | |
| @@ -219,7 +225,7 @@ define i1 @masked_or_A_slightly_optimized_logical(i32 %A) { | |
| ; CHECK-NEXT: [[T0:%.*]] = icmp ult i32 [[A:%.*]], 8 | |
| ; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A]], 39 | |
| ; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASK2]], [[A]] | |
| -; CHECK-NEXT: [[RES:%.*]] = or i1 [[T0]], [[TST2]] | |
| +; CHECK-NEXT: [[RES:%.*]] = select i1 [[T0]], i1 true, i1 [[TST2]] | |
| ; CHECK-NEXT: ret i1 [[RES]] | |
| ; | |
| %t0 = icmp ult i32 %A, 8 | |
| diff --git a/llvm/test/Transforms/InstCombine/icmp.ll b/llvm/test/Transforms/InstCombine/icmp.ll | |
| index b48466e678d8..a03dc73e5cf9 100644 | |
| --- a/llvm/test/Transforms/InstCombine/icmp.ll | |
| +++ b/llvm/test/Transforms/InstCombine/icmp.ll | |
| @@ -2232,9 +2232,10 @@ define i1 @or_icmp_eq_B_0_icmp_ult_A_B(i64 %a, i64 %b) { | |
| define i1 @or_icmp_eq_B_0_icmp_ult_A_B_logical(i64 %a, i64 %b) { | |
| ; CHECK-LABEL: @or_icmp_eq_B_0_icmp_ult_A_B_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[B:%.*]], -1 | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i64 [[TMP1]], [[A:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[B:%.*]], 0 | |
| +; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[A:%.*]], [[B]] | |
| +; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], i1 true, i1 [[TMP2]] | |
| +; CHECK-NEXT: ret i1 [[TMP3]] | |
| ; | |
| %1 = icmp eq i64 %b, 0 | |
| %2 = icmp ult i64 %a, %b | |
| @@ -2280,9 +2281,10 @@ define i1 @or_icmp_ne_A_0_icmp_ne_B_0(i64 %a, i64 %b) { | |
| define i1 @or_icmp_ne_A_0_icmp_ne_B_0_logical(i64 %a, i64 %b) { | |
| ; CHECK-LABEL: @or_icmp_ne_A_0_icmp_ne_B_0_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i64 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], 0 | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A:%.*]], 0 | |
| +; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B:%.*]], 0 | |
| +; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], i1 true, i1 [[TMP2]] | |
| +; CHECK-NEXT: ret i1 [[TMP3]] | |
| ; | |
| %1 = icmp ne i64 %a, 0 | |
| %2 = icmp ne i64 %b, 0 | |
| diff --git a/llvm/test/Transforms/InstCombine/ispow2.ll b/llvm/test/Transforms/InstCombine/ispow2.ll | |
| index c54c6271ec07..170f5f25827c 100644 | |
| --- a/llvm/test/Transforms/InstCombine/ispow2.ll | |
| +++ b/llvm/test/Transforms/InstCombine/ispow2.ll | |
| @@ -194,8 +194,10 @@ define i1 @is_pow2_ctpop(i32 %x) { | |
| define i1 @is_pow2_ctpop_logical(i32 %x) { | |
| ; CHECK-LABEL: @is_pow2_ctpop_logical( | |
| ; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), [[RNG0]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[T0]], 1 | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[T0]], 2 | |
| +; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X]], 0 | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOTZERO]], i1 [[CMP]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %t0 = tail call i32 @llvm.ctpop.i32(i32 %x) | |
| %cmp = icmp ult i32 %t0, 2 | |
| @@ -233,8 +235,8 @@ define i1 @is_pow2_ctpop_extra_uses_logical(i32 %x) { | |
| ; CHECK-NEXT: call void @use_i1(i1 [[CMP]]) | |
| ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X]], 0 | |
| ; CHECK-NEXT: call void @use_i1(i1 [[NOTZERO]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[T0]], 1 | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOTZERO]], i1 [[CMP]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %t0 = tail call i32 @llvm.ctpop.i32(i32 %x) | |
| %cmp = icmp ult i32 %t0, 2 | |
| @@ -282,7 +284,7 @@ define i1 @is_pow2_ctpop_wrong_cmp_op1_logical(i32 %x) { | |
| ; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), [[RNG0]] | |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[T0]], 3 | |
| ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X]], 0 | |
| -; CHECK-NEXT: [[R:%.*]] = and i1 [[NOTZERO]], [[CMP]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOTZERO]], i1 [[CMP]], i1 false | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %t0 = tail call i32 @llvm.ctpop.i32(i32 %x) | |
| @@ -314,7 +316,7 @@ define i1 @is_pow2_ctpop_wrong_cmp_op2_logical(i32 %x) { | |
| ; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), [[RNG0]] | |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[T0]], 2 | |
| ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X]], 1 | |
| -; CHECK-NEXT: [[R:%.*]] = and i1 [[NOTZERO]], [[CMP]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOTZERO]], i1 [[CMP]], i1 false | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %t0 = tail call i32 @llvm.ctpop.i32(i32 %x) | |
| @@ -346,7 +348,7 @@ define i1 @is_pow2_ctpop_wrong_pred1_logical(i32 %x) { | |
| ; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), [[RNG0]] | |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 2 | |
| ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X]], 0 | |
| -; CHECK-NEXT: [[R:%.*]] = and i1 [[NOTZERO]], [[CMP]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOTZERO]], i1 [[CMP]], i1 false | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %t0 = tail call i32 @llvm.ctpop.i32(i32 %x) | |
| @@ -378,7 +380,7 @@ define i1 @is_pow2_ctpop_wrong_pred2_logical(i32 %x) { | |
| ; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), [[RNG0]] | |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[T0]], 2 | |
| ; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[X]], 0 | |
| -; CHECK-NEXT: [[R:%.*]] = and i1 [[CMP2]], [[CMP]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP2]], i1 [[CMP]], i1 false | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %t0 = tail call i32 @llvm.ctpop.i32(i32 %x) | |
| @@ -406,8 +408,10 @@ define i1 @isnot_pow2_ctpop(i32 %x) { | |
| define i1 @isnot_pow2_ctpop_logical(i32 %x) { | |
| ; CHECK-LABEL: @isnot_pow2_ctpop_logical( | |
| ; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), [[RNG0]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[T0]], 1 | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 1 | |
| +; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i32 [[X]], 0 | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[ISZERO]], i1 true, i1 [[CMP]] | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %t0 = tail call i32 @llvm.ctpop.i32(i32 %x) | |
| %cmp = icmp ugt i32 %t0, 1 | |
| @@ -444,8 +448,8 @@ define i1 @isnot_pow2_ctpop_extra_uses_logical(i32 %x) { | |
| ; CHECK-NEXT: call void @use_i1(i1 [[CMP]]) | |
| ; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i32 [[X]], 0 | |
| ; CHECK-NEXT: call void @use_i1(i1 [[ISZERO]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[T0]], 1 | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[ISZERO]], i1 true, i1 [[CMP]] | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %t0 = tail call i32 @llvm.ctpop.i32(i32 %x) | |
| %cmp = icmp ugt i32 %t0, 1 | |
| @@ -493,7 +497,7 @@ define i1 @isnot_pow2_ctpop_wrong_cmp_op1_logical(i32 %x) { | |
| ; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), [[RNG0]] | |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 2 | |
| ; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i32 [[X]], 0 | |
| -; CHECK-NEXT: [[R:%.*]] = or i1 [[ISZERO]], [[CMP]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[ISZERO]], i1 true, i1 [[CMP]] | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %t0 = tail call i32 @llvm.ctpop.i32(i32 %x) | |
| @@ -525,7 +529,7 @@ define i1 @isnot_pow2_ctpop_wrong_cmp_op2_logical(i32 %x) { | |
| ; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), [[RNG0]] | |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 1 | |
| ; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i32 [[X]], 1 | |
| -; CHECK-NEXT: [[R:%.*]] = or i1 [[ISZERO]], [[CMP]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[ISZERO]], i1 true, i1 [[CMP]] | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %t0 = tail call i32 @llvm.ctpop.i32(i32 %x) | |
| @@ -557,7 +561,7 @@ define i1 @isnot_pow2_ctpop_wrong_pred1_logical(i32 %x) { | |
| ; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), [[RNG0]] | |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[T0]], 1 | |
| ; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i32 [[X]], 0 | |
| -; CHECK-NEXT: [[R:%.*]] = or i1 [[ISZERO]], [[CMP]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[ISZERO]], i1 true, i1 [[CMP]] | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %t0 = tail call i32 @llvm.ctpop.i32(i32 %x) | |
| @@ -589,7 +593,7 @@ define i1 @isnot_pow2_ctpop_wrong_pred2_logical(i32 %x) { | |
| ; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), [[RNG0]] | |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 1 | |
| ; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[X]], 0 | |
| -; CHECK-NEXT: [[R:%.*]] = or i1 [[CMP2]], [[CMP]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP2]], i1 true, i1 [[CMP]] | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %t0 = tail call i32 @llvm.ctpop.i32(i32 %x) | |
| @@ -616,8 +620,10 @@ define i1 @is_pow2_negate_op(i32 %x) { | |
| define i1 @is_pow2_negate_op_logical(i32 %x) { | |
| ; CHECK-LABEL: @is_pow2_negate_op_logical( | |
| ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), [[RNG0]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1 | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP1]], 2 | |
| +; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X]], 0 | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOTZERO]], i1 [[CMP]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %neg = sub i32 0, %x | |
| %and = and i32 %neg, %x | |
| @@ -658,8 +664,10 @@ define i1 @is_pow2_decrement_op(i8 %x) { | |
| define i1 @is_pow2_decrement_op_logical(i8 %x) { | |
| ; CHECK-LABEL: @is_pow2_decrement_op_logical( | |
| ; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X:%.*]]), [[RNG1]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], 1 | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[TMP1]], 2 | |
| +; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i8 [[X]], 0 | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP]], i1 [[NOTZERO]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %dec = add i8 %x, -1 | |
| %and = and i8 %dec, %x | |
| @@ -700,8 +708,10 @@ define i1 @isnot_pow2_negate_op(i32 %x) { | |
| define i1 @isnot_pow2_negate_op_logical(i32 %x) { | |
| ; CHECK-LABEL: @isnot_pow2_negate_op_logical( | |
| ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), [[RNG0]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 1 | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP1]], 1 | |
| +; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i32 [[X]], 0 | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP]], i1 true, i1 [[ISZERO]] | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %neg = sub i32 0, %x | |
| %and = and i32 %neg, %x | |
| @@ -742,8 +752,10 @@ define i1 @isnot_pow2_decrement_op(i8 %x) { | |
| define i1 @isnot_pow2_decrement_op_logical(i8 %x) { | |
| ; CHECK-LABEL: @isnot_pow2_decrement_op_logical( | |
| ; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X:%.*]]), [[RNG1]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i8 [[TMP1]], 1 | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 [[TMP1]], 1 | |
| +; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i8 [[X]], 0 | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[ISZERO]], i1 true, i1 [[CMP]] | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %dec = add i8 %x, -1 | |
| %and = and i8 %dec, %x | |
| diff --git a/llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll b/llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll | |
| index f67cb024c2e3..79a047a17077 100644 | |
| --- a/llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll | |
| +++ b/llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll | |
| @@ -378,8 +378,11 @@ define i1 @bools(i1 %a, i1 %b, i1 %c) { | |
| define i1 @bools_logical(i1 %a, i1 %b, i1 %c) { | |
| ; CHECK-LABEL: @bools_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C:%.*]], i1 [[B:%.*]], i1 [[A:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[NOT:%.*]] = xor i1 [[C:%.*]], true | |
| +; CHECK-NEXT: [[AND1:%.*]] = select i1 [[NOT]], i1 [[A:%.*]], i1 false | |
| +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 false | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[AND1]], i1 true, i1 [[AND2]] | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %not = xor i1 %c, -1 | |
| %and1 = select i1 %not, i1 %a, i1 false | |
| @@ -409,9 +412,10 @@ define i1 @bools_multi_uses1(i1 %a, i1 %b, i1 %c) { | |
| define i1 @bools_multi_uses1_logical(i1 %a, i1 %b, i1 %c) { | |
| ; CHECK-LABEL: @bools_multi_uses1_logical( | |
| ; CHECK-NEXT: [[NOT:%.*]] = xor i1 [[C:%.*]], true | |
| -; CHECK-NEXT: [[AND1:%.*]] = and i1 [[NOT]], [[A:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 [[A]] | |
| -; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[TMP1]], [[AND1]] | |
| +; CHECK-NEXT: [[AND1:%.*]] = select i1 [[NOT]], i1 [[A:%.*]], i1 false | |
| +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 false | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[AND1]], i1 true, i1 [[AND2]] | |
| +; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[OR]], [[AND1]] | |
| ; CHECK-NEXT: ret i1 [[XOR]] | |
| ; | |
| %not = xor i1 %c, -1 | |
| @@ -441,8 +445,13 @@ define i1 @bools_multi_uses2(i1 %a, i1 %b, i1 %c) { | |
| define i1 @bools_multi_uses2_logical(i1 %a, i1 %b, i1 %c) { | |
| ; CHECK-LABEL: @bools_multi_uses2_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C:%.*]], i1 [[B:%.*]], i1 [[A:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[NOT:%.*]] = xor i1 [[C:%.*]], true | |
| +; CHECK-NEXT: [[AND1:%.*]] = select i1 [[NOT]], i1 [[A:%.*]], i1 false | |
| +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 false | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[AND1]], i1 true, i1 [[AND2]] | |
| +; CHECK-NEXT: [[ADD:%.*]] = xor i1 [[AND1]], [[AND2]] | |
| +; CHECK-NEXT: [[AND3:%.*]] = select i1 [[OR]], i1 [[ADD]], i1 false | |
| +; CHECK-NEXT: ret i1 [[AND3]] | |
| ; | |
| %not = xor i1 %c, -1 | |
| %and1 = select i1 %not, i1 %a, i1 false | |
| diff --git a/llvm/test/Transforms/InstCombine/logical-select.ll b/llvm/test/Transforms/InstCombine/logical-select.ll | |
| index 5c16fc446cdd..e887f1642fac 100644 | |
| --- a/llvm/test/Transforms/InstCombine/logical-select.ll | |
| +++ b/llvm/test/Transforms/InstCombine/logical-select.ll | |
| @@ -378,8 +378,11 @@ define i1 @bools(i1 %a, i1 %b, i1 %c) { | |
| define i1 @bools_logical(i1 %a, i1 %b, i1 %c) { | |
| ; CHECK-LABEL: @bools_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C:%.*]], i1 [[B:%.*]], i1 [[A:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[NOT:%.*]] = xor i1 [[C:%.*]], true | |
| +; CHECK-NEXT: [[AND1:%.*]] = select i1 [[NOT]], i1 [[A:%.*]], i1 false | |
| +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 false | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[AND1]], i1 true, i1 [[AND2]] | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %not = xor i1 %c, -1 | |
| %and1 = select i1 %not, i1 %a, i1 false | |
| @@ -409,9 +412,10 @@ define i1 @bools_multi_uses1(i1 %a, i1 %b, i1 %c) { | |
| define i1 @bools_multi_uses1_logical(i1 %a, i1 %b, i1 %c) { | |
| ; CHECK-LABEL: @bools_multi_uses1_logical( | |
| ; CHECK-NEXT: [[NOT:%.*]] = xor i1 [[C:%.*]], true | |
| -; CHECK-NEXT: [[AND1:%.*]] = and i1 [[NOT]], [[A:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 [[A]] | |
| -; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[TMP1]], [[AND1]] | |
| +; CHECK-NEXT: [[AND1:%.*]] = select i1 [[NOT]], i1 [[A:%.*]], i1 false | |
| +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 false | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[AND1]], i1 true, i1 [[AND2]] | |
| +; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[OR]], [[AND1]] | |
| ; CHECK-NEXT: ret i1 [[XOR]] | |
| ; | |
| %not = xor i1 %c, -1 | |
| @@ -441,8 +445,13 @@ define i1 @bools_multi_uses2(i1 %a, i1 %b, i1 %c) { | |
| define i1 @bools_multi_uses2_logical(i1 %a, i1 %b, i1 %c) { | |
| ; CHECK-LABEL: @bools_multi_uses2_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C:%.*]], i1 [[B:%.*]], i1 [[A:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[NOT:%.*]] = xor i1 [[C:%.*]], true | |
| +; CHECK-NEXT: [[AND1:%.*]] = select i1 [[NOT]], i1 [[A:%.*]], i1 false | |
| +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 false | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[AND1]], i1 true, i1 [[AND2]] | |
| +; CHECK-NEXT: [[ADD:%.*]] = xor i1 [[AND1]], [[AND2]] | |
| +; CHECK-NEXT: [[AND3:%.*]] = select i1 [[OR]], i1 [[ADD]], i1 false | |
| +; CHECK-NEXT: ret i1 [[AND3]] | |
| ; | |
| %not = xor i1 %c, -1 | |
| %and1 = select i1 %not, i1 %a, i1 false | |
| diff --git a/llvm/test/Transforms/InstCombine/onehot_merge.ll b/llvm/test/Transforms/InstCombine/onehot_merge.ll | |
| index bc0047e7a84a..c44e6a87250d 100644 | |
| --- a/llvm/test/Transforms/InstCombine/onehot_merge.ll | |
| +++ b/llvm/test/Transforms/InstCombine/onehot_merge.ll | |
| @@ -66,10 +66,12 @@ define i1 @foo1_and_logical(i32 %k, i32 %c1, i32 %c2) { | |
| ; CHECK-LABEL: @foo1_and_logical( | |
| ; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] | |
| ; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: ret i1 [[TMP3]] | |
| +; CHECK-NEXT: [[T1:%.*]] = and i32 [[T]], [[K:%.*]] | |
| +; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 | |
| +; CHECK-NEXT: [[T5:%.*]] = and i32 [[T4]], [[K]] | |
| +; CHECK-NEXT: [[T6:%.*]] = icmp eq i32 [[T5]], 0 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T6]] | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t = shl i32 1, %c1 | |
| %t4 = shl i32 1, %c2 | |
| @@ -127,10 +129,12 @@ define i1 @foo1_and_commuted_logical(i32 %k, i32 %c1, i32 %c2) { | |
| ; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]] | |
| ; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] | |
| ; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: ret i1 [[TMP3]] | |
| +; CHECK-NEXT: [[T1:%.*]] = and i32 [[K2]], [[T]] | |
| +; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 | |
| +; CHECK-NEXT: [[T5:%.*]] = and i32 [[T4]], [[K2]] | |
| +; CHECK-NEXT: [[T6:%.*]] = icmp eq i32 [[T5]], 0 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T6]] | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %k2 = mul i32 %k, %k ; to trick the complexity sorting | |
| %t = shl i32 1, %c1 | |
| @@ -229,10 +233,12 @@ define i1 @foo1_or_logical(i32 %k, i32 %c1, i32 %c2) { | |
| ; CHECK-LABEL: @foo1_or_logical( | |
| ; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] | |
| ; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: ret i1 [[TMP3]] | |
| +; CHECK-NEXT: [[T1:%.*]] = and i32 [[T]], [[K:%.*]] | |
| +; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 | |
| +; CHECK-NEXT: [[T5:%.*]] = and i32 [[T4]], [[K]] | |
| +; CHECK-NEXT: [[T6:%.*]] = icmp ne i32 [[T5]], 0 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 [[T6]], i1 false | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t = shl i32 1, %c1 | |
| %t4 = shl i32 1, %c2 | |
| @@ -290,10 +296,12 @@ define i1 @foo1_or_commuted_logical(i32 %k, i32 %c1, i32 %c2) { | |
| ; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]] | |
| ; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] | |
| ; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: ret i1 [[TMP3]] | |
| +; CHECK-NEXT: [[T1:%.*]] = and i32 [[K2]], [[T]] | |
| +; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 | |
| +; CHECK-NEXT: [[T5:%.*]] = and i32 [[T4]], [[K2]] | |
| +; CHECK-NEXT: [[T6:%.*]] = icmp ne i32 [[T5]], 0 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 [[T6]], i1 false | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %k2 = mul i32 %k, %k ; to trick the complexity sorting | |
| %t = shl i32 1, %c1 | |
| @@ -350,10 +358,12 @@ define i1 @foo1_and_signbit_lshr_logical(i32 %k, i32 %c1, i32 %c2) { | |
| ; CHECK-LABEL: @foo1_and_signbit_lshr_logical( | |
| ; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] | |
| ; CHECK-NEXT: [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: ret i1 [[TMP3]] | |
| +; CHECK-NEXT: [[T1:%.*]] = and i32 [[T]], [[K:%.*]] | |
| +; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 | |
| +; CHECK-NEXT: [[T5:%.*]] = and i32 [[T4]], [[K]] | |
| +; CHECK-NEXT: [[T6:%.*]] = icmp eq i32 [[T5]], 0 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T6]] | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t = shl i32 1, %c1 | |
| %t4 = lshr i32 -2147483648, %c2 | |
| @@ -407,10 +417,12 @@ define i1 @foo1_or_signbit_lshr_logical(i32 %k, i32 %c1, i32 %c2) { | |
| ; CHECK-LABEL: @foo1_or_signbit_lshr_logical( | |
| ; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] | |
| ; CHECK-NEXT: [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: ret i1 [[TMP3]] | |
| +; CHECK-NEXT: [[T1:%.*]] = and i32 [[T]], [[K:%.*]] | |
| +; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 | |
| +; CHECK-NEXT: [[T5:%.*]] = and i32 [[T4]], [[K]] | |
| +; CHECK-NEXT: [[T6:%.*]] = icmp ne i32 [[T5]], 0 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 [[T6]], i1 false | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t = shl i32 1, %c1 | |
| %t4 = lshr i32 -2147483648, %c2 | |
| @@ -468,7 +480,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_logical(i32 %k, i32 %c | |
| ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 | |
| ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] | |
| ; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1 | |
| -; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T4]] | |
| ; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 1, %c1 | |
| @@ -506,7 +518,7 @@ define i1 @foo1_or_signbit_lshr_without_shifting_signbit_logical(i32 %k, i32 %c1 | |
| ; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 | |
| ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] | |
| ; CHECK-NEXT: [[T4:%.*]] = icmp slt i32 [[T3]], 0 | |
| -; CHECK-NEXT: [[OR:%.*]] = and i1 [[T2]], [[T4]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 [[T4]], i1 false | |
| ; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 1, %c1 | |
| @@ -538,10 +550,11 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_both_sides(i32 %k, i32 | |
| define i1 @foo1_and_signbit_lshr_without_shifting_signbit_both_sides_logical(i32 %k, i32 %c1, i32 %c2) { | |
| ; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_both_sides_logical( | |
| ; CHECK-NEXT: [[T0:%.*]] = shl i32 [[K:%.*]], [[C1:%.*]] | |
| +; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[T0]], -1 | |
| ; CHECK-NEXT: [[T2:%.*]] = shl i32 [[K]], [[C2:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T0]], [[T2]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1 | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[T3:%.*]] = icmp sgt i32 [[T2]], -1 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T1]], i1 true, i1 [[T3]] | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 %k, %c1 | |
| %t1 = icmp sgt i32 %t0, -1 | |
| @@ -570,10 +583,11 @@ define i1 @foo1_or_signbit_lshr_without_shifting_signbit_both_sides(i32 %k, i32 | |
| define i1 @foo1_or_signbit_lshr_without_shifting_signbit_both_sides_logical(i32 %k, i32 %c1, i32 %c2) { | |
| ; CHECK-LABEL: @foo1_or_signbit_lshr_without_shifting_signbit_both_sides_logical( | |
| ; CHECK-NEXT: [[T0:%.*]] = shl i32 [[K:%.*]], [[C1:%.*]] | |
| +; CHECK-NEXT: [[T1:%.*]] = icmp slt i32 [[T0]], 0 | |
| ; CHECK-NEXT: [[T2:%.*]] = shl i32 [[K]], [[C2:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T0]], [[T2]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0 | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[T3:%.*]] = icmp slt i32 [[T2]], 0 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T1]], i1 [[T3]], i1 false | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 %k, %c1 | |
| %t1 = icmp slt i32 %t0, 0 | |
| @@ -612,10 +626,12 @@ define i1 @foo1_and_extra_use_shl_logical(i32 %k, i32 %c1, i32 %c2, i32* %p) { | |
| ; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] | |
| ; CHECK-NEXT: store i32 [[T0]], i32* [[P:%.*]], align 4 | |
| ; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: ret i1 [[TMP3]] | |
| +; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[K:%.*]] | |
| +; CHECK-NEXT: [[T3:%.*]] = icmp eq i32 [[T2]], 0 | |
| +; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[K]] | |
| +; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], 0 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]] | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 1, %c1 | |
| store i32 %t0, i32* %p ; extra use of shl | |
| @@ -657,10 +673,11 @@ define i1 @foo1_and_extra_use_and_logical(i32 %k, i32 %c1, i32 %c2, i32* %p) { | |
| ; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] | |
| ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[K:%.*]] | |
| ; CHECK-NEXT: store i32 [[T2]], i32* [[P:%.*]], align 4 | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: ret i1 [[TMP3]] | |
| +; CHECK-NEXT: [[T3:%.*]] = icmp eq i32 [[T2]], 0 | |
| +; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[K]] | |
| +; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], 0 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]] | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 1, %c1 | |
| %t1 = shl i32 1, %c2 | |
| @@ -704,10 +721,10 @@ define i1 @foo1_and_extra_use_cmp_logical(i32 %k, i32 %c1, i32 %c2, i1* %p) { | |
| ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[K:%.*]] | |
| ; CHECK-NEXT: [[T3:%.*]] = icmp eq i32 [[T2]], 0 | |
| ; CHECK-NEXT: store i1 [[T3]], i1* [[P:%.*]], align 1 | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: ret i1 [[TMP3]] | |
| +; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[K]] | |
| +; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], 0 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]] | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 1, %c1 | |
| %t1 = shl i32 1, %c2 | |
| @@ -747,10 +764,12 @@ define i1 @foo1_and_extra_use_shl2_logical(i32 %k, i32 %c1, i32 %c2, i32* %p) { | |
| ; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] | |
| ; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] | |
| ; CHECK-NEXT: store i32 [[T1]], i32* [[P:%.*]], align 4 | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: ret i1 [[TMP3]] | |
| +; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[K:%.*]] | |
| +; CHECK-NEXT: [[T3:%.*]] = icmp eq i32 [[T2]], 0 | |
| +; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[K]] | |
| +; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], 0 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]] | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 1, %c1 | |
| %t1 = shl i32 1, %c2 | |
| @@ -790,12 +809,13 @@ define i1 @foo1_and_extra_use_and2_logical(i32 %k, i32 %c1, i32 %c2, i32* %p) { | |
| ; CHECK-LABEL: @foo1_and_extra_use_and2_logical( | |
| ; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] | |
| ; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] | |
| -; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[K:%.*]] | |
| +; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[K:%.*]] | |
| +; CHECK-NEXT: [[T3:%.*]] = icmp eq i32 [[T2]], 0 | |
| +; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[K]] | |
| ; CHECK-NEXT: store i32 [[T4]], i32* [[P:%.*]], align 4 | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: ret i1 [[TMP3]] | |
| +; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], 0 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]] | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 1, %c1 | |
| %t1 = shl i32 1, %c2 | |
| @@ -836,13 +856,13 @@ define i1 @foo1_and_extra_use_cmp2_logical(i32 %k, i32 %c1, i32 %c2, i1* %p) { | |
| ; CHECK-LABEL: @foo1_and_extra_use_cmp2_logical( | |
| ; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] | |
| ; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] | |
| -; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[K:%.*]] | |
| +; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[K:%.*]] | |
| +; CHECK-NEXT: [[T3:%.*]] = icmp eq i32 [[T2]], 0 | |
| +; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[K]] | |
| ; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], 0 | |
| ; CHECK-NEXT: store i1 [[T5]], i1* [[P:%.*]], align 1 | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K]] | |
| -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] | |
| -; CHECK-NEXT: ret i1 [[TMP3]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T3]], i1 true, i1 [[T5]] | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 1, %c1 | |
| %t1 = shl i32 1, %c2 | |
| @@ -886,7 +906,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl1_logical | |
| ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 | |
| ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] | |
| ; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1 | |
| -; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T4]] | |
| ; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 1, %c1 | |
| @@ -929,7 +949,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_and_logical( | |
| ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 | |
| ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] | |
| ; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1 | |
| -; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T4]] | |
| ; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 1, %c1 | |
| @@ -972,7 +992,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp1_logical | |
| ; CHECK-NEXT: store i1 [[T2]], i1* [[P:%.*]], align 1 | |
| ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] | |
| ; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1 | |
| -; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T4]] | |
| ; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 1, %c1 | |
| @@ -1015,7 +1035,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl2_logical | |
| ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] | |
| ; CHECK-NEXT: store i32 [[T3]], i32* [[P:%.*]], align 4 | |
| ; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1 | |
| -; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T4]] | |
| ; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 1, %c1 | |
| @@ -1058,7 +1078,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp2_logical | |
| ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] | |
| ; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1 | |
| ; CHECK-NEXT: store i1 [[T4]], i1* [[P:%.*]], align 1 | |
| -; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T4]] | |
| ; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 1, %c1 | |
| @@ -1100,7 +1120,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_not_pwr2_logical(i32 % | |
| ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 | |
| ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] | |
| ; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1 | |
| -; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T4]] | |
| ; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %t0 = shl i32 3, %c1 | |
| diff --git a/llvm/test/Transforms/InstCombine/or-fcmp.ll b/llvm/test/Transforms/InstCombine/or-fcmp.ll | |
| index da12ddf668c4..fed8459efc25 100644 | |
| --- a/llvm/test/Transforms/InstCombine/or-fcmp.ll | |
| +++ b/llvm/test/Transforms/InstCombine/or-fcmp.ll | |
| @@ -14,8 +14,10 @@ define i1 @PR1738(double %x, double %y) { | |
| define i1 @PR1738_logical(double %x, double %y) { | |
| ; CHECK-LABEL: @PR1738_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno double [[X:%.*]], [[Y:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[CMP1:%.*]] = fcmp uno double [[X:%.*]], 0.000000e+00 | |
| +; CHECK-NEXT: [[CMP2:%.*]] = fcmp uno double [[Y:%.*]], 0.000000e+00 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]] | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %cmp1 = fcmp uno double %x, 0.0 | |
| %cmp2 = fcmp uno double %y, 0.0 | |
| @@ -52,8 +54,10 @@ define i1 @PR41069(double %a, double %b, double %c, double %d) { | |
| define i1 @PR41069_logical(double %a, double %b, double %c, double %d) { | |
| ; CHECK-LABEL: @PR41069_logical( | |
| ; CHECK-NEXT: [[UNO1:%.*]] = fcmp uno double [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno double [[D:%.*]], [[C:%.*]] | |
| -; CHECK-NEXT: [[R:%.*]] = or i1 [[TMP1]], [[UNO1]] | |
| +; CHECK-NEXT: [[UNO2:%.*]] = fcmp uno double [[C:%.*]], 0.000000e+00 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[UNO1]], i1 true, i1 [[UNO2]] | |
| +; CHECK-NEXT: [[UNO3:%.*]] = fcmp uno double [[D:%.*]], 0.000000e+00 | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[OR]], i1 true, i1 [[UNO3]] | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %uno1 = fcmp uno double %a, %b | |
| @@ -82,8 +86,10 @@ define i1 @PR41069_commute(double %a, double %b, double %c, double %d) { | |
| define i1 @PR41069_commute_logical(double %a, double %b, double %c, double %d) { | |
| ; CHECK-LABEL: @PR41069_commute_logical( | |
| ; CHECK-NEXT: [[UNO1:%.*]] = fcmp uno double [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno double [[D:%.*]], [[C:%.*]] | |
| -; CHECK-NEXT: [[R:%.*]] = or i1 [[TMP1]], [[UNO1]] | |
| +; CHECK-NEXT: [[UNO2:%.*]] = fcmp uno double [[C:%.*]], 0.000000e+00 | |
| +; CHECK-NEXT: [[UNO3:%.*]] = fcmp uno double [[D:%.*]], 0.000000e+00 | |
| +; CHECK-NEXT: [[TMP1:%.*]] = or i1 [[UNO3]], [[UNO1]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP1]], i1 true, i1 [[UNO2]] | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %uno1 = fcmp uno double %a, %b | |
| @@ -133,8 +139,10 @@ define i1 @fcmp_uno_nonzero(float %x, float %y) { | |
| define i1 @fcmp_uno_nonzero_logical(float %x, float %y) { | |
| ; CHECK-LABEL: @fcmp_uno_nonzero_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno float [[X:%.*]], [[Y:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[CMP1:%.*]] = fcmp uno float [[X:%.*]], 0.000000e+00 | |
| +; CHECK-NEXT: [[CMP2:%.*]] = fcmp uno float [[Y:%.*]], 0.000000e+00 | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]] | |
| +; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %cmp1 = fcmp uno float %x, 1.0 | |
| %cmp2 = fcmp uno float %y, 2.0 | |
| diff --git a/llvm/test/Transforms/InstCombine/or.ll b/llvm/test/Transforms/InstCombine/or.ll | |
| index ff6244526563..33e755061300 100644 | |
| --- a/llvm/test/Transforms/InstCombine/or.ll | |
| +++ b/llvm/test/Transforms/InstCombine/or.ll | |
| @@ -212,8 +212,8 @@ define i1 @test25_logical(i32 %A, i32 %B) { | |
| ; CHECK-LABEL: @test25_logical( | |
| ; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[A:%.*]], 0 | |
| ; CHECK-NEXT: [[D:%.*]] = icmp ne i32 [[B:%.*]], 57 | |
| -; CHECK-NEXT: [[F:%.*]] = and i1 [[C]], [[D]] | |
| -; CHECK-NEXT: ret i1 [[F]] | |
| +; CHECK-NEXT: [[E:%.*]] = select i1 [[C]], i1 [[D]], i1 false | |
| +; CHECK-NEXT: ret i1 [[E]] | |
| ; | |
| %C = icmp eq i32 %A, 0 | |
| %D = icmp eq i32 %B, 57 | |
| @@ -238,9 +238,10 @@ define i1 @test26(i32 %A, i32 %B) { | |
| define i1 @test26_logical(i32 %A, i32 %B) { | |
| ; CHECK-LABEL: @test26_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0 | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[C1:%.*]] = icmp eq i32 [[A:%.*]], 0 | |
| +; CHECK-NEXT: [[C2:%.*]] = icmp eq i32 [[B:%.*]], 0 | |
| +; CHECK-NEXT: [[D:%.*]] = select i1 [[C1]], i1 [[C2]], i1 false | |
| +; CHECK-NEXT: ret i1 [[D]] | |
| ; | |
| %C1 = icmp eq i32 %A, 0 | |
| %C2 = icmp eq i32 %B, 0 | |
| @@ -293,9 +294,10 @@ define i1 @test28(i32 %A, i32 %B) { | |
| define i1 @test28_logical(i32 %A, i32 %B) { | |
| ; CHECK-LABEL: @test28_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[C1:%.*]] = icmp ne i32 [[A:%.*]], 0 | |
| +; CHECK-NEXT: [[C2:%.*]] = icmp ne i32 [[B:%.*]], 0 | |
| +; CHECK-NEXT: [[D:%.*]] = select i1 [[C1]], i1 true, i1 [[C2]] | |
| +; CHECK-NEXT: ret i1 [[D]] | |
| ; | |
| %C1 = icmp ne i32 %A, 0 | |
| %C2 = icmp ne i32 %B, 0 | |
| @@ -420,7 +422,7 @@ define i1 @test33(i1 %X, i1 %Y) { | |
| define i1 @test33_logical(i1 %X, i1 %Y) { | |
| ; CHECK-LABEL: @test33_logical( | |
| -; CHECK-NEXT: [[A:%.*]] = or i1 [[X:%.*]], [[Y:%.*]] | |
| +; CHECK-NEXT: [[A:%.*]] = select i1 [[X:%.*]], i1 true, i1 [[Y:%.*]] | |
| ; CHECK-NEXT: ret i1 [[A]] | |
| ; | |
| %a = select i1 %X, i1 true, i1 %Y | |
| @@ -990,8 +992,10 @@ define i1 @or_andn_cmp_1(i32 %a, i32 %b, i32 %c) { | |
| define i1 @or_andn_cmp_1_logical(i32 %a, i32 %b, i32 %c) { | |
| ; CHECK-LABEL: @or_andn_cmp_1_logical( | |
| ; CHECK-NEXT: [[X:%.*]] = icmp sgt i32 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X_INV:%.*]] = icmp sle i32 [[A]], [[B]] | |
| ; CHECK-NEXT: [[Y:%.*]] = icmp ugt i32 [[C:%.*]], 42 | |
| -; CHECK-NEXT: [[OR:%.*]] = or i1 [[X]], [[Y]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[Y]], i1 [[X_INV]], i1 false | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[X]], i1 true, i1 [[AND]] | |
| ; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %x = icmp sgt i32 %a, %b | |
| @@ -1041,8 +1045,10 @@ define i1 @or_andn_cmp_3(i72 %a, i72 %b, i72 %c) { | |
| define i1 @or_andn_cmp_3_logical(i72 %a, i72 %b, i72 %c) { | |
| ; CHECK-LABEL: @or_andn_cmp_3_logical( | |
| ; CHECK-NEXT: [[X:%.*]] = icmp ugt i72 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X_INV:%.*]] = icmp ule i72 [[A]], [[B]] | |
| ; CHECK-NEXT: [[Y:%.*]] = icmp ugt i72 [[C:%.*]], 42 | |
| -; CHECK-NEXT: [[OR:%.*]] = or i1 [[X]], [[Y]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[X_INV]], i1 [[Y]], i1 false | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[X]], i1 true, i1 [[AND]] | |
| ; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %x = icmp ugt i72 %a, %b | |
| @@ -1091,9 +1097,11 @@ define i1 @orn_and_cmp_1(i37 %a, i37 %b, i37 %c) { | |
| define i1 @orn_and_cmp_1_logical(i37 %a, i37 %b, i37 %c) { | |
| ; CHECK-LABEL: @orn_and_cmp_1_logical( | |
| -; CHECK-NEXT: [[X_INV:%.*]] = icmp sle i37 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X:%.*]] = icmp sgt i37 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X_INV:%.*]] = icmp sle i37 [[A]], [[B]] | |
| ; CHECK-NEXT: [[Y:%.*]] = icmp ugt i37 [[C:%.*]], 42 | |
| -; CHECK-NEXT: [[OR:%.*]] = or i1 [[X_INV]], [[Y]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[Y]], i1 [[X]], i1 false | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[X_INV]], i1 true, i1 [[AND]] | |
| ; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %x = icmp sgt i37 %a, %b | |
| @@ -1124,9 +1132,11 @@ define i1 @orn_and_cmp_2(i16 %a, i16 %b, i16 %c) { | |
| define i1 @orn_and_cmp_2_logical(i16 %a, i16 %b, i16 %c) { | |
| ; CHECK-LABEL: @orn_and_cmp_2_logical( | |
| -; CHECK-NEXT: [[X_INV:%.*]] = icmp slt i16 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X:%.*]] = icmp sge i16 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X_INV:%.*]] = icmp slt i16 [[A]], [[B]] | |
| ; CHECK-NEXT: [[Y:%.*]] = icmp ugt i16 [[C:%.*]], 42 | |
| -; CHECK-NEXT: [[OR:%.*]] = or i1 [[Y]], [[X_INV]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[Y]], i1 [[X]], i1 false | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[AND]], i1 true, i1 [[X_INV]] | |
| ; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %x = icmp sge i16 %a, %b | |
| @@ -1175,9 +1185,11 @@ define i1 @orn_and_cmp_4(i32 %a, i32 %b, i32 %c) { | |
| define i1 @orn_and_cmp_4_logical(i32 %a, i32 %b, i32 %c) { | |
| ; CHECK-LABEL: @orn_and_cmp_4_logical( | |
| -; CHECK-NEXT: [[X_INV:%.*]] = icmp ne i32 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[X_INV:%.*]] = icmp ne i32 [[A]], [[B]] | |
| ; CHECK-NEXT: [[Y:%.*]] = icmp ugt i32 [[C:%.*]], 42 | |
| -; CHECK-NEXT: [[OR:%.*]] = or i1 [[Y]], [[X_INV]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[X]], i1 [[Y]], i1 false | |
| +; CHECK-NEXT: [[OR:%.*]] = or i1 [[AND]], [[X_INV]] | |
| ; CHECK-NEXT: ret i1 [[OR]] | |
| ; | |
| %x = icmp eq i32 %a, %b | |
| @@ -1240,8 +1252,8 @@ define i32 @PR46712_logical(i1 %x, i1 %y, i1 %b, i64 %z) { | |
| ; CHECK-NEXT: entry: | |
| ; CHECK-NEXT: br i1 [[B:%.*]], label [[TRUE:%.*]], label [[END:%.*]] | |
| ; CHECK: true: | |
| -; CHECK-NEXT: [[BOOL5_NOT:%.*]] = icmp eq i64 [[Z:%.*]], 0 | |
| -; CHECK-NEXT: [[SEL:%.*]] = zext i1 [[BOOL5_NOT]] to i32 | |
| +; CHECK-NEXT: [[BOOL5:%.*]] = icmp eq i64 [[Z:%.*]], 0 | |
| +; CHECK-NEXT: [[SEL:%.*]] = zext i1 [[BOOL5]] to i32 | |
| ; CHECK-NEXT: br label [[END]] | |
| ; CHECK: end: | |
| ; CHECK-NEXT: [[T5:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SEL]], [[TRUE]] ] | |
| diff --git a/llvm/test/Transforms/InstCombine/prevent-cmp-merge.ll b/llvm/test/Transforms/InstCombine/prevent-cmp-merge.ll | |
| index 17d1dd28e126..3dd89f8eda12 100644 | |
| --- a/llvm/test/Transforms/InstCombine/prevent-cmp-merge.ll | |
| +++ b/llvm/test/Transforms/InstCombine/prevent-cmp-merge.ll | |
| @@ -26,7 +26,7 @@ define zeroext i1 @test1_logical(i32 %lhs, i32 %rhs) { | |
| ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[LHS:%.*]], 5 | |
| ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[XOR]], 10 | |
| ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[XOR]], [[RHS:%.*]] | |
| -; CHECK-NEXT: [[SEL:%.*]] = or i1 [[CMP1]], [[CMP2]] | |
| +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]] | |
| ; CHECK-NEXT: ret i1 [[SEL]] | |
| ; | |
| diff --git a/llvm/test/Transforms/InstCombine/range-check.ll b/llvm/test/Transforms/InstCombine/range-check.ll | |
| index 5d56e0a90360..4639d71a457c 100644 | |
| --- a/llvm/test/Transforms/InstCombine/range-check.ll | |
| +++ b/llvm/test/Transforms/InstCombine/range-check.ll | |
| @@ -20,8 +20,10 @@ define i1 @test_and1(i32 %x, i32 %n) { | |
| define i1 @test_and1_logical(i32 %x, i32 %n) { | |
| ; CHECK-LABEL: @test_and1_logical( | |
| ; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[NN]], [[X:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], -1 | |
| +; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[NN]], [[X]] | |
| +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i1 [[B]], i1 false | |
| +; CHECK-NEXT: ret i1 [[C]] | |
| ; | |
| %nn = and i32 %n, 2147483647 | |
| %a = icmp sge i32 %x, 0 | |
| @@ -46,8 +48,10 @@ define i1 @test_and2(i32 %x, i32 %n) { | |
| define i1 @test_and2_logical(i32 %x, i32 %n) { | |
| ; CHECK-LABEL: @test_and2_logical( | |
| ; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 [[NN]], [[X:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], -1 | |
| +; CHECK-NEXT: [[B:%.*]] = icmp sge i32 [[NN]], [[X]] | |
| +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i1 [[B]], i1 false | |
| +; CHECK-NEXT: ret i1 [[C]] | |
| ; | |
| %nn = and i32 %n, 2147483647 | |
| %a = icmp sgt i32 %x, -1 | |
| @@ -124,8 +128,10 @@ define i1 @test_or1(i32 %x, i32 %n) { | |
| define i1 @test_or1_logical(i32 %x, i32 %n) { | |
| ; CHECK-LABEL: @test_or1_logical( | |
| ; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[NN]], [[X:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[A:%.*]] = icmp slt i32 [[X:%.*]], 0 | |
| +; CHECK-NEXT: [[B:%.*]] = icmp sle i32 [[NN]], [[X]] | |
| +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i1 true, i1 [[B]] | |
| +; CHECK-NEXT: ret i1 [[C]] | |
| ; | |
| %nn = and i32 %n, 2147483647 | |
| %a = icmp slt i32 %x, 0 | |
| @@ -150,8 +156,10 @@ define i1 @test_or2(i32 %x, i32 %n) { | |
| define i1 @test_or2_logical(i32 %x, i32 %n) { | |
| ; CHECK-LABEL: @test_or2_logical( | |
| ; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NN]], [[X:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[A:%.*]] = icmp slt i32 [[X:%.*]], 0 | |
| +; CHECK-NEXT: [[B:%.*]] = icmp slt i32 [[NN]], [[X]] | |
| +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i1 true, i1 [[B]] | |
| +; CHECK-NEXT: ret i1 [[C]] | |
| ; | |
| %nn = and i32 %n, 2147483647 | |
| %a = icmp sle i32 %x, -1 | |
| @@ -290,7 +298,7 @@ define i1 @negative3_logical(i32 %x, i32 %y, i32 %n) { | |
| ; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 | |
| ; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[NN]], [[X:%.*]] | |
| ; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[Y:%.*]], -1 | |
| -; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] | |
| +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i1 [[B]], i1 false | |
| ; CHECK-NEXT: ret i1 [[C]] | |
| ; | |
| %nn = and i32 %n, 2147483647 | |
| diff --git a/llvm/test/Transforms/InstCombine/result-of-add-of-negative-is-non-zero-and-no-underflow.ll b/llvm/test/Transforms/InstCombine/result-of-add-of-negative-is-non-zero-and-no-underflow.ll | |
| index bcc62dc983c6..5bdc9f6d6497 100644 | |
| --- a/llvm/test/Transforms/InstCombine/result-of-add-of-negative-is-non-zero-and-no-underflow.ll | |
| +++ b/llvm/test/Transforms/InstCombine/result-of-add-of-negative-is-non-zero-and-no-underflow.ll | |
| @@ -30,7 +30,7 @@ define i1 @t0_bad_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ult i8 [[ADJUSTED]], [[BASE]] | |
| -; CHECK-NEXT: [[R:%.*]] = and i1 [[NOT_NULL]], [[NO_UNDERFLOW]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = add i8 %base, %offset | |
| @@ -69,9 +69,10 @@ define i1 @t1_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) | |
| ; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]] | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| +; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ult i8 [[ADJUSTED]], [[BASE]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %cmp = icmp slt i8 %base, 0 | |
| call void @llvm.assume(i1 %cmp) | |
| @@ -112,9 +113,10 @@ define i1 @t2_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) | |
| ; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET]] | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| +; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ult i8 [[ADJUSTED]], [[BASE]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %cmp = icmp slt i8 %offset, 0 | |
| call void @llvm.assume(i1 %cmp) | |
| @@ -160,9 +162,9 @@ define i1 @t3_oneuse0_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ult i8 [[ADJUSTED]], [[BASE]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %cmp = icmp slt i8 %base, 0 | |
| call void @llvm.assume(i1 %cmp) | |
| @@ -205,11 +207,11 @@ define i1 @t4_oneuse1_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) | |
| ; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]] | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| +; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ult i8 [[ADJUSTED]], [[BASE]] | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %cmp = icmp slt i8 %base, 0 | |
| call void @llvm.assume(i1 %cmp) | |
| @@ -258,7 +260,7 @@ define i1 @t5_oneuse2_bad_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| ; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ult i8 [[ADJUSTED]], [[BASE]] | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| -; CHECK-NEXT: [[R:%.*]] = and i1 [[NOT_NULL]], [[NO_UNDERFLOW]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %cmp = icmp slt i8 %base, 0 | |
| @@ -342,9 +344,10 @@ define i1 @t7_commutativity1_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) | |
| ; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]] | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| +; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ult i8 [[ADJUSTED]], [[BASE]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %cmp = icmp slt i8 %base, 0 | |
| call void @llvm.assume(i1 %cmp) | |
| @@ -426,9 +429,10 @@ define i1 @t8_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) | |
| ; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]] | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i8 [[TMP1]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp eq i8 [[ADJUSTED]], 0 | |
| +; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp uge i8 [[ADJUSTED]], [[BASE]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 true, i1 [[NO_UNDERFLOW]] | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %cmp = icmp slt i8 %base, 0 | |
| call void @llvm.assume(i1 %cmp) | |
| @@ -469,9 +473,10 @@ define i1 @t9_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) | |
| ; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]] | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| +; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ult i8 [[ADJUSTED]], [[OFFSET]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %cmp = icmp slt i8 %base, 0 | |
| call void @llvm.assume(i1 %cmp) | |
| diff --git a/llvm/test/Transforms/InstCombine/result-of-add-of-negative-or-zero-is-non-zero-and-no-underflow.ll b/llvm/test/Transforms/InstCombine/result-of-add-of-negative-or-zero-is-non-zero-and-no-underflow.ll | |
| index e2f256140b51..153f260df6e1 100644 | |
| --- a/llvm/test/Transforms/InstCombine/result-of-add-of-negative-or-zero-is-non-zero-and-no-underflow.ll | |
| +++ b/llvm/test/Transforms/InstCombine/result-of-add-of-negative-or-zero-is-non-zero-and-no-underflow.ll | |
| @@ -26,9 +26,10 @@ define i1 @t0_logical(i8 %base, i8 %offset) { | |
| ; CHECK-LABEL: @t0_logical( | |
| ; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]] | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| +; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ule i8 [[ADJUSTED]], [[BASE]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = add i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -64,9 +65,9 @@ define i1 @t1_oneuse0_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ule i8 [[ADJUSTED]], [[BASE]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = add i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -99,11 +100,11 @@ define i1 @t2_oneuse1_logical(i8 %base, i8 %offset) { | |
| ; CHECK-LABEL: @t2_oneuse1_logical( | |
| ; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]] | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| +; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ule i8 [[ADJUSTED]], [[BASE]] | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = add i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -142,7 +143,7 @@ define i1 @n3_oneuse2_bad_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| ; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ule i8 [[ADJUSTED]], [[BASE]] | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| -; CHECK-NEXT: [[R:%.*]] = and i1 [[NOT_NULL]], [[NO_UNDERFLOW]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = add i8 %base, %offset | |
| @@ -206,9 +207,10 @@ define i1 @t5_commutativity1_logical(i8 %base, i8 %offset) { | |
| ; CHECK-LABEL: @t5_commutativity1_logical( | |
| ; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]] | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| +; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ule i8 [[ADJUSTED]], [[BASE]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = add i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -270,9 +272,10 @@ define i1 @t7_logical(i8 %base, i8 %offset) { | |
| ; CHECK-LABEL: @t7_logical( | |
| ; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]] | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[ADJUSTED]], -1 | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i8 [[TMP1]], [[BASE]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp eq i8 [[ADJUSTED]], 0 | |
| +; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ugt i8 [[ADJUSTED]], [[BASE]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 true, i1 [[NO_UNDERFLOW]] | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = add i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -303,9 +306,10 @@ define i1 @t8_logical(i8 %base, i8 %offset) { | |
| ; CHECK-LABEL: @t8_logical( | |
| ; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]] | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| +; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ule i8 [[ADJUSTED]], [[OFFSET]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = add i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| diff --git a/llvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll b/llvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll | |
| index b875396a8c6d..d93b0a7b33df 100644 | |
| --- a/llvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll | |
| +++ b/llvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll | |
| @@ -45,8 +45,8 @@ define i1 @t0_noncanonical_ignoreme_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = sub i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -87,8 +87,8 @@ define i1 @t1_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = sub i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -127,7 +127,8 @@ define i1 @t1_strict_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| -; CHECK-NEXT: ret i1 [[NO_UNDERFLOW]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = sub i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -177,7 +178,7 @@ define i1 @t2_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = xor i1 [[UNDERFLOW]], true | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| -; CHECK-NEXT: [[R:%.*]] = and i1 [[NOT_NULL]], [[NO_UNDERFLOW]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %agg = call {i8, i1} @llvm.usub.with.overflow(i8 %base, i8 %offset) | |
| @@ -224,8 +225,8 @@ define i1 @t3_commutability0_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = sub i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -265,8 +266,8 @@ define i1 @t4_commutability1_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NO_UNDERFLOW]], i1 [[NOT_NULL]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = sub i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -306,8 +307,8 @@ define i1 @t5_commutability2_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NO_UNDERFLOW]], i1 [[NOT_NULL]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = sub i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -357,7 +358,7 @@ define i1 @t6_commutability_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = xor i1 [[UNDERFLOW]], true | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| -; CHECK-NEXT: [[R:%.*]] = and i1 [[NOT_NULL]], [[NO_UNDERFLOW]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NO_UNDERFLOW]], i1 [[NOT_NULL]], i1 false | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %agg = call {i8, i1} @llvm.usub.with.overflow(i8 %base, i8 %offset) | |
| @@ -405,8 +406,8 @@ define i1 @t7_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @use1(i1 [[UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NULL:%.*]] = icmp eq i8 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NULL]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[BASE]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NULL]], i1 true, i1 [[UNDERFLOW]] | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = sub i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -445,7 +446,8 @@ define i1 @t7_nonstrict_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @use1(i1 [[UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NULL:%.*]] = icmp eq i8 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NULL]]) | |
| -; CHECK-NEXT: ret i1 [[UNDERFLOW]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NULL]], i1 true, i1 [[UNDERFLOW]] | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = sub i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -489,7 +491,7 @@ define i1 @t8_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: [[UNDERFLOW:%.*]] = extractvalue { i8, i1 } [[AGG]], 1 | |
| ; CHECK-NEXT: call void @use1(i1 [[UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NULL:%.*]] = icmp eq i8 [[ADJUSTED]], 0 | |
| -; CHECK-NEXT: [[R:%.*]] = or i1 [[NULL]], [[UNDERFLOW]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NULL]], i1 true, i1 [[UNDERFLOW]] | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %agg = call {i8, i1} @llvm.usub.with.overflow(i8 %base, i8 %offset) | |
| @@ -534,8 +536,8 @@ define i1 @t9_commutative_logical(i8 %base, i8 %offset) { | |
| ; CHECK-NEXT: call void @use1(i1 [[UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NULL:%.*]] = icmp eq i8 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NULL]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[BASE]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NULL]], i1 true, i1 [[UNDERFLOW]] | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = sub i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -582,8 +584,8 @@ define i1 @t10_logical(i64 %base, i64* nonnull %offsetptr) { | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i64 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[OFFSET]], [[BASE]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %offset = ptrtoint i64* %offsetptr to i64 | |
| @@ -629,8 +631,8 @@ define i1 @t11_commutative_logical(i64 %base, i64* nonnull %offsetptr) { | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i64 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[OFFSET]], [[BASE]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %offset = ptrtoint i64* %offsetptr to i64 | |
| @@ -677,8 +679,8 @@ define i1 @t12_logical(i64 %base, i64* nonnull %offsetptr) { | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp eq i64 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i64 [[OFFSET]], [[BASE]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 true, i1 [[NO_UNDERFLOW]] | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %offset = ptrtoint i64* %offsetptr to i64 | |
| @@ -724,8 +726,8 @@ define i1 @t13_logical(i64 %base, i64* nonnull %offsetptr) { | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp eq i64 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i64 [[OFFSET]], [[BASE]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 true, i1 [[NO_UNDERFLOW]] | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %offset = ptrtoint i64* %offsetptr to i64 | |
| @@ -768,7 +770,7 @@ define i1 @t14_bad_logical(i64 %base, i64 %offset) { | |
| ; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]]) | |
| ; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i64 [[ADJUSTED]], 0 | |
| ; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]]) | |
| -; CHECK-NEXT: [[R:%.*]] = and i1 [[NOT_NULL]], [[NO_UNDERFLOW]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_NULL]], i1 [[NO_UNDERFLOW]], i1 false | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = sub i64 %base, %offset | |
| @@ -800,8 +802,10 @@ define i1 @base_ult_offset_logical(i8 %base, i8 %offset) { | |
| ; CHECK-LABEL: @base_ult_offset_logical( | |
| ; CHECK-NEXT: [[ADJUSTED:%.*]] = sub i8 [[BASE:%.*]], [[OFFSET:%.*]] | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[BASE]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0 | |
| +; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ule i8 [[BASE]], [[OFFSET]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NO_UNDERFLOW]], i1 [[NOT_NULL]], i1 false | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = sub i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| @@ -829,8 +833,10 @@ define i1 @base_uge_offset_logical(i8 %base, i8 %offset) { | |
| ; CHECK-LABEL: @base_uge_offset_logical( | |
| ; CHECK-NEXT: [[ADJUSTED:%.*]] = sub i8 [[BASE:%.*]], [[OFFSET:%.*]] | |
| ; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]]) | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[BASE]], [[OFFSET]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp eq i8 [[ADJUSTED]], 0 | |
| +; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NO_UNDERFLOW]], i1 true, i1 [[NOT_NULL]] | |
| +; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %adjusted = sub i8 %base, %offset | |
| call void @use8(i8 %adjusted) | |
| diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll | |
| index d603de371ba0..ca115b3040d3 100644 | |
| --- a/llvm/test/Transforms/InstCombine/select.ll | |
| +++ b/llvm/test/Transforms/InstCombine/select.ll | |
| @@ -25,7 +25,7 @@ define i32 @test6(i1 %C) { | |
| define i1 @trueval_is_true(i1 %C, i1 %X) { | |
| ; CHECK-LABEL: @trueval_is_true( | |
| -; CHECK-NEXT: [[R:%.*]] = or i1 [[C:%.*]], [[X:%.*]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i1 true, i1 [[X:%.*]] | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %R = select i1 %C, i1 true, i1 %X | |
| @@ -34,7 +34,7 @@ define i1 @trueval_is_true(i1 %C, i1 %X) { | |
| define <2 x i1> @trueval_is_true_vec(<2 x i1> %C, <2 x i1> %X) { | |
| ; CHECK-LABEL: @trueval_is_true_vec( | |
| -; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[C:%.*]], [[X:%.*]] | |
| +; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C:%.*]], <2 x i1> <i1 true, i1 true>, <2 x i1> [[X:%.*]] | |
| ; CHECK-NEXT: ret <2 x i1> [[R]] | |
| ; | |
| %R = select <2 x i1> %C, <2 x i1> <i1 true, i1 true>, <2 x i1> %X | |
| @@ -43,7 +43,7 @@ define <2 x i1> @trueval_is_true_vec(<2 x i1> %C, <2 x i1> %X) { | |
| define <2 x i1> @trueval_is_true_vec_undef_elt(<2 x i1> %C, <2 x i1> %X) { | |
| ; CHECK-LABEL: @trueval_is_true_vec_undef_elt( | |
| -; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[C:%.*]], [[X:%.*]] | |
| +; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C:%.*]], <2 x i1> <i1 undef, i1 true>, <2 x i1> [[X:%.*]] | |
| ; CHECK-NEXT: ret <2 x i1> [[R]] | |
| ; | |
| %R = select <2 x i1> %C, <2 x i1> <i1 undef, i1 true>, <2 x i1> %X | |
| @@ -52,7 +52,7 @@ define <2 x i1> @trueval_is_true_vec_undef_elt(<2 x i1> %C, <2 x i1> %X) { | |
| define i1 @test8(i1 %C, i1 %X) { | |
| ; CHECK-LABEL: @test8( | |
| -; CHECK-NEXT: [[R:%.*]] = and i1 [[C:%.*]], [[X:%.*]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i1 [[X:%.*]], i1 false | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %R = select i1 %C, i1 %X, i1 false | |
| @@ -61,7 +61,7 @@ define i1 @test8(i1 %C, i1 %X) { | |
| define <2 x i1> @test8vec(<2 x i1> %C, <2 x i1> %X) { | |
| ; CHECK-LABEL: @test8vec( | |
| -; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[C:%.*]], [[X:%.*]] | |
| +; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C:%.*]], <2 x i1> [[X:%.*]], <2 x i1> zeroinitializer | |
| ; CHECK-NEXT: ret <2 x i1> [[R]] | |
| ; | |
| %R = select <2 x i1> %C, <2 x i1> %X, <2 x i1> <i1 false, i1 false> | |
| @@ -70,7 +70,7 @@ define <2 x i1> @test8vec(<2 x i1> %C, <2 x i1> %X) { | |
| define <vscale x 2 x i1> @test8vvec(<vscale x 2 x i1> %C, <vscale x 2 x i1> %X) { | |
| ; CHECK-LABEL: @test8vvec( | |
| -; CHECK-NEXT: [[R:%.*]] = and <vscale x 2 x i1> [[C:%.*]], [[X:%.*]] | |
| +; CHECK-NEXT: [[R:%.*]] = select <vscale x 2 x i1> [[C:%.*]], <vscale x 2 x i1> [[X:%.*]], <vscale x 2 x i1> zeroinitializer | |
| ; CHECK-NEXT: ret <vscale x 2 x i1> [[R]] | |
| ; | |
| %R = select <vscale x 2 x i1> %C, <vscale x 2 x i1> %X, <vscale x 2 x i1> zeroinitializer | |
| @@ -80,7 +80,7 @@ define <vscale x 2 x i1> @test8vvec(<vscale x 2 x i1> %C, <vscale x 2 x i1> %X) | |
| define i1 @test9(i1 %C, i1 %X) { | |
| ; CHECK-LABEL: @test9( | |
| ; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C:%.*]], true | |
| -; CHECK-NEXT: [[R:%.*]] = and i1 [[NOT_C]], [[X:%.*]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_C]], i1 [[X:%.*]], i1 false | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %R = select i1 %C, i1 false, i1 %X | |
| @@ -90,7 +90,7 @@ define i1 @test9(i1 %C, i1 %X) { | |
| define <2 x i1> @test9vec(<2 x i1> %C, <2 x i1> %X) { | |
| ; CHECK-LABEL: @test9vec( | |
| ; CHECK-NEXT: [[NOT_C:%.*]] = xor <2 x i1> [[C:%.*]], <i1 true, i1 true> | |
| -; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[NOT_C]], [[X:%.*]] | |
| +; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[NOT_C]], <2 x i1> [[X:%.*]], <2 x i1> zeroinitializer | |
| ; CHECK-NEXT: ret <2 x i1> [[R]] | |
| ; | |
| %R = select <2 x i1> %C, <2 x i1> <i1 false, i1 false>, <2 x i1> %X | |
| @@ -100,7 +100,7 @@ define <2 x i1> @test9vec(<2 x i1> %C, <2 x i1> %X) { | |
| define <vscale x 2 x i1> @test9vvec(<vscale x 2 x i1> %C, <vscale x 2 x i1> %X) { | |
| ; CHECK-LABEL: @test9vvec( | |
| ; CHECK-NEXT: [[NOT_C:%.*]] = xor <vscale x 2 x i1> [[C:%.*]], shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer) | |
| -; CHECK-NEXT: [[R:%.*]] = and <vscale x 2 x i1> [[NOT_C]], [[X:%.*]] | |
| +; CHECK-NEXT: [[R:%.*]] = select <vscale x 2 x i1> [[NOT_C]], <vscale x 2 x i1> [[X:%.*]], <vscale x 2 x i1> zeroinitializer | |
| ; CHECK-NEXT: ret <vscale x 2 x i1> [[R]] | |
| ; | |
| %R = select <vscale x 2 x i1> %C, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i1> %X | |
| @@ -110,7 +110,7 @@ define <vscale x 2 x i1> @test9vvec(<vscale x 2 x i1> %C, <vscale x 2 x i1> %X) | |
| define i1 @test10(i1 %C, i1 %X) { | |
| ; CHECK-LABEL: @test10( | |
| ; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C:%.*]], true | |
| -; CHECK-NEXT: [[R:%.*]] = or i1 [[NOT_C]], [[X:%.*]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_C]], i1 true, i1 [[X:%.*]] | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %R = select i1 %C, i1 %X, i1 true | |
| @@ -120,7 +120,7 @@ define i1 @test10(i1 %C, i1 %X) { | |
| define <2 x i1> @test10vec(<2 x i1> %C, <2 x i1> %X) { | |
| ; CHECK-LABEL: @test10vec( | |
| ; CHECK-NEXT: [[NOT_C:%.*]] = xor <2 x i1> [[C:%.*]], <i1 true, i1 true> | |
| -; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[NOT_C]], [[X:%.*]] | |
| +; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[NOT_C]], <2 x i1> <i1 true, i1 true>, <2 x i1> [[X:%.*]] | |
| ; CHECK-NEXT: ret <2 x i1> [[R]] | |
| ; | |
| %R = select <2 x i1> %C, <2 x i1> %X, <2 x i1> <i1 true, i1 true> | |
| @@ -129,7 +129,7 @@ define <2 x i1> @test10vec(<2 x i1> %C, <2 x i1> %X) { | |
| define i1 @test23(i1 %a, i1 %b) { | |
| ; CHECK-LABEL: @test23( | |
| -; CHECK-NEXT: [[C:%.*]] = and i1 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[C:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false | |
| ; CHECK-NEXT: ret i1 [[C]] | |
| ; | |
| %c = select i1 %a, i1 %b, i1 %a | |
| @@ -138,7 +138,7 @@ define i1 @test23(i1 %a, i1 %b) { | |
| define <2 x i1> @test23vec(<2 x i1> %a, <2 x i1> %b) { | |
| ; CHECK-LABEL: @test23vec( | |
| -; CHECK-NEXT: [[C:%.*]] = and <2 x i1> [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[C:%.*]] = select <2 x i1> [[A:%.*]], <2 x i1> [[B:%.*]], <2 x i1> zeroinitializer | |
| ; CHECK-NEXT: ret <2 x i1> [[C]] | |
| ; | |
| %c = select <2 x i1> %a, <2 x i1> %b, <2 x i1> %a | |
| @@ -147,7 +147,7 @@ define <2 x i1> @test23vec(<2 x i1> %a, <2 x i1> %b) { | |
| define i1 @test24(i1 %a, i1 %b) { | |
| ; CHECK-LABEL: @test24( | |
| -; CHECK-NEXT: [[C:%.*]] = or i1 [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[C:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[B:%.*]] | |
| ; CHECK-NEXT: ret i1 [[C]] | |
| ; | |
| %c = select i1 %a, i1 %a, i1 %b | |
| @@ -156,7 +156,7 @@ define i1 @test24(i1 %a, i1 %b) { | |
| define <2 x i1> @test24vec(<2 x i1> %a, <2 x i1> %b) { | |
| ; CHECK-LABEL: @test24vec( | |
| -; CHECK-NEXT: [[C:%.*]] = or <2 x i1> [[A:%.*]], [[B:%.*]] | |
| +; CHECK-NEXT: [[C:%.*]] = select <2 x i1> [[A:%.*]], <2 x i1> <i1 true, i1 true>, <2 x i1> [[B:%.*]] | |
| ; CHECK-NEXT: ret <2 x i1> [[C]] | |
| ; | |
| %c = select <2 x i1> %a, <2 x i1> %a, <2 x i1> %b | |
| @@ -166,7 +166,7 @@ define <2 x i1> @test24vec(<2 x i1> %a, <2 x i1> %b) { | |
| define i1 @test62(i1 %A, i1 %B) { | |
| ; CHECK-LABEL: @test62( | |
| ; CHECK-NEXT: [[NOT:%.*]] = xor i1 [[A:%.*]], true | |
| -; CHECK-NEXT: [[C:%.*]] = and i1 [[NOT]], [[B:%.*]] | |
| +; CHECK-NEXT: [[C:%.*]] = select i1 [[NOT]], i1 [[B:%.*]], i1 false | |
| ; CHECK-NEXT: ret i1 [[C]] | |
| ; | |
| %not = xor i1 %A, true | |
| @@ -177,7 +177,7 @@ define i1 @test62(i1 %A, i1 %B) { | |
| define <2 x i1> @test62vec(<2 x i1> %A, <2 x i1> %B) { | |
| ; CHECK-LABEL: @test62vec( | |
| ; CHECK-NEXT: [[NOT:%.*]] = xor <2 x i1> [[A:%.*]], <i1 true, i1 true> | |
| -; CHECK-NEXT: [[C:%.*]] = and <2 x i1> [[NOT]], [[B:%.*]] | |
| +; CHECK-NEXT: [[C:%.*]] = select <2 x i1> [[NOT]], <2 x i1> [[B:%.*]], <2 x i1> zeroinitializer | |
| ; CHECK-NEXT: ret <2 x i1> [[C]] | |
| ; | |
| %not = xor <2 x i1> %A, <i1 true, i1 true> | |
| @@ -188,7 +188,7 @@ define <2 x i1> @test62vec(<2 x i1> %A, <2 x i1> %B) { | |
| define i1 @test63(i1 %A, i1 %B) { | |
| ; CHECK-LABEL: @test63( | |
| ; CHECK-NEXT: [[NOT:%.*]] = xor i1 [[A:%.*]], true | |
| -; CHECK-NEXT: [[C:%.*]] = or i1 [[NOT]], [[B:%.*]] | |
| +; CHECK-NEXT: [[C:%.*]] = select i1 [[NOT]], i1 true, i1 [[B:%.*]] | |
| ; CHECK-NEXT: ret i1 [[C]] | |
| ; | |
| %not = xor i1 %A, true | |
| @@ -199,7 +199,7 @@ define i1 @test63(i1 %A, i1 %B) { | |
| define <2 x i1> @test63vec(<2 x i1> %A, <2 x i1> %B) { | |
| ; CHECK-LABEL: @test63vec( | |
| ; CHECK-NEXT: [[NOT:%.*]] = xor <2 x i1> [[A:%.*]], <i1 true, i1 true> | |
| -; CHECK-NEXT: [[C:%.*]] = or <2 x i1> [[NOT]], [[B:%.*]] | |
| +; CHECK-NEXT: [[C:%.*]] = select <2 x i1> [[NOT]], <2 x i1> <i1 true, i1 true>, <2 x i1> [[B:%.*]] | |
| ; CHECK-NEXT: ret <2 x i1> [[C]] | |
| ; | |
| %not = xor <2 x i1> %A, <i1 true, i1 true> | |
| @@ -317,7 +317,7 @@ define i1 @test14a(i1 %C, i32 %X) { | |
| ; CHECK-LABEL: @test14a( | |
| ; CHECK-NEXT: [[R1:%.*]] = icmp slt i32 [[X:%.*]], 1 | |
| ; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C:%.*]], true | |
| -; CHECK-NEXT: [[R:%.*]] = or i1 [[R1]], [[NOT_C]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_C]], i1 true, i1 [[R1]] | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %V = select i1 %C, i32 %X, i32 0 | |
| @@ -329,7 +329,7 @@ define i1 @test14a(i1 %C, i32 %X) { | |
| define i1 @test14b(i1 %C, i32 %X) { | |
| ; CHECK-LABEL: @test14b( | |
| ; CHECK-NEXT: [[R1:%.*]] = icmp slt i32 [[X:%.*]], 1 | |
| -; CHECK-NEXT: [[R:%.*]] = or i1 [[R1]], [[C:%.*]] | |
| +; CHECK-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i1 true, i1 [[R1]] | |
| ; CHECK-NEXT: ret i1 [[R]] | |
| ; | |
| %V = select i1 %C, i32 0, i32 %X | |
| @@ -400,7 +400,7 @@ define i1 @test17(i32* %X, i1 %C) { | |
| ; CHECK-LABEL: @test17( | |
| ; CHECK-NEXT: [[RV1:%.*]] = icmp eq i32* [[X:%.*]], null | |
| ; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C:%.*]], true | |
| -; CHECK-NEXT: [[RV:%.*]] = or i1 [[RV1]], [[NOT_C]] | |
| +; CHECK-NEXT: [[RV:%.*]] = select i1 [[NOT_C]], i1 true, i1 [[RV1]] | |
| ; CHECK-NEXT: ret i1 [[RV]] | |
| ; | |
| %R = select i1 %C, i32* %X, i32* null | |
| diff --git a/llvm/test/Transforms/InstCombine/sign-test-and-or.ll b/llvm/test/Transforms/InstCombine/sign-test-and-or.ll | |
| index a71cb54b9fc2..c6e1217843a3 100644 | |
| --- a/llvm/test/Transforms/InstCombine/sign-test-and-or.ll | |
| +++ b/llvm/test/Transforms/InstCombine/sign-test-and-or.ll | |
| @@ -17,9 +17,10 @@ define i1 @test1(i32 %a, i32 %b) { | |
| define i1 @test1_logical(i32 %a, i32 %b) { | |
| ; CHECK-LABEL: @test1_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0 | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[A:%.*]], 0 | |
| +; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[B:%.*]], 0 | |
| +; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[TMP1]], i1 true, i1 [[TMP2]] | |
| +; CHECK-NEXT: ret i1 [[OR_COND]] | |
| ; | |
| %1 = icmp slt i32 %a, 0 | |
| %2 = icmp slt i32 %b, 0 | |
| @@ -41,9 +42,10 @@ define i1 @test2(i32 %a, i32 %b) { | |
| define i1 @test2_logical(i32 %a, i32 %b) { | |
| ; CHECK-LABEL: @test2_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1 | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[A:%.*]], -1 | |
| +; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[B:%.*]], -1 | |
| +; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[TMP1]], i1 true, i1 [[TMP2]] | |
| +; CHECK-NEXT: ret i1 [[OR_COND]] | |
| ; | |
| %1 = icmp sgt i32 %a, -1 | |
| %2 = icmp sgt i32 %b, -1 | |
| @@ -65,9 +67,10 @@ define i1 @test3(i32 %a, i32 %b) { | |
| define i1 @test3_logical(i32 %a, i32 %b) { | |
| ; CHECK-LABEL: @test3_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0 | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[A:%.*]], 0 | |
| +; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[B:%.*]], 0 | |
| +; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[TMP1]], i1 [[TMP2]], i1 false | |
| +; CHECK-NEXT: ret i1 [[OR_COND]] | |
| ; | |
| %1 = icmp slt i32 %a, 0 | |
| %2 = icmp slt i32 %b, 0 | |
| @@ -89,9 +92,10 @@ define i1 @test4(i32 %a, i32 %b) { | |
| define i1 @test4_logical(i32 %a, i32 %b) { | |
| ; CHECK-LABEL: @test4_logical( | |
| -; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1 | |
| -; CHECK-NEXT: ret i1 [[TMP2]] | |
| +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[A:%.*]], -1 | |
| +; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[B:%.*]], -1 | |
| +; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[TMP1]], i1 [[TMP2]], i1 false | |
| +; CHECK-NEXT: ret i1 [[OR_COND]] | |
| ; | |
| %1 = icmp sgt i32 %a, -1 | |
| %2 = icmp sgt i32 %b, -1 | |
| diff --git a/llvm/test/Transforms/InstCombine/signed-truncation-check.ll b/llvm/test/Transforms/InstCombine/signed-truncation-check.ll | |
| index 62a62b97e90d..105e77284b93 100644 | |
| --- a/llvm/test/Transforms/InstCombine/signed-truncation-check.ll | |
| +++ b/llvm/test/Transforms/InstCombine/signed-truncation-check.ll | |
| @@ -155,9 +155,9 @@ define i1 @positive_with_extra_and(i32 %arg, i1 %z) { | |
| define i1 @positive_with_extra_and_logical(i32 %arg, i1 %z) { | |
| ; CHECK-LABEL: @positive_with_extra_and_logical( | |
| -; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128 | |
| -; CHECK-NEXT: [[TMP1:%.*]] = and i1 [[T5_SIMPLIFIED]], [[Z:%.*]] | |
| -; CHECK-NEXT: ret i1 [[TMP1]] | |
| +; CHECK-NEXT: [[DOTSIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128 | |
| +; CHECK-NEXT: [[T5:%.*]] = select i1 [[DOTSIMPLIFIED]], i1 [[Z:%.*]], i1 false | |
| +; CHECK-NEXT: ret i1 [[T5]] | |
| ; | |
| %t1 = icmp sgt i32 %arg, -1 | |
| %t2 = add i32 %arg, 128 | |
| @@ -449,7 +449,7 @@ define i1 @positive_different_trunc_both_logical(i32 %arg) { | |
| ; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[ARG]] to i16 | |
| ; CHECK-NEXT: [[T4:%.*]] = add i16 [[T3]], 128 | |
| ; CHECK-NEXT: [[T5:%.*]] = icmp ult i16 [[T4]], 256 | |
| -; CHECK-NEXT: [[T6:%.*]] = and i1 [[T2]], [[T5]] | |
| +; CHECK-NEXT: [[T6:%.*]] = select i1 [[T2]], i1 [[T5]], i1 false | |
| ; CHECK-NEXT: ret i1 [[T6]] | |
| ; | |
| %t1 = trunc i32 %arg to i15 | |
| @@ -606,7 +606,7 @@ define i1 @oneuse_shl_ashr_logical(i32 %arg) { | |
| ; CHECK-NEXT: call void @use32(i32 [[T4]]) | |
| ; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], [[ARG]] | |
| ; CHECK-NEXT: call void @use1(i1 [[T5]]) | |
| -; CHECK-NEXT: [[T6:%.*]] = and i1 [[T2]], [[T5]] | |
| +; CHECK-NEXT: [[T6:%.*]] = select i1 [[T2]], i1 [[T5]], i1 false | |
| ; CHECK-NEXT: ret i1 [[T6]] | |
| ; | |
| %t1 = trunc i32 %arg to i8 | |
| @@ -664,7 +664,7 @@ define zeroext i1 @oneuse_trunc_sext_logical(i32 %arg) { | |
| ; CHECK-NEXT: call void @use32(i32 [[T4]]) | |
| ; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], [[ARG]] | |
| ; CHECK-NEXT: call void @use1(i1 [[T5]]) | |
| -; CHECK-NEXT: [[T6:%.*]] = and i1 [[T2]], [[T5]] | |
| +; CHECK-NEXT: [[T6:%.*]] = select i1 [[T2]], i1 [[T5]], i1 false | |
| ; CHECK-NEXT: ret i1 [[T6]] | |
| ; | |
| %t1 = trunc i32 %arg to i8 | |
| @@ -705,7 +705,7 @@ define i1 @negative_not_arg_logical(i32 %arg, i32 %arg2) { | |
| ; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1 | |
| ; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG2:%.*]], 128 | |
| ; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256 | |
| -; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]] | |
| +; CHECK-NEXT: [[T4:%.*]] = select i1 [[T1]], i1 [[T3]], i1 false | |
| ; CHECK-NEXT: ret i1 [[T4]] | |
| ; | |
| %t1 = icmp sgt i32 %arg, -1 | |
| @@ -738,7 +738,7 @@ define i1 @negative_trunc_not_arg_logical(i32 %arg, i32 %arg2) { | |
| ; CHECK-NEXT: [[T2:%.*]] = icmp sgt i8 [[T1]], -1 | |
| ; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG2:%.*]], 128 | |
| ; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256 | |
| -; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]] | |
| +; CHECK-NEXT: [[T5:%.*]] = select i1 [[T2]], i1 [[T4]], i1 false | |
| ; CHECK-NEXT: ret i1 [[T5]] | |
| ; | |
| %t1 = trunc i32 %arg to i8 | |
| @@ -772,7 +772,7 @@ define i1 @positive_with_mask_not_arg_logical(i32 %arg, i32 %arg2) { | |
| ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 | |
| ; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG2:%.*]], 128 | |
| ; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256 | |
| -; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]] | |
| +; CHECK-NEXT: [[T5:%.*]] = select i1 [[T2]], i1 [[T4]], i1 false | |
| ; CHECK-NEXT: ret i1 [[T5]] | |
| ; | |
| %t1 = and i32 %arg, 1140850688 | |
| @@ -1025,7 +1025,7 @@ define i1 @bad_trunc_stc_logical(i32 %arg) { | |
| ; CHECK-NEXT: [[T2:%.*]] = trunc i32 [[ARG]] to i16 | |
| ; CHECK-NEXT: [[T3:%.*]] = add i16 [[T2]], 128 | |
| ; CHECK-NEXT: [[T4:%.*]] = icmp ult i16 [[T3]], 256 | |
| -; CHECK-NEXT: [[T5:%.*]] = and i1 [[T1]], [[T4]] | |
| +; CHECK-NEXT: [[T5:%.*]] = select i1 [[T1]], i1 [[T4]], i1 false | |
| ; CHECK-NEXT: ret i1 [[T5]] | |
| ; | |
| %t1 = icmp sgt i32 %arg, -1 ; checks a bit outside of the i16 | |
| diff --git a/llvm/test/Transforms/InstCombine/umul-sign-check.ll b/llvm/test/Transforms/InstCombine/umul-sign-check.ll | |
| index 8fa659396f2e..352474c1b202 100644 | |
| --- a/llvm/test/Transforms/InstCombine/umul-sign-check.ll | |
| +++ b/llvm/test/Transforms/InstCombine/umul-sign-check.ll | |
| @@ -32,10 +32,11 @@ define i1 @test1(i64 %a, i64 %b, i64* %ptr) { | |
| define i1 @test1_logical(i64 %a, i64 %b, i64* %ptr) { | |
| ; CHECK-LABEL: @test1_logical( | |
| -; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0 | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0 | |
| -; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]] | |
| +; CHECK-NEXT: [[RES:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A:%.*]], i64 [[B:%.*]]) | |
| +; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[RES]], 1 | |
| +; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i64, i1 } [[RES]], 0 | |
| +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[MUL]], 0 | |
| +; CHECK-NEXT: [[OVERFLOW_1:%.*]] = select i1 [[OVERFLOW]], i1 true, i1 [[CMP]] | |
| ; CHECK-NEXT: store i64 [[MUL]], i64* [[PTR:%.*]], align 8 | |
| ; CHECK-NEXT: ret i1 [[OVERFLOW_1]] | |
| ; | |
| @@ -71,10 +72,11 @@ define i1 @test1_or_ops_swapped(i64 %a, i64 %b, i64* %ptr) { | |
| define i1 @test1_or_ops_swapped_logical(i64 %a, i64 %b, i64* %ptr) { | |
| ; CHECK-LABEL: @test1_or_ops_swapped_logical( | |
| -; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0 | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0 | |
| -; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]] | |
| +; CHECK-NEXT: [[RES:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A:%.*]], i64 [[B:%.*]]) | |
| +; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[RES]], 1 | |
| +; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i64, i1 } [[RES]], 0 | |
| +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[MUL]], 0 | |
| +; CHECK-NEXT: [[OVERFLOW_1:%.*]] = select i1 [[CMP]], i1 true, i1 [[OVERFLOW]] | |
| ; CHECK-NEXT: store i64 [[MUL]], i64* [[PTR:%.*]], align 8 | |
| ; CHECK-NEXT: ret i1 [[OVERFLOW_1]] | |
| ; | |
| @@ -112,10 +114,11 @@ define i1 @test2(i64 %a, i64 %b, i64* %ptr) { | |
| define i1 @test2_logical(i64 %a, i64 %b, i64* %ptr) { | |
| ; CHECK-LABEL: @test2_logical( | |
| -; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0 | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0 | |
| -; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]] | |
| +; CHECK-NEXT: [[RES:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A:%.*]], i64 [[B:%.*]]) | |
| +; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[RES]], 1 | |
| +; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i64, i1 } [[RES]], 0 | |
| +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[MUL]], 0 | |
| +; CHECK-NEXT: [[OVERFLOW_1:%.*]] = select i1 [[OVERFLOW]], i1 true, i1 [[CMP]] | |
| ; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]] | |
| ; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8 | |
| ; CHECK-NEXT: ret i1 [[OVERFLOW_1]] | |
| @@ -156,9 +159,9 @@ define i1 @test3_multiple_overflow_users_logical(i64 %a, i64 %b, i64* %ptr) { | |
| ; CHECK-LABEL: @test3_multiple_overflow_users_logical( | |
| ; CHECK-NEXT: [[RES:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A:%.*]], i64 [[B:%.*]]) | |
| ; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[RES]], 1 | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0 | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0 | |
| -; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]] | |
| +; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i64, i1 } [[RES]], 0 | |
| +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[MUL]], 0 | |
| +; CHECK-NEXT: [[OVERFLOW_1:%.*]] = select i1 [[OVERFLOW]], i1 true, i1 [[CMP]] | |
| ; CHECK-NEXT: call void @use(i1 [[OVERFLOW]]) | |
| ; CHECK-NEXT: ret i1 [[OVERFLOW_1]] | |
| ; | |
| @@ -201,7 +204,7 @@ define i1 @test3_multiple_overflow_and_mul_users_logical(i64 %a, i64 %b, i64* %p | |
| ; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[RES]], 1 | |
| ; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i64, i1 } [[RES]], 0 | |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[MUL]], 0 | |
| -; CHECK-NEXT: [[OVERFLOW_1:%.*]] = or i1 [[OVERFLOW]], [[CMP]] | |
| +; CHECK-NEXT: [[OVERFLOW_1:%.*]] = select i1 [[OVERFLOW]], i1 true, i1 [[CMP]] | |
| ; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]] | |
| ; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8 | |
| ; CHECK-NEXT: call void @use(i1 [[OVERFLOW]]) | |
| @@ -246,10 +249,10 @@ define i1 @test3_multiple_res_users(i64 %a, i64 %b, i64* %ptr) { | |
| define i1 @test3_multiple_res_users_logical(i64 %a, i64 %b, i64* %ptr) { | |
| ; CHECK-LABEL: @test3_multiple_res_users_logical( | |
| ; CHECK-NEXT: [[RES:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A:%.*]], i64 [[B:%.*]]) | |
| +; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[RES]], 1 | |
| ; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i64, i1 } [[RES]], 0 | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0 | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0 | |
| -; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]] | |
| +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[MUL]], 0 | |
| +; CHECK-NEXT: [[OVERFLOW_1:%.*]] = select i1 [[OVERFLOW]], i1 true, i1 [[CMP]] | |
| ; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]] | |
| ; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8 | |
| ; CHECK-NEXT: call void @use.2({ i64, i1 } [[RES]]) | |
| @@ -294,10 +297,11 @@ define i1 @test3_multiple_mul_users(i64 %a, i64 %b, i64* %ptr) { | |
| define i1 @test3_multiple_mul_users_logical(i64 %a, i64 %b, i64* %ptr) { | |
| ; CHECK-LABEL: @test3_multiple_mul_users_logical( | |
| -; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0 | |
| -; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0 | |
| -; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]] | |
| +; CHECK-NEXT: [[RES:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A:%.*]], i64 [[B:%.*]]) | |
| +; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[RES]], 1 | |
| +; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i64, i1 } [[RES]], 0 | |
| +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[MUL]], 0 | |
| +; CHECK-NEXT: [[OVERFLOW_1:%.*]] = select i1 [[OVERFLOW]], i1 true, i1 [[CMP]] | |
| ; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]] | |
| ; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8 | |
| ; CHECK-NEXT: call void @use.3(i64 [[MUL]]) | |
| @@ -344,7 +348,7 @@ define i1 @test4_no_icmp_ne_logical(i64 %a, i64 %b, i64* %ptr) { | |
| ; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[RES]], 1 | |
| ; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i64, i1 } [[RES]], 0 | |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 [[MUL]], 0 | |
| -; CHECK-NEXT: [[OVERFLOW_1:%.*]] = or i1 [[OVERFLOW]], [[CMP]] | |
| +; CHECK-NEXT: [[OVERFLOW_1:%.*]] = select i1 [[OVERFLOW]], i1 true, i1 [[CMP]] | |
| ; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]] | |
| ; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8 | |
| ; CHECK-NEXT: ret i1 [[OVERFLOW_1]] | |
| diff --git a/llvm/test/Transforms/InstCombine/usub-overflow-known-by-implied-cond.ll b/llvm/test/Transforms/InstCombine/usub-overflow-known-by-implied-cond.ll | |
| index abe6e682761f..40d65b4f8c21 100644 | |
| --- a/llvm/test/Transforms/InstCombine/usub-overflow-known-by-implied-cond.ll | |
| +++ b/llvm/test/Transforms/InstCombine/usub-overflow-known-by-implied-cond.ll | |
| @@ -264,7 +264,7 @@ bb3: | |
| define i32 @test9_logical(i32 %a, i32 %b, i1 %cond2) { | |
| ; CHECK-LABEL: @test9_logical( | |
| ; CHECK-NEXT: [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[COND]], [[COND2:%.*]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[COND]], i1 [[COND2:%.*]], i1 false | |
| ; CHECK-NEXT: br i1 [[AND]], label [[BB1:%.*]], label [[BB3:%.*]] | |
| ; CHECK: bb1: | |
| ; CHECK-NEXT: br i1 false, label [[BB3]], label [[BB2:%.*]] | |
| @@ -326,7 +326,7 @@ bb3: | |
| define i32 @test10_logical(i32 %a, i32 %b, i1 %cond2) { | |
| ; CHECK-LABEL: @test10_logical( | |
| ; CHECK-NEXT: [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[COND]], [[COND2:%.*]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[COND]], i1 [[COND2:%.*]], i1 false | |
| ; CHECK-NEXT: br i1 [[AND]], label [[BB3:%.*]], label [[BB1:%.*]] | |
| ; CHECK: bb1: | |
| ; CHECK-NEXT: [[SUB1:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[A]], i32 [[B]]) | |
| @@ -390,7 +390,7 @@ bb3: | |
| define i32 @test11_logical(i32 %a, i32 %b, i1 %cond2) { | |
| ; CHECK-LABEL: @test11_logical( | |
| ; CHECK-NEXT: [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[OR:%.*]] = or i1 [[COND]], [[COND2:%.*]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[COND]], i1 true, i1 [[COND2:%.*]] | |
| ; CHECK-NEXT: br i1 [[OR]], label [[BB1:%.*]], label [[BB3:%.*]] | |
| ; CHECK: bb1: | |
| ; CHECK-NEXT: [[SUB1:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[A]], i32 [[B]]) | |
| @@ -454,7 +454,7 @@ bb3: | |
| define i32 @test12_logical(i32 %a, i32 %b, i1 %cond2) { | |
| ; CHECK-LABEL: @test12_logical( | |
| ; CHECK-NEXT: [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[OR:%.*]] = or i1 [[COND]], [[COND2:%.*]] | |
| +; CHECK-NEXT: [[OR:%.*]] = select i1 [[COND]], i1 true, i1 [[COND2:%.*]] | |
| ; CHECK-NEXT: br i1 [[OR]], label [[BB3:%.*]], label [[BB1:%.*]] | |
| ; CHECK: bb1: | |
| ; CHECK-NEXT: [[SUB1:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[A]], i32 [[B]]) | |
| diff --git a/llvm/test/Transforms/InstCombine/widenable-conditions.ll b/llvm/test/Transforms/InstCombine/widenable-conditions.ll | |
| index 31aa98ff998b..54e4f95a4ee1 100644 | |
| --- a/llvm/test/Transforms/InstCombine/widenable-conditions.ll | |
| +++ b/llvm/test/Transforms/InstCombine/widenable-conditions.ll | |
| @@ -20,8 +20,8 @@ define i1 @test1(i1 %a, i1 %b) { | |
| define i1 @test1_logical(i1 %a, i1 %b) { | |
| ; CHECK-LABEL: @test1_logical( | |
| ; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition() | |
| -; CHECK-NEXT: [[LHS:%.*]] = and i1 [[WC]], [[B:%.*]] | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[LHS]], [[A:%.*]] | |
| +; CHECK-NEXT: [[LHS:%.*]] = select i1 [[B:%.*]], i1 [[WC]], i1 false | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[LHS]], i1 [[A:%.*]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %wc = call i1 @llvm.experimental.widenable.condition() | |
| @@ -49,9 +49,9 @@ define i1 @test1b(i1 %a, i1 %b) { | |
| define i1 @test1b_logical(i1 %a, i1 %b) { | |
| ; CHECK-LABEL: @test1b_logical( | |
| ; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition() | |
| -; CHECK-NEXT: [[LHS:%.*]] = and i1 [[WC]], [[B:%.*]] | |
| +; CHECK-NEXT: [[LHS:%.*]] = select i1 [[B:%.*]], i1 [[WC]], i1 false | |
| ; CHECK-NEXT: call void @use(i1 [[LHS]]) | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[LHS]], [[A:%.*]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[LHS]], i1 [[A:%.*]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %wc = call i1 @llvm.experimental.widenable.condition() | |
| @@ -87,8 +87,8 @@ define i1 @test1c_logical(i1 %a, i1 %b) { | |
| ; CHECK-NEXT: call void @use(i1 [[B:%.*]]) | |
| ; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition() | |
| ; CHECK-NEXT: call void @use(i1 [[WC]]) | |
| -; CHECK-NEXT: [[LHS:%.*]] = and i1 [[WC]], [[B]] | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[LHS]], [[A]] | |
| +; CHECK-NEXT: [[LHS:%.*]] = select i1 [[B]], i1 [[WC]], i1 false | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[LHS]], i1 [[A]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| call void @use(i1 %a) | |
| @@ -116,8 +116,8 @@ define i1 @test2(i1 %a, i1 %b) { | |
| define i1 @test2_logical(i1 %a, i1 %b) { | |
| ; CHECK-LABEL: @test2_logical( | |
| ; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition() | |
| -; CHECK-NEXT: [[LHS:%.*]] = and i1 [[WC]], [[B:%.*]] | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[LHS]], [[A:%.*]] | |
| +; CHECK-NEXT: [[LHS:%.*]] = select i1 [[WC]], i1 [[B:%.*]], i1 false | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[LHS]], i1 [[A:%.*]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %wc = call i1 @llvm.experimental.widenable.condition() | |
| @@ -146,9 +146,9 @@ define i1 @test3(i1 %a, i1 %b, i1 %c) { | |
| define i1 @test3_logical(i1 %a, i1 %b, i1 %c) { | |
| ; CHECK-LABEL: @test3_logical( | |
| ; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition() | |
| -; CHECK-NEXT: [[LHS:%.*]] = and i1 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[RHS:%.*]] = and i1 [[WC]], [[C:%.*]] | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[LHS]], [[RHS]] | |
| +; CHECK-NEXT: [[LHS:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false | |
| +; CHECK-NEXT: [[TMP1:%.*]] = and i1 [[LHS]], [[C:%.*]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i1 [[WC]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %wc = call i1 @llvm.experimental.widenable.condition() | |
| @@ -176,9 +176,9 @@ define i1 @test4(i1 %a, i1 %b, i1 %c) { | |
| define i1 @test4_logical(i1 %a, i1 %b, i1 %c) { | |
| ; CHECK-LABEL: @test4_logical( | |
| ; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition() | |
| -; CHECK-NEXT: [[LHS:%.*]] = and i1 [[A:%.*]], [[B:%.*]] | |
| -; CHECK-NEXT: [[RHS:%.*]] = and i1 [[WC]], [[C:%.*]] | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[LHS]], [[RHS]] | |
| +; CHECK-NEXT: [[LHS:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false | |
| +; CHECK-NEXT: [[TMP1:%.*]] = and i1 [[LHS]], [[WC]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i1 [[C:%.*]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %wc = call i1 @llvm.experimental.widenable.condition() | |
| @@ -225,7 +225,7 @@ define i1 @test6_logical(i1 %a, i1 %b) { | |
| ; CHECK-LABEL: @test6_logical( | |
| ; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition() | |
| ; CHECK-NEXT: [[WC2:%.*]] = call i1 @llvm.experimental.widenable.condition() | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[WC]], [[WC2]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[WC]], i1 [[WC2]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %wc = call i1 @llvm.experimental.widenable.condition() | |
| @@ -254,7 +254,7 @@ define i1 @test7_logical(i1 %a, i1 %b) { | |
| ; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition() | |
| ; CHECK-NEXT: call void @use(i1 [[WC]]) | |
| ; CHECK-NEXT: [[WC2:%.*]] = call i1 @llvm.experimental.widenable.condition() | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[WC]], [[WC2]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[WC]], i1 [[WC2]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %wc = call i1 @llvm.experimental.widenable.condition() | |
| @@ -284,7 +284,7 @@ define i1 @test8_logical(i1 %a, i1 %b) { | |
| ; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition() | |
| ; CHECK-NEXT: [[WC2:%.*]] = call i1 @llvm.experimental.widenable.condition() | |
| ; CHECK-NEXT: call void @use(i1 [[WC2]]) | |
| -; CHECK-NEXT: [[AND:%.*]] = and i1 [[WC]], [[WC2]] | |
| +; CHECK-NEXT: [[AND:%.*]] = select i1 [[WC]], i1 [[WC2]], i1 false | |
| ; CHECK-NEXT: ret i1 [[AND]] | |
| ; | |
| %wc = call i1 @llvm.experimental.widenable.condition() | |
| diff --git a/llvm/test/Transforms/InstCombine/zext-or-icmp.ll b/llvm/test/Transforms/InstCombine/zext-or-icmp.ll | |
| index a77aa7ac7ebd..03a38ca321bf 100644 | |
| --- a/llvm/test/Transforms/InstCombine/zext-or-icmp.ll | |
| +++ b/llvm/test/Transforms/InstCombine/zext-or-icmp.ll | |
| @@ -23,11 +23,11 @@ define i8 @zext_or_icmp_icmp(i8 %a, i8 %b) { | |
| define i8 @zext_or_icmp_icmp_logical(i8 %a, i8 %b) { | |
| ; CHECK-LABEL: @zext_or_icmp_icmp_logical( | |
| ; CHECK-NEXT: [[MASK:%.*]] = and i8 [[A:%.*]], 1 | |
| +; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp eq i8 [[MASK]], 0 | |
| ; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp eq i8 [[B:%.*]], 0 | |
| -; CHECK-NEXT: [[TOBOOL22:%.*]] = zext i1 [[TOBOOL2]] to i8 | |
| -; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[MASK]], 1 | |
| -; CHECK-NEXT: [[ZEXT3:%.*]] = or i8 [[TMP1]], [[TOBOOL22]] | |
| -; CHECK-NEXT: ret i8 [[ZEXT3]] | |
| +; CHECK-NEXT: [[BOTHCOND:%.*]] = select i1 [[TOBOOL1]], i1 true, i1 [[TOBOOL2]] | |
| +; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[BOTHCOND]] to i8 | |
| +; CHECK-NEXT: ret i8 [[ZEXT]] | |
| ; | |
| %mask = and i8 %a, 1 | |
| %toBool1 = icmp eq i8 %mask, 0 | |
| @@ -86,7 +86,7 @@ define i32 @dont_widen_undef_logical() { | |
| ; CHECK-NEXT: [[M_1_OP:%.*]] = lshr i32 1, [[M_011]] | |
| ; CHECK-NEXT: [[SEXT_MASK:%.*]] = and i32 [[M_1_OP]], 65535 | |
| ; CHECK-NEXT: [[CMP115:%.*]] = icmp ne i32 [[SEXT_MASK]], 0 | |
| -; CHECK-NEXT: [[CMP1:%.*]] = or i1 [[CMP_I]], [[CMP115]] | |
| +; CHECK-NEXT: [[CMP1:%.*]] = select i1 [[CMP_I]], i1 true, i1 [[CMP115]] | |
| ; CHECK-NEXT: [[CONV2:%.*]] = zext i1 [[CMP1]] to i32 | |
| ; CHECK-NEXT: ret i32 [[CONV2]] | |
| ; |
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