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Changes between "next" & "v3" - including all changes on instructions
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gistfile1.diff
diff -Nurp capstone-next.git/include/arm.h capstone-v3.git/include/arm.h
--- capstone-next.git/include/arm.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/arm.h 2014-09-24 22:57:32.000000000 +0800
@@ -50,6 +50,53 @@ typedef enum arm_cc {
ARM_CC_AL // Always (unconditional) Always (unconditional)
} arm_cc;
+typedef enum arm_sysreg {
+ //> Special registers for MSR
+ ARM_SYSREG_INVALID = 0,
+
+ // SPSR* registers can be OR combined
+ ARM_SYSREG_SPSR_C = 1,
+ ARM_SYSREG_SPSR_X = 2,
+ ARM_SYSREG_SPSR_S = 4,
+ ARM_SYSREG_SPSR_F = 8,
+
+ // CPSR* registers can be OR combined
+ ARM_SYSREG_CPSR_C = 16,
+ ARM_SYSREG_CPSR_X = 32,
+ ARM_SYSREG_CPSR_S = 64,
+ ARM_SYSREG_CPSR_F = 128,
+
+ // independent registers
+ ARM_SYSREG_APSR = 256,
+ ARM_SYSREG_APSR_G,
+ ARM_SYSREG_APSR_NZCVQ,
+ ARM_SYSREG_APSR_NZCVQG,
+
+ ARM_SYSREG_IAPSR,
+ ARM_SYSREG_IAPSR_G,
+ ARM_SYSREG_IAPSR_NZCVQG,
+
+ ARM_SYSREG_EAPSR,
+ ARM_SYSREG_EAPSR_G,
+ ARM_SYSREG_EAPSR_NZCVQG,
+
+ ARM_SYSREG_XPSR,
+ ARM_SYSREG_XPSR_G,
+ ARM_SYSREG_XPSR_NZCVQG,
+
+ ARM_SYSREG_IPSR,
+ ARM_SYSREG_EPSR,
+ ARM_SYSREG_IEPSR,
+
+ ARM_SYSREG_MSP,
+ ARM_SYSREG_PSP,
+ ARM_SYSREG_PRIMASK,
+ ARM_SYSREG_BASEPRI,
+ ARM_SYSREG_BASEPRI_MAX,
+ ARM_SYSREG_FAULTMASK,
+ ARM_SYSREG_CONTROL,
+} arm_sysreg;
+
//> Operand type for instruction's operands
typedef enum arm_op_type {
ARM_OP_INVALID = 0, // Uninitialized.
@@ -59,8 +106,88 @@ typedef enum arm_op_type {
ARM_OP_IMM, // Immediate operand.
ARM_OP_FP, // Floating-Point immediate operand.
ARM_OP_MEM, // Memory operand
+ ARM_OP_SETEND, // operand for SETEND instruction
+ ARM_OP_SYSREG, // MSR/MSR special register operand
} arm_op_type;
+//> Operand type for SETEND instruction
+typedef enum arm_setend_type {
+ ARM_SETEND_INVALID = 0, // Uninitialized.
+ ARM_SETEND_BE, // BE operand.
+ ARM_SETEND_LE, // LE operand
+} arm_setend_type;
+
+typedef enum arm_cpsmode_type {
+ ARM_CPSMODE_INVALID = 0,
+ ARM_CPSMODE_IE = 2,
+ ARM_CPSMODE_ID = 3
+} arm_cpsmode_type;
+
+//> Operand type for SETEND instruction
+typedef enum arm_cpsflag_type {
+ ARM_CPSFLAG_INVALID = 0,
+ ARM_CPSFLAG_F = 1,
+ ARM_CPSFLAG_I = 2,
+ ARM_CPSFLAG_A = 4,
+ ARM_CPSFLAG_NONE = 16, // no flag
+} arm_cpsflag_type;
+
+//> Data type for elements of vector instructions.
+typedef enum arm_vectordata_type {
+ ARM_VECTORDATA_INVALID = 0,
+
+ // Integer type
+ ARM_VECTORDATA_I8,
+ ARM_VECTORDATA_I16,
+ ARM_VECTORDATA_I32,
+ ARM_VECTORDATA_I64,
+
+ // Signed integer type
+ ARM_VECTORDATA_S8,
+ ARM_VECTORDATA_S16,
+ ARM_VECTORDATA_S32,
+ ARM_VECTORDATA_S64,
+
+ // Unsigned integer type
+ ARM_VECTORDATA_U8,
+ ARM_VECTORDATA_U16,
+ ARM_VECTORDATA_U32,
+ ARM_VECTORDATA_U64,
+
+ // Data type for VMUL/VMULL
+ ARM_VECTORDATA_P8,
+
+ // Floating type
+ ARM_VECTORDATA_F32,
+ ARM_VECTORDATA_F64,
+
+ // Convert float <-> float
+ ARM_VECTORDATA_F16F64, // f16.f64
+ ARM_VECTORDATA_F64F16, // f64.f16
+ ARM_VECTORDATA_F32F16, // f32.f16
+ ARM_VECTORDATA_F16F32, // f32.f16
+ ARM_VECTORDATA_F64F32, // f64.f32
+ ARM_VECTORDATA_F32F64, // f32.f64
+
+ // Convert integer <-> float
+ ARM_VECTORDATA_S32F32, // s32.f32
+ ARM_VECTORDATA_U32F32, // u32.f32
+ ARM_VECTORDATA_F32S32, // f32.s32
+ ARM_VECTORDATA_F32U32, // f32.u32
+ ARM_VECTORDATA_F64S16, // f64.s16
+ ARM_VECTORDATA_F32S16, // f32.s16
+ ARM_VECTORDATA_F64S32, // f64.s32
+ ARM_VECTORDATA_S16F64, // s16.f64
+ ARM_VECTORDATA_S16F32, // s16.f64
+ ARM_VECTORDATA_S32F64, // s32.f64
+ ARM_VECTORDATA_U16F64, // u16.f64
+ ARM_VECTORDATA_U16F32, // u16.f32
+ ARM_VECTORDATA_U32F64, // u32.f64
+ ARM_VECTORDATA_F64U16, // f64.u16
+ ARM_VECTORDATA_F32U16, // f32.u16
+ ARM_VECTORDATA_F64U32, // f64.u32
+} arm_vectordata_type;
+
// Instruction's operand referring to memory
// This is associated with ARM_OP_MEM operand type above
typedef struct arm_op_mem {
@@ -72,21 +199,28 @@ typedef struct arm_op_mem {
// Instruction operand
typedef struct cs_arm_op {
+ int vector_index; // Vector Index for some vector operands (or -1 if irrelevant)
struct {
arm_shifter type;
unsigned int value;
} shift;
arm_op_type type; // operand type
union {
- unsigned int reg; // register value for REG operand
+ unsigned int reg; // register value for REG/SYSREG operand
int32_t imm; // immediate value for C-IMM, P-IMM or IMM operand
double fp; // floating point value for FP operand
arm_op_mem mem; // base/index/scale/disp value for MEM operand
+ arm_setend_type setend; // SETEND instruction's operand type
};
} cs_arm_op;
// Instruction structure
typedef struct cs_arm {
+ bool usermode; // User-mode registers to be loaded (for LDM/STM instructions)
+ int vector_size; // Scalar size for vector instructions
+ arm_vectordata_type vector_data; // Data type for elements of vector instructions
+ arm_cpsmode_type cps_mode; // CPS mode for CPS instruction
+ arm_cpsflag_type cps_flag; // CPS mode for CPS instruction
arm_cc cc; // conditional code for this insn
bool update_flags; // does this insn update flags?
bool writeback; // does this insn write-back?
@@ -458,6 +592,7 @@ typedef enum arm_insn {
ARM_INS_UADD8,
ARM_INS_UASX,
ARM_INS_UBFX,
+ ARM_INS_UDF,
ARM_INS_UDIV,
ARM_INS_UHADD16,
ARM_INS_UHADD8,
@@ -655,6 +790,16 @@ typedef enum arm_insn {
ARM_INS_POP,
ARM_INS_PUSH,
+ // special instructions
+ ARM_INS_NOP,
+ ARM_INS_YIELD,
+ ARM_INS_WFE,
+ ARM_INS_WFI,
+ ARM_INS_SEV,
+ ARM_INS_SEVL,
+ ARM_INS_VPUSH,
+ ARM_INS_VPOP,
+
ARM_INS_MAX, // <-- mark the end of the list of instructions
} arm_insn;
diff -Nurp capstone-next.git/include/arm64.h capstone-v3.git/include/arm64.h
--- capstone-next.git/include/arm64.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/arm64.h 2014-09-24 22:57:32.000000000 +0800
@@ -61,6 +61,175 @@ typedef enum arm64_cc {
// is "always".
} arm64_cc;
+//> System registers
+typedef enum arm64_mrs_reg {
+ //> System registers for MRS
+ ARM64_SYSREG_INVALID = 0,
+ ARM64_SYSREG_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
+ ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
+ ARM64_SYSREG_MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
+ ARM64_SYSREG_OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
+ ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
+ ARM64_SYSREG_PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
+ ARM64_SYSREG_PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
+ ARM64_SYSREG_MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
+ ARM64_SYSREG_CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
+ ARM64_SYSREG_CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
+ ARM64_SYSREG_CTR_EL0 = 0xd801, // 11 011 0000 0000 001
+ ARM64_SYSREG_MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
+ ARM64_SYSREG_REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
+ ARM64_SYSREG_AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
+ ARM64_SYSREG_DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
+ ARM64_SYSREG_ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
+ ARM64_SYSREG_ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
+ ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
+ ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
+ ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
+ ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
+ ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
+ ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
+ ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
+ ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
+ ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
+ ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
+ ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
+ ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
+ ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
+ ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
+ ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
+ ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
+ ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
+ ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
+ ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
+ ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
+ ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
+ ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
+ ARM64_SYSREG_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
+ ARM64_SYSREG_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
+ ARM64_SYSREG_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
+ ARM64_SYSREG_RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
+ ARM64_SYSREG_RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
+ ARM64_SYSREG_RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
+ ARM64_SYSREG_ISR_EL1 = 0xc608, // 11 000 1100 0001 000
+ ARM64_SYSREG_CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
+ ARM64_SYSREG_CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
+
+ // Trace registers
+ ARM64_SYSREG_TRCSTATR = 0x8818, // 10 001 0000 0011 000
+ ARM64_SYSREG_TRCIDR8 = 0x8806, // 10 001 0000 0000 110
+ ARM64_SYSREG_TRCIDR9 = 0x880e, // 10 001 0000 0001 110
+ ARM64_SYSREG_TRCIDR10 = 0x8816, // 10 001 0000 0010 110
+ ARM64_SYSREG_TRCIDR11 = 0x881e, // 10 001 0000 0011 110
+ ARM64_SYSREG_TRCIDR12 = 0x8826, // 10 001 0000 0100 110
+ ARM64_SYSREG_TRCIDR13 = 0x882e, // 10 001 0000 0101 110
+ ARM64_SYSREG_TRCIDR0 = 0x8847, // 10 001 0000 1000 111
+ ARM64_SYSREG_TRCIDR1 = 0x884f, // 10 001 0000 1001 111
+ ARM64_SYSREG_TRCIDR2 = 0x8857, // 10 001 0000 1010 111
+ ARM64_SYSREG_TRCIDR3 = 0x885f, // 10 001 0000 1011 111
+ ARM64_SYSREG_TRCIDR4 = 0x8867, // 10 001 0000 1100 111
+ ARM64_SYSREG_TRCIDR5 = 0x886f, // 10 001 0000 1101 111
+ ARM64_SYSREG_TRCIDR6 = 0x8877, // 10 001 0000 1110 111
+ ARM64_SYSREG_TRCIDR7 = 0x887f, // 10 001 0000 1111 111
+ ARM64_SYSREG_TRCOSLSR = 0x888c, // 10 001 0001 0001 100
+ ARM64_SYSREG_TRCPDSR = 0x88ac, // 10 001 0001 0101 100
+ ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
+ ARM64_SYSREG_TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
+ ARM64_SYSREG_TRCLSR = 0x8bee, // 10 001 0111 1101 110
+ ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
+ ARM64_SYSREG_TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
+ ARM64_SYSREG_TRCDEVID = 0x8b97, // 10 001 0111 0010 111
+ ARM64_SYSREG_TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
+ ARM64_SYSREG_TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
+ ARM64_SYSREG_TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
+ ARM64_SYSREG_TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
+ ARM64_SYSREG_TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
+ ARM64_SYSREG_TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
+ ARM64_SYSREG_TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
+ ARM64_SYSREG_TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
+ ARM64_SYSREG_TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
+ ARM64_SYSREG_TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
+ ARM64_SYSREG_TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
+ ARM64_SYSREG_TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
+ ARM64_SYSREG_TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
+
+ // GICv3 registers
+ ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
+ ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
+ ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
+ ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
+ ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
+ ARM64_SYSREG_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
+ ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
+ ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101
+} arm64_sysreg;
+
+typedef enum arm64_msr_reg {
+ //> System registers for MSR
+ ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
+ ARM64_SYSREG_OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
+ ARM64_SYSREG_PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
+
+ // Trace Registers
+ ARM64_SYSREG_TRCOSLAR = 0x8884, // 10 001 0001 0000 100
+ ARM64_SYSREG_TRCLAR = 0x8be6, // 10 001 0111 1100 110
+
+ // GICv3 registers
+ ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
+ ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
+ ARM64_SYSREG_ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
+ ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
+ ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
+ ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111
+} arm64_msr_reg;
+
+//> System PState Field (MSR instruction)
+typedef enum arm64_pstate {
+ ARM64_PSTATE_INVALID = 0,
+ ARM64_PSTATE_SPSEL = 0x05,
+ ARM64_PSTATE_DAIFSET = 0x1e,
+ ARM64_PSTATE_DAIFCLR = 0x1f
+} arm64_pstate;
+
+//> Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)
+typedef enum arm64_vas {
+ ARM64_VAS_INVALID = 0,
+ ARM64_VAS_8B,
+ ARM64_VAS_16B,
+ ARM64_VAS_4H,
+ ARM64_VAS_8H,
+ ARM64_VAS_2S,
+ ARM64_VAS_4S,
+ ARM64_VAS_1D,
+ ARM64_VAS_2D,
+ ARM64_VAS_1Q,
+} arm64_vas;
+
+//> Vector element size specifier
+typedef enum arm64_vess {
+ ARM64_VESS_INVALID = 0,
+ ARM64_VESS_B,
+ ARM64_VESS_H,
+ ARM64_VESS_S,
+ ARM64_VESS_D,
+} arm64_vess;
+
+//> Memory barrier operands
+typedef enum arm64_barrier_op {
+ ARM64_BARRIER_INVALID = 0,
+ ARM64_BARRIER_OSHLD = 0x1,
+ ARM64_BARRIER_OSHST = 0x2,
+ ARM64_BARRIER_OSH = 0x3,
+ ARM64_BARRIER_NSHLD = 0x5,
+ ARM64_BARRIER_NSHST = 0x6,
+ ARM64_BARRIER_NSH = 0x7,
+ ARM64_BARRIER_ISHLD = 0x9,
+ ARM64_BARRIER_ISHST = 0xa,
+ ARM64_BARRIER_ISH = 0xb,
+ ARM64_BARRIER_LD = 0xd,
+ ARM64_BARRIER_ST = 0xe,
+ ARM64_BARRIER_SY = 0xf
+} arm64_barrier_op;
+
//> Operand type for instruction's operands
typedef enum arm64_op_type {
ARM64_OP_INVALID = 0, // Uninitialized.
@@ -69,8 +238,111 @@ typedef enum arm64_op_type {
ARM64_OP_IMM, // Immediate operand.
ARM64_OP_FP, // Floating-Point immediate operand.
ARM64_OP_MEM, // Memory operand
+ ARM64_OP_REG_MRS, // MRS register operand.
+ ARM64_OP_REG_MSR, // MSR register operand.
+ ARM64_OP_PSTATE, // PState operand.
+ ARM64_OP_SYS, // SYS operand for IC/DC/AT/TLBI instructions.
+ ARM64_OP_PREFETCH, // Prefetch operand (PRFM).
+ ARM64_OP_BARRIER, // Memory barrier operand (ISB/DMB/DSB instructions).
} arm64_op_type;
+//> TLBI operations
+typedef enum arm64_tlbi_op {
+ ARM64_TLBI_INVALID = 0,
+ ARM64_TLBI_VMALLE1IS,
+ ARM64_TLBI_VAE1IS,
+ ARM64_TLBI_ASIDE1IS,
+ ARM64_TLBI_VAAE1IS,
+ ARM64_TLBI_VALE1IS,
+ ARM64_TLBI_VAALE1IS,
+ ARM64_TLBI_ALLE2IS,
+ ARM64_TLBI_VAE2IS,
+ ARM64_TLBI_ALLE1IS,
+ ARM64_TLBI_VALE2IS,
+ ARM64_TLBI_VMALLS12E1IS,
+ ARM64_TLBI_ALLE3IS,
+ ARM64_TLBI_VAE3IS,
+ ARM64_TLBI_VALE3IS,
+ ARM64_TLBI_IPAS2E1IS,
+ ARM64_TLBI_IPAS2LE1IS,
+ ARM64_TLBI_IPAS2E1,
+ ARM64_TLBI_IPAS2LE1,
+ ARM64_TLBI_VMALLE1,
+ ARM64_TLBI_VAE1,
+ ARM64_TLBI_ASIDE1,
+ ARM64_TLBI_VAAE1,
+ ARM64_TLBI_VALE1,
+ ARM64_TLBI_VAALE1,
+ ARM64_TLBI_ALLE2,
+ ARM64_TLBI_VAE2,
+ ARM64_TLBI_ALLE1,
+ ARM64_TLBI_VALE2,
+ ARM64_TLBI_VMALLS12E1,
+ ARM64_TLBI_ALLE3,
+ ARM64_TLBI_VAE3,
+ ARM64_TLBI_VALE3,
+} arm64_tlbi_op;
+
+//> AT operations
+typedef enum arm64_at_op {
+ ARM64_AT_S1E1R,
+ ARM64_AT_S1E1W,
+ ARM64_AT_S1E0R,
+ ARM64_AT_S1E0W,
+ ARM64_AT_S1E2R,
+ ARM64_AT_S1E2W,
+ ARM64_AT_S12E1R,
+ ARM64_AT_S12E1W,
+ ARM64_AT_S12E0R,
+ ARM64_AT_S12E0W,
+ ARM64_AT_S1E3R,
+ ARM64_AT_S1E3W,
+} arm64_at_op;
+
+//> DC operations
+typedef enum arm64_dc_op {
+ ARM64_DC_INVALID = 0,
+ ARM64_DC_ZVA,
+ ARM64_DC_IVAC,
+ ARM64_DC_ISW,
+ ARM64_DC_CVAC,
+ ARM64_DC_CSW,
+ ARM64_DC_CVAU,
+ ARM64_DC_CIVAC,
+ ARM64_DC_CISW,
+} arm64_dc_op;
+
+//> IC operations
+typedef enum arm64_ic_op {
+ ARM64_IC_INVALID = 0,
+ ARM64_IC_IALLUIS,
+ ARM64_IC_IALLU,
+ ARM64_IC_IVAU,
+} arm64_ic_op;
+
+//> Prefetch operations (PRFM)
+typedef enum arm64_prefetch_op {
+ ARM64_PRFM_INVALID = 0,
+ ARM64_PRFM_PLDL1KEEP = 0x00 + 1,
+ ARM64_PRFM_PLDL1STRM = 0x01 + 1,
+ ARM64_PRFM_PLDL2KEEP = 0x02 + 1,
+ ARM64_PRFM_PLDL2STRM = 0x03 + 1,
+ ARM64_PRFM_PLDL3KEEP = 0x04 + 1,
+ ARM64_PRFM_PLDL3STRM = 0x05 + 1,
+ ARM64_PRFM_PLIL1KEEP = 0x08 + 1,
+ ARM64_PRFM_PLIL1STRM = 0x09 + 1,
+ ARM64_PRFM_PLIL2KEEP = 0x0a + 1,
+ ARM64_PRFM_PLIL2STRM = 0x0b + 1,
+ ARM64_PRFM_PLIL3KEEP = 0x0c + 1,
+ ARM64_PRFM_PLIL3STRM = 0x0d + 1,
+ ARM64_PRFM_PSTL1KEEP = 0x10 + 1,
+ ARM64_PRFM_PSTL1STRM = 0x11 + 1,
+ ARM64_PRFM_PSTL2KEEP = 0x12 + 1,
+ ARM64_PRFM_PSTL2STRM = 0x13 + 1,
+ ARM64_PRFM_PSTL3KEEP = 0x14 + 1,
+ ARM64_PRFM_PSTL3STRM = 0x15 + 1,
+} arm64_prefetch_op;
+
// Instruction's operand referring to memory
// This is associated with ARM64_OP_MEM operand type above
typedef struct arm64_op_mem {
@@ -81,6 +353,9 @@ typedef struct arm64_op_mem {
// Instruction operand
typedef struct cs_arm64_op {
+ int vector_index; // Vector Index for some vector operands (or -1 if irrelevant)
+ arm64_vas vas; // Vector Arrangement Specifier
+ arm64_vess vess; // Vector Element Size Specifier
struct {
arm64_shifter type; // shifter type of this operand
unsigned int value; // shifter value of this operand
@@ -92,6 +367,10 @@ typedef struct cs_arm64_op {
int32_t imm; // immediate value, or index for C-IMM or IMM operand
double fp; // floating point value for FP operand
arm64_op_mem mem; // base/index/scale/disp value for MEM operand
+ arm64_pstate pstate; // PState field of MSR instruction.
+ unsigned int sys; // IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op)
+ arm64_prefetch_op prefetch; // PRFM operation.
+ arm64_barrier_op barrier; // Memory barrier operation (ISB/DMB/DSB instructions).
};
} cs_arm64_op;
@@ -112,10 +391,12 @@ typedef struct cs_arm64 {
typedef enum arm64_reg {
ARM64_REG_INVALID = 0,
+ ARM64_REG_X29,
+ ARM64_REG_X30,
ARM64_REG_NZCV,
+ ARM64_REG_SP,
ARM64_REG_WSP,
ARM64_REG_WZR,
- ARM64_REG_SP,
ARM64_REG_XZR,
ARM64_REG_B0,
ARM64_REG_B1,
@@ -337,8 +618,39 @@ typedef enum arm64_reg {
ARM64_REG_X26,
ARM64_REG_X27,
ARM64_REG_X28,
- ARM64_REG_X29,
- ARM64_REG_X30,
+
+ ARM64_REG_V0,
+ ARM64_REG_V1,
+ ARM64_REG_V2,
+ ARM64_REG_V3,
+ ARM64_REG_V4,
+ ARM64_REG_V5,
+ ARM64_REG_V6,
+ ARM64_REG_V7,
+ ARM64_REG_V8,
+ ARM64_REG_V9,
+ ARM64_REG_V10,
+ ARM64_REG_V11,
+ ARM64_REG_V12,
+ ARM64_REG_V13,
+ ARM64_REG_V14,
+ ARM64_REG_V15,
+ ARM64_REG_V16,
+ ARM64_REG_V17,
+ ARM64_REG_V18,
+ ARM64_REG_V19,
+ ARM64_REG_V20,
+ ARM64_REG_V21,
+ ARM64_REG_V22,
+ ARM64_REG_V23,
+ ARM64_REG_V24,
+ ARM64_REG_V25,
+ ARM64_REG_V26,
+ ARM64_REG_V27,
+ ARM64_REG_V28,
+ ARM64_REG_V29,
+ ARM64_REG_V30,
+ ARM64_REG_V31,
ARM64_REG_MAX, // <-- mark the end of the list of registers
@@ -356,33 +668,29 @@ typedef enum arm64_insn {
ARM64_INS_ABS,
ARM64_INS_ADC,
- ARM64_INS_ADDHN2,
ARM64_INS_ADDHN,
+ ARM64_INS_ADDHN2,
ARM64_INS_ADDP,
- ARM64_INS_ADDV,
ARM64_INS_ADD,
- ARM64_INS_CMN,
- ARM64_INS_ADRP,
+ ARM64_INS_ADDV,
ARM64_INS_ADR,
+ ARM64_INS_ADRP,
ARM64_INS_AESD,
ARM64_INS_AESE,
ARM64_INS_AESIMC,
ARM64_INS_AESMC,
ARM64_INS_AND,
ARM64_INS_ASR,
- ARM64_INS_AT,
- ARM64_INS_BFI,
+ ARM64_INS_B,
ARM64_INS_BFM,
- ARM64_INS_BFXIL,
ARM64_INS_BIC,
ARM64_INS_BIF,
ARM64_INS_BIT,
- ARM64_INS_BLR,
ARM64_INS_BL,
- ARM64_INS_BRK,
+ ARM64_INS_BLR,
ARM64_INS_BR,
+ ARM64_INS_BRK,
ARM64_INS_BSL,
- ARM64_INS_B,
ARM64_INS_CBNZ,
ARM64_INS_CBZ,
ARM64_INS_CCMN,
@@ -397,9 +705,9 @@ typedef enum arm64_insn {
ARM64_INS_CMHS,
ARM64_INS_CMLE,
ARM64_INS_CMLT,
- ARM64_INS_CMP,
ARM64_INS_CMTST,
ARM64_INS_CNT,
+ ARM64_INS_MOV,
ARM64_INS_CRC32B,
ARM64_INS_CRC32CB,
ARM64_INS_CRC32CH,
@@ -415,7 +723,6 @@ typedef enum arm64_insn {
ARM64_INS_DCPS1,
ARM64_INS_DCPS2,
ARM64_INS_DCPS3,
- ARM64_INS_DC,
ARM64_INS_DMB,
ARM64_INS_DRPS,
ARM64_INS_DSB,
@@ -429,10 +736,10 @@ typedef enum arm64_insn {
ARM64_INS_FABS,
ARM64_INS_FACGE,
ARM64_INS_FACGT,
- ARM64_INS_FADDP,
ARM64_INS_FADD,
- ARM64_INS_FCCMPE,
+ ARM64_INS_FADDP,
ARM64_INS_FCCMP,
+ ARM64_INS_FCCMPE,
ARM64_INS_FCMEQ,
ARM64_INS_FCMGE,
ARM64_INS_FCMGT,
@@ -443,41 +750,41 @@ typedef enum arm64_insn {
ARM64_INS_FCSEL,
ARM64_INS_FCVTAS,
ARM64_INS_FCVTAU,
+ ARM64_INS_FCVT,
ARM64_INS_FCVTL,
ARM64_INS_FCVTL2,
ARM64_INS_FCVTMS,
ARM64_INS_FCVTMU,
- ARM64_INS_FCVTN,
- ARM64_INS_FCVTN2,
ARM64_INS_FCVTNS,
ARM64_INS_FCVTNU,
+ ARM64_INS_FCVTN,
+ ARM64_INS_FCVTN2,
ARM64_INS_FCVTPS,
ARM64_INS_FCVTPU,
ARM64_INS_FCVTXN,
ARM64_INS_FCVTXN2,
ARM64_INS_FCVTZS,
ARM64_INS_FCVTZU,
- ARM64_INS_FCVT,
ARM64_INS_FDIV,
ARM64_INS_FMADD,
+ ARM64_INS_FMAX,
+ ARM64_INS_FMAXNM,
ARM64_INS_FMAXNMP,
ARM64_INS_FMAXNMV,
- ARM64_INS_FMAXNM,
ARM64_INS_FMAXP,
ARM64_INS_FMAXV,
- ARM64_INS_FMAX,
+ ARM64_INS_FMIN,
+ ARM64_INS_FMINNM,
ARM64_INS_FMINNMP,
ARM64_INS_FMINNMV,
- ARM64_INS_FMINNM,
ARM64_INS_FMINP,
ARM64_INS_FMINV,
- ARM64_INS_FMIN,
ARM64_INS_FMLA,
ARM64_INS_FMLS,
ARM64_INS_FMOV,
ARM64_INS_FMSUB,
- ARM64_INS_FMULX,
ARM64_INS_FMUL,
+ ARM64_INS_FMULX,
ARM64_INS_FNEG,
ARM64_INS_FNMADD,
ARM64_INS_FNMSUB,
@@ -499,60 +806,51 @@ typedef enum arm64_insn {
ARM64_INS_HINT,
ARM64_INS_HLT,
ARM64_INS_HVC,
- ARM64_INS_IC,
ARM64_INS_INS,
+
ARM64_INS_ISB,
ARM64_INS_LD1,
ARM64_INS_LD1R,
- ARM64_INS_LD2,
ARM64_INS_LD2R,
- ARM64_INS_LD3,
+ ARM64_INS_LD2,
ARM64_INS_LD3R,
+ ARM64_INS_LD3,
ARM64_INS_LD4,
ARM64_INS_LD4R,
+
ARM64_INS_LDARB,
- ARM64_INS_LDAR,
ARM64_INS_LDARH,
+ ARM64_INS_LDAR,
ARM64_INS_LDAXP,
ARM64_INS_LDAXRB,
- ARM64_INS_LDAXR,
ARM64_INS_LDAXRH,
+ ARM64_INS_LDAXR,
+ ARM64_INS_LDNP,
+ ARM64_INS_LDP,
ARM64_INS_LDPSW,
+ ARM64_INS_LDRB,
+ ARM64_INS_LDR,
+ ARM64_INS_LDRH,
ARM64_INS_LDRSB,
- ARM64_INS_LDURSB,
ARM64_INS_LDRSH,
- ARM64_INS_LDURSH,
ARM64_INS_LDRSW,
- ARM64_INS_LDR,
+ ARM64_INS_LDTRB,
+ ARM64_INS_LDTRH,
ARM64_INS_LDTRSB,
+
ARM64_INS_LDTRSH,
ARM64_INS_LDTRSW,
+ ARM64_INS_LDTR,
+ ARM64_INS_LDURB,
+ ARM64_INS_LDUR,
+ ARM64_INS_LDURH,
+ ARM64_INS_LDURSB,
+ ARM64_INS_LDURSH,
ARM64_INS_LDURSW,
ARM64_INS_LDXP,
ARM64_INS_LDXRB,
- ARM64_INS_LDXR,
ARM64_INS_LDXRH,
- ARM64_INS_LDRH,
- ARM64_INS_LDURH,
- ARM64_INS_STRH,
- ARM64_INS_STURH,
- ARM64_INS_LDTRH,
- ARM64_INS_STTRH,
- ARM64_INS_LDUR,
- ARM64_INS_STR,
- ARM64_INS_STUR,
- ARM64_INS_LDTR,
- ARM64_INS_STTR,
- ARM64_INS_LDRB,
- ARM64_INS_LDURB,
- ARM64_INS_STRB,
- ARM64_INS_STURB,
- ARM64_INS_LDTRB,
- ARM64_INS_STTRB,
- ARM64_INS_LDP,
- ARM64_INS_LDNP,
- ARM64_INS_STNP,
- ARM64_INS_STP,
+ ARM64_INS_LDXR,
ARM64_INS_LSL,
ARM64_INS_LSR,
ARM64_INS_MADD,
@@ -567,7 +865,6 @@ typedef enum arm64_insn {
ARM64_INS_MSUB,
ARM64_INS_MUL,
ARM64_INS_MVNI,
- ARM64_INS_MVN,
ARM64_INS_NEG,
ARM64_INS_NOT,
ARM64_INS_ORN,
@@ -577,12 +874,8 @@ typedef enum arm64_insn {
ARM64_INS_PMUL,
ARM64_INS_PRFM,
ARM64_INS_PRFUM,
- ARM64_INS_SQRSHRUN2,
- ARM64_INS_SQRSHRUN,
- ARM64_INS_SQSHRUN2,
- ARM64_INS_SQSHRUN,
- ARM64_INS_RADDHN2,
ARM64_INS_RADDHN,
+ ARM64_INS_RADDHN2,
ARM64_INS_RBIT,
ARM64_INS_RET,
ARM64_INS_REV16,
@@ -592,25 +885,24 @@ typedef enum arm64_insn {
ARM64_INS_ROR,
ARM64_INS_RSHRN2,
ARM64_INS_RSHRN,
- ARM64_INS_RSUBHN2,
ARM64_INS_RSUBHN,
+ ARM64_INS_RSUBHN2,
ARM64_INS_SABAL2,
ARM64_INS_SABAL,
+
ARM64_INS_SABA,
ARM64_INS_SABDL2,
ARM64_INS_SABDL,
ARM64_INS_SABD,
ARM64_INS_SADALP,
- ARM64_INS_SADDL2,
ARM64_INS_SADDLP,
ARM64_INS_SADDLV,
+ ARM64_INS_SADDL2,
ARM64_INS_SADDL,
ARM64_INS_SADDW2,
ARM64_INS_SADDW,
ARM64_INS_SBC,
- ARM64_INS_SBFIZ,
ARM64_INS_SBFM,
- ARM64_INS_SBFX,
ARM64_INS_SCVTF,
ARM64_INS_SDIV,
ARM64_INS_SHA1C,
@@ -619,8 +911,8 @@ typedef enum arm64_insn {
ARM64_INS_SHA1P,
ARM64_INS_SHA1SU0,
ARM64_INS_SHA1SU1,
- ARM64_INS_SHA256H,
ARM64_INS_SHA256H2,
+ ARM64_INS_SHA256H,
ARM64_INS_SHA256SU0,
ARM64_INS_SHA256SU1,
ARM64_INS_SHADD,
@@ -650,27 +942,31 @@ typedef enum arm64_insn {
ARM64_INS_SMULL,
ARM64_INS_SQABS,
ARM64_INS_SQADD,
- ARM64_INS_SQDMLAL2,
ARM64_INS_SQDMLAL,
- ARM64_INS_SQDMLSL2,
+ ARM64_INS_SQDMLAL2,
ARM64_INS_SQDMLSL,
+ ARM64_INS_SQDMLSL2,
ARM64_INS_SQDMULH,
- ARM64_INS_SQDMULL2,
ARM64_INS_SQDMULL,
+ ARM64_INS_SQDMULL2,
ARM64_INS_SQNEG,
ARM64_INS_SQRDMULH,
ARM64_INS_SQRSHL,
ARM64_INS_SQRSHRN,
ARM64_INS_SQRSHRN2,
+ ARM64_INS_SQRSHRUN,
+ ARM64_INS_SQRSHRUN2,
ARM64_INS_SQSHLU,
ARM64_INS_SQSHL,
ARM64_INS_SQSHRN,
ARM64_INS_SQSHRN2,
+ ARM64_INS_SQSHRUN,
+ ARM64_INS_SQSHRUN2,
ARM64_INS_SQSUB,
- ARM64_INS_SQXTN,
ARM64_INS_SQXTN2,
- ARM64_INS_SQXTUN,
+ ARM64_INS_SQXTN,
ARM64_INS_SQXTUN2,
+ ARM64_INS_SQXTUN,
ARM64_INS_SRHADD,
ARM64_INS_SRI,
ARM64_INS_SRSHL,
@@ -690,34 +986,40 @@ typedef enum arm64_insn {
ARM64_INS_ST3,
ARM64_INS_ST4,
ARM64_INS_STLRB,
- ARM64_INS_STLR,
ARM64_INS_STLRH,
+ ARM64_INS_STLR,
ARM64_INS_STLXP,
ARM64_INS_STLXRB,
- ARM64_INS_STLXR,
ARM64_INS_STLXRH,
+ ARM64_INS_STLXR,
+ ARM64_INS_STNP,
+ ARM64_INS_STP,
+ ARM64_INS_STRB,
+ ARM64_INS_STR,
+ ARM64_INS_STRH,
+ ARM64_INS_STTRB,
+ ARM64_INS_STTRH,
+ ARM64_INS_STTR,
+ ARM64_INS_STURB,
+ ARM64_INS_STUR,
+ ARM64_INS_STURH,
ARM64_INS_STXP,
ARM64_INS_STXRB,
- ARM64_INS_STXR,
ARM64_INS_STXRH,
- ARM64_INS_SUBHN2,
+ ARM64_INS_STXR,
ARM64_INS_SUBHN,
+ ARM64_INS_SUBHN2,
ARM64_INS_SUB,
ARM64_INS_SUQADD,
ARM64_INS_SVC,
- ARM64_INS_SXTB,
- ARM64_INS_SXTH,
- ARM64_INS_SXTW,
ARM64_INS_SYSL,
ARM64_INS_SYS,
ARM64_INS_TBL,
ARM64_INS_TBNZ,
ARM64_INS_TBX,
ARM64_INS_TBZ,
- ARM64_INS_TLBI,
ARM64_INS_TRN1,
ARM64_INS_TRN2,
- ARM64_INS_TST,
ARM64_INS_UABAL2,
ARM64_INS_UABAL,
ARM64_INS_UABA,
@@ -725,15 +1027,13 @@ typedef enum arm64_insn {
ARM64_INS_UABDL,
ARM64_INS_UABD,
ARM64_INS_UADALP,
- ARM64_INS_UADDL2,
ARM64_INS_UADDLP,
ARM64_INS_UADDLV,
+ ARM64_INS_UADDL2,
ARM64_INS_UADDL,
ARM64_INS_UADDW2,
ARM64_INS_UADDW,
- ARM64_INS_UBFIZ,
ARM64_INS_UBFM,
- ARM64_INS_UBFX,
ARM64_INS_UCVTF,
ARM64_INS_UDIV,
ARM64_INS_UHADD,
@@ -762,8 +1062,8 @@ typedef enum arm64_insn {
ARM64_INS_UQSHRN,
ARM64_INS_UQSHRN2,
ARM64_INS_UQSUB,
- ARM64_INS_UQXTN,
ARM64_INS_UQXTN2,
+ ARM64_INS_UQXTN,
ARM64_INS_URECPE,
ARM64_INS_URHADD,
ARM64_INS_URSHL,
@@ -780,12 +1080,10 @@ typedef enum arm64_insn {
ARM64_INS_USUBL,
ARM64_INS_USUBW2,
ARM64_INS_USUBW,
- ARM64_INS_UXTB,
- ARM64_INS_UXTH,
ARM64_INS_UZP1,
ARM64_INS_UZP2,
- ARM64_INS_XTN,
ARM64_INS_XTN2,
+ ARM64_INS_XTN,
ARM64_INS_ZIP1,
ARM64_INS_ZIP2,
@@ -793,7 +1091,6 @@ typedef enum arm64_insn {
ARM64_INS_MNEG,
ARM64_INS_UMNEGL,
ARM64_INS_SMNEGL,
- ARM64_INS_MOV,
ARM64_INS_NOP,
ARM64_INS_YIELD,
ARM64_INS_WFE,
@@ -801,6 +1098,31 @@ typedef enum arm64_insn {
ARM64_INS_SEV,
ARM64_INS_SEVL,
ARM64_INS_NGC,
+ ARM64_INS_SBFIZ,
+ ARM64_INS_UBFIZ,
+ ARM64_INS_SBFX,
+ ARM64_INS_UBFX,
+ ARM64_INS_BFI,
+ ARM64_INS_BFXIL,
+ ARM64_INS_CMN,
+ ARM64_INS_MVN,
+ ARM64_INS_TST,
+ ARM64_INS_CSET,
+ ARM64_INS_CINC,
+ ARM64_INS_CSETM,
+ ARM64_INS_CINV,
+ ARM64_INS_CNEG,
+ ARM64_INS_SXTB,
+ ARM64_INS_SXTH,
+ ARM64_INS_SXTW,
+ ARM64_INS_CMP,
+ ARM64_INS_UXTB,
+ ARM64_INS_UXTH,
+ ARM64_INS_UXTW,
+ ARM64_INS_IC,
+ ARM64_INS_DC,
+ ARM64_INS_AT,
+ ARM64_INS_TLBI,
ARM64_INS_MAX, // <-- mark the end of the list of insn
} arm64_insn;
@@ -812,6 +1134,7 @@ typedef enum arm64_insn_group {
ARM64_GRP_CRYPTO,
ARM64_GRP_FPARMV8,
ARM64_GRP_NEON,
+ ARM64_GRP_CRC,
ARM64_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)
diff -Nurp capstone-next.git/include/capstone.h capstone-v3.git/include/capstone.h
--- capstone-next.git/include/capstone.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/capstone.h 2014-09-24 22:57:32.000000000 +0800
@@ -27,9 +27,18 @@ extern "C" {
#define CAPSTONE_EXPORT
#endif
+#ifdef __GNUC__
+#define CAPSTONE_DEPRECATED __attribute__((deprecated))
+#elif defined(_MSC_VER)
+#define CAPSTONE_DEPRECATED __declspec(deprecated)
+#else
+#pragma message("WARNING: You need to implement CAPSTONE_DEPRECATED for this compiler")
+#define CAPSTONE_DEPRECATED
+#endif
+
// Capstone API version
-#define CS_API_MAJOR 2
-#define CS_API_MINOR 2
+#define CS_API_MAJOR 3
+#define CS_API_MINOR 0
// Macro to create combined version which can be compared to
// result of cs_version() API.
@@ -70,8 +79,12 @@ typedef enum cs_mode {
CS_MODE_32 = 1 << 2, // 32-bit mode
CS_MODE_64 = 1 << 3, // 64-bit mode
CS_MODE_THUMB = 1 << 4, // ARM's Thumb mode, including Thumb-2
+ CS_MODE_MCLASS = 1 << 5, // ARM's Cortex-M series
CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS architecture)
CS_MODE_N64 = 1 << 5, // Nintendo-64 mode (MIPS architecture)
+ CS_MODE_MIPS3 = 1 << 6, // Mips III ISA
+ CS_MODE_MIPS32R6 = 1 << 7, // Mips32r6 ISA
+ CS_MODE_MIPSGP64 = 1 << 8, // General Purpose Registers are 64-bit wide (MIPS arch)
CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc architecture)
CS_MODE_BIG_ENDIAN = 1 << 31 // big endian mode
} cs_mode;
@@ -115,7 +128,7 @@ typedef enum cs_opt_value {
// User-defined callback function for SKIPDATA option
// @code: the input buffer containing code to be disassembled. This is the
-// same buffer passed to cs_disasm_ex().
+// same buffer passed to cs_disasm().
// @code_size: size (in bytes) of the above @code buffer.
// @offset: the position of the currently-examining byte in the input
// buffer @code mentioned above.
@@ -128,14 +141,14 @@ typedef size_t (*cs_skipdata_cb_t)(const
typedef struct cs_opt_skipdata {
// Capstone considers data to skip as special "instructions".
// User can specify the string for this instruction's "mnemonic" here.
- // By default (if @mnemonic is NULL), Capstone use ".db".
+ // By default (if @mnemonic is NULL), Capstone use ".byte".
const char *mnemonic;
// User-defined callback function to be called when Capstone hits data.
// If the returned value from this callback is positive (>0), Capstone
// will skip exactly that number of bytes & continue. Otherwise, if
// the callback returns 0, Capstone stops disassembling and returns
- // immediately from cs_disasm_ex()
+ // immediately from cs_disasm()
// NOTE: if this callback pointer is NULL, Capstone would skip a number
// of bytes depending on architectures, as following:
// Arm: 2 bytes (Thumb mode) or 4 bytes.
@@ -232,7 +245,7 @@ typedef struct cs_insn {
// These are values returned by cs_errno()
typedef enum cs_err {
CS_ERR_OK = 0, // No error: everything was fine
- CS_ERR_MEM, // Out-Of-Memory error: cs_open(), cs_disasm_ex()
+ CS_ERR_MEM, // Out-Of-Memory error: cs_open(), cs_disasm()
CS_ERR_ARCH, // Unsupported architecture: cs_open()
CS_ERR_HANDLE, // Invalid handle: cs_op_count(), cs_op_index()
CS_ERR_CSH, // Invalid csh argument: cs_close(), cs_errno(), cs_option()
@@ -376,23 +389,33 @@ const char *cs_strerror(cs_err code);
On failure, call cs_errno() for error code.
*/
CAPSTONE_EXPORT
-size_t cs_disasm_ex(csh handle,
+size_t cs_disasm(csh handle,
const uint8_t *code, size_t code_size,
uint64_t address,
size_t count,
cs_insn **insn);
+/* Deprecated function - to be retired in the next version!
+ Use cs_disasm() instead of cs_disasm_ex()
+*/
+CAPSTONE_EXPORT
+CAPSTONE_DEPRECATED
+size_t cs_disasm_ex(csh handle,
+ const uint8_t *code, size_t code_size,
+ uint64_t address,
+ size_t count,
+ cs_insn **insn);
/*
- Free memory allocated in @insn by cs_disasm_ex()
+ Free memory allocated in @insn by cs_disasm()
- @insn: pointer returned by @insn argument in cs_disasm_ex()
- @count: number of cs_insn structures returned by cs_disasm_ex()
+ @insn: pointer returned by @insn argument in cs_disasm()
+ @count: number of cs_insn structures returned by cs_disasm()
*/
CAPSTONE_EXPORT
void cs_free(cs_insn *insn, size_t count);
/*
- Return friendly name of regiser in a string
+ Return friendly name of regiser in a string.
Find the instruction id from header file of corresponding architecture (arm.h for ARM,
x86.h for X86, ...)
@@ -400,21 +423,21 @@ void cs_free(cs_insn *insn, size_t count
store register name.
@handle: handle returned by cs_open()
- @reg: register id
+ @reg_id: register id
@return: string name of the register, or NULL if @reg_id is invalid.
*/
CAPSTONE_EXPORT
const char *cs_reg_name(csh handle, unsigned int reg_id);
/*
- Return friendly name of an instruction in a string
+ Return friendly name of an instruction in a string.
Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
store instruction name.
@handle: handle returned by cs_open()
- @insn: instruction id
+ @insn_id: instruction id
@return: string name of the instruction, or NULL if @insn_id is invalid.
*/
@@ -422,6 +445,21 @@ CAPSTONE_EXPORT
const char *cs_insn_name(csh handle, unsigned int insn_id);
/*
+ Return friendly name of a group id (that an instruction can belong to)
+ Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ store group name.
+
+ @handle: handle returned by cs_open()
+ @group_id: group id
+
+ @return: string name of the group, or NULL if @group_id is invalid.
+*/
+CAPSTONE_EXPORT
+const char *cs_group_name(csh handle, unsigned int insn_id);
+
+/*
Check if a disassembled instruction belong to a particular group.
Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
Internally, this simply verifies if @group_id matches any member of insn->groups array.
@@ -432,7 +470,7 @@ const char *cs_insn_name(csh handle, uns
update @groups array.
@handle: handle returned by cs_open()
- @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm()
@group_id: group that you want to check if this instruction belong to.
@return: true if this instruction indeed belongs to aboved group, or false otherwise.
@@ -450,7 +488,7 @@ bool cs_insn_group(csh handle, const cs_
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
update @regs_read array.
- @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm()
@reg_id: register that you want to check if this instruction used it.
@return: true if this instruction indeed implicitly used aboved register, or false otherwise.
@@ -468,7 +506,7 @@ bool cs_reg_read(csh handle, const cs_in
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
update @regs_write array.
- @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm()
@reg_id: register that you want to check if this instruction modified it.
@return: true if this instruction indeed implicitly modified aboved register, or false otherwise.
@@ -483,7 +521,7 @@ bool cs_reg_write(csh handle, const cs_i
NOTE: this API is only valid when detail option is ON (which is OFF by default)
@handle: handle returned by cs_open()
- @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm()
@op_type: Operand type to be found.
@return: number of operands of given type @op_type in instruction @insn,
@@ -500,7 +538,7 @@ int cs_op_count(csh handle, const cs_ins
NOTE: this API is only valid when detail option is ON (which is OFF by default)
@handle: handle returned by cs_open()
- @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm()
@op_type: Operand type to be found.
@position: position of the operand to be found. This must be in the range
[1, cs_op_count(handle, insn, op_type)]
diff -Nurp capstone-next.git/include/mips.h capstone-v3.git/include/mips.h
--- capstone-next.git/include/mips.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/mips.h 2014-09-24 22:57:32.000000000 +0800
@@ -55,7 +55,7 @@ typedef struct cs_mips {
//> MIPS registers
typedef enum mips_reg {
MIPS_REG_INVALID = 0,
- // General purpose registers
+ //> General purpose registers
MIPS_REG_0,
MIPS_REG_1,
MIPS_REG_2,
@@ -89,7 +89,7 @@ typedef enum mips_reg {
MIPS_REG_30,
MIPS_REG_31,
- // DSP registers
+ //> DSP registers
MIPS_REG_DSPCCOND,
MIPS_REG_DSPCARRY,
MIPS_REG_DSPEFI,
@@ -102,13 +102,23 @@ typedef enum mips_reg {
MIPS_REG_DSPPOS,
MIPS_REG_DSPSCOUNT,
- // ACC registers
+ //> ACC registers
MIPS_REG_AC0,
MIPS_REG_AC1,
MIPS_REG_AC2,
MIPS_REG_AC3,
- // FPU registers
+ //> COP registers
+ MIPS_REG_CC0,
+ MIPS_REG_CC1,
+ MIPS_REG_CC2,
+ MIPS_REG_CC3,
+ MIPS_REG_CC4,
+ MIPS_REG_CC5,
+ MIPS_REG_CC6,
+ MIPS_REG_CC7,
+
+ //> FPU registers
MIPS_REG_F0,
MIPS_REG_F1,
MIPS_REG_F2,
@@ -151,7 +161,7 @@ typedef enum mips_reg {
MIPS_REG_FCC6,
MIPS_REG_FCC7,
- // AFPR128
+ //> AFPR128
MIPS_REG_W0,
MIPS_REG_W1,
MIPS_REG_W2,
@@ -189,6 +199,14 @@ typedef enum mips_reg {
MIPS_REG_LO,
MIPS_REG_PC,
+ MIPS_REG_P0,
+ MIPS_REG_P1,
+ MIPS_REG_P2,
+
+ MIPS_REG_MPL0,
+ MIPS_REG_MPL1,
+ MIPS_REG_MPL2,
+
MIPS_REG_MAX, // <-- mark the end of the list or registers
// alias registers
@@ -242,6 +260,7 @@ typedef enum mips_insn {
MIPS_INS_ABSQ_S,
MIPS_INS_ADD,
+ MIPS_INS_ADDIUPC,
MIPS_INS_ADDQH,
MIPS_INS_ADDQH_R,
MIPS_INS_ADDQ,
@@ -260,40 +279,97 @@ typedef enum mips_insn {
MIPS_INS_ADD_A,
MIPS_INS_ADDI,
MIPS_INS_ADDIU,
+ MIPS_INS_ALIGN,
+ MIPS_INS_ALUIPC,
MIPS_INS_AND,
MIPS_INS_ANDI,
MIPS_INS_APPEND,
MIPS_INS_ASUB_S,
MIPS_INS_ASUB_U,
+ MIPS_INS_AUI,
+ MIPS_INS_AUIPC,
MIPS_INS_AVER_S,
MIPS_INS_AVER_U,
MIPS_INS_AVE_S,
MIPS_INS_AVE_U,
+ MIPS_INS_BADDU,
+ MIPS_INS_BAL,
+ MIPS_INS_BALC,
MIPS_INS_BALIGN,
+ MIPS_INS_BC,
+ MIPS_INS_BC0F,
+ MIPS_INS_BC0FL,
+ MIPS_INS_BC0T,
+ MIPS_INS_BC0TL,
+ MIPS_INS_BC1EQZ,
MIPS_INS_BC1F,
+ MIPS_INS_BC1FL,
+ MIPS_INS_BC1NEZ,
MIPS_INS_BC1T,
+ MIPS_INS_BC1TL,
+ MIPS_INS_BC2EQZ,
+ MIPS_INS_BC2F,
+ MIPS_INS_BC2FL,
+ MIPS_INS_BC2NEZ,
+ MIPS_INS_BC2T,
+ MIPS_INS_BC2TL,
+ MIPS_INS_BC3F,
+ MIPS_INS_BC3FL,
+ MIPS_INS_BC3T,
+ MIPS_INS_BC3TL,
MIPS_INS_BCLRI,
MIPS_INS_BCLR,
MIPS_INS_BEQ,
+ MIPS_INS_BEQC,
+ MIPS_INS_BEQL,
+ MIPS_INS_BEQZALC,
+ MIPS_INS_BEQZC,
+ MIPS_INS_BGEC,
+ MIPS_INS_BGEUC,
MIPS_INS_BGEZ,
MIPS_INS_BGEZAL,
+ MIPS_INS_BGEZALC,
+ MIPS_INS_BGEZALL,
+ MIPS_INS_BGEZALS,
+ MIPS_INS_BGEZC,
+ MIPS_INS_BGEZL,
MIPS_INS_BGTZ,
+ MIPS_INS_BGTZALC,
+ MIPS_INS_BGTZC,
+ MIPS_INS_BGTZL,
MIPS_INS_BINSLI,
MIPS_INS_BINSL,
MIPS_INS_BINSRI,
MIPS_INS_BINSR,
MIPS_INS_BITREV,
+ MIPS_INS_BITSWAP,
MIPS_INS_BLEZ,
+ MIPS_INS_BLEZALC,
+ MIPS_INS_BLEZC,
+ MIPS_INS_BLEZL,
+ MIPS_INS_BLTC,
+ MIPS_INS_BLTUC,
MIPS_INS_BLTZ,
MIPS_INS_BLTZAL,
+ MIPS_INS_BLTZALC,
+ MIPS_INS_BLTZALL,
+ MIPS_INS_BLTZALS,
+ MIPS_INS_BLTZC,
+ MIPS_INS_BLTZL,
MIPS_INS_BMNZI,
MIPS_INS_BMNZ,
MIPS_INS_BMZI,
MIPS_INS_BMZ,
MIPS_INS_BNE,
+ MIPS_INS_BNEC,
MIPS_INS_BNEGI,
MIPS_INS_BNEG,
+ MIPS_INS_BNEL,
+ MIPS_INS_BNEZALC,
+ MIPS_INS_BNEZC,
+ MIPS_INS_BNVC,
MIPS_INS_BNZ,
+ MIPS_INS_BOVC,
MIPS_INS_BPOSGE32,
MIPS_INS_BREAK,
MIPS_INS_BSELI,
@@ -306,11 +382,15 @@ typedef enum mips_insn {
MIPS_INS_BNEZ,
MIPS_INS_BTEQZ,
MIPS_INS_BTNEZ,
+ MIPS_INS_CACHE,
MIPS_INS_CEIL,
MIPS_INS_CEQI,
MIPS_INS_CEQ,
MIPS_INS_CFC1,
MIPS_INS_CFCMSA,
+ MIPS_INS_CINS,
+ MIPS_INS_CINS32,
+ MIPS_INS_CLASS,
MIPS_INS_CLEI_S,
MIPS_INS_CLEI_U,
MIPS_INS_CLE_S,
@@ -336,8 +416,15 @@ typedef enum mips_insn {
MIPS_INS_DADDI,
MIPS_INS_DADDIU,
MIPS_INS_DADDU,
+ MIPS_INS_DAHI,
+ MIPS_INS_DALIGN,
+ MIPS_INS_DATI,
+ MIPS_INS_DAUI,
+ MIPS_INS_DBITSWAP,
MIPS_INS_DCLO,
MIPS_INS_DCLZ,
+ MIPS_INS_DDIV,
+ MIPS_INS_DDIVU,
MIPS_INS_DERET,
MIPS_INS_DEXT,
MIPS_INS_DEXTM,
@@ -346,17 +433,25 @@ typedef enum mips_insn {
MIPS_INS_DINS,
MIPS_INS_DINSM,
MIPS_INS_DINSU,
+ MIPS_INS_DIV,
+ MIPS_INS_DIVU,
MIPS_INS_DIV_S,
MIPS_INS_DIV_U,
MIPS_INS_DLSA,
MIPS_INS_DMFC0,
MIPS_INS_DMFC1,
MIPS_INS_DMFC2,
+ MIPS_INS_DMOD,
+ MIPS_INS_DMODU,
MIPS_INS_DMTC0,
MIPS_INS_DMTC1,
MIPS_INS_DMTC2,
+ MIPS_INS_DMUH,
+ MIPS_INS_DMUHU,
+ MIPS_INS_DMUL,
MIPS_INS_DMULT,
MIPS_INS_DMULTU,
+ MIPS_INS_DMULU,
MIPS_INS_DOTP_S,
MIPS_INS_DOTP_U,
MIPS_INS_DPADD_S,
@@ -368,6 +463,7 @@ typedef enum mips_insn {
MIPS_INS_DPAU,
MIPS_INS_DPAX,
MIPS_INS_DPA,
+ MIPS_INS_DPOP,
MIPS_INS_DPSQX_SA,
MIPS_INS_DPSQX_S,
MIPS_INS_DPSQ_SA,
@@ -381,7 +477,6 @@ typedef enum mips_insn {
MIPS_INS_DROTR32,
MIPS_INS_DROTRV,
MIPS_INS_DSBH,
- MIPS_INS_DDIV,
MIPS_INS_DSHD,
MIPS_INS_DSLL,
MIPS_INS_DSLL32,
@@ -392,10 +487,9 @@ typedef enum mips_insn {
MIPS_INS_DSRL,
MIPS_INS_DSRL32,
MIPS_INS_DSRLV,
+ MIPS_INS_DSUB,
MIPS_INS_DSUBU,
- MIPS_INS_DDIVU,
- MIPS_INS_DIV,
- MIPS_INS_DIVU,
+ MIPS_INS_EHB,
MIPS_INS_EI,
MIPS_INS_ERET,
MIPS_INS_EXT,
@@ -411,6 +505,8 @@ typedef enum mips_insn {
MIPS_INS_EXTR_R,
MIPS_INS_EXTR_S,
MIPS_INS_EXTR,
+ MIPS_INS_EXTS,
+ MIPS_INS_EXTS32,
MIPS_INS_ABS,
MIPS_INS_FADD,
MIPS_INS_FCAF,
@@ -485,7 +581,13 @@ typedef enum mips_insn {
MIPS_INS_J,
MIPS_INS_JAL,
MIPS_INS_JALR,
+ MIPS_INS_JALRS,
+ MIPS_INS_JALS,
+ MIPS_INS_JALX,
+ MIPS_INS_JIALC,
+ MIPS_INS_JIC,
MIPS_INS_JR,
+ MIPS_INS_JRADDIUSP,
MIPS_INS_JRC,
MIPS_INS_JALRC,
MIPS_INS_LB,
@@ -494,8 +596,10 @@ typedef enum mips_insn {
MIPS_INS_LD,
MIPS_INS_LDC1,
MIPS_INS_LDC2,
+ MIPS_INS_LDC3,
MIPS_INS_LDI,
MIPS_INS_LDL,
+ MIPS_INS_LDPC,
MIPS_INS_LDR,
MIPS_INS_LDXC1,
MIPS_INS_LH,
@@ -509,22 +613,28 @@ typedef enum mips_insn {
MIPS_INS_LW,
MIPS_INS_LWC1,
MIPS_INS_LWC2,
+ MIPS_INS_LWC3,
MIPS_INS_LWL,
+ MIPS_INS_LWPC,
MIPS_INS_LWR,
+ MIPS_INS_LWUPC,
MIPS_INS_LWU,
MIPS_INS_LWX,
MIPS_INS_LWXC1,
MIPS_INS_LI,
MIPS_INS_MADD,
+ MIPS_INS_MADDF,
MIPS_INS_MADDR_Q,
MIPS_INS_MADDU,
MIPS_INS_MADDV,
MIPS_INS_MADD_Q,
MIPS_INS_MAQ_SA,
MIPS_INS_MAQ_S,
+ MIPS_INS_MAXA,
MIPS_INS_MAXI_S,
MIPS_INS_MAXI_U,
MIPS_INS_MAX_A,
+ MIPS_INS_MAX,
MIPS_INS_MAX_S,
MIPS_INS_MAX_U,
MIPS_INS_MFC0,
@@ -533,12 +643,16 @@ typedef enum mips_insn {
MIPS_INS_MFHC1,
MIPS_INS_MFHI,
MIPS_INS_MFLO,
+ MIPS_INS_MINA,
MIPS_INS_MINI_S,
MIPS_INS_MINI_U,
MIPS_INS_MIN_A,
+ MIPS_INS_MIN,
MIPS_INS_MIN_S,
MIPS_INS_MIN_U,
+ MIPS_INS_MOD,
MIPS_INS_MODSUB,
+ MIPS_INS_MODU,
MIPS_INS_MOD_S,
MIPS_INS_MOD_U,
MIPS_INS_MOVE,
@@ -547,6 +661,7 @@ typedef enum mips_insn {
MIPS_INS_MOVT,
MIPS_INS_MOVZ,
MIPS_INS_MSUB,
+ MIPS_INS_MSUBF,
MIPS_INS_MSUBR_Q,
MIPS_INS_MSUBU,
MIPS_INS_MSUBV,
@@ -558,6 +673,14 @@ typedef enum mips_insn {
MIPS_INS_MTHI,
MIPS_INS_MTHLIP,
MIPS_INS_MTLO,
+ MIPS_INS_MTM0,
+ MIPS_INS_MTM1,
+ MIPS_INS_MTM2,
+ MIPS_INS_MTP0,
+ MIPS_INS_MTP1,
+ MIPS_INS_MTP2,
+ MIPS_INS_MUH,
+ MIPS_INS_MUHU,
MIPS_INS_MULEQ_S,
MIPS_INS_MULEU_S,
MIPS_INS_MULQ_RS,
@@ -567,6 +690,7 @@ typedef enum mips_insn {
MIPS_INS_MULSA,
MIPS_INS_MULT,
MIPS_INS_MULTU,
+ MIPS_INS_MULU,
MIPS_INS_MULV,
MIPS_INS_MUL_Q,
MIPS_INS_MUL_S,
@@ -580,10 +704,12 @@ typedef enum mips_insn {
MIPS_INS_OR,
MIPS_INS_ORI,
MIPS_INS_PACKRL,
+ MIPS_INS_PAUSE,
MIPS_INS_PCKEV,
MIPS_INS_PCKOD,
MIPS_INS_PCNT,
MIPS_INS_PICK,
+ MIPS_INS_POP,
MIPS_INS_PRECEQU,
MIPS_INS_PRECEQ,
MIPS_INS_PRECEU,
@@ -593,12 +719,14 @@ typedef enum mips_insn {
MIPS_INS_PRECR,
MIPS_INS_PRECR_SRA,
MIPS_INS_PRECR_SRA_R,
+ MIPS_INS_PREF,
MIPS_INS_PREPEND,
MIPS_INS_RADDU,
MIPS_INS_RDDSP,
MIPS_INS_RDHWR,
MIPS_INS_REPLV,
MIPS_INS_REPL,
+ MIPS_INS_RINT,
MIPS_INS_ROTR,
MIPS_INS_ROTRV,
MIPS_INS_ROUND,
@@ -608,13 +736,20 @@ typedef enum mips_insn {
MIPS_INS_SC,
MIPS_INS_SCD,
MIPS_INS_SD,
+ MIPS_INS_SDBBP,
MIPS_INS_SDC1,
MIPS_INS_SDC2,
+ MIPS_INS_SDC3,
MIPS_INS_SDL,
MIPS_INS_SDR,
MIPS_INS_SDXC1,
MIPS_INS_SEB,
MIPS_INS_SEH,
+ MIPS_INS_SELEQZ,
+ MIPS_INS_SELNEZ,
+ MIPS_INS_SEL,
+ MIPS_INS_SEQ,
+ MIPS_INS_SEQI,
MIPS_INS_SH,
MIPS_INS_SHF,
MIPS_INS_SHILO,
@@ -638,6 +773,8 @@ typedef enum mips_insn {
MIPS_INS_SLTI,
MIPS_INS_SLTIU,
MIPS_INS_SLTU,
+ MIPS_INS_SNE,
+ MIPS_INS_SNEI,
MIPS_INS_SPLATI,
MIPS_INS_SPLAT,
MIPS_INS_SRA,
@@ -650,6 +787,7 @@ typedef enum mips_insn {
MIPS_INS_SRLRI,
MIPS_INS_SRLR,
MIPS_INS_SRLV,
+ MIPS_INS_SSNOP,
MIPS_INS_ST,
MIPS_INS_SUBQH,
MIPS_INS_SUBQH_R,
@@ -669,6 +807,7 @@ typedef enum mips_insn {
MIPS_INS_SW,
MIPS_INS_SWC1,
MIPS_INS_SWC2,
+ MIPS_INS_SWC3,
MIPS_INS_SWL,
MIPS_INS_SWR,
MIPS_INS_SWXC1,
@@ -680,6 +819,10 @@ typedef enum mips_insn {
MIPS_INS_TGEI,
MIPS_INS_TGEIU,
MIPS_INS_TGEU,
+ MIPS_INS_TLBP,
+ MIPS_INS_TLBR,
+ MIPS_INS_TLBWI,
+ MIPS_INS_TLBWR,
MIPS_INS_TLT,
MIPS_INS_TLTI,
MIPS_INS_TLTIU,
@@ -687,6 +830,9 @@ typedef enum mips_insn {
MIPS_INS_TNE,
MIPS_INS_TNEI,
MIPS_INS_TRUNC,
+ MIPS_INS_V3MULU,
+ MIPS_INS_VMM0,
+ MIPS_INS_VMULU,
MIPS_INS_VSHF,
MIPS_INS_WAIT,
MIPS_INS_WRDSP,
@@ -698,7 +844,11 @@ typedef enum mips_insn {
MIPS_INS_NOP,
MIPS_INS_NEGU,
- MIPS_INS_MAX,
+ //> special instructions
+ MIPS_INS_JALR_HB, // jump and link with Hazard Barrier
+ MIPS_INS_JR_HB, // jump register with Hazard Barrier
+
+ MIPS_INS_MAXIMUM,
} mips_insn;
//> Group of MIPS instructions
@@ -723,6 +873,21 @@ typedef enum mips_insn_group {
MIPS_GRP_NOTFP64BIT,
MIPS_GRP_NOTINMICROMIPS,
MIPS_GRP_NOTNACL,
+ MIPS_GRP_NOTMIPS32R6,
+ MIPS_GRP_NOTMIPS64R6,
+ MIPS_GRP_CNMIPS,
+ MIPS_GRP_MIPS32,
+ MIPS_GRP_MIPS32R6,
+ MIPS_GRP_MIPS64R6,
+ MIPS_GRP_MIPS2,
+ MIPS_GRP_MIPS3,
+ MIPS_GRP_MIPS3_32,
+ MIPS_GRP_MIPS3_32R2,
+ MIPS_GRP_MIPS4_32,
+ MIPS_GRP_MIPS4_32R2,
+ MIPS_GRP_MIPS5_32R2,
+ MIPS_GRP_GP32BIT,
+ MIPS_GRP_GP64BIT,
MIPS_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)
diff -Nurp capstone-next.git/include/ppc.h capstone-v3.git/include/ppc.h
--- capstone-next.git/include/ppc.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/ppc.h 2014-09-24 22:57:32.000000000 +0800
@@ -17,6 +17,7 @@ extern "C" {
//> PPC branch codes for some branch instructions
typedef enum ppc_bc {
+ PPC_BC_INVALID = 0,
PPC_BC_LT = (0 << 5) | 12,
PPC_BC_LE = (1 << 5) | 4,
PPC_BC_EQ = (2 << 5) | 12,
@@ -25,27 +26,15 @@ typedef enum ppc_bc {
PPC_BC_NE = (2 << 5) | 4,
PPC_BC_UN = (3 << 5) | 12,
PPC_BC_NU = (3 << 5) | 4,
- PPC_BC_LT_MINUS = (0 << 5) | 14,
- PPC_BC_LE_MINUS = (1 << 5) | 6,
- PPC_BC_EQ_MINUS = (2 << 5) | 14,
- PPC_BC_GE_MINUS = (0 << 5) | 6,
- PPC_BC_GT_MINUS = (1 << 5) | 14,
- PPC_BC_NE_MINUS = (2 << 5) | 6,
- PPC_BC_UN_MINUS = (3 << 5) | 14,
- PPC_BC_NU_MINUS = (3 << 5) | 6,
- PPC_BC_LT_PLUS = (0 << 5) | 15,
- PPC_BC_LE_PLUS = (1 << 5) | 7,
- PPC_BC_EQ_PLUS = (2 << 5) | 15,
- PPC_BC_GE_PLUS = (0 << 5) | 7,
- PPC_BC_GT_PLUS = (1 << 5) | 15,
- PPC_BC_NE_PLUS = (2 << 5) | 7,
- PPC_BC_UN_PLUS = (3 << 5) | 15,
- PPC_BC_NU_PLUS = (3 << 5) | 7
+
+ // extra conditions
+ PPC_BC_SO = 4 << 5, // summary overflow
+ PPC_BC_NS = 4 << 5, // not summary overflow
} ppc_bc;
//> PPC branch hint for some branch instructions
typedef enum ppc_bh {
- PPC_BH_NO = 0, // no hint
+ PPC_BH_INVALID = 0, // no hint
PPC_BH_PLUS, // PLUS hint
PPC_BH_MINUS, // MINUS hint
} ppc_bh;
@@ -97,6 +86,7 @@ typedef enum ppc_reg {
PPC_REG_INVALID = 0,
PPC_REG_CARRY,
+ PPC_REG_CC,
PPC_REG_CR0,
PPC_REG_CR1,
PPC_REG_CR2,
@@ -105,30 +95,6 @@ typedef enum ppc_reg {
PPC_REG_CR5,
PPC_REG_CR6,
PPC_REG_CR7,
- PPC_REG_CR8,
- PPC_REG_CR9,
- PPC_REG_CR10,
- PPC_REG_CR11,
- PPC_REG_CR12,
- PPC_REG_CR13,
- PPC_REG_CR14,
- PPC_REG_CR15,
- PPC_REG_CR16,
- PPC_REG_CR17,
- PPC_REG_CR18,
- PPC_REG_CR19,
- PPC_REG_CR20,
- PPC_REG_CR21,
- PPC_REG_CR22,
- PPC_REG_CR23,
- PPC_REG_CR24,
- PPC_REG_CR25,
- PPC_REG_CR26,
- PPC_REG_CR27,
- PPC_REG_CR28,
- PPC_REG_CR29,
- PPC_REG_CR30,
- PPC_REG_CR31,
PPC_REG_CTR,
PPC_REG_F0,
PPC_REG_F1,
@@ -228,8 +194,72 @@ typedef enum ppc_reg {
PPC_REG_V30,
PPC_REG_V31,
PPC_REG_VRSAVE,
+ PPC_REG_VS0,
+ PPC_REG_VS1,
+ PPC_REG_VS2,
+ PPC_REG_VS3,
+ PPC_REG_VS4,
+ PPC_REG_VS5,
+ PPC_REG_VS6,
+ PPC_REG_VS7,
+ PPC_REG_VS8,
+ PPC_REG_VS9,
+ PPC_REG_VS10,
+ PPC_REG_VS11,
+ PPC_REG_VS12,
+ PPC_REG_VS13,
+ PPC_REG_VS14,
+ PPC_REG_VS15,
+ PPC_REG_VS16,
+ PPC_REG_VS17,
+ PPC_REG_VS18,
+ PPC_REG_VS19,
+ PPC_REG_VS20,
+ PPC_REG_VS21,
+ PPC_REG_VS22,
+ PPC_REG_VS23,
+ PPC_REG_VS24,
+ PPC_REG_VS25,
+ PPC_REG_VS26,
+ PPC_REG_VS27,
+ PPC_REG_VS28,
+ PPC_REG_VS29,
+ PPC_REG_VS30,
+ PPC_REG_VS31,
+ PPC_REG_VS32,
+ PPC_REG_VS33,
+ PPC_REG_VS34,
+ PPC_REG_VS35,
+ PPC_REG_VS36,
+ PPC_REG_VS37,
+ PPC_REG_VS38,
+ PPC_REG_VS39,
+ PPC_REG_VS40,
+ PPC_REG_VS41,
+ PPC_REG_VS42,
+ PPC_REG_VS43,
+ PPC_REG_VS44,
+ PPC_REG_VS45,
+ PPC_REG_VS46,
+ PPC_REG_VS47,
+ PPC_REG_VS48,
+ PPC_REG_VS49,
+ PPC_REG_VS50,
+ PPC_REG_VS51,
+ PPC_REG_VS52,
+ PPC_REG_VS53,
+ PPC_REG_VS54,
+ PPC_REG_VS55,
+ PPC_REG_VS56,
+ PPC_REG_VS57,
+ PPC_REG_VS58,
+ PPC_REG_VS59,
+ PPC_REG_VS60,
+ PPC_REG_VS61,
+ PPC_REG_VS62,
+ PPC_REG_VS63,
- // extra registers for mapping.c
+ // extra registers for PPCMapping.c
PPC_REG_RM,
PPC_REG_CTR8,
PPC_REG_LR8,
@@ -256,7 +286,12 @@ typedef enum ppc_insn {
PPC_INS_ANDI,
PPC_INS_B,
PPC_INS_BA,
+ PPC_INS_BC,
+ PPC_INS_BCCTR,
+ PPC_INS_BCCTRL,
PPC_INS_BCL,
+ PPC_INS_BCLR,
+ PPC_INS_BCLRL,
PPC_INS_BCTR,
PPC_INS_BCTRL,
PPC_INS_BDNZ,
@@ -275,6 +310,7 @@ typedef enum ppc_insn {
PPC_INS_BLA,
PPC_INS_BLR,
PPC_INS_BLRL,
+ PPC_INS_BRINC,
PPC_INS_CMPD,
PPC_INS_CMPDI,
PPC_INS_CMPLD,
@@ -301,6 +337,7 @@ typedef enum ppc_insn {
PPC_INS_DCBTST,
PPC_INS_DCBZ,
PPC_INS_DCBZL,
+ PPC_INS_DCCCI,
PPC_INS_DIVD,
PPC_INS_DIVDU,
PPC_INS_DIVW,
@@ -313,6 +350,177 @@ typedef enum ppc_insn {
PPC_INS_DSTT,
PPC_INS_EIEIO,
PPC_INS_EQV,
+ PPC_INS_EVABS,
+ PPC_INS_EVADDIW,
+ PPC_INS_EVADDSMIAAW,
+ PPC_INS_EVADDSSIAAW,
+ PPC_INS_EVADDUMIAAW,
+ PPC_INS_EVADDUSIAAW,
+ PPC_INS_EVADDW,
+ PPC_INS_EVAND,
+ PPC_INS_EVANDC,
+ PPC_INS_EVCMPEQ,
+ PPC_INS_EVCMPGTS,
+ PPC_INS_EVCMPGTU,
+ PPC_INS_EVCMPLTS,
+ PPC_INS_EVCMPLTU,
+ PPC_INS_EVCNTLSW,
+ PPC_INS_EVCNTLZW,
+ PPC_INS_EVDIVWS,
+ PPC_INS_EVDIVWU,
+ PPC_INS_EVEQV,
+ PPC_INS_EVEXTSB,
+ PPC_INS_EVEXTSH,
+ PPC_INS_EVLDD,
+ PPC_INS_EVLDDX,
+ PPC_INS_EVLDH,
+ PPC_INS_EVLDHX,
+ PPC_INS_EVLDW,
+ PPC_INS_EVLDWX,
+ PPC_INS_EVLHHESPLAT,
+ PPC_INS_EVLHHESPLATX,
+ PPC_INS_EVLHHOSSPLAT,
+ PPC_INS_EVLHHOSSPLATX,
+ PPC_INS_EVLHHOUSPLAT,
+ PPC_INS_EVLHHOUSPLATX,
+ PPC_INS_EVLWHE,
+ PPC_INS_EVLWHEX,
+ PPC_INS_EVLWHOS,
+ PPC_INS_EVLWHOSX,
+ PPC_INS_EVLWHOU,
+ PPC_INS_EVLWHOUX,
+ PPC_INS_EVLWHSPLAT,
+ PPC_INS_EVLWHSPLATX,
+ PPC_INS_EVLWWSPLAT,
+ PPC_INS_EVLWWSPLATX,
+ PPC_INS_EVMERGEHI,
+ PPC_INS_EVMERGEHILO,
+ PPC_INS_EVMERGELO,
+ PPC_INS_EVMERGELOHI,
+ PPC_INS_EVMHEGSMFAA,
+ PPC_INS_EVMHEGSMFAN,
+ PPC_INS_EVMHEGSMIAA,
+ PPC_INS_EVMHEGSMIAN,
+ PPC_INS_EVMHEGUMIAA,
+ PPC_INS_EVMHEGUMIAN,
+ PPC_INS_EVMHESMF,
+ PPC_INS_EVMHESMFA,
+ PPC_INS_EVMHESMFAAW,
+ PPC_INS_EVMHESMFANW,
+ PPC_INS_EVMHESMI,
+ PPC_INS_EVMHESMIA,
+ PPC_INS_EVMHESMIAAW,
+ PPC_INS_EVMHESMIANW,
+ PPC_INS_EVMHESSF,
+ PPC_INS_EVMHESSFA,
+ PPC_INS_EVMHESSFAAW,
+ PPC_INS_EVMHESSFANW,
+ PPC_INS_EVMHESSIAAW,
+ PPC_INS_EVMHESSIANW,
+ PPC_INS_EVMHEUMI,
+ PPC_INS_EVMHEUMIA,
+ PPC_INS_EVMHEUMIAAW,
+ PPC_INS_EVMHEUMIANW,
+ PPC_INS_EVMHEUSIAAW,
+ PPC_INS_EVMHEUSIANW,
+ PPC_INS_EVMHOGSMFAA,
+ PPC_INS_EVMHOGSMFAN,
+ PPC_INS_EVMHOGSMIAA,
+ PPC_INS_EVMHOGSMIAN,
+ PPC_INS_EVMHOGUMIAA,
+ PPC_INS_EVMHOGUMIAN,
+ PPC_INS_EVMHOSMF,
+ PPC_INS_EVMHOSMFA,
+ PPC_INS_EVMHOSMFAAW,
+ PPC_INS_EVMHOSMFANW,
+ PPC_INS_EVMHOSMI,
+ PPC_INS_EVMHOSMIA,
+ PPC_INS_EVMHOSMIAAW,
+ PPC_INS_EVMHOSMIANW,
+ PPC_INS_EVMHOSSF,
+ PPC_INS_EVMHOSSFA,
+ PPC_INS_EVMHOSSFAAW,
+ PPC_INS_EVMHOSSFANW,
+ PPC_INS_EVMHOSSIAAW,
+ PPC_INS_EVMHOSSIANW,
+ PPC_INS_EVMHOUMI,
+ PPC_INS_EVMHOUMIA,
+ PPC_INS_EVMHOUMIAAW,
+ PPC_INS_EVMHOUMIANW,
+ PPC_INS_EVMHOUSIAAW,
+ PPC_INS_EVMHOUSIANW,
+ PPC_INS_EVMRA,
+ PPC_INS_EVMWHSMF,
+ PPC_INS_EVMWHSMFA,
+ PPC_INS_EVMWHSMI,
+ PPC_INS_EVMWHSMIA,
+ PPC_INS_EVMWHSSF,
+ PPC_INS_EVMWHSSFA,
+ PPC_INS_EVMWHUMI,
+ PPC_INS_EVMWHUMIA,
+ PPC_INS_EVMWLSMIAAW,
+ PPC_INS_EVMWLSMIANW,
+ PPC_INS_EVMWLSSIAAW,
+ PPC_INS_EVMWLSSIANW,
+ PPC_INS_EVMWLUMI,
+ PPC_INS_EVMWLUMIA,
+ PPC_INS_EVMWLUMIAAW,
+ PPC_INS_EVMWLUMIANW,
+ PPC_INS_EVMWLUSIAAW,
+ PPC_INS_EVMWLUSIANW,
+ PPC_INS_EVMWSMF,
+ PPC_INS_EVMWSMFA,
+ PPC_INS_EVMWSMFAA,
+ PPC_INS_EVMWSMFAN,
+ PPC_INS_EVMWSMI,
+ PPC_INS_EVMWSMIA,
+ PPC_INS_EVMWSMIAA,
+ PPC_INS_EVMWSMIAN,
+ PPC_INS_EVMWSSF,
+ PPC_INS_EVMWSSFA,
+ PPC_INS_EVMWSSFAA,
+ PPC_INS_EVMWSSFAN,
+ PPC_INS_EVMWUMI,
+ PPC_INS_EVMWUMIA,
+ PPC_INS_EVMWUMIAA,
+ PPC_INS_EVMWUMIAN,
+ PPC_INS_EVNAND,
+ PPC_INS_EVNEG,
+ PPC_INS_EVNOR,
+ PPC_INS_EVOR,
+ PPC_INS_EVORC,
+ PPC_INS_EVRLW,
+ PPC_INS_EVRLWI,
+ PPC_INS_EVRNDW,
+ PPC_INS_EVSLW,
+ PPC_INS_EVSLWI,
+ PPC_INS_EVSPLATFI,
+ PPC_INS_EVSPLATI,
+ PPC_INS_EVSRWIS,
+ PPC_INS_EVSRWIU,
+ PPC_INS_EVSRWS,
+ PPC_INS_EVSRWU,
+ PPC_INS_EVSTDD,
+ PPC_INS_EVSTDDX,
+ PPC_INS_EVSTDH,
+ PPC_INS_EVSTDHX,
+ PPC_INS_EVSTDW,
+ PPC_INS_EVSTDWX,
+ PPC_INS_EVSTWHE,
+ PPC_INS_EVSTWHEX,
+ PPC_INS_EVSTWHO,
+ PPC_INS_EVSTWHOX,
+ PPC_INS_EVSTWWE,
+ PPC_INS_EVSTWWEX,
+ PPC_INS_EVSTWWO,
+ PPC_INS_EVSTWWOX,
+ PPC_INS_EVSUBFSMIAAW,
+ PPC_INS_EVSUBFSSIAAW,
+ PPC_INS_EVSUBFUMIAAW,
+ PPC_INS_EVSUBFUSIAAW,
+ PPC_INS_EVSUBFW,
+ PPC_INS_EVSUBIFW,
+ PPC_INS_EVXOR,
PPC_INS_EXTSB,
PPC_INS_EXTSH,
PPC_INS_EXTSW,
@@ -361,6 +569,7 @@ typedef enum ppc_insn {
PPC_INS_FSUB,
PPC_INS_FSUBS,
PPC_INS_ICBI,
+ PPC_INS_ICCCI,
PPC_INS_ISEL,
PPC_INS_ISYNC,
PPC_INS_LA,
@@ -396,6 +605,7 @@ typedef enum ppc_insn {
PPC_INS_LI,
PPC_INS_LIS,
PPC_INS_LMW,
+ PPC_INS_LSWI,
PPC_INS_LVEBX,
PPC_INS_LVEHX,
PPC_INS_LVEWX,
@@ -412,19 +622,28 @@ typedef enum ppc_insn {
PPC_INS_LWZU,
PPC_INS_LWZUX,
PPC_INS_LWZX,
+ PPC_INS_LXSDX,
+ PPC_INS_LXVD2X,
+ PPC_INS_LXVDSX,
+ PPC_INS_LXVW4X,
+ PPC_INS_MBAR,
PPC_INS_MCRF,
PPC_INS_MFCR,
PPC_INS_MFCTR,
+ PPC_INS_MFDCR,
PPC_INS_MFFS,
PPC_INS_MFLR,
PPC_INS_MFMSR,
PPC_INS_MFOCRF,
PPC_INS_MFSPR,
+ PPC_INS_MFSR,
+ PPC_INS_MFSRIN,
PPC_INS_MFTB,
PPC_INS_MFVSCR,
PPC_INS_MSYNC,
PPC_INS_MTCRF,
PPC_INS_MTCTR,
+ PPC_INS_MTDCR,
PPC_INS_MTFSB0,
PPC_INS_MTFSB1,
PPC_INS_MTFSF,
@@ -433,6 +652,8 @@ typedef enum ppc_insn {
PPC_INS_MTMSRD,
PPC_INS_MTOCRF,
PPC_INS_MTSPR,
+ PPC_INS_MTSR,
+ PPC_INS_MTSRIN,
PPC_INS_MTVSCR,
PPC_INS_MULHD,
PPC_INS_MULHDU,
@@ -451,6 +672,11 @@ typedef enum ppc_insn {
PPC_INS_ORIS,
PPC_INS_POPCNTD,
PPC_INS_POPCNTW,
+ PPC_INS_RFCI,
+ PPC_INS_RFDI,
+ PPC_INS_RFI,
+ PPC_INS_RFID,
+ PPC_INS_RFMCI,
PPC_INS_RLDCL,
PPC_INS_RLDCR,
PPC_INS_RLDIC,
@@ -498,6 +724,7 @@ typedef enum ppc_insn {
PPC_INS_STHUX,
PPC_INS_STHX,
PPC_INS_STMW,
+ PPC_INS_STSWI,
PPC_INS_STVEBX,
PPC_INS_STVEHX,
PPC_INS_STVEWX,
@@ -509,6 +736,9 @@ typedef enum ppc_insn {
PPC_INS_STWU,
PPC_INS_STWUX,
PPC_INS_STWX,
+ PPC_INS_STXSDX,
+ PPC_INS_STXVD2X,
+ PPC_INS_STXVW4X,
PPC_INS_SUBF,
PPC_INS_SUBFC,
PPC_INS_SUBFE,
@@ -518,9 +748,16 @@ typedef enum ppc_insn {
PPC_INS_SYNC,
PPC_INS_TD,
PPC_INS_TDI,
+ PPC_INS_TLBIA,
PPC_INS_TLBIE,
PPC_INS_TLBIEL,
+ PPC_INS_TLBIVAX,
+ PPC_INS_TLBLD,
+ PPC_INS_TLBLI,
+ PPC_INS_TLBRE,
+ PPC_INS_TLBSX,
PPC_INS_TLBSYNC,
+ PPC_INS_TLBWE,
PPC_INS_TRAP,
PPC_INS_TW,
PPC_INS_TWI,
@@ -667,16 +904,310 @@ typedef enum ppc_insn {
PPC_INS_VUPKLSH,
PPC_INS_VXOR,
PPC_INS_WAIT,
+ PPC_INS_WRTEE,
+ PPC_INS_WRTEEI,
PPC_INS_XOR,
PPC_INS_XORI,
PPC_INS_XORIS,
- PPC_INS_BC,
+ PPC_INS_XSABSDP,
+ PPC_INS_XSADDDP,
+ PPC_INS_XSCMPODP,
+ PPC_INS_XSCMPUDP,
+ PPC_INS_XSCPSGNDP,
+ PPC_INS_XSCVDPSP,
+ PPC_INS_XSCVDPSXDS,
+ PPC_INS_XSCVDPSXWS,
+ PPC_INS_XSCVDPUXDS,
+ PPC_INS_XSCVDPUXWS,
+ PPC_INS_XSCVSPDP,
+ PPC_INS_XSCVSXDDP,
+ PPC_INS_XSCVUXDDP,
+ PPC_INS_XSDIVDP,
+ PPC_INS_XSMADDADP,
+ PPC_INS_XSMADDMDP,
+ PPC_INS_XSMAXDP,
+ PPC_INS_XSMINDP,
+ PPC_INS_XSMSUBADP,
+ PPC_INS_XSMSUBMDP,
+ PPC_INS_XSMULDP,
+ PPC_INS_XSNABSDP,
+ PPC_INS_XSNEGDP,
+ PPC_INS_XSNMADDADP,
+ PPC_INS_XSNMADDMDP,
+ PPC_INS_XSNMSUBADP,
+ PPC_INS_XSNMSUBMDP,
+ PPC_INS_XSRDPI,
+ PPC_INS_XSRDPIC,
+ PPC_INS_XSRDPIM,
+ PPC_INS_XSRDPIP,
+ PPC_INS_XSRDPIZ,
+ PPC_INS_XSREDP,
+ PPC_INS_XSRSQRTEDP,
+ PPC_INS_XSSQRTDP,
+ PPC_INS_XSSUBDP,
+ PPC_INS_XSTDIVDP,
+ PPC_INS_XSTSQRTDP,
+ PPC_INS_XVABSDP,
+ PPC_INS_XVABSSP,
+ PPC_INS_XVADDDP,
+ PPC_INS_XVADDSP,
+ PPC_INS_XVCMPEQDP,
+ PPC_INS_XVCMPEQSP,
+ PPC_INS_XVCMPGEDP,
+ PPC_INS_XVCMPGESP,
+ PPC_INS_XVCMPGTDP,
+ PPC_INS_XVCMPGTSP,
+ PPC_INS_XVCPSGNDP,
+ PPC_INS_XVCPSGNSP,
+ PPC_INS_XVCVDPSP,
+ PPC_INS_XVCVDPSXDS,
+ PPC_INS_XVCVDPSXWS,
+ PPC_INS_XVCVDPUXDS,
+ PPC_INS_XVCVDPUXWS,
+ PPC_INS_XVCVSPDP,
+ PPC_INS_XVCVSPSXDS,
+ PPC_INS_XVCVSPSXWS,
+ PPC_INS_XVCVSPUXDS,
+ PPC_INS_XVCVSPUXWS,
+ PPC_INS_XVCVSXDDP,
+ PPC_INS_XVCVSXDSP,
+ PPC_INS_XVCVSXWDP,
+ PPC_INS_XVCVSXWSP,
+ PPC_INS_XVCVUXDDP,
+ PPC_INS_XVCVUXDSP,
+ PPC_INS_XVCVUXWDP,
+ PPC_INS_XVCVUXWSP,
+ PPC_INS_XVDIVDP,
+ PPC_INS_XVDIVSP,
+ PPC_INS_XVMADDADP,
+ PPC_INS_XVMADDASP,
+ PPC_INS_XVMADDMDP,
+ PPC_INS_XVMADDMSP,
+ PPC_INS_XVMAXDP,
+ PPC_INS_XVMAXSP,
+ PPC_INS_XVMINDP,
+ PPC_INS_XVMINSP,
+ PPC_INS_XVMSUBADP,
+ PPC_INS_XVMSUBASP,
+ PPC_INS_XVMSUBMDP,
+ PPC_INS_XVMSUBMSP,
+ PPC_INS_XVMULDP,
+ PPC_INS_XVMULSP,
+ PPC_INS_XVNABSDP,
+ PPC_INS_XVNABSSP,
+ PPC_INS_XVNEGDP,
+ PPC_INS_XVNEGSP,
+ PPC_INS_XVNMADDADP,
+ PPC_INS_XVNMADDASP,
+ PPC_INS_XVNMADDMDP,
+ PPC_INS_XVNMADDMSP,
+ PPC_INS_XVNMSUBADP,
+ PPC_INS_XVNMSUBASP,
+ PPC_INS_XVNMSUBMDP,
+ PPC_INS_XVNMSUBMSP,
+ PPC_INS_XVRDPI,
+ PPC_INS_XVRDPIC,
+ PPC_INS_XVRDPIM,
+ PPC_INS_XVRDPIP,
+ PPC_INS_XVRDPIZ,
+ PPC_INS_XVREDP,
+ PPC_INS_XVRESP,
+ PPC_INS_XVRSPI,
+ PPC_INS_XVRSPIC,
+ PPC_INS_XVRSPIM,
+ PPC_INS_XVRSPIP,
+ PPC_INS_XVRSPIZ,
+ PPC_INS_XVRSQRTEDP,
+ PPC_INS_XVRSQRTESP,
+ PPC_INS_XVSQRTDP,
+ PPC_INS_XVSQRTSP,
+ PPC_INS_XVSUBDP,
+ PPC_INS_XVSUBSP,
+ PPC_INS_XVTDIVDP,
+ PPC_INS_XVTDIVSP,
+ PPC_INS_XVTSQRTDP,
+ PPC_INS_XVTSQRTSP,
+ PPC_INS_XXLAND,
+ PPC_INS_XXLANDC,
+ PPC_INS_XXLNOR,
+ PPC_INS_XXLOR,
+ PPC_INS_XXLXOR,
+ PPC_INS_XXMRGHW,
+ PPC_INS_XXMRGLW,
+ PPC_INS_XXPERMDI,
+ PPC_INS_XXSEL,
+ PPC_INS_XXSLDWI,
+ PPC_INS_XXSPLTW,
PPC_INS_BCA,
- PPC_INS_BCCTR,
- PPC_INS_BCCTRL,
PPC_INS_BCLA,
- PPC_INS_BCLR,
- PPC_INS_BCLRL,
+
+ // extra & alias instructions
+ PPC_INS_SLWI,
+ PPC_INS_SRWI,
+ PPC_INS_SLDI,
+
+ PPC_INS_BTA,
+ PPC_INS_CRSET,
+ PPC_INS_CRNOT,
+ PPC_INS_CRMOVE,
+ PPC_INS_CRCLR,
+ PPC_INS_MFBR0,
+ PPC_INS_MFBR1,
+ PPC_INS_MFBR2,
+ PPC_INS_MFBR3,
+ PPC_INS_MFBR4,
+ PPC_INS_MFBR5,
+ PPC_INS_MFBR6,
+ PPC_INS_MFBR7,
+ PPC_INS_MFXER,
+ PPC_INS_MFRTCU,
+ PPC_INS_MFRTCL,
+ PPC_INS_MFDSCR,
+ PPC_INS_MFDSISR,
+ PPC_INS_MFDAR,
+ PPC_INS_MFSRR2,
+ PPC_INS_MFSRR3,
+ PPC_INS_MFCFAR,
+ PPC_INS_MFAMR,
+ PPC_INS_MFPID,
+ PPC_INS_MFTBLO,
+ PPC_INS_MFTBHI,
+ PPC_INS_MFDBATU,
+ PPC_INS_MFDBATL,
+ PPC_INS_MFIBATU,
+ PPC_INS_MFIBATL,
+ PPC_INS_MFDCCR,
+ PPC_INS_MFICCR,
+ PPC_INS_MFDEAR,
+ PPC_INS_MFESR,
+ PPC_INS_MFSPEFSCR,
+ PPC_INS_MFTCR,
+ PPC_INS_MFASR,
+ PPC_INS_MFPVR,
+ PPC_INS_MFTBU,
+ PPC_INS_MTCR,
+ PPC_INS_MTBR0,
+ PPC_INS_MTBR1,
+ PPC_INS_MTBR2,
+ PPC_INS_MTBR3,
+ PPC_INS_MTBR4,
+ PPC_INS_MTBR5,
+ PPC_INS_MTBR6,
+ PPC_INS_MTBR7,
+ PPC_INS_MTXER,
+ PPC_INS_MTDSCR,
+ PPC_INS_MTDSISR,
+ PPC_INS_MTDAR,
+ PPC_INS_MTSRR2,
+ PPC_INS_MTSRR3,
+ PPC_INS_MTCFAR,
+ PPC_INS_MTAMR,
+ PPC_INS_MTPID,
+ PPC_INS_MTTBL,
+ PPC_INS_MTTBU,
+ PPC_INS_MTTBLO,
+ PPC_INS_MTTBHI,
+ PPC_INS_MTDBATU,
+ PPC_INS_MTDBATL,
+ PPC_INS_MTIBATU,
+ PPC_INS_MTIBATL,
+ PPC_INS_MTDCCR,
+ PPC_INS_MTICCR,
+ PPC_INS_MTDEAR,
+ PPC_INS_MTESR,
+ PPC_INS_MTSPEFSCR,
+ PPC_INS_MTTCR,
+ PPC_INS_NOT,
+ PPC_INS_MR,
+ PPC_INS_ROTLD,
+ PPC_INS_ROTLDI,
+ PPC_INS_CLRLDI,
+ PPC_INS_ROTLWI,
+ PPC_INS_CLRLWI,
+ PPC_INS_ROTLW,
+ PPC_INS_SUB,
+ PPC_INS_SUBC,
+ PPC_INS_LWSYNC,
+ PPC_INS_PTESYNC,
+ PPC_INS_TDLT,
+ PPC_INS_TDEQ,
+ PPC_INS_TDGT,
+ PPC_INS_TDNE,
+ PPC_INS_TDLLT,
+ PPC_INS_TDLGT,
+ PPC_INS_TDU,
+ PPC_INS_TDLTI,
+ PPC_INS_TDEQI,
+ PPC_INS_TDGTI,
+ PPC_INS_TDNEI,
+ PPC_INS_TDLLTI,
+ PPC_INS_TDLGTI,
+ PPC_INS_TDUI,
+ PPC_INS_TLBREHI,
+ PPC_INS_TLBRELO,
+ PPC_INS_TLBWEHI,
+ PPC_INS_TLBWELO,
+ PPC_INS_TWLT,
+ PPC_INS_TWEQ,
+ PPC_INS_TWGT,
+ PPC_INS_TWNE,
+ PPC_INS_TWLLT,
+ PPC_INS_TWLGT,
+ PPC_INS_TWU,
+ PPC_INS_TWLTI,
+ PPC_INS_TWEQI,
+ PPC_INS_TWGTI,
+ PPC_INS_TWNEI,
+ PPC_INS_TWLLTI,
+ PPC_INS_TWLGTI,
+ PPC_INS_TWUI,
+ PPC_INS_WAITRSV,
+ PPC_INS_WAITIMPL,
+ PPC_INS_XNOP,
+ PPC_INS_XVMOVDP,
+ PPC_INS_XVMOVSP,
+ PPC_INS_XXSPLTD,
+ PPC_INS_XXMRGHD,
+ PPC_INS_XXMRGLD,
+ PPC_INS_XXSWAPD,
+ PPC_INS_BT,
+ PPC_INS_BF,
+ PPC_INS_BDNZT,
+ PPC_INS_BDNZF,
+ PPC_INS_BDZF,
+ PPC_INS_BDZT,
+ PPC_INS_BFA,
+ PPC_INS_BDNZTA,
+ PPC_INS_BDNZFA,
+ PPC_INS_BDZTA,
+ PPC_INS_BDZFA,
+ PPC_INS_BTCTR,
+ PPC_INS_BFCTR,
+ PPC_INS_BTCTRL,
+ PPC_INS_BFCTRL,
+ PPC_INS_BTL,
+ PPC_INS_BFL,
+ PPC_INS_BDNZTL,
+ PPC_INS_BDNZFL,
+ PPC_INS_BDZTL,
+ PPC_INS_BDZFL,
+ PPC_INS_BTLA,
+ PPC_INS_BFLA,
+ PPC_INS_BDNZTLA,
+ PPC_INS_BDNZFLA,
+ PPC_INS_BDZTLA,
+ PPC_INS_BDZFLA,
+ PPC_INS_BTLR,
+ PPC_INS_BFLR,
+ PPC_INS_BDNZTLR,
+ PPC_INS_BDZTLR,
+ PPC_INS_BDZFLR,
+ PPC_INS_BTLRL,
+ PPC_INS_BFLRL,
+ PPC_INS_BDNZTLRL,
+ PPC_INS_BDNZFLRL,
+ PPC_INS_BDZTLRL,
+ PPC_INS_BDZFLRL,
PPC_INS_MAX, // <-- mark the end of the list of instructions
} ppc_insn;
@@ -690,6 +1221,11 @@ typedef enum ppc_insn_group {
PPC_GRP_MODE64,
PPC_GRP_BOOKE,
PPC_GRP_NOTBOOKE,
+ PPC_GRP_SPE,
+ PPC_GRP_VSX,
+ PPC_GRP_E500,
+ PPC_GRP_PPC4XX,
+ PPC_GRP_PPC6XX,
PPC_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)
diff -Nurp capstone-next.git/include/sparc.h capstone-v3.git/include/sparc.h
--- capstone-next.git/include/sparc.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/sparc.h 2014-09-24 22:57:32.000000000 +0800
@@ -96,7 +96,7 @@ typedef struct cs_sparc_op {
// Instruction structure
typedef struct cs_sparc {
sparc_cc cc; // code condition for this insn
- sparc_hint hint; // branch hint: encoding as bitwise OR of SPARC_HINT_*.
+ sparc_hint hint; // branch hint: encoding as bitwise OR of sparc_hint.
// Number of operands of this instruction,
// or 0 when instruction has no operand.
uint8_t op_count;
@@ -194,6 +194,9 @@ typedef enum sparc_reg {
SPARC_REG_SP,
SPARC_REG_Y,
+ // special register
+ SPARC_REG_XCC,
+
SPARC_REG_MAX, // <-- mark the end of the list of registers
// extras
@@ -220,7 +223,6 @@ typedef enum sparc_insn {
SPARC_INS_ARRAY16,
SPARC_INS_ARRAY32,
SPARC_INS_ARRAY8,
- SPARC_INS_BA,
SPARC_INS_B,
SPARC_INS_JMP,
SPARC_INS_BMASK,
@@ -460,7 +462,6 @@ typedef enum sparc_insn {
SPARC_INS_SUBXCC,
SPARC_INS_SUB,
SPARC_INS_SWAP,
- SPARC_INS_TA,
SPARC_INS_TADDCCTV,
SPARC_INS_TADDCC,
SPARC_INS_T,
@@ -484,6 +485,10 @@ typedef enum sparc_insn {
SPARC_INS_XORCC,
SPARC_INS_XOR,
+ // alias instructions
+ SPARC_INS_RET,
+ SPARC_INS_RETL,
+
SPARC_INS_MAX, // <-- mark the end of the list of instructions
} sparc_insn;
diff -Nurp capstone-next.git/include/systemz.h capstone-v3.git/include/systemz.h
--- capstone-next.git/include/systemz.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/systemz.h 2014-09-24 22:57:32.000000000 +0800
@@ -547,11 +547,14 @@ typedef enum sysz_insn {
SYSZ_INS_LDGR,
SYSZ_INS_LDR,
SYSZ_INS_LDXBR,
+ SYSZ_INS_LDXBRA,
SYSZ_INS_LDY,
SYSZ_INS_LE,
SYSZ_INS_LEDBR,
+ SYSZ_INS_LEDBRA,
SYSZ_INS_LER,
SYSZ_INS_LEXBR,
+ SYSZ_INS_LEXBRA,
SYSZ_INS_LEY,
SYSZ_INS_LFH,
SYSZ_INS_LG,
@@ -797,17 +800,18 @@ typedef enum sysz_insn {
SYSZ_INS_XR,
SYSZ_INS_XRK,
SYSZ_INS_XY,
+
SYSZ_INS_MAX, // <-- mark the end of the list of instructions
} sysz_insn;
//> Group of SystemZ instructions
typedef enum sysz_insn_group {
SYSZ_GRP_INVALID = 0,
- SYSZ_GRP_FEATUREDISTINCTOPS,
- SYSZ_GRP_FEATUREFPEXTENSION,
- SYSZ_GRP_FEATUREHIGHWORD,
- SYSZ_GRP_FEATUREINTERLOCKEDACCESS1,
- SYSZ_GRP_FEATURELOADSTOREONCOND,
+ SYSZ_GRP_DISTINCTOPS,
+ SYSZ_GRP_FPEXTENSION,
+ SYSZ_GRP_HIGHWORD,
+ SYSZ_GRP_INTERLOCKEDACCESS1,
+ SYSZ_GRP_LOADSTOREONCOND,
SYSZ_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)
diff -Nurp capstone-next.git/include/x86.h capstone-v3.git/include/x86.h
--- capstone-next.git/include/x86.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/x86.h 2014-09-24 22:57:32.000000000 +0800
@@ -31,7 +31,7 @@ typedef enum x86_reg {
X86_REG_CR11, X86_REG_CR12, X86_REG_CR13, X86_REG_CR14, X86_REG_CR15,
X86_REG_DR0, X86_REG_DR1, X86_REG_DR2, X86_REG_DR3, X86_REG_DR4,
X86_REG_DR5, X86_REG_DR6, X86_REG_DR7, X86_REG_FP0, X86_REG_FP1,
- X86_REG_FP2, X86_REG_FP3, X86_REG_FP4, X86_REG_FP5, X86_REG_FP6,
+ X86_REG_FP2, X86_REG_FP3, X86_REG_FP4, X86_REG_FP5, X86_REG_FP6, X86_REG_FP7,
X86_REG_K0, X86_REG_K1, X86_REG_K2, X86_REG_K3, X86_REG_K4,
X86_REG_K5, X86_REG_K6, X86_REG_K7, X86_REG_MM0, X86_REG_MM1,
X86_REG_MM2, X86_REG_MM3, X86_REG_MM4, X86_REG_MM5, X86_REG_MM6,
@@ -76,12 +76,89 @@ typedef enum x86_op_type {
X86_OP_MEM, // Memory operand
} x86_op_type;
+//> AVX broadcast type
+typedef enum x86_avx_bcast {
+ X86_AVX_BCAST_INVALID = 0, // Uninitialized.
+ X86_AVX_BCAST_2, // AVX512 broadcast type {1to2}
+ X86_AVX_BCAST_4, // AVX512 broadcast type {1to4}
+ X86_AVX_BCAST_8, // AVX512 broadcast type {1to8}
+ X86_AVX_BCAST_16, // AVX512 broadcast type {1to16}
+} x86_avx_bcast;
+
+//> SSE Code Condition type
+typedef enum x86_sse_cc {
+ X86_SSE_CC_INVALID = 0, // Uninitialized.
+ X86_SSE_CC_EQ,
+ X86_SSE_CC_LT,
+ X86_SSE_CC_LE,
+ X86_SSE_CC_UNORD,
+ X86_SSE_CC_NEQ,
+ X86_SSE_CC_NLT,
+ X86_SSE_CC_NLE,
+ X86_SSE_CC_ORD,
+ X86_SSE_CC_EQ_UQ,
+ X86_SSE_CC_NGE,
+ X86_SSE_CC_NGT,
+ X86_SSE_CC_FALSE,
+ X86_SSE_CC_NEQ_OQ,
+ X86_SSE_CC_GE,
+ X86_SSE_CC_GT,
+ X86_SSE_CC_TRUE,
+} x86_sse_cc;
+
+//> AVX Code Condition type
+typedef enum x86_avx_cc {
+ X86_AVX_CC_INVALID = 0, // Uninitialized.
+ X86_AVX_CC_EQ,
+ X86_AVX_CC_LT,
+ X86_AVX_CC_LE,
+ X86_AVX_CC_UNORD,
+ X86_AVX_CC_NEQ,
+ X86_AVX_CC_NLT,
+ X86_AVX_CC_NLE,
+ X86_AVX_CC_ORD,
+ X86_AVX_CC_EQ_UQ,
+ X86_AVX_CC_NGE,
+ X86_AVX_CC_NGT,
+ X86_AVX_CC_FALSE,
+ X86_AVX_CC_NEQ_OQ,
+ X86_AVX_CC_GE,
+ X86_AVX_CC_GT,
+ X86_AVX_CC_TRUE,
+ X86_AVX_CC_EQ_OS,
+ X86_AVX_CC_LT_OQ,
+ X86_AVX_CC_LE_OQ,
+ X86_AVX_CC_UNORD_S,
+ X86_AVX_CC_NEQ_US,
+ X86_AVX_CC_NLT_UQ,
+ X86_AVX_CC_NLE_UQ,
+ X86_AVX_CC_ORD_S,
+ X86_AVX_CC_EQ_US,
+ X86_AVX_CC_NGE_UQ,
+ X86_AVX_CC_NGT_UQ,
+ X86_AVX_CC_FALSE_OS,
+ X86_AVX_CC_NEQ_OS,
+ X86_AVX_CC_GE_OQ,
+ X86_AVX_CC_GT_OQ,
+ X86_AVX_CC_TRUE_US,
+} x86_avx_cc;
+
+//> AVX static rounding mode type
+typedef enum x86_avx_rm {
+ X86_AVX_RM_INVALID = 0, // Uninitialized.
+ X86_AVX_RM_RN, // Round to nearest
+ X86_AVX_RM_RD, // Round down
+ X86_AVX_RM_RU, // Round up
+ X86_AVX_RM_RZ, // Round toward zero
+} x86_avx_rm;
+
// Instruction's operand referring to memory
// This is associated with X86_OP_MEM operand type above
typedef struct x86_op_mem {
- unsigned int base; // base register
- unsigned int index; // index register
- int scale; // scale for index register (can be 1, or -1)
+ unsigned int segment; // segment register (or X86_REG_INVALID if irrelevant)
+ unsigned int base; // base register (or X86_REG_INVALID if irrelevant)
+ unsigned int index; // index register (or X86_REG_INVALID if irrelevant)
+ int scale; // scale for index register
int64_t disp; // displacement value
} x86_op_mem;
@@ -94,36 +171,39 @@ typedef struct cs_x86_op {
double fp; // floating point value for FP operand
x86_op_mem mem; // base/index/scale/disp value for MEM operand
};
+
+ // size of this operand (in bytes).
+ uint8_t size;
+
+ // AVX broadcast type, or 0 if irrelevant
+ x86_avx_bcast avx_bcast;
+
+ // AVX zero opmask {z}
+ bool avx_zero_opmask;
} cs_x86_op;
// Instruction structure
typedef struct cs_x86 {
- // (Optional) instruction prefix, which can be up to 5 bytes.
+ // Instruction prefix, which can be up to 4 bytes.
// A prefix byte gets value 0 when irrelevant.
- uint8_t prefix[5];
+ // prefix[0] indicates REP/REPNE/LOCK prefix (0xf3/0xf2/0xf0 respectively)
+ // prefix[1] indicates segment override (irrelevant for x86_64):
+ // 0x2e = CS, 0x36 = SS, 0x3e = DS, 0x26 = ES, 0x64 = FS, 0x65 = GS
+ // prefix[2] indicates operand-size override (0x66)
+ // prefix[3] indicates address-size override (0x67)
+ uint8_t prefix[4];
- // (Optional) segment override, which can be among CS, DS, SS, ES, FS, GS.
- // This field get value 0 when irrelevant.
- x86_reg segment;
-
- // Instruction opcode, wich can be from 1 to 3 bytes in size.
+ // Instruction opcode, wich can be from 1 to 4 bytes in size.
// This contains VEX opcode as well.
- // An opcode byte gets value 0 when irrelevant.
- uint8_t opcode[3];
+ // An trailing opcode byte gets value 0 when irrelevant.
+ uint8_t opcode[4];
- // Operand size, which can be overrided with above prefix[5].
- uint8_t op_size;
+ // REX prefix: only a non-zero value is relavant for x86_64
+ uint8_t rex;
// Address size, which can be overrided with above prefix[5].
uint8_t addr_size;
- // Size of (optional) displacement.
- // This field get value 0 when irrelevant.
- uint8_t disp_size;
-
- // Size of immediate operand
- uint8_t imm_size;
-
// ModR/M byte
uint8_t modrm;
@@ -141,6 +221,18 @@ typedef struct cs_x86 {
// SIB base register, or X86_REG_INVALID when irrelevant.
x86_reg sib_base;
+ // SSE Code Condition
+ x86_sse_cc sse_cc;
+
+ // AVX Code Condition
+ x86_avx_cc avx_cc;
+
+ // AVX Suppress all Exception
+ bool avx_sae;
+
+ // AVX static rounding mode
+ x86_avx_rm avx_rm;
+
// Number of operands of this instruction,
// or 0 when instruction has no operand.
uint8_t op_count;
@@ -247,11 +339,11 @@ typedef enum x86_insn {
X86_INS_CMP,
X86_INS_CMPPD,
X86_INS_CMPPS,
- X86_INS_CMPSW,
+ X86_INS_CMPSB,
X86_INS_CMPSD,
X86_INS_CMPSQ,
- X86_INS_CMPSB,
X86_INS_CMPSS,
+ X86_INS_CMPSW,
X86_INS_CMPXCHG16B,
X86_INS_CMPXCHG,
X86_INS_CMPXCHG8B,
@@ -265,7 +357,6 @@ typedef enum x86_insn {
X86_INS_CPUID,
X86_INS_CQO,
X86_INS_CRC32,
- X86_INS_CS,
X86_INS_CVTDQ2PD,
X86_INS_CVTDQ2PS,
X86_INS_CVTPD2DQ,
@@ -301,9 +392,10 @@ typedef enum x86_insn {
X86_INS_FDIVP,
X86_INS_DPPD,
X86_INS_DPPS,
- X86_INS_DS,
+ X86_INS_RET,
+ X86_INS_ENCLS,
+ X86_INS_ENCLU,
X86_INS_ENTER,
- X86_INS_ES,
X86_INS_EXTRACTPS,
X86_INS_EXTRQ,
X86_INS_F2XM1,
@@ -341,7 +433,6 @@ typedef enum x86_insn {
X86_INS_FSETPM,
X86_INS_FSINCOS,
X86_INS_FNSTENV,
- X86_INS_FS,
X86_INS_FXAM,
X86_INS_FXRSTOR,
X86_INS_FXRSTOR64,
@@ -359,7 +450,6 @@ typedef enum x86_insn {
X86_INS_XORPD,
X86_INS_XORPS,
X86_INS_GETSEC,
- X86_INS_GS,
X86_INS_HADDPD,
X86_INS_HADDPS,
X86_INS_HLT,
@@ -368,13 +458,13 @@ typedef enum x86_insn {
X86_INS_IDIV,
X86_INS_FILD,
X86_INS_IMUL,
- X86_INS_INSW,
X86_INS_IN,
- X86_INS_INSD,
- X86_INS_INSB,
X86_INS_INC,
+ X86_INS_INSB,
X86_INS_INSERTPS,
X86_INS_INSERTQ,
+ X86_INS_INSD,
+ X86_INS_INSW,
X86_INS_INT,
X86_INS_INT1,
X86_INS_INT3,
@@ -428,16 +518,37 @@ typedef enum x86_insn {
X86_INS_JP,
X86_INS_JRCXZ,
X86_INS_JS,
+ X86_INS_KANDB,
+ X86_INS_KANDD,
+ X86_INS_KANDNB,
+ X86_INS_KANDND,
+ X86_INS_KANDNQ,
X86_INS_KANDNW,
+ X86_INS_KANDQ,
X86_INS_KANDW,
+ X86_INS_KMOVB,
+ X86_INS_KMOVD,
+ X86_INS_KMOVQ,
X86_INS_KMOVW,
+ X86_INS_KNOTB,
+ X86_INS_KNOTD,
+ X86_INS_KNOTQ,
X86_INS_KNOTW,
+ X86_INS_KORB,
+ X86_INS_KORD,
+ X86_INS_KORQ,
X86_INS_KORTESTW,
X86_INS_KORW,
X86_INS_KSHIFTLW,
X86_INS_KSHIFTRW,
X86_INS_KUNPCKBW,
+ X86_INS_KXNORB,
+ X86_INS_KXNORD,
+ X86_INS_KXNORQ,
X86_INS_KXNORW,
+ X86_INS_KXORB,
+ X86_INS_KXORD,
+ X86_INS_KXORQ,
X86_INS_KXORW,
X86_INS_LAHF,
X86_INS_LAR,
@@ -733,8 +844,6 @@ typedef enum x86_insn {
X86_INS_RDTSCP,
X86_INS_REPNE,
X86_INS_REP,
- X86_INS_RET,
- X86_INS_REX64,
X86_INS_ROL,
X86_INS_ROR,
X86_INS_RORX,
@@ -751,10 +860,10 @@ typedef enum x86_insn {
X86_INS_SAR,
X86_INS_SARX,
X86_INS_SBB,
- X86_INS_SCASW,
+ X86_INS_SCASB,
X86_INS_SCASD,
X86_INS_SCASQ,
- X86_INS_SCASB,
+ X86_INS_SCASW,
X86_INS_SETAE,
X86_INS_SETA,
X86_INS_SETBE,
@@ -798,7 +907,6 @@ typedef enum x86_insn {
X86_INS_SQRTSD,
X86_INS_SQRTSS,
X86_INS_FSQRT,
- X86_INS_SS,
X86_INS_STAC,
X86_INS_STC,
X86_INS_STD,
@@ -870,6 +978,8 @@ typedef enum x86_insn {
X86_INS_VBLENDVPS,
X86_INS_VBROADCASTF128,
X86_INS_VBROADCASTI128,
+ X86_INS_VBROADCASTI32X4,
+ X86_INS_VBROADCASTI64X4,
X86_INS_VBROADCASTSD,
X86_INS_VBROADCASTSS,
X86_INS_VCMPPD,
@@ -1004,6 +1114,14 @@ typedef enum x86_insn {
X86_INS_VXORPS,
X86_INS_VGATHERDPD,
X86_INS_VGATHERDPS,
+ X86_INS_VGATHERPF0DPD,
+ X86_INS_VGATHERPF0DPS,
+ X86_INS_VGATHERPF0QPD,
+ X86_INS_VGATHERPF0QPS,
+ X86_INS_VGATHERPF1DPD,
+ X86_INS_VGATHERPF1DPS,
+ X86_INS_VGATHERPF1QPD,
+ X86_INS_VGATHERPF1QPS,
X86_INS_VGATHERQPD,
X86_INS_VGATHERQPS,
X86_INS_VHADDPD,
@@ -1042,8 +1160,10 @@ typedef enum x86_insn {
X86_INS_VMOVDQA32,
X86_INS_VMOVDQA64,
X86_INS_VMOVDQA,
+ X86_INS_VMOVDQU16,
X86_INS_VMOVDQU32,
X86_INS_VMOVDQU64,
+ X86_INS_VMOVDQU8,
X86_INS_VMOVDQU,
X86_INS_VMOVHLPS,
X86_INS_VMOVHPD,
@@ -1194,6 +1314,8 @@ typedef enum x86_insn {
X86_INS_VPINSRD,
X86_INS_VPINSRQ,
X86_INS_VPINSRW,
+ X86_INS_VPLZCNTD,
+ X86_INS_VPLZCNTQ,
X86_INS_VPMACSDD,
X86_INS_VPMACSDQH,
X86_INS_VPMACSDQL,
@@ -1360,6 +1482,14 @@ typedef enum x86_insn {
X86_INS_VRSQRTSS,
X86_INS_VSCATTERDPD,
X86_INS_VSCATTERDPS,
+ X86_INS_VSCATTERPF0DPD,
+ X86_INS_VSCATTERPF0DPS,
+ X86_INS_VSCATTERPF0QPD,
+ X86_INS_VSCATTERPF0QPS,
+ X86_INS_VSCATTERPF1DPD,
+ X86_INS_VSCATTERPF1DPS,
+ X86_INS_VSCATTERPF1QPD,
+ X86_INS_VSCATTERPF1QPS,
X86_INS_VSCATTERQPD,
X86_INS_VSCATTERQPS,
X86_INS_VSHUFPD,
@@ -1452,6 +1582,13 @@ typedef enum x86_insn_group {
X86_GRP_TBM,
X86_GRP_16BITMODE,
X86_GRP_NOT64BITMODE,
+ X86_GRP_SGX,
+ X86_GRP_DQI,
+ X86_GRP_BWI,
+ X86_GRP_PFI,
+ X86_GRP_VLX,
+ X86_GRP_SMAP,
+ X86_GRP_NOVLX,
X86_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)
X86_GRP_VM, // all virtualization instructions (VT-x + AMD-V)
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