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Created September 24, 2014 15:12
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Changes from "next" to "v3" - with changes on instruction REMOVED (to keep it short)
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gistfile1.diff
diff -Nurp capstone-next.git/include/arm.h capstone-v3.git/include/arm.h
--- capstone-next.git/include/arm.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/arm.h 2014-09-24 22:57:32.000000000 +0800
@@ -50,6 +50,53 @@ typedef enum arm_cc {
ARM_CC_AL // Always (unconditional) Always (unconditional)
} arm_cc;
+typedef enum arm_sysreg {
+ //> Special registers for MSR
+ ARM_SYSREG_INVALID = 0,
+
+ // SPSR* registers can be OR combined
+ ARM_SYSREG_SPSR_C = 1,
+ ARM_SYSREG_SPSR_X = 2,
+ ARM_SYSREG_SPSR_S = 4,
+ ARM_SYSREG_SPSR_F = 8,
+
+ // CPSR* registers can be OR combined
+ ARM_SYSREG_CPSR_C = 16,
+ ARM_SYSREG_CPSR_X = 32,
+ ARM_SYSREG_CPSR_S = 64,
+ ARM_SYSREG_CPSR_F = 128,
+
+ // independent registers
+ ARM_SYSREG_APSR = 256,
+ ARM_SYSREG_APSR_G,
+ ARM_SYSREG_APSR_NZCVQ,
+ ARM_SYSREG_APSR_NZCVQG,
+
+ ARM_SYSREG_IAPSR,
+ ARM_SYSREG_IAPSR_G,
+ ARM_SYSREG_IAPSR_NZCVQG,
+
+ ARM_SYSREG_EAPSR,
+ ARM_SYSREG_EAPSR_G,
+ ARM_SYSREG_EAPSR_NZCVQG,
+
+ ARM_SYSREG_XPSR,
+ ARM_SYSREG_XPSR_G,
+ ARM_SYSREG_XPSR_NZCVQG,
+
+ ARM_SYSREG_IPSR,
+ ARM_SYSREG_EPSR,
+ ARM_SYSREG_IEPSR,
+
+ ARM_SYSREG_MSP,
+ ARM_SYSREG_PSP,
+ ARM_SYSREG_PRIMASK,
+ ARM_SYSREG_BASEPRI,
+ ARM_SYSREG_BASEPRI_MAX,
+ ARM_SYSREG_FAULTMASK,
+ ARM_SYSREG_CONTROL,
+} arm_sysreg;
+
//> Operand type for instruction's operands
typedef enum arm_op_type {
ARM_OP_INVALID = 0, // Uninitialized.
@@ -59,8 +106,88 @@ typedef enum arm_op_type {
ARM_OP_IMM, // Immediate operand.
ARM_OP_FP, // Floating-Point immediate operand.
ARM_OP_MEM, // Memory operand
+ ARM_OP_SETEND, // operand for SETEND instruction
+ ARM_OP_SYSREG, // MSR/MSR special register operand
} arm_op_type;
+//> Operand type for SETEND instruction
+typedef enum arm_setend_type {
+ ARM_SETEND_INVALID = 0, // Uninitialized.
+ ARM_SETEND_BE, // BE operand.
+ ARM_SETEND_LE, // LE operand
+} arm_setend_type;
+
+typedef enum arm_cpsmode_type {
+ ARM_CPSMODE_INVALID = 0,
+ ARM_CPSMODE_IE = 2,
+ ARM_CPSMODE_ID = 3
+} arm_cpsmode_type;
+
+//> Operand type for SETEND instruction
+typedef enum arm_cpsflag_type {
+ ARM_CPSFLAG_INVALID = 0,
+ ARM_CPSFLAG_F = 1,
+ ARM_CPSFLAG_I = 2,
+ ARM_CPSFLAG_A = 4,
+ ARM_CPSFLAG_NONE = 16, // no flag
+} arm_cpsflag_type;
+
+//> Data type for elements of vector instructions.
+typedef enum arm_vectordata_type {
+ ARM_VECTORDATA_INVALID = 0,
+
+ // Integer type
+ ARM_VECTORDATA_I8,
+ ARM_VECTORDATA_I16,
+ ARM_VECTORDATA_I32,
+ ARM_VECTORDATA_I64,
+
+ // Signed integer type
+ ARM_VECTORDATA_S8,
+ ARM_VECTORDATA_S16,
+ ARM_VECTORDATA_S32,
+ ARM_VECTORDATA_S64,
+
+ // Unsigned integer type
+ ARM_VECTORDATA_U8,
+ ARM_VECTORDATA_U16,
+ ARM_VECTORDATA_U32,
+ ARM_VECTORDATA_U64,
+
+ // Data type for VMUL/VMULL
+ ARM_VECTORDATA_P8,
+
+ // Floating type
+ ARM_VECTORDATA_F32,
+ ARM_VECTORDATA_F64,
+
+ // Convert float <-> float
+ ARM_VECTORDATA_F16F64, // f16.f64
+ ARM_VECTORDATA_F64F16, // f64.f16
+ ARM_VECTORDATA_F32F16, // f32.f16
+ ARM_VECTORDATA_F16F32, // f32.f16
+ ARM_VECTORDATA_F64F32, // f64.f32
+ ARM_VECTORDATA_F32F64, // f32.f64
+
+ // Convert integer <-> float
+ ARM_VECTORDATA_S32F32, // s32.f32
+ ARM_VECTORDATA_U32F32, // u32.f32
+ ARM_VECTORDATA_F32S32, // f32.s32
+ ARM_VECTORDATA_F32U32, // f32.u32
+ ARM_VECTORDATA_F64S16, // f64.s16
+ ARM_VECTORDATA_F32S16, // f32.s16
+ ARM_VECTORDATA_F64S32, // f64.s32
+ ARM_VECTORDATA_S16F64, // s16.f64
+ ARM_VECTORDATA_S16F32, // s16.f64
+ ARM_VECTORDATA_S32F64, // s32.f64
+ ARM_VECTORDATA_U16F64, // u16.f64
+ ARM_VECTORDATA_U16F32, // u16.f32
+ ARM_VECTORDATA_U32F64, // u32.f64
+ ARM_VECTORDATA_F64U16, // f64.u16
+ ARM_VECTORDATA_F32U16, // f32.u16
+ ARM_VECTORDATA_F64U32, // f64.u32
+} arm_vectordata_type;
+
// Instruction's operand referring to memory
// This is associated with ARM_OP_MEM operand type above
typedef struct arm_op_mem {
@@ -72,21 +199,28 @@ typedef struct arm_op_mem {
// Instruction operand
typedef struct cs_arm_op {
+ int vector_index; // Vector Index for some vector operands (or -1 if irrelevant)
struct {
arm_shifter type;
unsigned int value;
} shift;
arm_op_type type; // operand type
union {
- unsigned int reg; // register value for REG operand
+ unsigned int reg; // register value for REG/SYSREG operand
int32_t imm; // immediate value for C-IMM, P-IMM or IMM operand
double fp; // floating point value for FP operand
arm_op_mem mem; // base/index/scale/disp value for MEM operand
+ arm_setend_type setend; // SETEND instruction's operand type
};
} cs_arm_op;
// Instruction structure
typedef struct cs_arm {
+ bool usermode; // User-mode registers to be loaded (for LDM/STM instructions)
+ int vector_size; // Scalar size for vector instructions
+ arm_vectordata_type vector_data; // Data type for elements of vector instructions
+ arm_cpsmode_type cps_mode; // CPS mode for CPS instruction
+ arm_cpsflag_type cps_flag; // CPS mode for CPS instruction
arm_cc cc; // conditional code for this insn
bool update_flags; // does this insn update flags?
bool writeback; // does this insn write-back?
diff -Nurp capstone-next.git/include/arm64.h capstone-v3.git/include/arm64.h
--- capstone-next.git/include/arm64.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/arm64.h 2014-09-24 22:57:32.000000000 +0800
@@ -61,6 +61,175 @@ typedef enum arm64_cc {
// is "always".
} arm64_cc;
+//> System registers
+typedef enum arm64_mrs_reg {
+ //> System registers for MRS
+ ARM64_SYSREG_INVALID = 0,
+ ARM64_SYSREG_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
+ ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
+ ARM64_SYSREG_MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
+ ARM64_SYSREG_OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
+ ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
+ ARM64_SYSREG_PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
+ ARM64_SYSREG_PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
+ ARM64_SYSREG_MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
+ ARM64_SYSREG_CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
+ ARM64_SYSREG_CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
+ ARM64_SYSREG_CTR_EL0 = 0xd801, // 11 011 0000 0000 001
+ ARM64_SYSREG_MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
+ ARM64_SYSREG_REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
+ ARM64_SYSREG_AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
+ ARM64_SYSREG_DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
+ ARM64_SYSREG_ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
+ ARM64_SYSREG_ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
+ ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
+ ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
+ ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
+ ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
+ ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
+ ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
+ ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
+ ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
+ ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
+ ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
+ ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
+ ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
+ ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
+ ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
+ ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
+ ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
+ ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
+ ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
+ ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
+ ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
+ ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
+ ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
+ ARM64_SYSREG_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
+ ARM64_SYSREG_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
+ ARM64_SYSREG_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
+ ARM64_SYSREG_RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
+ ARM64_SYSREG_RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
+ ARM64_SYSREG_RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
+ ARM64_SYSREG_ISR_EL1 = 0xc608, // 11 000 1100 0001 000
+ ARM64_SYSREG_CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
+ ARM64_SYSREG_CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
+
+ // Trace registers
+ ARM64_SYSREG_TRCSTATR = 0x8818, // 10 001 0000 0011 000
+ ARM64_SYSREG_TRCIDR8 = 0x8806, // 10 001 0000 0000 110
+ ARM64_SYSREG_TRCIDR9 = 0x880e, // 10 001 0000 0001 110
+ ARM64_SYSREG_TRCIDR10 = 0x8816, // 10 001 0000 0010 110
+ ARM64_SYSREG_TRCIDR11 = 0x881e, // 10 001 0000 0011 110
+ ARM64_SYSREG_TRCIDR12 = 0x8826, // 10 001 0000 0100 110
+ ARM64_SYSREG_TRCIDR13 = 0x882e, // 10 001 0000 0101 110
+ ARM64_SYSREG_TRCIDR0 = 0x8847, // 10 001 0000 1000 111
+ ARM64_SYSREG_TRCIDR1 = 0x884f, // 10 001 0000 1001 111
+ ARM64_SYSREG_TRCIDR2 = 0x8857, // 10 001 0000 1010 111
+ ARM64_SYSREG_TRCIDR3 = 0x885f, // 10 001 0000 1011 111
+ ARM64_SYSREG_TRCIDR4 = 0x8867, // 10 001 0000 1100 111
+ ARM64_SYSREG_TRCIDR5 = 0x886f, // 10 001 0000 1101 111
+ ARM64_SYSREG_TRCIDR6 = 0x8877, // 10 001 0000 1110 111
+ ARM64_SYSREG_TRCIDR7 = 0x887f, // 10 001 0000 1111 111
+ ARM64_SYSREG_TRCOSLSR = 0x888c, // 10 001 0001 0001 100
+ ARM64_SYSREG_TRCPDSR = 0x88ac, // 10 001 0001 0101 100
+ ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
+ ARM64_SYSREG_TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
+ ARM64_SYSREG_TRCLSR = 0x8bee, // 10 001 0111 1101 110
+ ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
+ ARM64_SYSREG_TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
+ ARM64_SYSREG_TRCDEVID = 0x8b97, // 10 001 0111 0010 111
+ ARM64_SYSREG_TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
+ ARM64_SYSREG_TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
+ ARM64_SYSREG_TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
+ ARM64_SYSREG_TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
+ ARM64_SYSREG_TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
+ ARM64_SYSREG_TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
+ ARM64_SYSREG_TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
+ ARM64_SYSREG_TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
+ ARM64_SYSREG_TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
+ ARM64_SYSREG_TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
+ ARM64_SYSREG_TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
+ ARM64_SYSREG_TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
+ ARM64_SYSREG_TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
+
+ // GICv3 registers
+ ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
+ ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
+ ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
+ ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
+ ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
+ ARM64_SYSREG_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
+ ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
+ ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101
+} arm64_sysreg;
+
+typedef enum arm64_msr_reg {
+ //> System registers for MSR
+ ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
+ ARM64_SYSREG_OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
+ ARM64_SYSREG_PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
+
+ // Trace Registers
+ ARM64_SYSREG_TRCOSLAR = 0x8884, // 10 001 0001 0000 100
+ ARM64_SYSREG_TRCLAR = 0x8be6, // 10 001 0111 1100 110
+
+ // GICv3 registers
+ ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
+ ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
+ ARM64_SYSREG_ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
+ ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
+ ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
+ ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111
+} arm64_msr_reg;
+
+//> System PState Field (MSR instruction)
+typedef enum arm64_pstate {
+ ARM64_PSTATE_INVALID = 0,
+ ARM64_PSTATE_SPSEL = 0x05,
+ ARM64_PSTATE_DAIFSET = 0x1e,
+ ARM64_PSTATE_DAIFCLR = 0x1f
+} arm64_pstate;
+
+//> Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)
+typedef enum arm64_vas {
+ ARM64_VAS_INVALID = 0,
+ ARM64_VAS_8B,
+ ARM64_VAS_16B,
+ ARM64_VAS_4H,
+ ARM64_VAS_8H,
+ ARM64_VAS_2S,
+ ARM64_VAS_4S,
+ ARM64_VAS_1D,
+ ARM64_VAS_2D,
+ ARM64_VAS_1Q,
+} arm64_vas;
+
+//> Vector element size specifier
+typedef enum arm64_vess {
+ ARM64_VESS_INVALID = 0,
+ ARM64_VESS_B,
+ ARM64_VESS_H,
+ ARM64_VESS_S,
+ ARM64_VESS_D,
+} arm64_vess;
+
+//> Memory barrier operands
+typedef enum arm64_barrier_op {
+ ARM64_BARRIER_INVALID = 0,
+ ARM64_BARRIER_OSHLD = 0x1,
+ ARM64_BARRIER_OSHST = 0x2,
+ ARM64_BARRIER_OSH = 0x3,
+ ARM64_BARRIER_NSHLD = 0x5,
+ ARM64_BARRIER_NSHST = 0x6,
+ ARM64_BARRIER_NSH = 0x7,
+ ARM64_BARRIER_ISHLD = 0x9,
+ ARM64_BARRIER_ISHST = 0xa,
+ ARM64_BARRIER_ISH = 0xb,
+ ARM64_BARRIER_LD = 0xd,
+ ARM64_BARRIER_ST = 0xe,
+ ARM64_BARRIER_SY = 0xf
+} arm64_barrier_op;
+
//> Operand type for instruction's operands
typedef enum arm64_op_type {
ARM64_OP_INVALID = 0, // Uninitialized.
@@ -69,8 +238,111 @@ typedef enum arm64_op_type {
ARM64_OP_IMM, // Immediate operand.
ARM64_OP_FP, // Floating-Point immediate operand.
ARM64_OP_MEM, // Memory operand
+ ARM64_OP_REG_MRS, // MRS register operand.
+ ARM64_OP_REG_MSR, // MSR register operand.
+ ARM64_OP_PSTATE, // PState operand.
+ ARM64_OP_SYS, // SYS operand for IC/DC/AT/TLBI instructions.
+ ARM64_OP_PREFETCH, // Prefetch operand (PRFM).
+ ARM64_OP_BARRIER, // Memory barrier operand (ISB/DMB/DSB instructions).
} arm64_op_type;
+//> TLBI operations
+typedef enum arm64_tlbi_op {
+ ARM64_TLBI_INVALID = 0,
+ ARM64_TLBI_VMALLE1IS,
+ ARM64_TLBI_VAE1IS,
+ ARM64_TLBI_ASIDE1IS,
+ ARM64_TLBI_VAAE1IS,
+ ARM64_TLBI_VALE1IS,
+ ARM64_TLBI_VAALE1IS,
+ ARM64_TLBI_ALLE2IS,
+ ARM64_TLBI_VAE2IS,
+ ARM64_TLBI_ALLE1IS,
+ ARM64_TLBI_VALE2IS,
+ ARM64_TLBI_VMALLS12E1IS,
+ ARM64_TLBI_ALLE3IS,
+ ARM64_TLBI_VAE3IS,
+ ARM64_TLBI_VALE3IS,
+ ARM64_TLBI_IPAS2E1IS,
+ ARM64_TLBI_IPAS2LE1IS,
+ ARM64_TLBI_IPAS2E1,
+ ARM64_TLBI_IPAS2LE1,
+ ARM64_TLBI_VMALLE1,
+ ARM64_TLBI_VAE1,
+ ARM64_TLBI_ASIDE1,
+ ARM64_TLBI_VAAE1,
+ ARM64_TLBI_VALE1,
+ ARM64_TLBI_VAALE1,
+ ARM64_TLBI_ALLE2,
+ ARM64_TLBI_VAE2,
+ ARM64_TLBI_ALLE1,
+ ARM64_TLBI_VALE2,
+ ARM64_TLBI_VMALLS12E1,
+ ARM64_TLBI_ALLE3,
+ ARM64_TLBI_VAE3,
+ ARM64_TLBI_VALE3,
+} arm64_tlbi_op;
+
+//> AT operations
+typedef enum arm64_at_op {
+ ARM64_AT_S1E1R,
+ ARM64_AT_S1E1W,
+ ARM64_AT_S1E0R,
+ ARM64_AT_S1E0W,
+ ARM64_AT_S1E2R,
+ ARM64_AT_S1E2W,
+ ARM64_AT_S12E1R,
+ ARM64_AT_S12E1W,
+ ARM64_AT_S12E0R,
+ ARM64_AT_S12E0W,
+ ARM64_AT_S1E3R,
+ ARM64_AT_S1E3W,
+} arm64_at_op;
+
+//> DC operations
+typedef enum arm64_dc_op {
+ ARM64_DC_INVALID = 0,
+ ARM64_DC_ZVA,
+ ARM64_DC_IVAC,
+ ARM64_DC_ISW,
+ ARM64_DC_CVAC,
+ ARM64_DC_CSW,
+ ARM64_DC_CVAU,
+ ARM64_DC_CIVAC,
+ ARM64_DC_CISW,
+} arm64_dc_op;
+
+//> IC operations
+typedef enum arm64_ic_op {
+ ARM64_IC_INVALID = 0,
+ ARM64_IC_IALLUIS,
+ ARM64_IC_IALLU,
+ ARM64_IC_IVAU,
+} arm64_ic_op;
+
+//> Prefetch operations (PRFM)
+typedef enum arm64_prefetch_op {
+ ARM64_PRFM_INVALID = 0,
+ ARM64_PRFM_PLDL1KEEP = 0x00 + 1,
+ ARM64_PRFM_PLDL1STRM = 0x01 + 1,
+ ARM64_PRFM_PLDL2KEEP = 0x02 + 1,
+ ARM64_PRFM_PLDL2STRM = 0x03 + 1,
+ ARM64_PRFM_PLDL3KEEP = 0x04 + 1,
+ ARM64_PRFM_PLDL3STRM = 0x05 + 1,
+ ARM64_PRFM_PLIL1KEEP = 0x08 + 1,
+ ARM64_PRFM_PLIL1STRM = 0x09 + 1,
+ ARM64_PRFM_PLIL2KEEP = 0x0a + 1,
+ ARM64_PRFM_PLIL2STRM = 0x0b + 1,
+ ARM64_PRFM_PLIL3KEEP = 0x0c + 1,
+ ARM64_PRFM_PLIL3STRM = 0x0d + 1,
+ ARM64_PRFM_PSTL1KEEP = 0x10 + 1,
+ ARM64_PRFM_PSTL1STRM = 0x11 + 1,
+ ARM64_PRFM_PSTL2KEEP = 0x12 + 1,
+ ARM64_PRFM_PSTL2STRM = 0x13 + 1,
+ ARM64_PRFM_PSTL3KEEP = 0x14 + 1,
+ ARM64_PRFM_PSTL3STRM = 0x15 + 1,
+} arm64_prefetch_op;
+
// Instruction's operand referring to memory
// This is associated with ARM64_OP_MEM operand type above
typedef struct arm64_op_mem {
@@ -81,6 +353,9 @@ typedef struct arm64_op_mem {
// Instruction operand
typedef struct cs_arm64_op {
+ int vector_index; // Vector Index for some vector operands (or -1 if irrelevant)
+ arm64_vas vas; // Vector Arrangement Specifier
+ arm64_vess vess; // Vector Element Size Specifier
struct {
arm64_shifter type; // shifter type of this operand
unsigned int value; // shifter value of this operand
@@ -92,6 +367,10 @@ typedef struct cs_arm64_op {
int32_t imm; // immediate value, or index for C-IMM or IMM operand
double fp; // floating point value for FP operand
arm64_op_mem mem; // base/index/scale/disp value for MEM operand
+ arm64_pstate pstate; // PState field of MSR instruction.
+ unsigned int sys; // IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op)
+ arm64_prefetch_op prefetch; // PRFM operation.
+ arm64_barrier_op barrier; // Memory barrier operation (ISB/DMB/DSB instructions).
};
} cs_arm64_op;
@@ -812,6 +1134,7 @@ typedef enum arm64_insn_group {
ARM64_GRP_CRYPTO,
ARM64_GRP_FPARMV8,
ARM64_GRP_NEON,
+ ARM64_GRP_CRC,
ARM64_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)
diff -Nurp capstone-next.git/include/capstone.h capstone-v3.git/include/capstone.h
--- capstone-next.git/include/capstone.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/capstone.h 2014-09-24 22:57:32.000000000 +0800
@@ -27,9 +27,18 @@ extern "C" {
#define CAPSTONE_EXPORT
#endif
+#ifdef __GNUC__
+#define CAPSTONE_DEPRECATED __attribute__((deprecated))
+#elif defined(_MSC_VER)
+#define CAPSTONE_DEPRECATED __declspec(deprecated)
+#else
+#pragma message("WARNING: You need to implement CAPSTONE_DEPRECATED for this compiler")
+#define CAPSTONE_DEPRECATED
+#endif
+
// Capstone API version
-#define CS_API_MAJOR 2
-#define CS_API_MINOR 2
+#define CS_API_MAJOR 3
+#define CS_API_MINOR 0
// Macro to create combined version which can be compared to
// result of cs_version() API.
@@ -70,8 +79,12 @@ typedef enum cs_mode {
CS_MODE_32 = 1 << 2, // 32-bit mode
CS_MODE_64 = 1 << 3, // 64-bit mode
CS_MODE_THUMB = 1 << 4, // ARM's Thumb mode, including Thumb-2
+ CS_MODE_MCLASS = 1 << 5, // ARM's Cortex-M series
CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS architecture)
CS_MODE_N64 = 1 << 5, // Nintendo-64 mode (MIPS architecture)
+ CS_MODE_MIPS3 = 1 << 6, // Mips III ISA
+ CS_MODE_MIPS32R6 = 1 << 7, // Mips32r6 ISA
+ CS_MODE_MIPSGP64 = 1 << 8, // General Purpose Registers are 64-bit wide (MIPS arch)
CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc architecture)
CS_MODE_BIG_ENDIAN = 1 << 31 // big endian mode
} cs_mode;
@@ -115,7 +128,7 @@ typedef enum cs_opt_value {
// User-defined callback function for SKIPDATA option
// @code: the input buffer containing code to be disassembled. This is the
-// same buffer passed to cs_disasm_ex().
+// same buffer passed to cs_disasm().
// @code_size: size (in bytes) of the above @code buffer.
// @offset: the position of the currently-examining byte in the input
// buffer @code mentioned above.
@@ -128,14 +141,14 @@ typedef size_t (*cs_skipdata_cb_t)(const
typedef struct cs_opt_skipdata {
// Capstone considers data to skip as special "instructions".
// User can specify the string for this instruction's "mnemonic" here.
- // By default (if @mnemonic is NULL), Capstone use ".db".
+ // By default (if @mnemonic is NULL), Capstone use ".byte".
const char *mnemonic;
// User-defined callback function to be called when Capstone hits data.
// If the returned value from this callback is positive (>0), Capstone
// will skip exactly that number of bytes & continue. Otherwise, if
// the callback returns 0, Capstone stops disassembling and returns
- // immediately from cs_disasm_ex()
+ // immediately from cs_disasm()
// NOTE: if this callback pointer is NULL, Capstone would skip a number
// of bytes depending on architectures, as following:
// Arm: 2 bytes (Thumb mode) or 4 bytes.
@@ -232,7 +245,7 @@ typedef struct cs_insn {
// These are values returned by cs_errno()
typedef enum cs_err {
CS_ERR_OK = 0, // No error: everything was fine
- CS_ERR_MEM, // Out-Of-Memory error: cs_open(), cs_disasm_ex()
+ CS_ERR_MEM, // Out-Of-Memory error: cs_open(), cs_disasm()
CS_ERR_ARCH, // Unsupported architecture: cs_open()
CS_ERR_HANDLE, // Invalid handle: cs_op_count(), cs_op_index()
CS_ERR_CSH, // Invalid csh argument: cs_close(), cs_errno(), cs_option()
@@ -376,23 +389,33 @@ const char *cs_strerror(cs_err code);
On failure, call cs_errno() for error code.
*/
CAPSTONE_EXPORT
-size_t cs_disasm_ex(csh handle,
+size_t cs_disasm(csh handle,
const uint8_t *code, size_t code_size,
uint64_t address,
size_t count,
cs_insn **insn);
+/* Deprecated function - to be retired in the next version!
+ Use cs_disasm() instead of cs_disasm_ex()
+*/
+CAPSTONE_EXPORT
+CAPSTONE_DEPRECATED
+size_t cs_disasm_ex(csh handle,
+ const uint8_t *code, size_t code_size,
+ uint64_t address,
+ size_t count,
+ cs_insn **insn);
/*
- Free memory allocated in @insn by cs_disasm_ex()
+ Free memory allocated in @insn by cs_disasm()
- @insn: pointer returned by @insn argument in cs_disasm_ex()
- @count: number of cs_insn structures returned by cs_disasm_ex()
+ @insn: pointer returned by @insn argument in cs_disasm()
+ @count: number of cs_insn structures returned by cs_disasm()
*/
CAPSTONE_EXPORT
void cs_free(cs_insn *insn, size_t count);
/*
- Return friendly name of regiser in a string
+ Return friendly name of regiser in a string.
Find the instruction id from header file of corresponding architecture (arm.h for ARM,
x86.h for X86, ...)
@@ -400,21 +423,21 @@ void cs_free(cs_insn *insn, size_t count
store register name.
@handle: handle returned by cs_open()
- @reg: register id
+ @reg_id: register id
@return: string name of the register, or NULL if @reg_id is invalid.
*/
CAPSTONE_EXPORT
const char *cs_reg_name(csh handle, unsigned int reg_id);
/*
- Return friendly name of an instruction in a string
+ Return friendly name of an instruction in a string.
Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
store instruction name.
@handle: handle returned by cs_open()
- @insn: instruction id
+ @insn_id: instruction id
@return: string name of the instruction, or NULL if @insn_id is invalid.
*/
@@ -422,6 +445,21 @@ CAPSTONE_EXPORT
const char *cs_insn_name(csh handle, unsigned int insn_id);
/*
+ Return friendly name of a group id (that an instruction can belong to)
+ Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ store group name.
+
+ @handle: handle returned by cs_open()
+ @group_id: group id
+
+ @return: string name of the group, or NULL if @group_id is invalid.
+*/
+CAPSTONE_EXPORT
+const char *cs_group_name(csh handle, unsigned int insn_id);
+
+/*
Check if a disassembled instruction belong to a particular group.
Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
Internally, this simply verifies if @group_id matches any member of insn->groups array.
@@ -432,7 +470,7 @@ const char *cs_insn_name(csh handle, uns
update @groups array.
@handle: handle returned by cs_open()
- @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm()
@group_id: group that you want to check if this instruction belong to.
@return: true if this instruction indeed belongs to aboved group, or false otherwise.
@@ -450,7 +488,7 @@ bool cs_insn_group(csh handle, const cs_
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
update @regs_read array.
- @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm()
@reg_id: register that you want to check if this instruction used it.
@return: true if this instruction indeed implicitly used aboved register, or false otherwise.
@@ -468,7 +506,7 @@ bool cs_reg_read(csh handle, const cs_in
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
update @regs_write array.
- @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm()
@reg_id: register that you want to check if this instruction modified it.
@return: true if this instruction indeed implicitly modified aboved register, or false otherwise.
@@ -483,7 +521,7 @@ bool cs_reg_write(csh handle, const cs_i
NOTE: this API is only valid when detail option is ON (which is OFF by default)
@handle: handle returned by cs_open()
- @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm()
@op_type: Operand type to be found.
@return: number of operands of given type @op_type in instruction @insn,
@@ -500,7 +538,7 @@ int cs_op_count(csh handle, const cs_ins
NOTE: this API is only valid when detail option is ON (which is OFF by default)
@handle: handle returned by cs_open()
- @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm()
@op_type: Operand type to be found.
@position: position of the operand to be found. This must be in the range
[1, cs_op_count(handle, insn, op_type)]
diff -Nurp capstone-next.git/include/mips.h capstone-v3.git/include/mips.h
--- capstone-next.git/include/mips.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/mips.h 2014-09-24 22:57:32.000000000 +0800
@@ -55,7 +55,7 @@ typedef struct cs_mips {
//> MIPS registers
typedef enum mips_reg {
MIPS_REG_INVALID = 0,
- // General purpose registers
+ //> General purpose registers
MIPS_REG_0,
MIPS_REG_1,
MIPS_REG_2,
@@ -89,7 +89,7 @@ typedef enum mips_reg {
MIPS_REG_30,
MIPS_REG_31,
- // DSP registers
+ //> DSP registers
MIPS_REG_DSPCCOND,
MIPS_REG_DSPCARRY,
MIPS_REG_DSPEFI,
@@ -102,13 +102,23 @@ typedef enum mips_reg {
MIPS_REG_DSPPOS,
MIPS_REG_DSPSCOUNT,
- // ACC registers
+ //> ACC registers
MIPS_REG_AC0,
MIPS_REG_AC1,
MIPS_REG_AC2,
MIPS_REG_AC3,
- // FPU registers
+ //> COP registers
+ MIPS_REG_CC0,
+ MIPS_REG_CC1,
+ MIPS_REG_CC2,
+ MIPS_REG_CC3,
+ MIPS_REG_CC4,
+ MIPS_REG_CC5,
+ MIPS_REG_CC6,
+ MIPS_REG_CC7,
+
+ //> FPU registers
MIPS_REG_F0,
MIPS_REG_F1,
MIPS_REG_F2,
@@ -151,7 +161,7 @@ typedef enum mips_reg {
MIPS_REG_FCC6,
MIPS_REG_FCC7,
- // AFPR128
+ //> AFPR128
MIPS_REG_W0,
MIPS_REG_W1,
MIPS_REG_W2,
@@ -189,6 +199,14 @@ typedef enum mips_reg {
MIPS_REG_LO,
MIPS_REG_PC,
+ MIPS_REG_P0,
+ MIPS_REG_P1,
+ MIPS_REG_P2,
+
+ MIPS_REG_MPL0,
+ MIPS_REG_MPL1,
+ MIPS_REG_MPL2,
+
MIPS_REG_MAX, // <-- mark the end of the list or registers
// alias registers
@@ -723,6 +873,21 @@ typedef enum mips_insn_group {
MIPS_GRP_NOTFP64BIT,
MIPS_GRP_NOTINMICROMIPS,
MIPS_GRP_NOTNACL,
+ MIPS_GRP_NOTMIPS32R6,
+ MIPS_GRP_NOTMIPS64R6,
+ MIPS_GRP_CNMIPS,
+ MIPS_GRP_MIPS32,
+ MIPS_GRP_MIPS32R6,
+ MIPS_GRP_MIPS64R6,
+ MIPS_GRP_MIPS2,
+ MIPS_GRP_MIPS3,
+ MIPS_GRP_MIPS3_32,
+ MIPS_GRP_MIPS3_32R2,
+ MIPS_GRP_MIPS4_32,
+ MIPS_GRP_MIPS4_32R2,
+ MIPS_GRP_MIPS5_32R2,
+ MIPS_GRP_GP32BIT,
+ MIPS_GRP_GP64BIT,
MIPS_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)
diff -Nurp capstone-next.git/include/ppc.h capstone-v3.git/include/ppc.h
--- capstone-next.git/include/ppc.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/ppc.h 2014-09-24 22:57:32.000000000 +0800
@@ -17,6 +17,7 @@ extern "C" {
//> PPC branch codes for some branch instructions
typedef enum ppc_bc {
+ PPC_BC_INVALID = 0,
PPC_BC_LT = (0 << 5) | 12,
PPC_BC_LE = (1 << 5) | 4,
PPC_BC_EQ = (2 << 5) | 12,
@@ -25,27 +26,15 @@ typedef enum ppc_bc {
PPC_BC_NE = (2 << 5) | 4,
PPC_BC_UN = (3 << 5) | 12,
PPC_BC_NU = (3 << 5) | 4,
- PPC_BC_LT_MINUS = (0 << 5) | 14,
- PPC_BC_LE_MINUS = (1 << 5) | 6,
- PPC_BC_EQ_MINUS = (2 << 5) | 14,
- PPC_BC_GE_MINUS = (0 << 5) | 6,
- PPC_BC_GT_MINUS = (1 << 5) | 14,
- PPC_BC_NE_MINUS = (2 << 5) | 6,
- PPC_BC_UN_MINUS = (3 << 5) | 14,
- PPC_BC_NU_MINUS = (3 << 5) | 6,
- PPC_BC_LT_PLUS = (0 << 5) | 15,
- PPC_BC_LE_PLUS = (1 << 5) | 7,
- PPC_BC_EQ_PLUS = (2 << 5) | 15,
- PPC_BC_GE_PLUS = (0 << 5) | 7,
- PPC_BC_GT_PLUS = (1 << 5) | 15,
- PPC_BC_NE_PLUS = (2 << 5) | 7,
- PPC_BC_UN_PLUS = (3 << 5) | 15,
- PPC_BC_NU_PLUS = (3 << 5) | 7
+
+ // extra conditions
+ PPC_BC_SO = 4 << 5, // summary overflow
+ PPC_BC_NS = 4 << 5, // not summary overflow
} ppc_bc;
//> PPC branch hint for some branch instructions
typedef enum ppc_bh {
- PPC_BH_NO = 0, // no hint
+ PPC_BH_INVALID = 0, // no hint
PPC_BH_PLUS, // PLUS hint
PPC_BH_MINUS, // MINUS hint
} ppc_bh;
@@ -97,6 +86,7 @@ typedef enum ppc_reg {
PPC_REG_INVALID = 0,
PPC_REG_CARRY,
+ PPC_REG_CC,
PPC_REG_CR0,
PPC_REG_CR1,
PPC_REG_CR2,
@@ -105,30 +95,6 @@ typedef enum ppc_reg {
PPC_REG_CR5,
PPC_REG_CR6,
PPC_REG_CR7,
- PPC_REG_CR8,
- PPC_REG_CR9,
- PPC_REG_CR10,
- PPC_REG_CR11,
- PPC_REG_CR12,
- PPC_REG_CR13,
- PPC_REG_CR14,
- PPC_REG_CR15,
- PPC_REG_CR16,
- PPC_REG_CR17,
- PPC_REG_CR18,
- PPC_REG_CR19,
- PPC_REG_CR20,
- PPC_REG_CR21,
- PPC_REG_CR22,
- PPC_REG_CR23,
- PPC_REG_CR24,
- PPC_REG_CR25,
- PPC_REG_CR26,
- PPC_REG_CR27,
- PPC_REG_CR28,
- PPC_REG_CR29,
- PPC_REG_CR30,
- PPC_REG_CR31,
PPC_REG_CTR,
PPC_REG_F0,
PPC_REG_F1,
@@ -228,8 +194,72 @@ typedef enum ppc_reg {
PPC_REG_V30,
PPC_REG_V31,
PPC_REG_VRSAVE,
+ PPC_REG_VS0,
+ PPC_REG_VS1,
+ PPC_REG_VS2,
+ PPC_REG_VS3,
+ PPC_REG_VS4,
+ PPC_REG_VS5,
+ PPC_REG_VS6,
+ PPC_REG_VS7,
+ PPC_REG_VS8,
+ PPC_REG_VS9,
+ PPC_REG_VS10,
+ PPC_REG_VS11,
+ PPC_REG_VS12,
+ PPC_REG_VS13,
+ PPC_REG_VS14,
+ PPC_REG_VS15,
+ PPC_REG_VS16,
+ PPC_REG_VS17,
+ PPC_REG_VS18,
+ PPC_REG_VS19,
+ PPC_REG_VS20,
+ PPC_REG_VS21,
+ PPC_REG_VS22,
+ PPC_REG_VS23,
+ PPC_REG_VS24,
+ PPC_REG_VS25,
+ PPC_REG_VS26,
+ PPC_REG_VS27,
+ PPC_REG_VS28,
+ PPC_REG_VS29,
+ PPC_REG_VS30,
+ PPC_REG_VS31,
+ PPC_REG_VS32,
+ PPC_REG_VS33,
+ PPC_REG_VS34,
+ PPC_REG_VS35,
+ PPC_REG_VS36,
+ PPC_REG_VS37,
+ PPC_REG_VS38,
+ PPC_REG_VS39,
+ PPC_REG_VS40,
+ PPC_REG_VS41,
+ PPC_REG_VS42,
+ PPC_REG_VS43,
+ PPC_REG_VS44,
+ PPC_REG_VS45,
+ PPC_REG_VS46,
+ PPC_REG_VS47,
+ PPC_REG_VS48,
+ PPC_REG_VS49,
+ PPC_REG_VS50,
+ PPC_REG_VS51,
+ PPC_REG_VS52,
+ PPC_REG_VS53,
+ PPC_REG_VS54,
+ PPC_REG_VS55,
+ PPC_REG_VS56,
+ PPC_REG_VS57,
+ PPC_REG_VS58,
+ PPC_REG_VS59,
+ PPC_REG_VS60,
+ PPC_REG_VS61,
+ PPC_REG_VS62,
+ PPC_REG_VS63,
- // extra registers for mapping.c
+ // extra registers for PPCMapping.c
PPC_REG_RM,
PPC_REG_CTR8,
PPC_REG_LR8,
@@ -690,6 +1221,11 @@ typedef enum ppc_insn_group {
PPC_GRP_MODE64,
PPC_GRP_BOOKE,
PPC_GRP_NOTBOOKE,
+ PPC_GRP_SPE,
+ PPC_GRP_VSX,
+ PPC_GRP_E500,
+ PPC_GRP_PPC4XX,
+ PPC_GRP_PPC6XX,
PPC_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)
diff -Nurp capstone-next.git/include/sparc.h capstone-v3.git/include/sparc.h
--- capstone-next.git/include/sparc.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/sparc.h 2014-09-24 22:57:32.000000000 +0800
@@ -96,7 +96,7 @@ typedef struct cs_sparc_op {
// Instruction structure
typedef struct cs_sparc {
sparc_cc cc; // code condition for this insn
- sparc_hint hint; // branch hint: encoding as bitwise OR of SPARC_HINT_*.
+ sparc_hint hint; // branch hint: encoding as bitwise OR of sparc_hint.
// Number of operands of this instruction,
// or 0 when instruction has no operand.
uint8_t op_count;
@@ -194,6 +194,9 @@ typedef enum sparc_reg {
SPARC_REG_SP,
SPARC_REG_Y,
+ // special register
+ SPARC_REG_XCC,
+
SPARC_REG_MAX, // <-- mark the end of the list of registers
// extras
diff -Nurp capstone-next.git/include/systemz.h capstone-v3.git/include/systemz.h
--- capstone-next.git/include/systemz.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/systemz.h 2014-09-24 22:57:32.000000000 +0800
@@ -547,11 +547,14 @@ typedef enum sysz_insn {
SYSZ_INS_LDGR,
SYSZ_INS_LDR,
SYSZ_INS_LDXBR,
+ SYSZ_INS_LDXBRA,
SYSZ_INS_LDY,
SYSZ_INS_LE,
SYSZ_INS_LEDBR,
+ SYSZ_INS_LEDBRA,
SYSZ_INS_LER,
SYSZ_INS_LEXBR,
+ SYSZ_INS_LEXBRA,
SYSZ_INS_LEY,
SYSZ_INS_LFH,
SYSZ_INS_LG,
@@ -797,17 +800,18 @@ typedef enum sysz_insn {
SYSZ_INS_XR,
SYSZ_INS_XRK,
SYSZ_INS_XY,
+
SYSZ_INS_MAX, // <-- mark the end of the list of instructions
} sysz_insn;
//> Group of SystemZ instructions
typedef enum sysz_insn_group {
SYSZ_GRP_INVALID = 0,
- SYSZ_GRP_FEATUREDISTINCTOPS,
- SYSZ_GRP_FEATUREFPEXTENSION,
- SYSZ_GRP_FEATUREHIGHWORD,
- SYSZ_GRP_FEATUREINTERLOCKEDACCESS1,
- SYSZ_GRP_FEATURELOADSTOREONCOND,
+ SYSZ_GRP_DISTINCTOPS,
+ SYSZ_GRP_FPEXTENSION,
+ SYSZ_GRP_HIGHWORD,
+ SYSZ_GRP_INTERLOCKEDACCESS1,
+ SYSZ_GRP_LOADSTOREONCOND,
SYSZ_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)
diff -Nurp capstone-next.git/include/x86.h capstone-v3.git/include/x86.h
--- capstone-next.git/include/x86.h 2014-09-24 22:57:41.000000000 +0800
+++ capstone-v3.git/include/x86.h 2014-09-24 22:57:32.000000000 +0800
@@ -31,7 +31,7 @@ typedef enum x86_reg {
X86_REG_CR11, X86_REG_CR12, X86_REG_CR13, X86_REG_CR14, X86_REG_CR15,
X86_REG_DR0, X86_REG_DR1, X86_REG_DR2, X86_REG_DR3, X86_REG_DR4,
X86_REG_DR5, X86_REG_DR6, X86_REG_DR7, X86_REG_FP0, X86_REG_FP1,
- X86_REG_FP2, X86_REG_FP3, X86_REG_FP4, X86_REG_FP5, X86_REG_FP6,
+ X86_REG_FP2, X86_REG_FP3, X86_REG_FP4, X86_REG_FP5, X86_REG_FP6, X86_REG_FP7,
X86_REG_K0, X86_REG_K1, X86_REG_K2, X86_REG_K3, X86_REG_K4,
X86_REG_K5, X86_REG_K6, X86_REG_K7, X86_REG_MM0, X86_REG_MM1,
X86_REG_MM2, X86_REG_MM3, X86_REG_MM4, X86_REG_MM5, X86_REG_MM6,
@@ -76,12 +76,89 @@ typedef enum x86_op_type {
X86_OP_MEM, // Memory operand
} x86_op_type;
+//> AVX broadcast type
+typedef enum x86_avx_bcast {
+ X86_AVX_BCAST_INVALID = 0, // Uninitialized.
+ X86_AVX_BCAST_2, // AVX512 broadcast type {1to2}
+ X86_AVX_BCAST_4, // AVX512 broadcast type {1to4}
+ X86_AVX_BCAST_8, // AVX512 broadcast type {1to8}
+ X86_AVX_BCAST_16, // AVX512 broadcast type {1to16}
+} x86_avx_bcast;
+
+//> SSE Code Condition type
+typedef enum x86_sse_cc {
+ X86_SSE_CC_INVALID = 0, // Uninitialized.
+ X86_SSE_CC_EQ,
+ X86_SSE_CC_LT,
+ X86_SSE_CC_LE,
+ X86_SSE_CC_UNORD,
+ X86_SSE_CC_NEQ,
+ X86_SSE_CC_NLT,
+ X86_SSE_CC_NLE,
+ X86_SSE_CC_ORD,
+ X86_SSE_CC_EQ_UQ,
+ X86_SSE_CC_NGE,
+ X86_SSE_CC_NGT,
+ X86_SSE_CC_FALSE,
+ X86_SSE_CC_NEQ_OQ,
+ X86_SSE_CC_GE,
+ X86_SSE_CC_GT,
+ X86_SSE_CC_TRUE,
+} x86_sse_cc;
+
+//> AVX Code Condition type
+typedef enum x86_avx_cc {
+ X86_AVX_CC_INVALID = 0, // Uninitialized.
+ X86_AVX_CC_EQ,
+ X86_AVX_CC_LT,
+ X86_AVX_CC_LE,
+ X86_AVX_CC_UNORD,
+ X86_AVX_CC_NEQ,
+ X86_AVX_CC_NLT,
+ X86_AVX_CC_NLE,
+ X86_AVX_CC_ORD,
+ X86_AVX_CC_EQ_UQ,
+ X86_AVX_CC_NGE,
+ X86_AVX_CC_NGT,
+ X86_AVX_CC_FALSE,
+ X86_AVX_CC_NEQ_OQ,
+ X86_AVX_CC_GE,
+ X86_AVX_CC_GT,
+ X86_AVX_CC_TRUE,
+ X86_AVX_CC_EQ_OS,
+ X86_AVX_CC_LT_OQ,
+ X86_AVX_CC_LE_OQ,
+ X86_AVX_CC_UNORD_S,
+ X86_AVX_CC_NEQ_US,
+ X86_AVX_CC_NLT_UQ,
+ X86_AVX_CC_NLE_UQ,
+ X86_AVX_CC_ORD_S,
+ X86_AVX_CC_EQ_US,
+ X86_AVX_CC_NGE_UQ,
+ X86_AVX_CC_NGT_UQ,
+ X86_AVX_CC_FALSE_OS,
+ X86_AVX_CC_NEQ_OS,
+ X86_AVX_CC_GE_OQ,
+ X86_AVX_CC_GT_OQ,
+ X86_AVX_CC_TRUE_US,
+} x86_avx_cc;
+
+//> AVX static rounding mode type
+typedef enum x86_avx_rm {
+ X86_AVX_RM_INVALID = 0, // Uninitialized.
+ X86_AVX_RM_RN, // Round to nearest
+ X86_AVX_RM_RD, // Round down
+ X86_AVX_RM_RU, // Round up
+ X86_AVX_RM_RZ, // Round toward zero
+} x86_avx_rm;
+
// Instruction's operand referring to memory
// This is associated with X86_OP_MEM operand type above
typedef struct x86_op_mem {
- unsigned int base; // base register
- unsigned int index; // index register
- int scale; // scale for index register (can be 1, or -1)
+ unsigned int segment; // segment register (or X86_REG_INVALID if irrelevant)
+ unsigned int base; // base register (or X86_REG_INVALID if irrelevant)
+ unsigned int index; // index register (or X86_REG_INVALID if irrelevant)
+ int scale; // scale for index register
int64_t disp; // displacement value
} x86_op_mem;
@@ -94,36 +171,39 @@ typedef struct cs_x86_op {
double fp; // floating point value for FP operand
x86_op_mem mem; // base/index/scale/disp value for MEM operand
};
+
+ // size of this operand (in bytes).
+ uint8_t size;
+
+ // AVX broadcast type, or 0 if irrelevant
+ x86_avx_bcast avx_bcast;
+
+ // AVX zero opmask {z}
+ bool avx_zero_opmask;
} cs_x86_op;
// Instruction structure
typedef struct cs_x86 {
- // (Optional) instruction prefix, which can be up to 5 bytes.
+ // Instruction prefix, which can be up to 4 bytes.
// A prefix byte gets value 0 when irrelevant.
- uint8_t prefix[5];
+ // prefix[0] indicates REP/REPNE/LOCK prefix (0xf3/0xf2/0xf0 respectively)
+ // prefix[1] indicates segment override (irrelevant for x86_64):
+ // 0x2e = CS, 0x36 = SS, 0x3e = DS, 0x26 = ES, 0x64 = FS, 0x65 = GS
+ // prefix[2] indicates operand-size override (0x66)
+ // prefix[3] indicates address-size override (0x67)
+ uint8_t prefix[4];
- // (Optional) segment override, which can be among CS, DS, SS, ES, FS, GS.
- // This field get value 0 when irrelevant.
- x86_reg segment;
-
- // Instruction opcode, wich can be from 1 to 3 bytes in size.
+ // Instruction opcode, wich can be from 1 to 4 bytes in size.
// This contains VEX opcode as well.
- // An opcode byte gets value 0 when irrelevant.
- uint8_t opcode[3];
+ // An trailing opcode byte gets value 0 when irrelevant.
+ uint8_t opcode[4];
- // Operand size, which can be overrided with above prefix[5].
- uint8_t op_size;
+ // REX prefix: only a non-zero value is relavant for x86_64
+ uint8_t rex;
// Address size, which can be overrided with above prefix[5].
uint8_t addr_size;
- // Size of (optional) displacement.
- // This field get value 0 when irrelevant.
- uint8_t disp_size;
-
- // Size of immediate operand
- uint8_t imm_size;
-
// ModR/M byte
uint8_t modrm;
@@ -141,6 +221,18 @@ typedef struct cs_x86 {
// SIB base register, or X86_REG_INVALID when irrelevant.
x86_reg sib_base;
+ // SSE Code Condition
+ x86_sse_cc sse_cc;
+
+ // AVX Code Condition
+ x86_avx_cc avx_cc;
+
+ // AVX Suppress all Exception
+ bool avx_sae;
+
+ // AVX static rounding mode
+ x86_avx_rm avx_rm;
+
// Number of operands of this instruction,
// or 0 when instruction has no operand.
uint8_t op_count;
@@ -1452,6 +1582,13 @@ typedef enum x86_insn_group {
X86_GRP_TBM,
X86_GRP_16BITMODE,
X86_GRP_NOT64BITMODE,
+ X86_GRP_SGX,
+ X86_GRP_DQI,
+ X86_GRP_BWI,
+ X86_GRP_PFI,
+ X86_GRP_VLX,
+ X86_GRP_SMAP,
+ X86_GRP_NOVLX,
X86_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)
X86_GRP_VM, // all virtualization instructions (VT-x + AMD-V)
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