CS 352H Final Processor Architecture

352h-arch.txt

#CPU Architecture Specification for CS 352H - Fall 2012
 - Special Registers
 - Function Calls
 - Interrupts
 - Virtual Mem.
 - Register Windows
 - Memory Addressing Modes
 - Immediate Values

##Conventions
 - Big Endian
 - The "0" bit is the "leftmost" or greatest significance bit
 - The bits 0:5 on all instructions are reserved for the icode
 
##Special Registers
 - Null or Zero-source registers have historically been popular
   - Make it easy to zero registers
   - Make it easy to throw away the resulting value
   - Allows for some cute hacks with memory modes

##General Registers
32 registers
 
    0x1F - R31 - the link register
    0x1E - R30 - hardware zero value
    0x1D - R29 - the condition code register
    0x1C - R28 - the stack pointer __by convention__
        R27:R0 are entirely user-defined

##Immediate Values

    __li__ "Load Immediate"
        0:5   - icode
        6:10  - target register
        11:31 - value
        Loads the constant value to the targeted register

##Condition Code
The condition state of the processor is stored in regioster R29 and updated by
most instructions. R29 is a real register, and may be overwritten and read
directly using register-refferencing instructions.

####Bit Layout of the Condition Codes
    0 - Greater than
    1 - Less than
    2 - Above
    3 - Below
    4 - Equal    

##Arithmetic Operations
//These need argument specifications, bytecode IDs and condition code spec.
    __add__
    __sub__
    __div__
    __mod__
    __mul__
    __and__
    __or__
    __not__
    __xor__


##Function Calls
The first five arguments of all function calls go in registers R0:R4
The return value is placed in R0 in return

    __b__  "Branch"
        0:5   - instruction
        6:9   - base register
        10:31 - offset
        unconditionally sets the PC
        
    __bl__ "Branch and Link"
        0:5   - instruction
        6:9   - base register
        10:31 - offset
        unconditionally sets the PC, and sets the link register
    
    __ba__ "Branch Absolute"
        0:5   - instruction
        6:31  - address
        unconditionally sets the PC to the "address" value
    
    __bal__ "Branch Absolute & Link"
        0:5   - instruction
        6:31  - address
        unconditionally sets the PC to the "address" value, setting the link register
    
##Memory Addressing Modes
 - byte-addressed memory
 
    __ld__ "Load"
        0:5   - icode
        6:10  - target register
        11:15 - base register
        16:20 - index register
        21:31 - offset

    __st__ "Store"
        0:5   - icode
        6:10  - source register
        11:15 - base register
        16:20 - index register
        21:31 - offset

   same as "Load" but the target register instead is the source register

##Virtual Memory

    "software managed TLB"
    two 32-entry fully associative TLB, one for instructions and one for data
    4k page size
    entries are formatted [vpn, hw_addr]
    physical page address of ~0 is an invalid or unset page

    __itlb-add__ "Instruction TLB Add"
        0:5   - icode
        6:10  - vpn register
        11:15 - hardware address register
        16:31 - unused

    __dtlb-add__ "Data TLB Add"
        0:5   - icode
        6:10  - vpn register
        11:15 - hardware address register
        16:31 - unused

todo.txt

 - Better/clearer condition code spec. We do have a full ccode register remember
 - Arithmetic operations. These are still waaay up in the air
 - Someone please check my function call structure. I believe that it is correct but still.
 - Do we need a way to fetch the address of a page from the TLBs? If so, that's another instruction.
 - We need some sort of binary encoding for all this...