4bit CPU TD4 Verilog implementation

TD4.v

// Copyright (c) 2021 asfdrwe (asfdrwe@gmail.com)
// SPDX-License-Identifier: MIT
// USAGE: iverilog -o TD4 TD4.v && ./TD4 # PROGRAM => ROM.bin
module TD4(input wire cl,input wire rn,input wire[3:0]in,output wire[3:0]po,output wire[7:0]op,output wire[3:0]ou,output wire[3:0]ad);reg[3:0]ra,rb,ro;reg[3:0]pc=4'b0;reg cf=1'b1;assign ou=ro;assign po=pc;reg[7:0]rm[0:15];initial $readmemb("ROM.bin",rm);wire[7:0]oc;assign oc=rm[pc];assign op=oc;wire[1:0]as,ls;wire jm;wire[3:0]im;assign as=(oc[7:6]==2'b11)?2'b11:oc[5:4];assign ls=oc[7:6];assign jm=oc[4];assign im=oc[3:0];wire[3:0]ai;assign ai=(as==2'b00)?ra:(as==2'b01)?rb:(as==2'b10)?in:4'b0;wire[3:0]al;wire nf;assign {nf,al}=ai+im;assign ad=al;wire la,lb,lo,lp;assign la=(ls==2'b00)?1'b0:1'b1;assign lb=(ls==2'b01)?1'b0:1'b1;assign lo=(ls==2'b10)?1'b0:1'b1;assign lp=(ls==2'b11&&(jm==1'b1||cf))?1'b0:1'b1;wire[3:0]np;assign np=(lp==1'b0)?al:pc+1;always @(posedge cl or negedge rn) begin if(!rn)begin ra<=4'b0;rb<=4'b0;ro<=4'b0;cf<=1'b1;pc<=4'b0;end else begin ra<=#1(la==1'b0)?al:ra;rb<=#1(lb==1'b0)?al:rb;ro<=#1(lo==1'b0)?al:ro;cf<=#1 ~nf;pc<=#1 np;end end endmodule
module TD4_test;reg cl=1'b0;reg rn=1'b0;reg[3:0]in=4'b0;wire[7:0]op;wire[3:0]ou;wire[3:0]pc;wire[3:0]al;TD4 td4_1(cl,rn,in,pc,op,ou,al);initial begin $dumpfile("TD4.vcd");$dumpvars(0,TD4_test);$monitor("%t:pc=%h,op=%h,in=%h,ou=%h,al=%h",$time,pc,op,in,ou,al);end initial begin cl=1'b0;forever begin #1 cl=~cl;end end initial begin rn=1'b0;#1 rn=1'b1;#1000 $finish;end endmodule