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Ethernet PHY and iCE40LP384 reprogrammer over UDP
Raw
arty.xdc
#set_property DONT_TOUCH true [get_cells { evt1/mem1/srlatch_with_ands }]
#set_property DONT_TOUCH true [get_cells { evt1/pulse1/not1 }]
#set_property DONT_TOUCH true [get_cells { evt1/pulse1/xnor1 }]
#set_property DONT_TOUCH true [get_cells { evt1 }]
set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]
#set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets evt1/feedback]
#set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets evt1/mem1/in0]
#set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets s1/evt1/mem1/OUTPUT_EDGE]
#set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets s2/evt1/mem1/OUTPUT_EDGE]
#set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets s1/evt2/mem1/OUTPUT_EDGE]
#set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets s2/evt2/mem1/OUTPUT_EDGE]
#set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets s1/m/A]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { GCLK100 }];
set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { CK_RST }];
set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { BTN0 }];
set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { BTN1 }];
set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { BTN2 }];
set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { BTN3 }];
set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { SW0 }];
set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { SW1 }];
set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { SW2 }];
set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { SW3 }];
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { CK_IO39 }];
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { CK_IO37 }];
set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { LED4 }];
set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { LED5 }];
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { LED6 }];
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { LED7 }];
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { CK_IO0 }];
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { CK_IO1 }];
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { CK_IO2 }];
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CK_IO3 }];
set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { CK_IO4 }];
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { CK_IO5 }];
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { GCLK100 }];
# create_clock -add -name eth_phy_clk_pin -period 40.00 -waveform {0 20} [get_ports { ETH_REF_CLK }];
create_clock -add -name eth_phy_clk_pin -period 40.00 -waveform {0 20} [get_ports { JA9 }];
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ETH_REF_CLK_IBUF]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets LED2_B_OBUF]
set_output_delay -clock [get_clocks sys_clk_pin] -min 10.0 [get_ports LED4]
set_output_delay -clock [get_clocks sys_clk_pin] -max -10.0 [get_ports LED4]
set_output_delay -clock [get_clocks sys_clk_pin] -min 10.0 [get_ports LED5]
set_output_delay -clock [get_clocks sys_clk_pin] -max -10.0 [get_ports LED5]
set_output_delay -clock [get_clocks sys_clk_pin] -min 10.0 [get_ports LED6]
set_output_delay -clock [get_clocks sys_clk_pin] -max -10.0 [get_ports LED6]
set_output_delay -clock [get_clocks sys_clk_pin] -min 10.0 [get_ports LED7]
set_output_delay -clock [get_clocks sys_clk_pin] -max -10.0 [get_ports LED7]
set_output_delay -clock [get_clocks sys_clk_pin] -min 10.0 [get_ports CK_IO37]
set_output_delay -clock [get_clocks sys_clk_pin] -max -10.0 [get_ports CK_IO37]
set_output_delay -clock [get_clocks sys_clk_pin] -min 10.0 [get_ports CK_IO39]
set_output_delay -clock [get_clocks sys_clk_pin] -max -10.0 [get_ports CK_IO39]
set_output_delay -clock [get_clocks sys_clk_pin] -min 10.0 [get_ports CK_IO0]
set_output_delay -clock [get_clocks sys_clk_pin] -max -10.0 [get_ports CK_IO0]
set_output_delay -clock [get_clocks sys_clk_pin] -min 10.0 [get_ports CK_IO2]
set_output_delay -clock [get_clocks sys_clk_pin] -max -10.0 [get_ports CK_IO2]
set_output_delay -clock [get_clocks sys_clk_pin] -min 10.0 [get_ports CK_IO3]
set_output_delay -clock [get_clocks sys_clk_pin] -max -10.0 [get_ports CK_IO3]
set_output_delay -clock [get_clocks sys_clk_pin] -min 10.0 [get_ports CK_IO5]
set_output_delay -clock [get_clocks sys_clk_pin] -max -10.0 [get_ports CK_IO5]
# set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { ETH_TX_CLK }];
set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { ETH_RX_DV }];
# set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ETH_RX_CLK }];
set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }];
set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD0 }];
set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRS_DV }];
set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD1 }];
# set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ETH_COL }];
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }];
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD2 }];
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD3 }];
set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD3 }];
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD1 }];
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ETH_TX_EN }];
set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }];
# set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }];
set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD2 }];
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD0 }];
set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ETH_REF_CLK }];
set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { LED0_B }];
set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { LED0_R }];
set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { LED0_G }];
set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { LED1_B }];
set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { LED1_R }];
set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { LED1_G }];
set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { LED2_B }];
set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { LED2_R }];
set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { LED2_G }];
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { LED3_B }];
set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { LED3_R }];
set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { LED3_G }];
set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { CK_IO26 }];
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { CK_IO27 }];
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { CK_IO28 }];
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CK_IO29 }];
set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { CK_IO30 }];
set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { CK_IO31 }];
set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { CK_IO32 }];
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CK_IO33 }];
set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { CK_IO34 }];
# SPI Flash
set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { JD2 }];
set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { JD3 }];
set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD4 }];
set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { JD8 }];
set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD9 }];
set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD10 }];
set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { JD7 }];
set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JA1 }];
set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { JA2 }];
set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { JA3 }];
set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { JA4 }];
set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { JA7 }];
set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { JA8 }];
set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { JA9 }];
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { JA10 }];
create_clock -add -name eth_phy_rmii_clk_pin -period 20.00 -waveform {0 10} [get_ports { JA9 }];
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets JA9_IBUF]
Raw
bash_cmds.sh
# ask Linux to show what crc32 of your packet should be
crc32 <(echo -ne '\xff\xff\xff\xff\xff\xff\xc8\xd9\xd2\x78\x13\x34\x08\x06\x00\x01\x08\x00\x06\x04\x00\x01\xc8\xd9\xd2\x78\x13\x34\xc0\xa8\x00\x01\x00\x00\x00\x00\x00\x00\xc0\xa8\x00\x02\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
# 1 packet
arping -W 1 -D -I eno1 -c 1 192.168.254.54
# perf test
arping -W 0.001 -D -I eno1 -c 1500000 192.168.254.54
# capture everything in tcpdump
ethtool -k eno1
ethtool -K eno1 rx-checksum off
ethtool -K eno1 rx-all on
ethtool -K eno1 rx-fcs on
tcpdump -e -n -i eno1 -vv -XX -S -Q inout arp
tcpdump -e -n -i eno1 -vv -XX -S -Q inout udp
Raw
galois.v
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Parametrizable combinatorial parallel LFSR/CRC
*/
module Lfsr #
(
// width of LFSR
parameter LFSR_WIDTH = 31,
// LFSR polynomial
parameter LFSR_POLY = 31'h10000001,
// LFSR configuration: "GALOIS", "FIBONACCI"
parameter LFSR_CONFIG = "FIBONACCI",
// LFSR feed forward enable
parameter LFSR_FEED_FORWARD = 0,
// bit-reverse input and output
parameter REVERSE = 0,
// width of data input
parameter DATA_WIDTH = 8,
// implementation style: "AUTO", "LOOP", "REDUCTION"
parameter STYLE = "AUTO"
)
(
input wire [DATA_WIDTH-1:0] data_in,
input wire [LFSR_WIDTH-1:0] state_in,
output wire [DATA_WIDTH-1:0] data_out,
output wire [LFSR_WIDTH-1:0] state_out
);
/*
Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR
next state computation, shifting DATA_WIDTH bits per pass through the module. Input data
is XORed with LFSR feedback path, tie data_in to zero if this is not required.
Works in two parts: statically computes a set of bit masks, then uses these bit masks to
select bits for XORing to compute the next state.
Ports:
data_in
Data bits to be shifted through the LFSR (DATA_WIDTH bits)
state_in
LFSR/CRC current state input (LFSR_WIDTH bits)
data_out
Data bits shifted out of LFSR (DATA_WIDTH bits)
state_out
LFSR/CRC next state output (LFSR_WIDTH bits)
Parameters:
LFSR_WIDTH
Specify width of LFSR/CRC register
LFSR_POLY
Specify the LFSR/CRC polynomial in hex format. For example, the polynomial
x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
would be represented as
32'h04c11db7
Note that the largest term (x^32) is suppressed. This term is generated automatically based
on LFSR_WIDTH.
LFSR_CONFIG
Specify the LFSR configuration, either Fibonacci or Galois. Fibonacci is generally used
for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators,
scramblers, and descrambers, while Galois is generally used for cyclic redundancy check
generators and checkers.
Fibonacci style (example for 64b66b scrambler, 0x8000000001)
DIN (LSB first)
|
V
(+)<---------------------------(+)<-----------------------------.
| ^ |
| .----. .----. .----. | .----. .----. .----. |
+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--'
| '----' '----' '----' '----' '----' '----'
V
DOUT
Galois style (example for CRC16, 0x8005)
,-------------------+-------------------------+----------(+)<-- DIN (MSB first)
| | | ^
| .----. .----. V .----. .----. V .----. |
`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT
'----' '----' '----' '----' '----'
LFSR_FEED_FORWARD
Generate feed forward instead of feed back LFSR. Enable this for PRBS checking and self-
synchronous descrambling.
Fibonacci feed-forward style (example for 64b66b descrambler, 0x8000000001)
DIN (LSB first)
|
| .----. .----. .----. .----. .----. .----.
+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--.
| '----' '----' '----' | '----' '----' '----' |
| V |
(+)<---------------------------(+)------------------------------'
|
V
DOUT
Galois feed-forward style
,-------------------+-------------------------+------------+--- DIN (MSB first)
| | | |
| .----. .----. V .----. .----. V .----. V
`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |->(+)-> DOUT
'----' '----' '----' '----' '----'
REVERSE
Bit-reverse LFSR input and output. Shifts MSB first by default, set REVERSE for LSB first.
DATA_WIDTH
Specify width of input and output data bus. The module will perform one shift per input
data bit, so if the input data bus is not required tie data_in to zero and set DATA_WIDTH
to the required number of shifts per clock cycle.
STYLE
Specify implementation style. Can be "AUTO", "LOOP", or "REDUCTION". When "AUTO"
is selected, implemenation will be "LOOP" or "REDUCTION" based on synthesis translate
directives. "REDUCTION" and "LOOP" are functionally identical, however they simulate
and synthesize differently. "REDUCTION" is implemented with a loop over a Verilog
reduction operator. "LOOP" is implemented as a doubly-nested loop with no reduction
operator. "REDUCTION" is very fast for simulation in iverilog and synthesizes well in
Quartus but synthesizes poorly in ISE, likely due to large inferred XOR gates causing
problems with the optimizer. "LOOP" synthesizes will in both ISE and Quartus. "AUTO"
will default to "REDUCTION" when simulating and "LOOP" for synthesizers that obey
synthesis translate directives.
Settings for common LFSR/CRC implementations:
Name Configuration Length Polynomial Initial value Notes
CRC16-IBM Galois, bit-reverse 16 16'h8005 16'hffff
CRC16-CCITT Galois 16 16'h1021 16'h1d0f
CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
PRBS6 Fibonacci 6 6'h21 any
PRBS7 Fibonacci 7 7'h41 any
PRBS9 Fibonacci 9 9'h021 any ITU V.52
PRBS10 Fibonacci 10 10'h081 any ITU
PRBS11 Fibonacci 11 11'h201 any ITU O.152
PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152
PRBS17 Fibonacci 17 17'h04001 any
PRBS20 Fibonacci 20 20'h00009 any ITU V.57
PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151
PRBS29 Fibonacci, inverted 29 29'h08000001 any
PRBS31 Fibonacci, inverted 31 31'h10000001 any
64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet
128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3
*/
reg [LFSR_WIDTH-1:0] lfsr_mask_state[LFSR_WIDTH-1:0];
reg [DATA_WIDTH-1:0] lfsr_mask_data[LFSR_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] output_mask_state[DATA_WIDTH-1:0];
reg [DATA_WIDTH-1:0] output_mask_data[DATA_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] state_val = 0;
reg [DATA_WIDTH-1:0] data_val = 0;
integer i, j, k;
initial begin
// init bit masks
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
lfsr_mask_state[i] = {LFSR_WIDTH{1'b0}};
lfsr_mask_state[i][i] = 1'b1;
lfsr_mask_data[i] = {DATA_WIDTH{1'b0}};
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
output_mask_state[i] = {LFSR_WIDTH{1'b0}};
if (i < LFSR_WIDTH) begin
output_mask_state[i][i] = 1'b1;
end
output_mask_data[i] = {DATA_WIDTH{1'b0}};
end
// simulate shift register
if (LFSR_CONFIG == "FIBONACCI") begin
// Fibonacci configuration
for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin
// determine shift in value
// current value in last FF, XOR with input data bit (MSB first)
state_val = lfsr_mask_state[LFSR_WIDTH-1];
data_val = lfsr_mask_data[LFSR_WIDTH-1];
data_val = data_val ^ (1 << i);
// add XOR inputs from correct indicies
for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
if (LFSR_POLY & (1 << j)) begin
state_val = lfsr_mask_state[j-1] ^ state_val;
data_val = lfsr_mask_data[j-1] ^ data_val;
end
end
// shift
for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin
lfsr_mask_state[j] = lfsr_mask_state[j-1];
lfsr_mask_data[j] = lfsr_mask_data[j-1];
end
for (j = DATA_WIDTH-1; j > 0; j = j - 1) begin
output_mask_state[j] = output_mask_state[j-1];
output_mask_data[j] = output_mask_data[j-1];
end
output_mask_state[0] = state_val;
output_mask_data[0] = data_val;
if (LFSR_FEED_FORWARD) begin
// only shift in new input data
state_val = {LFSR_WIDTH{1'b0}};
data_val = 1 << i;
end
lfsr_mask_state[0] = state_val;
lfsr_mask_data[0] = data_val;
end
end else if (LFSR_CONFIG == "GALOIS") begin
// Galois configuration
for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin
// determine shift in value
// current value in last FF, XOR with input data bit (MSB first)
state_val = lfsr_mask_state[LFSR_WIDTH-1];
data_val = lfsr_mask_data[LFSR_WIDTH-1];
data_val = data_val ^ (1 << i);
// shift
for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin
lfsr_mask_state[j] = lfsr_mask_state[j-1];
lfsr_mask_data[j] = lfsr_mask_data[j-1];
end
for (j = DATA_WIDTH-1; j > 0; j = j - 1) begin
output_mask_state[j] = output_mask_state[j-1];
output_mask_data[j] = output_mask_data[j-1];
end
output_mask_state[0] = state_val;
output_mask_data[0] = data_val;
if (LFSR_FEED_FORWARD) begin
// only shift in new input data
state_val = {LFSR_WIDTH{1'b0}};
data_val = 1 << i;
end
lfsr_mask_state[0] = state_val;
lfsr_mask_data[0] = data_val;
// add XOR inputs at correct indicies
for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
if (LFSR_POLY & (1 << j)) begin
lfsr_mask_state[j] = lfsr_mask_state[j] ^ state_val;
lfsr_mask_data[j] = lfsr_mask_data[j] ^ data_val;
end
end
end
end else begin
$error("Error: unknown configuration setting!");
$finish;
end
// reverse bits if selected
if (REVERSE) begin
// reverse order
for (i = 0; i < LFSR_WIDTH/2; i = i + 1) begin
state_val = lfsr_mask_state[i];
data_val = lfsr_mask_data[i];
lfsr_mask_state[i] = lfsr_mask_state[LFSR_WIDTH-i-1];
lfsr_mask_data[i] = lfsr_mask_data[LFSR_WIDTH-i-1];
lfsr_mask_state[LFSR_WIDTH-i-1] = state_val;
lfsr_mask_data[LFSR_WIDTH-i-1] = data_val;
end
for (i = 0; i < DATA_WIDTH/2; i = i + 1) begin
state_val = output_mask_state[i];
data_val = output_mask_data[i];
output_mask_state[i] = output_mask_state[DATA_WIDTH-i-1];
output_mask_data[i] = output_mask_data[DATA_WIDTH-i-1];
output_mask_state[DATA_WIDTH-i-1] = state_val;
output_mask_data[DATA_WIDTH-i-1] = data_val;
end
// reverse bits
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_val = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
state_val[j] = lfsr_mask_state[i][LFSR_WIDTH-j-1];
end
lfsr_mask_state[i] = state_val;
data_val = 0;
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
data_val[j] = lfsr_mask_data[i][DATA_WIDTH-j-1];
end
lfsr_mask_data[i] = data_val;
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
state_val = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
state_val[j] = output_mask_state[i][LFSR_WIDTH-j-1];
end
output_mask_state[i] = state_val;
data_val = 0;
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
data_val[j] = output_mask_data[i][DATA_WIDTH-j-1];
end
output_mask_data[i] = data_val;
end
end
// for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
// $display("%b %b", lfsr_mask_state[i], lfsr_mask_data[i]);
// end
end
// synthesis translate_off
`define SIMULATION
// synthesis translate_on
`ifdef SIMULATION
// "AUTO" style is "REDUCTION" for faster simulation
parameter STYLE_INT = (STYLE == "AUTO") ? "REDUCTION" : STYLE;
`else
// "AUTO" style is "LOOP" for better synthesis result
parameter STYLE_INT = (STYLE == "AUTO") ? "LOOP" : STYLE;
`endif
genvar n;
generate
if (STYLE_INT == "REDUCTION") begin
// use Verilog reduction operator
// fast in iverilog
// significantly larger than generated code with ISE (inferred wide XORs may be tripping up optimizer)
// slightly smaller than generated code with Quartus
// --> better for simulation
for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : loop1
assign state_out[n] = ^{(state_in & lfsr_mask_state[n]), (data_in & lfsr_mask_data[n])};
end
for (n = 0; n < DATA_WIDTH; n = n + 1) begin : loop2
assign data_out[n] = ^{(state_in & output_mask_state[n]), (data_in & output_mask_data[n])};
end
end else if (STYLE_INT == "LOOP") begin
// use nested loops
// very slow in iverilog
// slightly smaller than generated code with ISE
// same size as generated code with Quartus
// --> better for synthesis
reg [LFSR_WIDTH-1:0] state_out_reg = 0;
reg [DATA_WIDTH-1:0] data_out_reg = 0;
assign state_out = state_out_reg;
assign data_out = data_out_reg;
always @* begin
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_out_reg[i] = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
if (lfsr_mask_state[i][j]) begin
state_out_reg[i] = state_out_reg[i] ^ state_in[j];
end
end
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
if (lfsr_mask_data[i][j]) begin
state_out_reg[i] = state_out_reg[i] ^ data_in[j];
end
end
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
data_out_reg[i] = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
if (output_mask_state[i][j]) begin
data_out_reg[i] = data_out_reg[i] ^ state_in[j];
end
end
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
if (output_mask_data[i][j]) begin
data_out_reg[i] = data_out_reg[i] ^ data_in[j];
end
end
end
end
end else begin
initial begin
$error("Error: unknown style setting!");
$finish;
end
end
endgenerate
endmodule
Raw
generated_lattice_cram_init.v
`timescale 1ns / 1ps
module RamSource (
input wire i_clock,
input wire i_reset,
input wire i_enable,
input wire [17:0] i_address,
output wire o_data,
input wire [1:0] i_data,
input wire i_we
);
wire [7:0] block;
// 0
RamFile #(
/*
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*/
) f0 (.i_clock (i_clock), .i_reset (i_reset), .i_enable (i_enable), .i_address (i_address[14:0]), .o_data (block[0]),
.i_data (i_data),
.i_we (i_we & ~i_address[15])
);
// 1
RamFile #(/*
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.INIT_50 (256'b0000000000000000000000000000000100000000000000001000001100110100100001011000001000001010000000100000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000001001000000001111011110010010000010),
.INIT_51 (256'b1111101111001100000000000000000000000000000000000000000000000000000000000000000001000000000000000000000100000000101001100000000000101100001000010000000000000010000001010111100000000111011110001100110000000000000000000000000000000000000000000000000000000000),
.INIT_52 (256'b1110000001100011100000001101001100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000010000010000000001110110110010000101000000000000000000001010110000000000),
.INIT_53 (256'b0000000000000000000000000000000000000000000000000000000000000000000000100000000011110001100100000011100011001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100),
.INIT_54 (256'b0000000000000010000000001010111001100001010110011001011000100000000000000000000000000000000000000000000000000000000000000011000000000000000000001000000000001100001000100110101000110011000000000000000000000100101100000000000000110010010110000000000000000000),
.INIT_55 (256'b1100000000100000000000000000000010000000001000000000000000100110101100110011000010000010000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000001111000000000000000000000000000000000000000000001011100000011001011001110011),
.INIT_56 (256'b1110001101100011001100000000000000000000000000000000000000000000000000000000000000000000000000000000000100110000000000000001100111100101111110110011000000000000110000000000000011100111100000000000000000000000000000000000000000000000000000000000001110000011),
.INIT_57 (256'b1000000100001001110110010001101101011010010000000000101000000000001001100000001001101011001100110000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100100001010110110100100000000000000000000000011110000),
.INIT_58 (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000001110100001011000110100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000010),
.INIT_59 (256'b0100100000000000000000000000000000000000000000000011011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010000000000000011110000101100101101001000000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A (256'b0000000000000000000000000000000000000000000000000000000000001111001100101000100001010000000000000000000000000000000000000000101011000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110101011101000),
.INIT_5B (256'b0000011100000000110011000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000100000001000000000010000000000000000000000010000000000100000000011001110000000010100001000000000000000000000000000000000000),
.INIT_5C (256'b0000000000000000000000000100000000001100001100110000000000000010100000001001000000000000011000110000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000001111000000000000000000001000000000000000000000000),
.INIT_5D (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110000000110000011001100000000000000010000000000000001100000000011101100000001000000000000000000000000000000000000000000000000000000000000000000100000000000),
.INIT_5E (256'b0110111001011000000000010000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000011100000000101010010110000000000000000000000000000000010000000000000000000000000000),
.INIT_5F (256'b0000000000000000000000000001000000000000000000000010000000110100001000000111110100110011000000000000000000000000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001010111000010000111),
.INIT_60 (256'b0010000010000000000010101001101001000000000000000000000000000000000000000000000000000000000000000000000000000000100000000001000000000001100000011001101001110011000000000000000000000000010001100000000000000000000000000000000000000000000000000000000000000000),
.INIT_61 (256'b0000000100110000000001000001100010101101101001001100110000000010110000000000000101000000000001111011011010010000000000000000000000000000000000000000000000000000000000000000000000000000001100001000000011101000000000000011111110101100110000000000001000000000),
.INIT_62 (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000011111000101100001111110110100100010000000000000001100000000001000000000011010110100100000000000000000000000000000000000000000000000000000000000000001000000000),
.INIT_63 (256'b0011111110100011001100001000000000000000000000110000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000010110100000011110110011000011100101101101001000000010010100000000000000000011010000101110101101001),
.INIT_64 (256'b1000000001101010101101000100010000000000000000000000000000000000010100011001100110100111001100000000000000001000000000100110000001000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000001001000011),
.INIT_65 (256'b000000000000000000000000000000000000000000000000000000000000000001100000)
*/
) f1 (.i_clock (i_clock), .i_reset (i_reset), .i_enable (i_enable), .i_address (i_address[14:0]), .o_data (block[1]),
.i_data (i_data),
.i_we (i_we & i_address[15])
);
wire [2:0] block_address = i_address[17:15];
assign o_data = block[ block_address ];
endmodule
Raw
ice40lp384.pcf
# full iCEstick pinout:
# http://www.pighixxx.com/test/portfolio-items/icestick/
# set_io io_13_9__1_led4 95
# set_io io_13_6__0_pmod4 81
# set_io io_13_6__0_pmod4 81
# TOP (bank 0)
set_io IOT_45 26 # (io 6 9 pad 0)
set_io IOT_47 27 # (io 5 9 pad 0)
set_io IOT_49_GBIN0 29 # GBUF0 (io 4 9 pad 0)
set_io IOT_50_GBIN1 30 # GBUF1 (io 3 9 pad 1)
set_io IOT_52 32 # (io 2 9 pad 1)
set_io IOT_53 31 # (io 2 9 pad 0)
# RIGHT (bank 1)
set_io IOR_34 18 # (io 7 4 pad 0)
set_io IOR_35_GBIN3 19 # GBUF3 (io 7 4 pad 1)
set_io IOR_36_GBIN2 20 # GBUF2 (io 7 5 pad 0)
set_io IOR_38 22 # (io 7 6 pad 0)
set_io IOR_39 23 # (io 7 6 pad 1)
# BOTTOM (bank 2)
set_io IOB_24_SPI_SDO 12 # (io 5 0 pad 0)
set_io IOB_25_SPI_SDI 13 # (io 5 0 pad 1)
set_io IOB_26_SPI_SCK 15 # (io 6 0 pad 0)
set_io IOB_27_SPI_SS_B 14 # (io 6 0 pad 1)
# LEFT (bank 3)
set_io IOL_2B 1 # D+ (io 0 7 pad 0)
set_io IOL_2A 2 # D- (io 0 7 pad 1)
set_io IOL_4A 5 # D- GBUF7 (io 0 5 pad 1)
set_io IOL_4B_GBIN7 6 # D+ GBUF7 (io 0 5 pad 0)
set_io IOL_5B 7 # D+ (io 0 4 pad 0)
set_io IOL_5A_GBIN6 8 # D- or GBUF6 (io 0 4 pad 1)
Raw
init-egl.h
#include <cassert>
#include <cstdarg>
#include <cstdio>
#include <cstdlib>
#include <EGL/egl.h>
using namespace std;
void error_fatal(const char* format, ...) {
printf("error: ");
va_list va;
va_start(va, format);
vprintf(format, va);
va_end(va);
printf("\n");
exit(1);
}
# define ERROR "ERROR"
# define OK(expr) (!(expr) ? (throw "ERROR##expr"), false : true)
void setup_egl(
EGLNativeWindowType native_window,
EGLDisplay* out_display,
EGLConfig* out_config,
EGLContext* out_context,
EGLSurface* out_window_surface) {
OK(eglBindAPI(EGL_OPENGL_ES_API));
EGLDisplay display = eglGetDisplay(EGL_DEFAULT_DISPLAY);
OK(display != EGL_NO_DISPLAY);
EGLint ignore = 0;
OK(eglInitialize(display, &ignore, &ignore));
EGLint configs_size = 256;
EGLConfig* configs = new EGLConfig[configs_size];
EGLint num_configs = 0;
const EGLint egl_config_attribs[] = {
EGL_COLOR_BUFFER_TYPE, EGL_RGB_BUFFER,
EGL_BUFFER_SIZE, 32,
EGL_RED_SIZE, 8,
EGL_GREEN_SIZE, 8,
EGL_BLUE_SIZE, 8,
EGL_ALPHA_SIZE, 8,
EGL_DEPTH_SIZE, 24,
EGL_STENCIL_SIZE, 8,
EGL_SAMPLE_BUFFERS, 0,
EGL_SAMPLES, 0,
EGL_SURFACE_TYPE, EGL_WINDOW_BIT,
EGL_RENDERABLE_TYPE, EGL_OPENGL_ES2_BIT,
EGL_NONE,
};
OK(eglChooseConfig(
display,
egl_config_attribs,
configs,
configs_size, // num requested configs
&num_configs)); // num returned configs
OK(num_configs);
EGLConfig config = configs[0];
delete [] configs;
const EGLint egl_context_attribs[] = {
EGL_CONTEXT_CLIENT_VERSION, 2,
EGL_NONE,
};
EGLContext context = eglCreateContext(
display,
config,
EGL_NO_CONTEXT,
egl_context_attribs);
OK(context);
const EGLint egl_surface_attribs[] = {
EGL_RENDER_BUFFER,
EGL_BACK_BUFFER,
EGL_NONE,
};
EGLSurface surface = eglCreateWindowSurface(
display,
config,
native_window,
egl_surface_attribs);
OK(surface);
OK(eglMakeCurrent(display, surface, surface, context));
// Check if surface is double buffered.
EGLint render_buffer;
OK(eglQueryContext(
display,
context,
EGL_RENDER_BUFFER,
&render_buffer));
if (render_buffer == EGL_SINGLE_BUFFER) {
printf("warn: EGL surface is single buffered\n");
}
*out_display = display;
*out_config = config;
*out_context = context;
*out_window_surface = surface;
}
Raw
lattice-conv.js
const fs = require('fs');
const srcFile = fs.readFileSync('./example-384.bin');
let files = ['', '', '', '', '', '', '', ''];
let index = 0;
let pos = 0;
let skip = 4;
let currentString = '';
let bitCounter = 0;
let rowCounter = 0;
const fileBinData = Buffer.alloc(7337);
let fileData = `\`timescale 1ns / 1ps
module RamSource (
input wire i_clock,
input wire i_reset,
input wire i_enable,
input wire [17:0] i_address,
output wire o_data,
input wire [1:0] i_data,
input wire i_we
);
wire [7:0] block;
// 0\n RamFile #(
`;
let fileCounter = 0;
if (srcFile[12] === 0x92) {
// 3 bytes: 92 00 20 (opcode 9 length 2 bytes payload 32 = "Enable warm boot"; for slave SPI should be 0)
console.log('Disabling warm boot for slave SPI...');
srcFile[13] = 0;
srcFile[14] = 0;
}
let crc = 0xFFFF;
console.log(crc >>> 15);
console.log(crc);
const updateCrc = (byte) => {
// CRC-16-CCITT, Initialize to 0xFFFF, No zero padding
for (let i = 7; i >= 0; i--) {
const data_bit = (byte >>> i) & 1;
const crc_bit = crc >>> 15;
const xor_value = (data_bit ^ crc_bit) ? 0x1021 : 0;
crc = 0xFFFF & ((crc << 1) ^ xor_value);
//const xor_value = ((crc >>> 15) ^ ((byte >>> i) & 1)) ? 0x1021 : 0;
//crc = (0xFFFF & (crc << 1)) ^ xor_value;
}
}
const src = Buffer.concat([srcFile, Buffer.alloc(7)]);
const hexByte = (byte) => ('00' + (byte).toString(16).toUpperCase()).substr(-2);
console.log(typeof(src), '00' + ((src.length - 4) * 8).toString(16));
const crcOpcode = srcFile[srcFile.length - 6];
const crcMsb = srcFile[srcFile.length - 5];
const crcLsb = srcFile[srcFile.length - 4];
console.log(`CRC16 ${ hexByte(crcOpcode) } ${ hexByte(crcMsb) } ${ hexByte(crcLsb) }`);
const lastCrcPos = srcFile.length - 6;
let binaryWriteoutPos = 0;
src.forEach((byte, n) => {
if (n > 11 && n < lastCrcPos) {
updateCrc(byte);
} else if (n === lastCrcPos) {
updateCrc(byte);
const msb_crc = crc >>> 8;
const lsb_crc = 0xFF & crc;
console.log(`Curr byte: ${ hexByte(byte) }. Computed CRC16 is ${ hexByte(msb_crc) } ${ hexByte(lsb_crc) }`); //${ ('0000' + (crc).toString(16).toUpperCase()).substr(-4) } ${ crc }`);
}
if (n == 13 || n == 14) {
// byte = 0;
//console.log(byte);
}
if (skip) {
--skip;
return;
//byte = 0;
}
let msb_lsb_byte = 0;
for (let i = 7; i >= 0; --i) {
// files[index] += byte & (1 << i) ? '1\n' : '0\n';
const bitValue = (byte & (1 << i)) ? 1 : 0;
currentString = (bitValue ? '1' : '0') + currentString;
++bitCounter;
msb_lsb_byte = msb_lsb_byte | (bitValue << (7 - i));
}
fileBinData.writeUInt8(msb_lsb_byte, binaryWriteoutPos++);
if (++pos >= 4096) {
pos = 0;
++index;
}
if (bitCounter === 256) {
bitCounter = 0;
const val = ('00'+(rowCounter).toString(16).toUpperCase()).substr(-2);
fileData += ` .INIT_${ val } (256'b${ currentString })`;
currentString = '';
++rowCounter;
if (rowCounter === 128) {
rowCounter = 0;
fileData += `
) f${ fileCounter } (.i_clock (i_clock), .i_reset (i_reset), .i_enable (i_enable), .i_address (i_address[14:0]), .o_data (block[${ fileCounter }]),
.i_data (i_data),
.i_we (i_we & ~i_address[15]));
// ${ fileCounter + 1 }
RamFile #(
`;
++fileCounter;
} else {
if (n < src.length - 4 - 1) {
fileData += `,\n`;
} else {
console.log(n);
}
}
}
// const b_val = ('00'+(byte).toString(16).toUpperCase()).substr(-2);
// process.stdout.write(b_val);
});
if (bitCounter < 256) {
const val = ('00'+(rowCounter).toString(16).toUpperCase()).substr(-2);
fileData += ` .INIT_${ val } (256'b${ currentString })`;
currentString = '';
++rowCounter;
if (rowCounter === 128) {
rowCounter = 0;
fileData += `
) f${ fileCounter } (.i_clock (i_clock), .i_reset (i_reset), .i_enable (i_enable), .i_address (i_address[14:0]), .o_data (block[${ fileCounter }]),
.i_data (i_data),
.i_we (i_we & i_address[15]));
// ${ fileCounter + 1 }
RamFile #(
`;
++fileCounter;
}
}
console.log('');
fileData += `
) f${ fileCounter } (.i_clock (i_clock), .i_reset (i_reset), .i_enable (i_enable), .i_address (i_address[14:0]), .o_data (block[${ fileCounter }]),
.i_data (i_data),
.i_we (i_we & i_address[15]));
wire [2:0] block_address = i_address[17:15];
assign o_data = block[ block_address ];
endmodule
`;
console.log(`Binary length ${ binaryWriteoutPos }`);
fs.writeFileSync('./RAMB36E1_init_params_new.v', fileData);
fs.writeFileSync('./example-384-processed.bin', fileBinData);
//let n = 0;
//files.forEach(file => {
// fs.writeFileSync(`./example.vivado${ ++n }.hex`, file);
//});
Raw
phy_rmii_wrapper.v
`timescale 1ns / 1ps
`define COUNTER_RESOLUTION_BITS 24
module EthernetPhyWrapper (
// Universal interface
input wire MDC, // Management data clock max 25 MHz
//inout wire MDIO, // Management data I/O starts in Z state
input wire TX_EN, // Active high
input wire TX0,
input wire TX1,
output wire CRS_DV, // High when data is available
output wire RX0,
output wire RX1,
output wire REFCLK, // 50 MHz RMII clock. In Arty, just returns XTAL1_CLKIN_50MHZ back to the rest of the board
// Arty interface PHY connections. Remove in real external RMII PHY.
// Emulates power-on reset because Arty boots the PHY in MII mode
// Management interface
// In the controller, wait 84 ms until feeding data on boot
output wire ARTY_ETH_MDC, // Management data clock max 25 MHz
// Keep in "Z" on boot (make sure it has a pull-up resistor in the PHY board)
//inout wire ARTY_ETH_MDIO, // Management data I/O
output wire ARTY_ETH_TX_EN, // Active high
output wire ARTY_ETH_TXD1,
output wire ARTY_ETH_TXD0,
input wire ARTY_ETH_RXD1,
input wire ARTY_ETH_RXD0,
input wire ARTY_ETH_CRS_DV, // "Data is ready" CRS_DV/LED_CFG not in full-duplex. Receive medium is not idle (carrier sense)
// Physical interface
output wire ARTY_ETH_REF_CLK, // 50 MHz in RMII mode. Derived from GCLK100
output wire ARTY_ETH_RSTN, // Reset active low 1 us power on reset only
// To put into RMII mode only
inout wire ARTY_ETH_RX_DV, // Put to 1 while resetting to put PHY into the RMII mode then go Z
// Tweak for Arty board. In the physical board 8720,
// 50 MHz signal comes from the REFCLK pin; its CLKIN connected to a real XTAL.
// No need to connect it in Lattice.
input wire ARTY_GCLK100, // Divided to make an analog of XTAL1_CLKIN_50MHZ
input wire DELAY_ENGINE_COUNTING,
input wire DELAY_ENGINE_COUNTED,
output wire DELAY_ENGINE_START,
output wire [`COUNTER_RESOLUTION_BITS-1:0] DELAY_ENGINE_DELAY
);
assign CRS_DV = ARTY_ETH_CRS_DV;
assign RX0 = ARTY_ETH_RXD0;
assign RX1 = ARTY_ETH_RXD1;
assign ARTY_ETH_TX_EN = TX_EN;
assign ARTY_ETH_TXD0 = TX0;
assign ARTY_ETH_TXD1 = TX1;
// Hardware emulation of RMII board:
// 1. Hold RESET 1 us since boot.
// 2. Wait 3 us before 32 MDC clocks.
// 3. Keep ETH_RX_DV at 1 for 30-40 ns after raising edge of MDC.
// 4. Generate internal MDC clock to emulate setting of RMII mode.
// Note MDC is an independent clock so it must be provided externally with different phase and so on.
// 5. Go to Z after the first flop
// 1. Divide the clock
// Use Ethernet 50 MHz source as the main clock
reg derived_clock_50_mhz = 1'b0;
always @(posedge ARTY_GCLK100)
begin
derived_clock_50_mhz <= #4 ~derived_clock_50_mhz;
end
wire GLOBAL_CLOCK_50MHZ;
// Throw the derived clock on global clock net
BUFG eth_50_mhz_clk_buf (
.O (GLOBAL_CLOCK_50MHZ),
.I (derived_clock_50_mhz)
);
assign ARTY_ETH_REF_CLK = GLOBAL_CLOCK_50MHZ;
assign REFCLK = GLOBAL_CLOCK_50MHZ;
// An MDC multiplexer because we have to send some signal there too:
reg initializing = 1'b1;
reg local_MDC = 1'b0;
reg [6:0] toggle_mdc_32_times = 7'd64; // 64 is up and down
assign ARTY_ETH_MDC = (initializing & local_MDC) | (~initializing & MDC);
reg HOLD_RX_DV_TO_ENABLE_RMII_ON_BOOT = 1'bz;
assign ARTY_ETH_RX_DV = HOLD_RX_DV_TO_ENABLE_RMII_ON_BOOT;
reg power_on_reset_signal = 1'b0;
assign ARTY_ETH_RSTN = power_on_reset_signal;
reg [`COUNTER_RESOLUTION_BITS-1:0] current_delay_signal = 0;
assign DELAY_ENGINE_DELAY = current_delay_signal;
reg start_waiting_signal = 1'b0;
assign DELAY_ENGINE_START = start_waiting_signal;
// State machine
reg waiting_phase_resetting = 1'b1;
reg waiting_phase_stabilizing = 1'b0;
reg latching_in_hardware_cfg_pins = 1'b0;
always @(posedge REFCLK)
begin
//if (initializing)
//begin
if (~DELAY_ENGINE_COUNTING & ~start_waiting_signal)
begin
// Launch counter first time wait for 1 us
if (~DELAY_ENGINE_COUNTED)
begin
if (waiting_phase_resetting)
begin
current_delay_signal <= #4 `COUNTER_RESOLUTION_BITS'd50;
start_waiting_signal <= #4 1'b1;
end
end
else
// Counting just completed
begin
// Switch to stabilizing wait mode. Wait for 3 us
// RELEASE RESET
if (waiting_phase_resetting)
begin
waiting_phase_resetting <= #4 1'b0;
waiting_phase_stabilizing <= #4 1'b1;
power_on_reset_signal <= #4 1'b1;
HOLD_RX_DV_TO_ENABLE_RMII_ON_BOOT <= #4 1'b1; // 1'bz
current_delay_signal <= #4 `COUNTER_RESOLUTION_BITS'd150;
start_waiting_signal <= #4 1'b1;
end
else
// Stabilizing is done. Give some MDC clock and wait for latching.
if (waiting_phase_stabilizing)
begin
waiting_phase_stabilizing <= #4 1'b0;
latching_in_hardware_cfg_pins <= #4 1'b1;
end
end
end
else
begin
// Release "Start" pulse
if (DELAY_ENGINE_COUNTING & start_waiting_signal)
begin
start_waiting_signal <= #4 1'b0;
end
end
if (latching_in_hardware_cfg_pins)
begin
local_MDC = #4 ~local_MDC;
toggle_mdc_32_times = #4 toggle_mdc_32_times - 6'b1;
// On the second raising edge of MDC, put HOLD_RX_DV_TO_ENABLE_RMII_ON_BOOT to Z:
if (toggle_mdc_32_times == 7'd62)
begin
HOLD_RX_DV_TO_ENABLE_RMII_ON_BOOT <= #4 1'bz;
end
if (!toggle_mdc_32_times)
begin
// Ready!
initializing <= #4 1'b0;
latching_in_hardware_cfg_pins <= #4 1'b0;
end
end
end
//end
endmodule
Raw
ram_file.v
`timescale 1ns / 1ps
module RamFile # (
parameter INIT_00 = 256'b0,
parameter INIT_01 = 256'b0,
parameter INIT_02 = 256'b0,
parameter INIT_03 = 256'b0,
parameter INIT_04 = 256'b0,
parameter INIT_05 = 256'b0,
parameter INIT_06 = 256'b0,
parameter INIT_07 = 256'b0,
parameter INIT_08 = 256'b0,
parameter INIT_09 = 256'b0,
parameter INIT_0A = 256'b0,
parameter INIT_0B = 256'b0,
parameter INIT_0C = 256'b0,
parameter INIT_0D = 256'b0,
parameter INIT_0E = 256'b0,
parameter INIT_0F = 256'b0,
parameter INIT_10 = 256'b0,
parameter INIT_11 = 256'b0,
parameter INIT_12 = 256'b0,
parameter INIT_13 = 256'b0,
parameter INIT_14 = 256'b0,
parameter INIT_15 = 256'b0,
parameter INIT_16 = 256'b0,
parameter INIT_17 = 256'b0,
parameter INIT_18 = 256'b0,
parameter INIT_19 = 256'b0,
parameter INIT_1A = 256'b0,
parameter INIT_1B = 256'b0,
parameter INIT_1C = 256'b0,
parameter INIT_1D = 256'b0,
parameter INIT_1E = 256'b0,
parameter INIT_1F = 256'b0,
parameter INIT_20 = 256'b0,
parameter INIT_21 = 256'b0,
parameter INIT_22 = 256'b0,
parameter INIT_23 = 256'b0,
parameter INIT_24 = 256'b0,
parameter INIT_25 = 256'b0,
parameter INIT_26 = 256'b0,
parameter INIT_27 = 256'b0,
parameter INIT_28 = 256'b0,
parameter INIT_29 = 256'b0,
parameter INIT_2A = 256'b0,
parameter INIT_2B = 256'b0,
parameter INIT_2C = 256'b0,
parameter INIT_2D = 256'b0,
parameter INIT_2E = 256'b0,
parameter INIT_2F = 256'b0,
parameter INIT_30 = 256'b0,
parameter INIT_31 = 256'b0,
parameter INIT_32 = 256'b0,
parameter INIT_33 = 256'b0,
parameter INIT_34 = 256'b0,
parameter INIT_35 = 256'b0,
parameter INIT_36 = 256'b0,
parameter INIT_37 = 256'b0,
parameter INIT_38 = 256'b0,
parameter INIT_39 = 256'b0,
parameter INIT_3A = 256'b0,
parameter INIT_3B = 256'b0,
parameter INIT_3C = 256'b0,
parameter INIT_3D = 256'b0,
parameter INIT_3E = 256'b0,
parameter INIT_3F = 256'b0,
parameter INIT_40 = 256'b0,
parameter INIT_41 = 256'b0,
parameter INIT_42 = 256'b0,
parameter INIT_43 = 256'b0,
parameter INIT_44 = 256'b0,
parameter INIT_45 = 256'b0,
parameter INIT_46 = 256'b0,
parameter INIT_47 = 256'b0,
parameter INIT_48 = 256'b0,
parameter INIT_49 = 256'b0,
parameter INIT_4A = 256'b0,
parameter INIT_4B = 256'b0,
parameter INIT_4C = 256'b0,
parameter INIT_4D = 256'b0,
parameter INIT_4E = 256'b0,
parameter INIT_4F = 256'b0,
parameter INIT_50 = 256'b0,
parameter INIT_51 = 256'b0,
parameter INIT_52 = 256'b0,
parameter INIT_53 = 256'b0,
parameter INIT_54 = 256'b0,
parameter INIT_55 = 256'b0,
parameter INIT_56 = 256'b0,
parameter INIT_57 = 256'b0,
parameter INIT_58 = 256'b0,
parameter INIT_59 = 256'b0,
parameter INIT_5A = 256'b0,
parameter INIT_5B = 256'b0,
parameter INIT_5C = 256'b0,
parameter INIT_5D = 256'b0,
parameter INIT_5E = 256'b0,
parameter INIT_5F = 256'b0,
parameter INIT_60 = 256'b0,
parameter INIT_61 = 256'b0,
parameter INIT_62 = 256'b0,
parameter INIT_63 = 256'b0,
parameter INIT_64 = 256'b0,
parameter INIT_65 = 256'b0,
parameter INIT_66 = 256'b0,
parameter INIT_67 = 256'b0,
parameter INIT_68 = 256'b0,
parameter INIT_69 = 256'b0,
parameter INIT_6A = 256'b0,
parameter INIT_6B = 256'b0,
parameter INIT_6C = 256'b0,
parameter INIT_6D = 256'b0,
parameter INIT_6E = 256'b0,
parameter INIT_6F = 256'b0,
parameter INIT_70 = 256'b0,
parameter INIT_71 = 256'b0,
parameter INIT_72 = 256'b0,
parameter INIT_73 = 256'b0,
parameter INIT_74 = 256'b0,
parameter INIT_75 = 256'b0,
parameter INIT_76 = 256'b0,
parameter INIT_77 = 256'b0,
parameter INIT_78 = 256'b0,
parameter INIT_79 = 256'b0,
parameter INIT_7A = 256'b0,
parameter INIT_7B = 256'b0,
parameter INIT_7C = 256'b0,
parameter INIT_7D = 256'b0,
parameter INIT_7E = 256'b0,
parameter INIT_7F = 256'b0
) (
input wire i_clock,
input wire i_reset,
input wire i_enable,
input wire [14:0] i_address,
output wire o_data,
input wire [1:0] i_data,
input wire i_we
);
wire [31:0] DO_PATTERN;
wire [15:0] ADDR_PATTERN;
assign ADDR_PATTERN[14:0] = i_address;
assign o_data = DO_PATTERN[0];
wire [31:0] DI_PATTERN;
assign DI_PATTERN[1:0] = i_data;
RAMB36E1 # (
.DOA_REG (0),
.INIT_00 (INIT_00),
.INIT_01 (INIT_01),
.INIT_02 (INIT_02),
.INIT_03 (INIT_03),
.INIT_04 (INIT_04),
.INIT_05 (INIT_05),
.INIT_06 (INIT_06),
.INIT_07 (INIT_07),
.INIT_08 (INIT_08),
.INIT_09 (INIT_09),
.INIT_0A (INIT_0A),
.INIT_0B (INIT_0B),
.INIT_0C (INIT_0C),
.INIT_0D (INIT_0D),
.INIT_0E (INIT_0E),
.INIT_0F (INIT_0F),
.INIT_10 (INIT_10),
.INIT_11 (INIT_11),
.INIT_12 (INIT_12),
.INIT_13 (INIT_13),
.INIT_14 (INIT_14),
.INIT_15 (INIT_15),
.INIT_16 (INIT_16),
.INIT_17 (INIT_17),
.INIT_18 (INIT_18),
.INIT_19 (INIT_19),
.INIT_1A (INIT_1A),
.INIT_1B (INIT_1B),
.INIT_1C (INIT_1C),
.INIT_1D (INIT_1D),
.INIT_1E (INIT_1E),
.INIT_1F (INIT_1F),
.INIT_20 (INIT_20),
.INIT_21 (INIT_21),
.INIT_22 (INIT_22),
.INIT_23 (INIT_23),
.INIT_24 (INIT_24),
.INIT_25 (INIT_25),
.INIT_26 (INIT_26),
.INIT_27 (INIT_27),
.INIT_28 (INIT_28),
.INIT_29 (INIT_29),
.INIT_2A (INIT_2A),
.INIT_2B (INIT_2B),
.INIT_2C (INIT_2C),
.INIT_2D (INIT_2D),
.INIT_2E (INIT_2E),
.INIT_2F (INIT_2F),
.INIT_30 (INIT_30),
.INIT_31 (INIT_31),
.INIT_32 (INIT_32),
.INIT_33 (INIT_33),
.INIT_34 (INIT_34),
.INIT_35 (INIT_35),
.INIT_36 (INIT_36),
.INIT_37 (INIT_37),
.INIT_38 (INIT_38),
.INIT_39 (INIT_39),
.INIT_3A (INIT_3A),
.INIT_3B (INIT_3B),
.INIT_3C (INIT_3C),
.INIT_3D (INIT_3D),
.INIT_3E (INIT_3E),
.INIT_3F (INIT_3F),
.INIT_40 (INIT_40),
.INIT_41 (INIT_41),
.INIT_42 (INIT_42),
.INIT_43 (INIT_43),
.INIT_44 (INIT_44),
.INIT_45 (INIT_45),
.INIT_46 (INIT_46),
.INIT_47 (INIT_47),
.INIT_48 (INIT_48),
.INIT_49 (INIT_49),
.INIT_4A (INIT_4A),
.INIT_4B (INIT_4B),
.INIT_4C (INIT_4C),
.INIT_4D (INIT_4D),
.INIT_4E (INIT_4E),
.INIT_4F (INIT_4F),
.INIT_50 (INIT_50),
.INIT_51 (INIT_51),
.INIT_52 (INIT_52),
.INIT_53 (INIT_53),
.INIT_54 (INIT_54),
.INIT_55 (INIT_55),
.INIT_56 (INIT_56),
.INIT_57 (INIT_57),
.INIT_58 (INIT_58),
.INIT_59 (INIT_59),
.INIT_5A (INIT_5A),
.INIT_5B (INIT_5B),
.INIT_5C (INIT_5C),
.INIT_5D (INIT_5D),
.INIT_5E (INIT_5E),
.INIT_5F (INIT_5F),
.INIT_60 (INIT_60),
.INIT_61 (INIT_61),
.INIT_62 (INIT_62),
.INIT_63 (INIT_63),
.INIT_64 (INIT_64),
.INIT_65 (INIT_65),
.INIT_66 (INIT_66),
.INIT_67 (INIT_67),
.INIT_68 (INIT_68),
.INIT_69 (INIT_69),
.INIT_6A (INIT_6A),
.INIT_6B (INIT_6B),
.INIT_6C (INIT_6C),
.INIT_6D (INIT_6D),
.INIT_6E (INIT_6E),
.INIT_6F (INIT_6F),
.INIT_70 (INIT_70),
.INIT_71 (INIT_71),
.INIT_72 (INIT_72),
.INIT_73 (INIT_73),
.INIT_74 (INIT_74),
.INIT_75 (INIT_75),
.INIT_76 (INIT_76),
.INIT_77 (INIT_77),
.INIT_78 (INIT_78),
.INIT_79 (INIT_79),
.INIT_7A (INIT_7A),
.INIT_7B (INIT_7B),
.INIT_7C (INIT_7C),
.INIT_7D (INIT_7D),
.INIT_7E (INIT_7E),
.INIT_7F (INIT_7F),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.RAM_MODE("TDP"),
.READ_WIDTH_A (1),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.SIM_COLLISION_CHECK("NONE"),
.SIM_DEVICE ("7SERIES"),
.SRVAL_A (72'h0),
.WRITE_MODE_A ("WRITE_FIRST"),
.WRITE_WIDTH_A (2)
) bram36_single_bl (
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.DOBDO (),
.DOPADOP (),
.DOPBDOP (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.ADDRBWRADDR (16'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CLKBWRCLK (1'b0),
.DIBDI (32'b0),
.DIPADIP (4'b0),
.DIPBDIP (4'b0),
.ENARDEN (i_enable),
.ENBWREN (1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.REGCEAREGCE (1'b0),
.REGCEB (1'b0),
.RSTRAMARSTRAM (i_reset),
.RSTRAMB (1'b0),
.RSTREGARSTREG (1'b0),
.RSTREGB (1'b0),
.WEBWE (8'b0),
.WEA ({3'b0, i_we}),
.DIADI (DI_PATTERN),
.CLKARDCLK (i_clock),
// 15-bit address
.ADDRARDADDR (ADDR_PATTERN),
// 1-bit output
.DOADO (DO_PATTERN)
);
endmodule
Raw
runApp.h
# include <GLES2/gl2.h>
# include <cstdio>
void runApp (int width, int height) {
printf("GL_VERSION : %s\n", glGetString(GL_VERSION) );
printf("GL_RENDERER : %s\n", glGetString(GL_RENDERER) );
glViewport(0, 0, width, height);
glClearColor(1.0f, 0.0f, 0.0f, 1.0f);
glClear(GL_COLOR_BUFFER_BIT);
/* Create swap chain GPGPU render textures
const gpgpuTexture = [,];
for (let i = 0; i < 2; ++i) {
gpgpuTexture[i] = {
texture: gl.createTexture(),
framebuffer: gl.createFramebuffer()
};
gl.bindTexture(gl.TEXTURE_2D, gpgpuTexture[i].texture);
gl.texParameteri(gl.TEXTURE_2D, gl.TEXTURE_MAG_FILTER, gl.NEAREST);
gl.texParameteri(gl.TEXTURE_2D, gl.TEXTURE_MIN_FILTER, gl.NEAREST);
gl.texImage2D(gl.TEXTURE_2D, 0, gl.RGBA, gpgpuTextureSide, gpgpuTextureSide, 0, gl.RGBA, gl.UNSIGNED_BYTE, data);
gl.bindFramebuffer(gl.FRAMEBUFFER, gpgpuTexture[i].framebuffer);
gl.framebufferTexture2D(gl.FRAMEBUFFER, gl.COLOR_ATTACHMENT0, gl.TEXTURE_2D, gpgpuTexture[i].texture, 0);
}
*/
//char* data[width * height * 8] = { 0 };
//glBindFramebuffer(GL_FRAMEBUFFER, 1);//gpgpuTexture[chainIdSrc].framebuffer);
//glReadPixels(0, 0, width, height, GL_RGBA, GL_UNSIGNED_BYTE, data);
}
Raw
testbench.v
`timescale 1ns / 1ps
module testbench ();
reg GCLK100 = 1'b0;
wire ETH_MDC;
wire ETH_MDIO, ETH_RX_DV;
reg signal_ETH_MDIO_write = 1'bz;
reg signal_ETH_RX_DV_write = 1'bz;
wire signal_ETH_MDIO_read;
wire signal_ETH_RX_DV_read;
assign signal_ETH_MDIO_read = ETH_MDIO;
assign ETH_MDIO = signal_ETH_MDIO_write;
assign signal_ETH_RX_DV_read = ETH_RX_DV;
assign ETH_RX_DV = signal_ETH_RX_DV_write;
reg ETH_REF_CLK = 1'b0;
wire ETH_RSTN;
reg ETH_CRS_DV = 1'b0, ETH_RXD0 = 1'b0, ETH_RXD1 = 1'b0;
wire ETH_TX_EN, ETH_TXD0, ETH_TXD1;
wire LED0_B, LED1_B, LED2_B, LED3_B;
wire LED0_R, LED1_R, LED2_R, LED3_R;
reg DONE = 1'b0;
wire CK_IO26, CK_IO27, CK_IO28, CK_IO29, CK_IO30, CK_IO31, CK_IO32, CK_IO33, CK_IO34;
reg BTN3 = 1'b0, BTN2 = 1'b0, BTN1 = 1'b0, SW3 = 1'b0, SW2 = 1'b0, SW1 = 1'b0, SW0 = 1'b0;
wire CK_IO0, CK_IO1, CK_IO2, CK_IO3, CK_IO4, CK_IO5;
reg CK_RST = 1'b1;
always begin
#5 GCLK100 = ~GCLK100;
end
always begin
#10 ETH_REF_CLK = ~ETH_REF_CLK;
end
top entire_fpga (
.GCLK100 (GCLK100),
.CK_RST (CK_RST),
.BTN0 (BTN0),
.BTN1 (BTN1),
.BTN2 (BTN2),
.BTN3 (BTN3),
.SW0 (SW0),
.SW1 (SW1),
.SW2 (SW2),
.SW3 (SW3),
.LED0_B (LED0_B),
.LED1_B (LED1_B),
.LED2_B (LED2_B),
.LED3_B (LED3_B),
.LED0_R (LED0_R),
.LED1_R (LED1_R),
.LED2_R (LED2_R),
.LED3_R (LED3_R),
/*
.ETH_RXD0 (ETH_RXD0),
.ETH_RXD1 (ETH_RXD1),
.ETH_CRS_DV (ETH_CRS_DV),
.ETH_TXD0 (ETH_TXD0),
.ETH_TXD1 (ETH_TXD1),
.ETH_TX_EN (ETH_TX_EN),
.ETH_MDC (ETH_MDC),
.ETH_MDIO (ETH_MDIO),
.ETH_RX_DV (ETH_RX_DV),
.ETH_REF_CLK (ETH_REF_CLK),
.ETH_RSTN (ETH_RSTN),
*/
// LED strip
/*
.CK_IO37 (CK_IO37),
.CK_IO39 (CK_IO39),
*/
// Lattice Reprogrammer
.CK_IO0 (CK_IO0),
.CK_IO1 (CK_IO1),
.CK_IO2 (CK_IO2),
.CK_IO3 (CK_IO3),
.CK_IO4 (CK_IO4),
.CK_IO5 (CK_IO5),
// Diagnostic outputs
.CK_IO26 (CK_IO26),
.CK_IO27 (CK_IO27),
.CK_IO28 (CK_IO28),
.CK_IO29 (CK_IO29),
.CK_IO30 (CK_IO30),
.CK_IO31 (CK_IO31),
.CK_IO32 (CK_IO32),
.CK_IO33 (CK_IO33),
.CK_IO34 (CK_IO34),
.JD7 (ETH_TXD1), // TX1
.JA1 (ETH_TXD0), // TX0
.JA2 (ETH_RXD1), // RX1
.JA3 (ETH_CRS_DV), // CRS_DV
.JA4 (ETH_MDC), // MDC
.JA7 (ETH_TX_EN), // TX_EN
.JA8 (ETH_RXD0), // RX0
.JA9 (ETH_REF_CLK), // REFCLK
.JA10 (ETH_MDIO) // MDIO
/* .LED4 (LED4),
.LED5 (LED5),
.LED6 (LED6),
.LED7 (LED7) */
);
/*
CustomDelay #(.CLOCK_FREQUENCY_HZ (100_000_000))
delay_service (
.CLK (GCLK100),
.DELAY_IN_NANOSECONDS (32'd80),
.RESET (REQUEST_DELAY),
.COMPLETE (DELAY_PASSED));
*/
initial begin
#4205 signal_ETH_RX_DV_write = 1'b1;
#1340
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#15
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
// SFD byte
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// ff ff ff ff ff ff c8 d9 d2 78 13 34 08 06 00 01 08 00 06 04 00 01 c8 d9 d2 78 13 34 c0 a8 00 01 00 00 00 00 00 00 c0 a8 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cd f4 59 79
// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
// \xff\xff\xff\xff\xff\xff\xc8\xd9\xd2\x78\x13\x34\x08\x06\x00\x01\x08\x00\x06\x04\x00\x01\xc8\xd9\xd2\x78\x13\x34\xc0\xa8\x00\x01\x00\x00\x00\x00\x00\x00\xc0\xa8\x00\x02\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00
// Another one for 192.168.254.54 and requester .11:
// \xc8\xd9\xd2\x78\x13\x34\x42\x55\x55\x55\x55\x55\x08\x06\x00\x01\x08\x00\x06\x04\x00\x02\x42\x55\x55\x55\x55\x55\xc0\xa8\xfe\x36\xc8\xd9\xd2\x78\x13\x34\xc0\xa8\xfe\x0b\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00
// Byte 0
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 1
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 2
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 3
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 4
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 5
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Bytes 6, 7, 8, 9, 10, 11 - sender's MAC c8 d9 d2 78 13 34
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 12: 0x08
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 13: 0x06
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 14: 0x00
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 15: 0x01
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 16: 0x08
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 17: 0x00
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 18: 0x06
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 19: 0x04
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 20: 0x00
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 21: 0x01
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 22, 23, 24, 25, 26, 27 - sender's MAC c8 d9 d2 78 13 34
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 28, 29, 30, 31 - sender's IP address c0 a8 00 01
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 32, 33, 34, 35, 36, 37 - dest MAC address (unknown)
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 38, 39, 40, 41 - dest IP address to resolve into MAC 36_fe_a8_c0
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#1280
// 58
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
// 59
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
// 60
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// 61
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// 62
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
// Last byte # 63
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
/*
#1345
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#1345
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#1340
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#15
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
// SFD byte
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// ff ff ff ff ff ff c8 d9 d2 78 13 34 08 06 00 01 08 00 06 04 00 01 c8 d9 d2 78 13 34 c0 a8 00 01 00 00 00 00 00 00 c0 a8 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cd f4 59 79
// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
// \xff\xff\xff\xff\xff\xff\xc8\xd9\xd2\x78\x13\x34\x08\x06\x00\x01\x08\x00\x06\x04\x00\x01\xc8\xd9\xd2\x78\x13\x34\xc0\xa8\x00\x01\x00\x00\x00\x00\x00\x00\xc0\xa8\x00\x02\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00
// Byte 0
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 1
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 2
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 3
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 4
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 5
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 6
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 7
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#4000
// 58
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
// 59
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
// 60
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// 61
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// 62
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
// Last byte # 63
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#1340
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#15
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
// SFD byte
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// ff ff ff ff ff ff c8 d9 d2 78 13 34 08 06 00 01 08 00 06 04 00 01 c8 d9 d2 78 13 34 c0 a8 00 01 00 00 00 00 00 00 c0 a8 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cd f4 59 79
// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
// \xff\xff\xff\xff\xff\xff\xc8\xd9\xd2\x78\x13\x34\x08\x06\x00\x01\x08\x00\x06\x04\x00\x01\xc8\xd9\xd2\x78\x13\x34\xc0\xa8\x00\x01\x00\x00\x00\x00\x00\x00\xc0\xa8\x00\x02\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00
// Bytes 0-5: target MAC 42 55 55 55 55 55
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
// Bytes 6, 7, 8, 9, 10, 11 - sender's MAC c8 d9 d2 78 13 34
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 12: 0x08
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 13: 0x06
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 14: 0x00
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 15: 0x01
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 16: 0x08
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 17: 0x00
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 18: 0x06
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 19: 0x04
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 20: 0x00
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 21: 0x01
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 22, 23, 24, 25, 26, 27 - sender's MAC c8 d9 d2 78 13 34
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 28, 29, 30, 31 - sender's IP address c0 a8 00 01
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 32, 33, 34, 35, 36, 37 - dest MAC address (unknown)
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 38, 39, 40, 41 - dest IP address to resolve into MAC 36_fe_a8_c0
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#1280
// 58
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
// 59
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
// 60
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// 61
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// 62
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
// Last byte # 63
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#1345
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#1345
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
*/
# 4000 CK_RST = 1'b0;
# 4200 CK_RST = 1'b1;
# 1_800_000 CK_RST = 1'b0;
# 4200 CK_RST = 1'b1;
#5000 DONE = 1'b1;
end
endmodule
/*
module testbench2 ();
reg GCLK100, CK_RST, BTN0, BTN1;
wire ETH_REF_CLK;//, CK_IO35, CK_IO38, BTN0;
wire CK_IO37, CK_IO39, LED6, LED7, ETH_MDC, ETH_MDIO, LED1_B;
// wire CK_IO34, CK_IO37, CK_IO36, CK_IO39, LED4, LED5, LED6, LED7;
reg BTN2, SW0;
top t (
.GCLK100 (GCLK100),
.CK_RST (CK_RST),
.BTN0 (BTN0),
.BTN1 (BTN1),
.BTN2 (BTN2),
.SW0 (SW0),
.LED1_B (LED1_B),
.ETH_REF_CLK (ETH_REF_CLK),
.ETH_MDC (ETH_MDC),
.ETH_MDIO (ETH_MDIO),
.CK_IO37 (CK_IO37),
.CK_IO39 (CK_IO39),
.CK_IO0 (CK_IO0),
.CK_IO1 (CK_IO1),
.CK_IO2 (CK_IO2),
.CK_IO3 (CK_IO3),
.CK_IO4 (CK_IO4),
.CK_IO5 (CK_IO5),
.LED4 (LED4),
.LED5 (LED5),
.LED6 (LED6),
.LED7 (LED7)
);
always begin
#5 GCLK100 = ~GCLK100;
end
*/
//always begin
// #20 ETH_REF_CLK = ~ETH_REF_CLK;
//end
/*
reg EVT_EDGE, not_in1, xnor_in1, xnor_in2;
wire EXIT_PULSE, xnor_out, not_out;
EdgeToPulse pulse1 (
.EDGE (EVT_EDGE),
.PULSE (EXIT_PULSE));
LUT4 # (
.INIT (16'b01010101_01010101)
) not1 (
.O (not_out),
.I0 (not_in1),
.I1 (1'b0),
.I2 (1'b0),
.I3 (1'b0)
);
LUT4 # (
.INIT (16'b10011001_10011001)
) xnor1 (
.O (xnor_out),
.I0 (xnor_in1),
.I1 (xnor_in2),
.I2 (1'b0),
.I3 (1'b0)
);
* /
initial begin
//Initialize clock
GCLK100 = 1'b0;
//ETH_REF_CLK = 1'b0;
CK_RST = 1'b1;
BTN0 = 1'b0;
BTN1 = 1'b0;
/*EVT_EDGE = 1'b0;
xnor_in1 = 1'b0;
xnor_in2 = 1'b0;
not_in1 = 1'b0;* /
BTN2 = 1'b0;
SW0 = 1'b0;
#15 CK_RST = 1'b0;
#3_000 CK_RST = 1'b1;
#10 BTN1 = 1'b1;
#10 BTN2 = 1'b1;
#10 BTN2 = 1'b0;
#10 SW0 = 1'b1;
#10 BTN2 = 1'b1;
#10 SW0 = 1'b0;
#10 SW0 = 1'b1;
/*#20 EVT_EDGE = 1'b1;
#20 EVT_EDGE = 1'b0;
#20 EVT_EDGE = 1'b1;
#20 EVT_EDGE = 1'b0;
#20 not_in1 = 1'b1;
#20 not_in1 = 1'b0;
#20 not_in1 = 1'b1;
#20 xnor_in1 = 1'b1;
#20 xnor_in1 = 1'b0;
#20 xnor_in2 = 1'b1;
#20 xnor_in1 = 1'b1;* /
#11_500_000 CK_RST = 1'b0;
#100 CK_RST = 1'b1;
//#185 BTN0 = 1'b1;
//#27 BTN0 = 1'b0;
//End simulation
//#90_000_000
//$finish;
end
endmodule
*/
/*
`define DELAY_IN_NS 2'd0
`define DELAY_IN_US 2'd1
`define DELAY_IN_MS 2'd2
`define DELAY_IN_S 2'd3
module CustomDelay #(
parameter CLOCK_CYCLE_NS = 10
) (
input wire CLK,
input wire [31:0] DELAY_IN_NANOSECONDS,
input wire RESET,
output wire COMPLETE
);
// Statically calculate the number of bits required to represent the counted number
// localparam CLOCK_CYCLE_IN_NS = 32'b1 / CLOCK_FREQUENCY_HZ;
//localparam NUMBER_OF_PULSES_FOR_MAXIMUM_DELAY = 32'h7FFFFFFF / CLOCK_CYCLE_IN_NS;
//localparam MAXIMUM_BITS = $clog2(NUMBER_OF_PULSES_FOR_MAXIMUM_DELAY);
reg [32:0] counter = 0;
reg complete = 1'b0;
reg counting = 1'b0;
always @(posedge CLK) begin
if (RESET)
begin
counter <= DELAY_IN_NANOSECONDS / CLOCK_CYCLE_NS;
complete <= 1'b0;
counting <= 1'b1;
end
if (counting & ~complete & counter == 32'b1 & ~RESET)
begin
complete <= 1'b1;
counting <= 1'b0;
end
if (counting)
begin
counter <= counter - 1;
end
end
assign COMPLETE = complete;
endmodule
*/
// Unused in RMII
//input wire ETH_RXD3,
//input wire ETH_RXD2,
//output wire ETH_TXD2,
//output wire ETH_TXD3,
// input wire ETH_COL, // PHYAD0 not in full-duplex. Always 0 in full-duplex. Not used in RMII
// input wire ETH_RXERR, // MDIX_EN synchronous to RX_CLK if error receiving
// input wire ETH_RX_DV, // MII_MODE asserted high when valid data received
//input wire ETH_TX_CLK, // 25 MHz derived from ETH_REF_CLK
// input wire ETH_RX_CLK, // 25 MHz recovered. Not used in RMII
Raw
top.v
`timescale 1ns / 1ps
`define COUNTER_RESOLUTION_BITS 24
// Can receive Ethernet packets on 100 Mbit/s up to 9200 bytes in size.
// Standard packets are 1500 bytes.
// Receives Ethernet header in dedicated memory to interface with external world:
// The packet structure:
//
module JumboFrameReprogrammer ();
endmodule
module SystemCounter #(
parameter RESOLUTION_BITS = 5
) (
input wire CLOCK,
output reg [RESOLUTION_BITS-1:0] COUNTER = 0
);
always @(posedge CLOCK)
begin
COUNTER <= #4 COUNTER + 1'b1;
end
endmodule
module DelayEngine # (
parameter COUNTER_RESOLUTION_BITS = `COUNTER_RESOLUTION_BITS ) (
input wire CLOCK,
output wire COUNTING,
input wire START,
input wire [COUNTER_RESOLUTION_BITS-1:0] DELAY,
output wire COUNTED
);
// Global supercounter
wire [COUNTER_RESOLUTION_BITS-1:0] SYSTEM_COUNTER;
SystemCounter #(
.RESOLUTION_BITS (COUNTER_RESOLUTION_BITS)
) system_counter (
.CLOCK (CLOCK),
.COUNTER (SYSTEM_COUNTER)
);
// Timers service
reg [COUNTER_RESOLUTION_BITS-1:0] timestamp_started_1 = 0;
reg [COUNTER_RESOLUTION_BITS-1:0] delay_1 = 0;
reg counting = 1'b0;
reg counted = 1'b0;
reg [COUNTER_RESOLUTION_BITS-1:0] time_passed_since_timestamp_1 = 0;
always @(posedge CLOCK)
begin
if (~counting & START)
begin
delay_1 = DELAY;
timestamp_started_1 <= #4 SYSTEM_COUNTER;
counting <= #4 1'b1;
counted <= #4 1'b0;
end
else
// Compute how many ticks have passed
begin
if (counting)
begin
time_passed_since_timestamp_1 <= #4 (SYSTEM_COUNTER - timestamp_started_1);
if (time_passed_since_timestamp_1 >= delay_1)
begin
counting <= #4 1'b0;
counted <= #4 1'b1;
end
end
end
end
assign COUNTING = counting;
assign COUNTED = counted;
endmodule
module top (
input wire GCLK100, // Quartz 100 MHz
input wire CK_RST,
input wire BTN0,
input wire BTN1,
input wire BTN2,
input wire BTN3,
input wire SW0,
input wire SW1,
input wire SW2,
input wire SW3,
output wire CK_IO37, //+
output wire CK_IO39, //+
output wire CK_IO5, //SCK
input wire CK_IO4, // SO
output wire CK_IO3, //SI
output wire CK_IO2, // SS_B
input wire CK_IO1, // CDONE
output wire CK_IO0, // CRESET_B
// ONLY OUTPUTS HERE, DON'T FRY THE BOARD!!!
output wire CK_IO26, // (black)
output wire CK_IO27,
output wire CK_IO28,
output wire CK_IO29,
output wire CK_IO30,
output wire CK_IO31,
output wire CK_IO32,
output wire CK_IO33, // (orange wire)
// A separate wire (the green one) DON'T FRY THE BOARD!
output wire CK_IO34,
// Management interface
/*
output wire ETH_MDC, // Management data clock max 25 MHz
inout wire ETH_MDIO, // Management data I/O
output wire ETH_TX_EN, // Active high
output wire ETH_TXD1,
output wire ETH_TXD0,
input wire ETH_RXD1,
input wire ETH_RXD0,
input wire ETH_CRS_DV, // "Data is ready" CRS_DV/LED_CFG not in full-duplex. Receive medium is not idle (carrier sense)
// Check that these are empty!!! (we're successfully in RMII)
input wire ETH_RXD2,
input wire ETH_RXD3,
// Physical interface
output wire ETH_REF_CLK, // 50 MHz in RMII mode
output wire ETH_RSTN, // Reset active low 1 us power on reset only
// To put into RMII mode only
inout wire ETH_RX_DV, // Put to 1 while resetting to put PHY into the RMII mode then go Z
*/
output wire LED4,
output wire LED5,
output wire LED6,
output wire LED7,
output wire LED0_B,
output wire LED0_R,
output wire LED0_G,
output wire LED1_B,
output wire LED1_R,
output wire LED1_G,
output wire LED2_B,
output wire LED2_R,
output wire LED2_G,
output wire LED3_B,
output wire LED3_R,
output wire LED3_G,
output wire JD7, // TX1
output wire JA1, // TX0
input wire JA2, // RX1
input wire JA3, // CRS_DV
output wire JA4, // MDC
output wire JA7, // TX_EN
input wire JA8, // RX0
input wire JA9, // REFCLK
inout wire JA10, // MDIO
inout wire JD2,
output wire JD3,
output wire JD4,
output wire JD8,
inout wire JD9,
output wire JD10
);
wire SPI_FLASH_SI = JD2; // blue
wire SPI_FLASH_SCK = JD3; // green
wire SPI_FLASH_NOT_HOLD = JD4; // yellow
wire SPI_FLASH_NOT_WP = JD8; // orange
wire SPI_FLASH_SO = JD9; // red
wire SPI_FLASH_NOT_CS = JD10; // brown
assign SPI_FLASH_NOT_CS = ~BTN0;
assign SPI_FLASH_SCK = GCLK100; //1'b0;
assign SPI_FLASH_NOT_WP = 1'b1;
assign SPI_FLASH_NOT_HOLD = 1'b1;
// 9 pins of RMII PHY
wire CRS_DV, RX0, RX1, REFCLK, MDIO;
reg MDC = 1'b0;
/*
reg mdio_signal_write = 1'bz;
wire mdio_signal_read;
assign ETH_MDIO = mdio_signal_write;
assign mdio_signal_read = ETH_MDIO;
*/
reg TX_EN = 1'b0;
reg TX0 = 1'b0;
reg TX1 = 1'b0;
/*
reg MDIO_src = 1'b0;
always @(posedge REFCLK)
begin
if (~MDC)
begin
mdio_signal_write <= #4 1'bz;
MDIO_src <= #4 mdio_signal_read;
end
else
mdio_signal_write <= #4 1'b0;
begin
end
end
*/
// Delay engine for the RMII emulator
wire DELAY_ENGINE_COUNTING, DELAY_ENGINE_COUNTED, DELAY_ENGINE_START;
wire [`COUNTER_RESOLUTION_BITS-1:0] DELAY_ENGINE_DELAY;
assign JA7 = TX_EN;
assign JD7 = TX1;
assign JA1 = TX0;
assign RX0 = JA8;
assign RX1 = JA2;
assign CRS_DV = JA3;
assign JA4 = MDC;
// assign REFCLK = JA9;
BUFG global_clock_50_mhz (
.I (JA9),
.O (REFCLK));
assign MDIO = JA10;
/*
EthernetPhyWrapper ethernet_rmii_chip (
// 9-pin RMII emulation
.MDC (MDC), // Management data clock max 25 MHz
// .MDIO (MDIO), // Management data I/O
.TX_EN (TX_EN), // Active high
.TX1 (TX1),
.TX0 (TX0),
.RX1 (RX1),
.RX0 (RX0),
.CRS_DV (CRS_DV),
.REFCLK (REFCLK),
// Arty interface. Remove in real external RMII PHY.
// Emulates power-on reset because Arty boots the PHY in MII mode
// Transparent wires
// Management interface
.ARTY_ETH_MDC (ETH_MDC), // Management data clock max 25 MHz
// .ARTY_ETH_MDIO (ETH_MDIO), // Management data I/O
.ARTY_ETH_TX_EN (ETH_TX_EN), // Active high
.ARTY_ETH_TXD1 (ETH_TXD1),
.ARTY_ETH_TXD0 (ETH_TXD0),
.ARTY_ETH_RXD1 (ETH_RXD1),
.ARTY_ETH_RXD0 (ETH_RXD0),
.ARTY_ETH_CRS_DV (ETH_CRS_DV), // "Data is ready" CRS_DV/LED_CFG not in full-duplex. Receive medium is not idle (carrier sense)
// Physical interface
.ARTY_ETH_REF_CLK (ETH_REF_CLK), // 50 MHz in RMII mode. Derived from GCLK100
.ARTY_ETH_RSTN (ETH_RSTN), // Reset active low 1 us power on reset only
// To put into RMII mode only
.ARTY_ETH_RX_DV (ETH_RX_DV), // Put to 1 while resetting to put PHY into the RMII mode then go Z
.ARTY_GCLK100 (GCLK100),
.DELAY_ENGINE_COUNTING (DELAY_ENGINE_COUNTING),
.DELAY_ENGINE_COUNTED (DELAY_ENGINE_COUNTED),
.DELAY_ENGINE_START (DELAY_ENGINE_START),
.DELAY_ENGINE_DELAY (DELAY_ENGINE_DELAY)
);
*/
DelayEngine delay_engine (
.CLOCK (REFCLK),
.COUNTING (DELAY_ENGINE_COUNTING),
.START (DELAY_ENGINE_START),
.DELAY (DELAY_ENGINE_DELAY),
.COUNTED (DELAY_ENGINE_COUNTED));
assign LED3_R = CRS_DV;
reg [7:0] receiving_byte = 8'd0;
reg [7:0] received_byte = 8'd0;
reg byte_is_ready = 1'b0;
reg [1:0] receive_ptr = 2'd0;
reg [13:0] receiving_byte_number = 14'd0;
reg receiving = 1'b0;
reg synchronized_crs_dv_0 = 1'b0;
reg synchronized_crs_dv = 1'b0;
reg sfd_detected = 1'b0;
reg [1:0] no_crs_toggle = 2'd0;
reg [31:0] crc_state = 32'hFFFFFFFF;
reg [7:0] latched_byte_for_crc32 = 8'd0;
(* keep = "true", DONT_TOUCH = "true" *) reg [31:0] fcs_reg = 32'h00000000;
wire [31:0] crc_next_combinational_slow;
(* keep = "true", DONT_TOUCH = "true" *) Lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.LFSR_CONFIG ("GALOIS"),
.STYLE("LOOP")
)
eth_crc_8 (
.data_in(latched_byte_for_crc32), // { RX1, RX0, receiving_byte[5:0] }
.state_in(crc_state),
.state_out(crc_next_combinational_slow)
);
reg byte_for_crc32_is_ready = 1'b0;
reg reset_crc_state = 1'b0;
/*
always @(posedge REFCLK)
begin
if (reset_crc_state)
begin
crc_state <= #4 32'hFFFFFFFF;
end
else
if (byte_for_crc32_is_ready)
begin
crc_state <= #13 crc_next_combinational_slow;
end
fcs_reg <= #4 ~crc_state;
end */
// ARP packet parser.
// We start responding while this packet runs the data.
// Because the response won't complete before a potential new packet can arrive,
// if we detected an ARP packet we're responding to, we will lock the parser until the send finishes.
// This may lead to misses of packets, but these are repeated often by the ARP stack.
reg arp_parser_is_locked = 1'b0;
reg sending_arp_response = 1'b0;
wire [10:0] arp_response_bit_address;
//TX1 <= #4 RX1;
//TX_EN <= #4 1'b1;
//TX0 <= #4 RX0;
//TX1 <= #4 RX1;
reg reset_arp_response_counter = 1'b0;
reg [1:0] skip_first_arp_sending_counter_pulse = 2'b10;
reg maybe_arp_request = 1'b1; // & each condition until the last one on every received byte. Sets to 1 on first packet
reg target_is_broadcast = 1'b1;
reg target_is_direct_mac_address = 1'b1;
assign LED0_R = ~maybe_arp_request;
assign LED1_R = ~target_is_broadcast;
assign LED2_R = ~target_is_direct_mac_address;
wire arp_response_sent;
reg [31:0] requester_ip_address = 32'b0;
reg [47:0] requester_mac_address = 48'b0;
// TODO: fix test
//wire [31:0] const_device_ip_address = 32'h02_00_a8_c0;
wire [31:0] const_device_ip_address = 32'h36_fe_a8_c0;
wire [47:0] const_device_mac_address = 48'h55_55_55_55_55_42;
wire [63:0] const_eth_preamble = 64'hD5_55_55_55_55_55_55_55;
// Offsets
wire [3:0] current_dibit_index_in_byte = receive_ptr * 3'd2;
wire [5:0] mac_index_combinational_slow = (receiving_byte_number - 14'd6) * 14'd8 + current_dibit_index_in_byte;
wire [4:0] ip_address_index_combinational_slow = (receiving_byte_number - 14'd28) * 14'd8 + current_dibit_index_in_byte;
wire [4:0] our_ip_address_index_combinational_slow = (receiving_byte_number - 14'd38) * 14'd8 + current_dibit_index_in_byte;
wire [5:0] our_mac_address_index_combinational_slow = receiving_byte_number * 14'd8 + current_dibit_index_in_byte;
wire [7:0] eth_frame_type_index_combinational_slow = (receiving_byte_number - 14'd12) * 14'd8 + current_dibit_index_in_byte;
wire [79:0] const_eth_frame_type_pattern = 80'h01000406000801000608;
wire [79:0] const_eth_frame_type_reply_pattern = 80'h02000406000801000608;
wire [15:0] const_eth_frame_type_ip_v4 = 16'h0008;
// 512 bytes max address (doesn't support 1500 packets yet)
reg [8:0] crc_encoding_byte_number = 9'b0;
reg maybe_udp_packet = 1'b1;
reg code_red = 1'b0;
assign LED3_G = code_red;
reg [7:0] received_udp_packet = 8'b0;
reg [1:0] bitstream_dibit = 2'b0;
reg bitstream_write_enable = 1'b0;
reg [17:0] bitstream_write_addr = 18'b0;
/*
always @(negedge REFCLK)
begin
if (bitstream_write_enable)
begin
bitstream_write_addr <= #4 bitstream_write_addr + 18'd1;
end
else
begin
bitstream_write_addr <= #4 18'b0;
end
end
*/
// assign bitstream_dibit = { RX1, RX0 };
always @(posedge REFCLK)
begin
if (receiving & sfd_detected)
begin
if (maybe_udp_packet)
begin
// Frame type == IPv4
if (receiving_byte_number >= 14'd12 & receiving_byte_number < 14'd14)
begin
maybe_udp_packet <= #4 const_eth_frame_type_ip_v4[eth_frame_type_index_combinational_slow +: 2] == { RX1, RX0 } ? maybe_udp_packet : 1'b0;
end
else if (receiving_byte_number >= 14'd30 & receiving_byte_number < 14'd34) begin
maybe_udp_packet <= #4 const_device_ip_address[((receiving_byte_number - 14'd30) * 14'd8 + current_dibit_index_in_byte) +: 2] == { RX1, RX0 } ? maybe_udp_packet : 1'b0;
end
/*else if (receiving_byte_number == 14'd14)
begin
code_red <= #4 1'b1;
end*/
else if (receiving_byte_number >= 14'd42 & receiving_byte_number < 14'd7379)
begin
bitstream_write_enable <= #4 1'b1;
bitstream_dibit <= #4 { RX1, RX0 };
// bitstream_dibit <= #4 { 1'b1, 1'b0 };
bitstream_write_addr <= #4 (receiving_byte_number - 14'd42) * 14'd8 + current_dibit_index_in_byte;
//if (receiving_byte_number >= 14'd7375) // 42
//begin
// receiving_byte_number
// current_dibit_index_in_byte
//if (receiving_byte_number == 14'd7375)
if (receiving_byte_number == 14'd7360) //0x1cc0 == 0x99
begin
received_udp_packet[((receiving_byte_number - 14'd7360) * 14'd8 + current_dibit_index_in_byte) +: 2] <= #4 { RX1, RX0 };
code_red <= #4 1'b1;
reset_synchronizer2 <= #4 1'b1;
end
//end
end
else if (receiving_byte_number == 14'd7379)
begin
bitstream_write_enable <= #4 1'b0;
reset_synchronizer2 <= #4 1'b0;
end
end
end
if (receiving & sfd_detected & ~arp_parser_is_locked)
begin
if (maybe_arp_request)
begin
// Testbench only
/*
if (receiving_byte_number >= 14'd6 & receiving_byte_number < 14'd41)
begin
bitstream_write_enable <= #4 1'b1;
bitstream_dibit <= #4 { RX1, RX0 };
bitstream_write_addr <= #4 (receiving_byte_number - 14'd6) * 14'd8 + current_dibit_index_in_byte;
end
else if (receiving_byte_number == 14'd41)
begin
bitstream_write_enable <= #4 1'b0;
end
*/
// Capture receiver's MAC address (might be broadcast our our)
if (receiving_byte_number < 14'd6) begin
target_is_direct_mac_address <= #4 const_device_mac_address[our_mac_address_index_combinational_slow +: 2] == { RX1, RX0 } ? target_is_direct_mac_address : 1'b0;
target_is_broadcast <= #4 target_is_broadcast & RX1 & RX0;
// Previous flag - the last flag will be caught in the byte 6
maybe_arp_request <= #4 (target_is_direct_mac_address | target_is_broadcast);
end
else
// Capture sender's MAC address
if (receiving_byte_number >= 14'd6 & receiving_byte_number < 14'd12) begin
if (receiving_byte_number == 14'd6)
begin
// It's calculated in the end of the cycle
maybe_arp_request <= #4 (target_is_direct_mac_address | target_is_broadcast);
end
requester_mac_address[mac_index_combinational_slow +: 2] <= #4 { RX1, RX0 };
end
else
// Frame type == ARP
if (receiving_byte_number >= 14'd12 & receiving_byte_number < 14'd22) begin
maybe_arp_request <= #4 const_eth_frame_type_pattern[eth_frame_type_index_combinational_slow +: 2] == { RX1, RX0 } ? maybe_arp_request : 1'b0;
end
else
// Capture sender's IP address
if (receiving_byte_number >= 14'd28 & receiving_byte_number < 14'd32) begin
requester_ip_address[ip_address_index_combinational_slow +: 2] <= #4 { RX1, RX0 };
end
else
// Finally compare if they're looking for us, and start sending a response if they do! :-)
if (receiving_byte_number >= 14'd38 & receiving_byte_number < 14'd42) begin
maybe_arp_request <= #4 const_device_ip_address[our_ip_address_index_combinational_slow +: 2] == { RX1, RX0 } ? maybe_arp_request : 1'b0;
end
else
if (receiving_byte_number == 14'd42)
begin
arp_parser_is_locked <= #4 1'b1;
sending_arp_response <= #4 1'b1;
reset_arp_response_counter <= #4 1'b1;
end
end
end
//end
// it's trivial now! :-) Voila!
//always @(posedge REFCLK)
//begin
// Send 72 bytes in di-bits
if (sending_arp_response)
begin
reset_arp_response_counter <= #4 1'b0;
if (~arp_response_sent)
begin
// Silly Xilinx counters don't start counting on "enable" (they are too power efficient LOL)
if (skip_first_arp_sending_counter_pulse > 2'b0)
begin
if (~arp_response_bit_address)
begin
skip_first_arp_sending_counter_pulse <= #4 skip_first_arp_sending_counter_pulse - 2'b1;
// Anyway, set the first two bits of preamble to let them settle
// { TX1, TX0 } <= #4 const_eth_preamble[ arp_response_bit_address +: 2 ];
crc_encoding_byte_number <= #4 14'b0;
//reset_crc_state <= #4 1'b0;
//byte_for_crc32_is_ready <= #4 1'b0;
//latched_byte_for_crc32 <= #4 { RX1, RX0, receiving_byte[5:0] };
//byte_for_crc32_is_ready <= #4 1'b1;
// Reset CRC32
// crc_state <= #4 32'hFFFFFFFF;
end
end
else
begin
// CODE RED!
TX_EN <= #4 1'b1;
// Calculate CRC32 1 byte per clock (it doesn't match to the bit address
// If arp_response_bit_address % 8 is 0 (the beginning of every byte)
// Byte address (arp_response_bit_address gets incremented by 2 so divide it by 2 to increment byte address by 1).
crc_encoding_byte_number <= #4 arp_response_bit_address[10:2];
if (crc_encoding_byte_number < 11'd60)
//if (crc_encoding_byte_number < 11'd58)
begin
if (~arp_response_bit_address[1])
begin
// Capture result of computation of CRC32 (latched_byte_for_crc32 + crc_state) => crc_next_combinational_slow => crc_state
//if (crc_encoding_byte_number < 11'd59)
//begin
crc_state <= #13 crc_next_combinational_slow;
//end
end
else
begin
if (crc_encoding_byte_number == 11'd0)
begin
// Initialize crc_state at the same time when supplying the 0th byte.
crc_state <= #4 32'hFFFFFFFF;
end
if (crc_encoding_byte_number < 11'd6)
begin
latched_byte_for_crc32 <= #4 requester_mac_address[ crc_encoding_byte_number * 11'd8 +: 8 ];
end
else
if (crc_encoding_byte_number >= 11'd6 & crc_encoding_byte_number < 11'd12)
begin
latched_byte_for_crc32 <= #4 const_device_mac_address[ (crc_encoding_byte_number - 11'd6) * 11'd8 +: 8 ];
end
else
if (crc_encoding_byte_number >= 11'd12 & crc_encoding_byte_number < 11'd22)
begin
latched_byte_for_crc32 <= #4 const_eth_frame_type_reply_pattern[ (crc_encoding_byte_number - 11'd12) * 11'd8 +: 8 ];
end
else
if (crc_encoding_byte_number >= 11'd22 & crc_encoding_byte_number < 11'd28)
begin
latched_byte_for_crc32 <= #4 const_device_mac_address[ (crc_encoding_byte_number - 11'd22) * 11'd8 +: 8 ];
end
else
if (crc_encoding_byte_number >= 11'd28 & crc_encoding_byte_number < 11'd32)
begin
latched_byte_for_crc32 <= #4 const_device_ip_address[ (crc_encoding_byte_number - 11'd28) * 11'd8 +: 8 ];
end
else
if (crc_encoding_byte_number >= 11'd32 & crc_encoding_byte_number < 11'd38)
begin
latched_byte_for_crc32 <= #4 requester_mac_address[ (crc_encoding_byte_number - 11'd32) * 11'd8 +: 8 ];
end
else
if (crc_encoding_byte_number >= 11'd38 & crc_encoding_byte_number < 11'd42)
begin
latched_byte_for_crc32 <= #4 requester_ip_address[ (crc_encoding_byte_number - 11'd38) * 11'd8 +: 8 ];
end
else
if (crc_encoding_byte_number >= 11'd42 & crc_encoding_byte_number < 11'd60)
// if (crc_encoding_byte_number >= 11'd42 & crc_encoding_byte_number < 11'd58)
begin
// Zero padding
latched_byte_for_crc32 <= #4 8'b0;
end
end
end
if (arp_response_bit_address < 11'd64)
begin
{ TX1, TX0 } <= #4 const_eth_preamble[ arp_response_bit_address +: 2 ];
end
else
if (arp_response_bit_address >= 11'd64 & arp_response_bit_address < 11'd112)
begin
{ TX1, TX0 } <= #4 requester_mac_address[ arp_response_bit_address - 11'd64 +: 2 ];
end
else
if (arp_response_bit_address >= 11'd112 & arp_response_bit_address < 11'd160)
begin
{ TX1, TX0 } <= #4 const_device_mac_address[ arp_response_bit_address - 11'd112 +: 2 ];
end
else
if (arp_response_bit_address >= 11'd160 & arp_response_bit_address < 11'd240)
begin
{ TX1, TX0 } <= #4 const_eth_frame_type_reply_pattern[ arp_response_bit_address - 11'd160 +: 2 ];
end
else
if (arp_response_bit_address >= 11'd240 & arp_response_bit_address < 11'd288)
begin
{ TX1, TX0 } <= #4 const_device_mac_address[ arp_response_bit_address - 11'd240 +: 2 ];
end
else
if (arp_response_bit_address >= 11'd288 & arp_response_bit_address < 11'd320)
begin
{ TX1, TX0 } <= #4 const_device_ip_address[ arp_response_bit_address - 11'd288 +: 2 ];
end
else
if (arp_response_bit_address >= 11'd320 & arp_response_bit_address < 11'd368)
begin
{ TX1, TX0 } <= #4 requester_mac_address[ arp_response_bit_address - 11'd320 +: 2 ];
end
else
if (arp_response_bit_address >= 11'd368 & arp_response_bit_address < 11'd400)
begin
{ TX1, TX0 } <= #4 requester_ip_address[ arp_response_bit_address - 11'd368 +: 2 ];
end
else
if (arp_response_bit_address >= 11'd400 & arp_response_bit_address < 11'd544)
//if (arp_response_bit_address >= 11'd400 & arp_response_bit_address < 11'd528)
begin
// Zero padding
{ TX1, TX0 } <= #4 2'b0;
end
else
if (arp_response_bit_address >= 11'd544 & arp_response_bit_address < 11'd576)
//if (arp_response_bit_address >= 11'd528 & arp_response_bit_address < 11'd560)
begin
// CRC32
{ TX1, TX0 } <= #4 ~crc_state[ arp_response_bit_address - 11'd544 +: 2 ];
//{ TX1, TX0 } <= #4 ~crc_state[ arp_response_bit_address - 11'd528 +: 2 ];
end
end
end
else
begin
sending_arp_response <= #4 1'b0;
skip_first_arp_sending_counter_pulse <= #4 2'b10;
TX_EN <= #4 1'b0;
{ TX1, TX0 } <= #4 2'b0;
// Unlock the parser so it can receive some ARP packets and collect a different data
// This unlock might happen in the middle of receiving of another packet,
// then unlock must happen after that receive will finishes.
// We don't reset "maybe_arp_request" here, it'll happen in the beginning of another packet,
// if the current packet was receiving, we'll drop it because we're not caching MAC and IP addresses of
// requestors yet (but it's totally doable with a double-buffering).
arp_parser_is_locked <= #4 1'b0;
end
end
//synchronized_crs_dv_0 <= #4 CRS_DV;
//synchronized_crs_dv <= synchronized_crs_dv_0;
//if (~receiving & synchronized_crs_dv & (RX1 | RX0))
if (~receiving & CRS_DV & ~RX1 & RX0 & ~sfd_detected)
begin
receiving <= #4 1'b1;
receiving_byte_number <= 14'd0;
receive_ptr <= #4 1'b0;
end
if (receiving)
begin
if (~sfd_detected)
begin
if (RX1 & RX0)
begin
sfd_detected <= #4 1'b1;
receive_ptr <= #4 1'b0;
// Reset parser because it might be tricked by the previous packet
// If it was sending, we're missing the parsing of the current packet:
// that bug is by design.
if (~arp_parser_is_locked)
begin
maybe_arp_request <= #4 1'b1;
maybe_udp_packet <= #4 1'b1;
target_is_broadcast <= #4 1'b1;
target_is_direct_mac_address <= #4 1'b1;
end
end
end
else
begin
if (receive_ptr == 2'd0)
begin
receiving_byte[1:0] <= #4 { RX1, RX0 };
//byte_for_crc32_is_ready <= #4 1'b0;
//if (receiving_byte_number == 14'b0)
//begin
// reset_crc_state <= #4 1'b1;
//end
end
if (receive_ptr == 2'd1)
begin
receiving_byte[3:2] <= #4 { RX1, RX0 };
//if (receiving_byte_number == 14'd0)
//begin
// reset_crc_state <= #4 1'b0;
//end
end
if (receive_ptr == 2'd2)
begin
receiving_byte[5:4] <= #4 { RX1, RX0 };
end
if (receive_ptr == 2'd3)
begin
receiving_byte[7:6] <= #4 { RX1, RX0 };
receiving_byte_number <= #4 receiving_byte_number + 14'd1;
//if (receiving_byte_number < 14'd60)
//begin
// latched_byte_for_crc32 <= #4 { RX1, RX0, receiving_byte[5:0] };
// byte_for_crc32_is_ready <= #4 1'b1;
//end
// Output it
// received_byte <= #4 { RX1, RX0, receiving_byte[5:0] };
// Or output a specific byte in the packet:
if (receiving_byte_number == {0,0,0,0,0,0,0,0,0,0, SW3, SW2, SW1, SW0 })
//if (receiving_byte_number == {0,0,0,0,0,0,0,0,1'b1,1'b1,1'b1,1'b1, SW1, SW0 }) //14'd6) // 0, 1, 2, 3, 4, 5 - DST MAC
//if (receiving_byte_number == 14'd63) // 0, 1, 2, 3, 4, 5 - DST MAC
//if (receiving_byte_number == 14'd41) // 0, 1, 2, 3, 4, 5 - DST MAC
begin
received_byte <= #4 { RX1, RX0, receiving_byte[5:0] };
byte_is_ready <= #4 1'b1;
end
end
receive_ptr <= #4 receive_ptr + 2'd1;
end
if (~CRS_DV)
begin
if (no_crs_toggle == 2'd3)
begin
receiving <= #4 1'b0;
sfd_detected <= #4 1'b0;
no_crs_toggle <= #4 2'd0;
end
no_crs_toggle <= no_crs_toggle + 1'b1;
end
end
if (CRS_DV)
begin
no_crs_toggle <= #4 2'd0;
end
end
assign LED1_B = sending_arp_response;
COUNTER_TC_MACRO # (
.COUNT_BY (48'h000000000002), // Count by a di-bit
.DEVICE ("7SERIES"),
.DIRECTION ("UP"),
.RESET_UPON_TC ("TRUE"), //Reset counter upon terminal count
.TC_VALUE (10'd576), // Terminal count value, number of bits to send an ARP response
.WIDTH_DATA (11) // Counter output bus width, 1-48
) arp_response_counter_registers (
.Q (arp_response_bit_address), // Counter output bus, width determined by WIDTH_DATA parameter
.TC (arp_response_sent), // 1-bit terminal count output, high = terminal count is reached
.CLK (REFCLK), // 1-bit positive edge clock input
.CE (sending_arp_response), // 1-bit active high clock enable input
.RST (reset_arp_response_counter) // 1-bit active high synchronous reset
);
/*
assign CK_IO26 = crc_state[0];
assign CK_IO27 = crc_state[1];
assign CK_IO28 = crc_state[2];
assign CK_IO29 = crc_state[3];
assign CK_IO30 = crc_state[4];
assign CK_IO31 = crc_state[5];
assign CK_IO32 = crc_state[6];
assign CK_IO33 = crc_state[7];
*/
/*
assign CK_IO26 = ~BTN1 ? received_byte[0] : fcs_reg[0 + 8 * SW0 + 16 * SW1];
assign CK_IO27 = ~BTN1 ? received_byte[1] : fcs_reg[1 + 8 * SW0 + 16 * SW1];
assign CK_IO28 = ~BTN1 ? received_byte[2] : fcs_reg[2 + 8 * SW0 + 16 * SW1];
assign CK_IO29 = ~BTN1 ? received_byte[3] : fcs_reg[3 + 8 * SW0 + 16 * SW1];
assign CK_IO30 = ~BTN1 ? received_byte[4] : fcs_reg[4 + 8 * SW0 + 16 * SW1];
assign CK_IO31 = ~BTN1 ? received_byte[5] : fcs_reg[5 + 8 * SW0 + 16 * SW1];
assign CK_IO32 = ~BTN1 ? received_byte[6] : fcs_reg[6 + 8 * SW0 + 16 * SW1];
assign CK_IO33 = ~BTN1 ? received_byte[7] : fcs_reg[7 + 8 * SW0 + 16 * SW1];
*/
/*
assign CK_IO26 = ~BTN1 ? received_byte[0] : fcs_reg[0 + 8 * SW0 + 16 * SW1];
assign CK_IO27 = ~BTN1 ? received_byte[1] : fcs_reg[1 + 8 * SW0 + 16 * SW1];
assign CK_IO28 = ~BTN1 ? received_byte[2] : fcs_reg[2 + 8 * SW0 + 16 * SW1];
assign CK_IO29 = ~BTN1 ? received_byte[3] : fcs_reg[3 + 8 * SW0 + 16 * SW1];
assign CK_IO30 = ~BTN1 ? received_byte[4] : fcs_reg[4 + 8 * SW0 + 16 * SW1];
assign CK_IO31 = ~BTN1 ? received_byte[5] : fcs_reg[5 + 8 * SW0 + 16 * SW1];
assign CK_IO32 = ~BTN1 ? received_byte[6] : fcs_reg[6 + 8 * SW0 + 16 * SW1];
assign CK_IO33 = ~BTN1 ? received_byte[7] : fcs_reg[7 + 8 * SW0 + 16 * SW1];*/
wire [7:0] fcs_0 = fcs_reg[7:0]; // { fcs_reg[0], fcs_reg[1], fcs_reg[2], fcs_reg[3], fcs_reg[4], fcs_reg[5], fcs_reg[6], fcs_reg[7] };
wire [7:0] fcs_1 = fcs_reg[15:8]; //{ fcs_reg[8], fcs_reg[9], fcs_reg[10], fcs_reg[11], fcs_reg[12], fcs_reg[13], fcs_reg[14], fcs_reg[15] };
wire [7:0] fcs_2 = fcs_reg[23:16]; //{ fcs_reg[16], fcs_reg[17], fcs_reg[18], fcs_reg[19], fcs_reg[20], fcs_reg[21], fcs_reg[22], fcs_reg[23] };
wire [7:0] fcs_3 = fcs_reg[31:24]; //{ fcs_reg[24], fcs_reg[25], fcs_reg[26], fcs_reg[27], fcs_reg[28], fcs_reg[29], fcs_reg[30], fcs_reg[31] };
/*
assign CK_IO26 = ~SW3 ? received_byte[0] : ~SW0 & ~SW1 ? fcs_0[0] : SW0 & ~SW1 ? fcs_1[0] : ~SW0 & SW1 ? fcs_2[0] : fcs_3[0];
assign CK_IO27 = ~SW3 ? received_byte[1] : ~SW0 & ~SW1 ? fcs_0[1] : SW0 & ~SW1 ? fcs_1[1] : ~SW0 & SW1 ? fcs_2[1] : fcs_3[1];
assign CK_IO28 = ~SW3 ? received_byte[2] : ~SW0 & ~SW1 ? fcs_0[2] : SW0 & ~SW1 ? fcs_1[2] : ~SW0 & SW1 ? fcs_2[2] : fcs_3[2];
assign CK_IO29 = ~SW3 ? received_byte[3] : ~SW0 & ~SW1 ? fcs_0[3] : SW0 & ~SW1 ? fcs_1[3] : ~SW0 & SW1 ? fcs_2[3] : fcs_3[3];
assign CK_IO30 = ~SW3 ? received_byte[4] : ~SW0 & ~SW1 ? fcs_0[4] : SW0 & ~SW1 ? fcs_1[4] : ~SW0 & SW1 ? fcs_2[4] : fcs_3[4];
assign CK_IO31 = ~SW3 ? received_byte[5] : ~SW0 & ~SW1 ? fcs_0[5] : SW0 & ~SW1 ? fcs_1[5] : ~SW0 & SW1 ? fcs_2[5] : fcs_3[5];
assign CK_IO32 = ~SW3 ? received_byte[6] : ~SW0 & ~SW1 ? fcs_0[6] : SW0 & ~SW1 ? fcs_1[6] : ~SW0 & SW1 ? fcs_2[6] : fcs_3[6];
assign CK_IO33 = ~SW3 ? received_byte[7] : ~SW0 & ~SW1 ? fcs_0[7] : SW0 & ~SW1 ? fcs_1[7] : ~SW0 & SW1 ? fcs_2[7] : fcs_3[7];
*/
/*
assign CK_IO26 = requester_mac_address[0];
assign CK_IO27 = requester_mac_address[1];
assign CK_IO28 = requester_mac_address[2];
assign CK_IO29 = requester_mac_address[3];
assign CK_IO30 = requester_mac_address[4];
assign CK_IO31 = requester_mac_address[5];
assign CK_IO32 = requester_mac_address[6];
assign CK_IO33 = requester_mac_address[7];
*/
assign CK_IO34 = byte_is_ready;
/*
SW0
SW1
LED0_B
LED1_B
*/
// assign ETH_RSTN = CK_RST;
// assign LED0_R = ETH_CRS_DV;
// assign LED1_R = ETH_RXERR;
// assign LED2_R = ETH_RX_DV;
// assign CK_IO34 = 1'b0;// ETH_MDIO;
//assign LED2_B = ETH_RXD2;
//assign LED3_B = ETH_RXD3;
/*
//assign CK_IO26 = ETH_RXD0;//BTN0;
//assign CK_IO27 = ETH_RXD1;//BTN1;
//assign CK_IO28 = ETH_RXD2;//BTN2;
//assign CK_IO29 = ETH_RXD3;//BTN3;
*/
/*
assign CK_IO26 = BTN0;
assign CK_IO27 = BTN1;
assign CK_IO28 = BTN2;
assign CK_IO29 = BTN3;
assign CK_IO30 = SW0;
assign CK_IO31 = SW1;
assign CK_IO32 = SW2;
assign CK_IO33 = SW3;
*/
assign CK_IO26 = received_udp_packet[0];
assign CK_IO27 = received_udp_packet[1];
assign CK_IO28 = received_udp_packet[2];
assign CK_IO29 = received_udp_packet[3];
assign CK_IO30 = received_udp_packet[4];
assign CK_IO31 = received_udp_packet[5];
assign CK_IO32 = received_udp_packet[6];
assign CK_IO33 = received_udp_packet[7];
// assign LED2_B = ~clk_25;
/*
reg [31:0] cnt_50 = {32'b0};
reg pulse_50;
reg clk_25 = 1'b0;
reg [31:0] cnt_2 = {32'b0};
reg pulse_2;
reg clk_1 = 1'b0;
reg [31:0] cnt_0_062 = {32'b0};
reg pulse_0_062;
reg clk_0_031 = 1'b0;
always @(posedge GCLK100)
begin
if (pulse_50)
begin
clk_25 = ~clk_25;
end
{ pulse_50, cnt_50 } <= cnt_50 + 32'h8000_0000; // 25 MHz
// { pulse_50, cnt_50 } <= cnt_50 + 32'h4000_0000; // 12.5 MHz
if (pulse_2)
begin
clk_1 = ~clk_1;
end
{ pulse_2, cnt_2 } <= cnt_2 + 32'h51eb851; // 1 MHz
if (pulse_0_062)
begin
clk_0_031 = ~clk_0_031;
end
// { pulse_0_062, cnt_0_062 } <= cnt_0_062 + 32'h28f5c2; // 31.250 kHz
{ pulse_0_062, cnt_0_062 } <= cnt_0_062 + 32'h147ae1; // 31.250 kHz
end
*/
assign CK_IO37 = LED0_G;
// assign CK_IO39 = clk_1;
/*
wire eth_md_mem0;
wire [6:0] counter_read_phy_cnt_addr;
reg counter_read_phy_counted_to_the_end = 1'b0;
wire counter_read_phy_counted_to_the_end_signal;
//assign ETH_REF_CLK = clk_25;
COUNTER_TC_MACRO # (
.COUNT_BY (48'h000000000001), // Count by value
.DEVICE ("7SERIES"), // Target Device: "7SERIES"
.DIRECTION ("UP"), // Counter direction, "UP" or "DOWN"
.RESET_UPON_TC ("FALSE"),//Reset counter upon terminal count, "TRUE" or "FALSE"
.TC_VALUE (7'h2F), // Working to read status
//.TC_VALUE (7'h40), // Writing control value
//.TC_VALUE (7'h0E), // Terminal count value
.WIDTH_DATA (7) // Counter output bus width, 1-48
) counter_read_phy (
.Q (counter_read_phy_cnt_addr), // Counter output bus, width determined by WIDTH_DATA parameter
.TC (counter_read_phy_counted_to_the_end_signal), // 1-bit terminal count output, high = terminal count is reached
.CLK (GCLK100), // 1-bit positive edge clock input
.CE (BTN1 & clk_0_031 & pulse_0_062), // 1-bit active high clock enable input
.RST (~CK_RST) // driven by reset synchronizer, not resetting state!
);
reg reading_from_phy = 1'b0;
//assign ETH_MDC = BTN1 & clk_0_031 & (counter_read_phy_cnt_addr > 6'h0) & ~reading_from_phy;
//assign ETH_MDIO = ~counter_read_phy_counted_to_the_end ? eth_md_mem0 : 1'bz; // To drive the inout net
RAM64X1S #(
//.INIT(64'b00_10000_10000_01_10__1111111_11111111_11111111_11111111_11) // READ 1
.INIT(64'b00_10000_10000_01_10__1111111_11111111_11111111_11111111_11) // READ 1
//.INIT(64'b00_11000_10000_01_10__1111111_11111111_11111111_11111111_11) // READ 3
//.INIT(64'b00010000100_01_00000_10000_10_10__1111111_11111111_11111111_11111111_11) // WRITE
// RRRRR AAAAA WR ST
) RAM64X1S_inst (
.O (eth_md_mem0), // 1-bit data output
.A0 (counter_read_phy_cnt_addr[0]), // Address[0] input bit
.A1 (counter_read_phy_cnt_addr[1]), // Address[1] input bit
.A2 (counter_read_phy_cnt_addr[2]), // Address[2] input bit
.A3 (counter_read_phy_cnt_addr[3]), // Address[3] input bit
.A4 (counter_read_phy_cnt_addr[4]), // Address[4] input bit
.A5 (counter_read_phy_cnt_addr[5]), // Address[5] input bit
.D (1'b0), // 1-bit data input
.WCLK (1'b0), // Write clock input
.WE (1'b0) // Write enable input
);
wire [5:0] phy_reg_value_cnt_addr;
wire phy_reg_value_counted_to_the_end;// = 1'b0;
COUNTER_TC_MACRO # (
.COUNT_BY (48'h000000000001), // Count by value
.DEVICE ("7SERIES"), // Target Device: "7SERIES"
.DIRECTION ("UP"), // Counter direction, "UP" or "DOWN"
.RESET_UPON_TC ("TRUE"),//Reset counter upon terminal count, "TRUE" or "FALSE"
.TC_VALUE (6'h12), // Terminal count value
.WIDTH_DATA (6) // Counter output bus width, 1-48
) counter_read_status (
.Q (phy_reg_value_cnt_addr), // Counter output bus, width determined by WIDTH_DATA parameter
.TC (phy_reg_value_counted_to_the_end), // 1-bit terminal count output, high = terminal count is reached
//.CLK (GCLK100 & ~reading_from_phy | reading_from_phy & BTN3), //clk_0_031), // 1-bit positive edge clock input
.CLK (GCLK100),// & ~reading_from_phy | reading_from_phy & BTN3), //clk_0_031), // 1-bit positive edge clock input
//.CE (counter_read_phy_counted_to_the_end & (clk_25 & pulse_50 & ~reading_from_phy | reading_from_phy)),// & clk_0_031 & pulse_0_062)), //BTN3)), // 1-bit active high clock enable input
.CE (counter_read_phy_counted_to_the_end & (clk_0_031 & pulse_0_062 & ~reading_from_phy | reading_from_phy & clk_0_031 & pulse_0_062)), //BTN3)), // 1-bit active high clock enable input
.RST (~CK_RST) // driven by reset synchronizer, not resetting state!
);
wire write_enable = counter_read_phy_counted_to_the_end & ~reading_from_phy;
RAM64X1S eth_read_status (
.O (LED0_G), // 1-bit data output
.A0 (phy_reg_value_cnt_addr[0]), // Address[0] input bit
.A1 (phy_reg_value_cnt_addr[1]), // Address[1] input bit
.A2 (phy_reg_value_cnt_addr[2]), // Address[2] input bit
.A3 (phy_reg_value_cnt_addr[3]), // Address[3] input bit
.A4 (phy_reg_value_cnt_addr[4]), // Address[4] input bit
.A5 (phy_reg_value_cnt_addr[5]), // Address[5] input bit
.D (ETH_MDIO), // 1-bit data input
.WCLK (ETH_MDC), // Write clock input
.WE (write_enable) // Write enable input
);
// assign LED3_B = ETH_MDIO & counter_read_phy_counted_to_the_end;
always @(posedge clk_25)
begin
if (counter_read_phy_counted_to_the_end_signal)
begin
counter_read_phy_counted_to_the_end = 1'b1;
end
if (phy_reg_value_counted_to_the_end)
begin
reading_from_phy = 1'b1;
end
end
*/
wire SPI_SCK;// = CK_IO5;
wire SPI_SO;// = CK_IO4;
wire SPI_SI;// = CK_IO3;
wire SPI_SS_B;// = CK_IO2;
wire CDONE;// = CK_IO1;
wire CRESET_B;// = CK_IO0;
wire reprogrammer_enable;// = 1'b1;//~CDONE;
IOBUF io_spi_sck (
.O(), // Buffer output: dc
.IO(CK_IO5), // Buffer inout port (connect directly to top-level port)
.I(SPI_SCK), // Buffer input
.T(~reprogrammer_enable) // 3-state enable input, high=input, low=output
);
IOBUF io_spi_si (
.O(), // Buffer output: dc
.IO(CK_IO3), // Buffer inout port (connect directly to top-level port)
.I(SPI_SI), // Buffer input
.T(~reprogrammer_enable) // 3-state enable input, high=input, low=output
);
IOBUF io_spi_ss_b (
.O(), // Buffer output: dc
.IO(CK_IO2), // Buffer inout port (connect directly to top-level port)
.I(SPI_SS_B), // Buffer input
.T(~reprogrammer_enable) // 3-state enable input, high=input, low=output
);
IOBUF io_spi_creset_b (
.O(), // Buffer output: dc
.IO(CK_IO0), // Buffer inout port (connect directly to top-level port)
.I(CRESET_B), // Buffer input
.T(~reprogrammer_enable) // 3-state enable input, high=input, low=output
);
assign LED0_B = reprogrammer_enable;
// Reprogrammer wiring;
//assign CK_IO5 = SPI_SCK;
assign SPI_SO = CK_IO4;
//assign CK_IO3 = SPI_SI;
//assign CK_IO2 = SPI_SS_B;
assign CDONE = CK_IO1;
//assign CK_IO0 = CRESET_B;
reg btn0_synchronizer1;
reg btn0_synchronizer2;
reg reset_synchronizer1;
reg reset_synchronizer2;
reg [31:0] cnt = {32'b0};
// Not used because REFCLK is 50 MHz!
//reg pix_stb;
//reg divided = 1'b0;
wire reset_src_wire = ~CK_RST;
wire reset = reset_synchronizer2;
reg resetting = 1'b0;
reg resetting_wait = 1'b0;
wire resetting_wait_counted_to_the_end;
reg ready = 1'b0;
reg button_pressed = 1'b0;
reg button_released = 1'b0;
reg memory_clear_wait = 1'b0;
wire memory_clear_wait_counted_to_the_end;
reg sending = 1'b0;
reg sent = 1'b0;
// Sending substate machine:
reg sending_skip_first_pulse_wait = 1'b0;
// reg sending_skip_first_pulse_detected = 1'b0;
reg sending_normal_sending_mode = 1'b0;
wire counted_to_the_end;
reg reset_pressed = 1'b0;
reg reset_released = 1'b0;
/*
Fsm s1 (
input wire CLOCK,
input wire FROM_A,
input wire FROM_B,
input wire FROM_C,
input wire EVT_E,
input wire EVT_F,
input wire EVT_G,
output wire TO_ON_E,
output wire TO_ON_F,
output wire TO_ON_G,
output wire ACTIVE,
output wire ENTERED,
output wire EXITED,
);
*/
always @(posedge REFCLK)//GCLK100)
begin
btn0_synchronizer1 <= BTN0;
btn0_synchronizer2 <= btn0_synchronizer1;
reset_synchronizer1 <= reset_src_wire;
//reset_synchronizer2 <= reset_synchronizer1;
// Not used because REFCLK is 50 MHz!
/*
if (pix_stb)
begin
divided = ~divided;
end
*/
// { pix_stb, cnt } <= cnt + 32'ha3cb22; // 1us // divide by 4: (2^32)/4 = 0x4000
// { pix_stb, cnt } <= cnt + 32'ha7c5;
// { pix_stb, cnt } <= cnt + 32'h28f5c28; // 500 kHz
//{ pix_stb, cnt } <= cnt + 32'h51eb851; // 1 MHz
// { pix_stb, cnt } <= cnt + 32'h9999_999a; // 30 MHz
// Not used because REFCLK is 50 MHz!
//{ pix_stb, cnt } <= cnt + 32'hffff_ffff; // 50 MHz
//{ pix_stb, cnt } <= cnt + 32'h8000_0000; // 25 MHz
// { pix_stb, cnt } <= cnt + 32'h7ae1_47ae; // 24 MHz
// { pix_stb, cnt } <= cnt + 32'h4000_0000; // 12.5 MHz
// { pix_stb, cnt } <= cnt + 32'h56;
if (reset & ~reset_pressed)
begin
reset_pressed = 1'b1;
reset_released = 1'b0;
end
if (~reset & reset_pressed)
begin
reset_pressed = 1'b0;
reset_released = 1'b1;
end
if (reset_released)
begin
reset_released = 1'b0;
resetting = 1'b1;
ready = 1'b0;
sending = 1'b0;
sending_skip_first_pulse_wait = 1'b0;
//sending_skip_first_pulse_detected = 1'b0;
sending_normal_sending_mode = 1'b0;
sent = 1'b0;
memory_clear_wait = 1'b0;
resetting_wait = 1'b0;
end
if (resetting & ~reset & ~resetting_wait)
begin
// resetting = 1'b0;
// ready = 1'b1;
resetting_wait = 1'b1;
end
if (resetting_wait & resetting_wait_counted_to_the_end)
begin
resetting_wait = 1'b0;
resetting = 1'b0;
memory_clear_wait = 1'b1;
end
if (memory_clear_wait & memory_clear_wait_counted_to_the_end)
begin
memory_clear_wait = 1'b0;
//ready = 1'b1;
//ready = 1'b0;
sent = 1'b0;
sending = 1'b1;
//button_released = 1'b0;
end
if (btn0_synchronizer2 & ~button_pressed)
begin
button_pressed = 1'b1;
end
if (~btn0_synchronizer2 & button_pressed)
begin
button_pressed = 1'b0;
button_released = 1'b1;
end
else if ((ready | sent) & button_released)
begin
ready = 1'b0;
sent = 1'b0;
sending = 1'b1;
button_released = 1'b0;
end
if (sending & counted_to_the_end)
begin
sending = 1'b0;
sending_skip_first_pulse_wait = 1'b0;
// sending_skip_first_pulse_detected = 1'b0;
sending_normal_sending_mode = 1'b0;
sent = 1'b1;
end
/* if (sending_skip_first_pulse_detected) // & ~divided) // the pulse is over: transition into normal send mode
begin
sending_skip_first_pulse_detected = 1'b0;
sending_normal_sending_mode = 1'b1;
end */
if (sending_skip_first_pulse_wait) // & divided) // became positive (first pulse)
begin
sending_skip_first_pulse_wait = 1'b0;
//sending_skip_first_pulse_detected = 1'b1;
sending_normal_sending_mode = 1'b1;
end
// First ender the sending substate
// if (sending & ~sending_skip_first_pulse_wait & ~sending_skip_first_pulse_detected & ~sending_normal_sending_mode)
if (sending & ~sending_skip_first_pulse_wait & ~sending_normal_sending_mode)
begin
sending_skip_first_pulse_wait = 1'b1;
end
end
wire [3:0] resetting_wait_cnt_addr;
COUNTER_TC_MACRO # (
.COUNT_BY (48'h000000000001), // Count by value
.DEVICE ("7SERIES"), // Target Device: "7SERIES"
.DIRECTION ("UP"), // Counter direction, "UP" or "DOWN"
.RESET_UPON_TC ("FALSE"),//Reset counter upon terminal count, "TRUE" or "FALSE"
//.TC_VALUE (3'h2), // Terminal count value
//.TC_VALUE (3'h4), // Terminal count value
.TC_VALUE (4'h9), // Terminal count value
.WIDTH_DATA (4) // Counter output bus width, 1-48
) counter_200_ns (
.Q (resetting_wait_cnt_addr), // Counter output bus, width determined by WIDTH_DATA parameter
.TC (resetting_wait_counted_to_the_end), // 1-bit terminal count output, high = terminal count is reached
// .CLK (GCLK100), // 1-bit positive edge clock input
.CLK (REFCLK), // 1-bit positive edge clock input
//.CE (pix_stb & divided & resetting_wait), // 1-bit active high clock enable input
.CE (resetting_wait), // 1-bit active high clock enable input
.RST (reset) // driven by reset synchronizer, not resetting state!
);
wire [15:0] memory_clear_wait_cnt_addr;
COUNTER_TC_MACRO # (
.COUNT_BY (48'h000000000001), // Count by value
.DEVICE ("7SERIES"), // Target Device: "7SERIES"
.DIRECTION ("UP"), // Counter direction, "UP" or "DOWN"
.RESET_UPON_TC ("FALSE"),//Reset counter upon terminal count, "TRUE" or "FALSE"
//.TC_VALUE (16'h9c40), // Terminal count value 800 us at 50 MHz
.TC_VALUE (16'h7530), // Terminal count value 600 us at 50 MHz
//.TC_VALUE (16'h4e20), // Terminal count value
.WIDTH_DATA (16) // Counter output bus width, 1-48
) counter_800_us (
.Q (memory_clear_wait_cnt_addr), // Counter output bus, width determined by WIDTH_DATA parameter
.TC (memory_clear_wait_counted_to_the_end), // 1-bit terminal count output, high = terminal count is reached
//.CLK (GCLK100), // 1-bit positive edge clock input
.CLK (REFCLK),
//.CE (pix_stb & divided & memory_clear_wait), // 1-bit active high clock enable input
.CE (memory_clear_wait), // 1-bit active high clock enable input
.RST (resetting) // 1-bit active high synchronous reset
);
wire [17:0] addr;
COUNTER_TC_MACRO # (
.COUNT_BY (48'h000000000001), // Count by value
.DEVICE ("7SERIES"), // Target Device: "7SERIES"
.DIRECTION ("UP"), // Counter direction, "UP" or "DOWN"
.RESET_UPON_TC ("TRUE"),//Reset counter upon terminal count, "TRUE" or "FALSE"
//.TC_VALUE (18'h3eef8), // Terminal count value
// .TC_VALUE (18'h3eff8), // Terminal count value
//.TC_VALUE (18'h2edf8), // Terminal count value for iCE40HX1K
.TC_VALUE (18'he579), // Terminal count value for iCE40LP384
.WIDTH_DATA (18) // Counter output bus width, 1-48
) counter1 (
.Q (addr), // Counter output bus, width determined by WIDTH_DATA parameter
.TC (counted_to_the_end), // 1-bit terminal count output, high = terminal count is reached
.CLK (~REFCLK), // 1-bit positive edge clock input
// .CE (pix_stb & divided & sending), // 1-bit active high clock enable input
.CE (sending), // 1-bit active high clock enable input
.RST (resetting) // 1-bit active high synchronous reset
);
assign reprogrammer_enable = ~counted_to_the_end;
// TODO: wait 49 SPI_SCK cycles after receiving the CDONE signal
wire output_data;
wire output_clock = sending & sending_normal_sending_mode & REFCLK & (addr != 18'b0); // divided;
// RamSource ram_source (.i_clock (GCLK100), .i_reset (resetting), .i_enable (sending_normal_sending_mode), .i_address (addr), .o_data (output_data));
/*
reg output_data_reg = 1'b0;
always @(posedge REFCLK)
begin
output_data_reg <= #4 output_data;
end
*/
// RamSource ram_source (.i_clock (GCLK100), .i_reset (1'b0), .i_enable (sending_normal_sending_mode), .i_address (addr), .o_data (output_data)); // was working recently
RamSource ram_source (.i_clock (~REFCLK), .i_reset (1'b0), .i_enable (sending_normal_sending_mode | bitstream_write_enable),
.i_address (bitstream_write_enable ? bitstream_write_addr : addr),
.o_data (output_data),
.i_data (bitstream_dibit),
.i_we (bitstream_write_enable)
);
/*
wire [7:0] block;
RamFile #(
.INIT_00 (256'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000),
.INIT_01 (256'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111),
.INIT_02 (256'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111),
.INIT_03 (256'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111),
) f0 (.i_clock (GCLK100), .i_reset (resetting), .i_enable (sending_normal_sending_mode), .i_address (addr[14:0]), .o_data (block[0]));
wire [2:0] block_address = addr[17:15];
assign output_data = block[ block_address ]; */
assign LED7 = output_data;
assign LED6 = output_clock;
assign LED5 = CDONE;
assign SPI_SS_B = sent; //~(reset | resetting | ready | sending | memory_clear_wait);
assign LED4 = SPI_SS_B & SPI_SO;
assign CRESET_B = ~resetting;
assign SPI_SCK = output_clock;
assign SPI_SI = output_data;
//assign SPI_SI = output_data_reg;
endmodule
Raw
udp_sender.cpp
# include <array>
# include <stdlib.h>
# include <stdio.h>
# include <string.h>
# include <xcb/xcb.h>
# include "./init-egl.h"
# include "./runApp.h"
# include <sys/epoll.h>
# include <fcntl.h>
# include <errno.h>
# include <signal.h>
# include <sys/signalfd.h>
# include <unistd.h>
# include <netdb.h>
# include <arpa/inet.h>
# include <ifaddrs.h>
# include <net/if.h>
# include <sys/socket.h>
# include <netinet/in.h>
#define _XOPEN_SOURCE 700
#include <termios.h>
// TODO: add crash handler so we can do graceful shutdown and cleanup everything
void printipv4(in_addr* ipv4) {
char str4[INET_ADDRSTRLEN] = { 0 };
inet_ntop(AF_INET, ipv4, str4, INET_ADDRSTRLEN);
printf("%s", str4);
}
# define ALEN(arr) (sizeof(arr)/sizeof(arr[0]))
int create_epoll_pump () {
// Create epoll file descriptor
// int epfd = epoll_create1(EPOLL_CLOEXEC);
int epfd = epoll_create1(0);
return epfd;
}
void make_async (int fd) {
fcntl(fd, F_SETFL, fcntl(fd, F_GETFL) | O_NONBLOCK);
}
void add_listener (int epoll_fd, int fd, int additional_conditions = 0) {
// Enable level triggering of arrived data on the fd
epoll_event event = { 0 };
// event.events = EPOLLIN | EPOLLET;
event.events = EPOLLIN | EPOLLET | additional_conditions;
event.data.ptr = 0;
event.data.fd = fd;
epoll_ctl(epoll_fd, EPOLL_CTL_ADD, fd, &event);
}
xcb_drawable_t create_xcb_window (
xcb_connection_t* c,
int launch_width,
int launch_height) {
// get the first screen
xcb_screen_t* screen = xcb_setup_roots_iterator(xcb_get_setup(c)).data;
xcb_drawable_t win = xcb_generate_id(c);
uint32_t mask = XCB_CW_EVENT_MASK;
uint32_t values[1] = {
XCB_EVENT_MASK_EXPOSURE
| XCB_EVENT_MASK_KEY_PRESS
| XCB_EVENT_MASK_KEY_RELEASE
| XCB_EVENT_MASK_RESIZE_REDIRECT
| XCB_EVENT_MASK_FOCUS_CHANGE
| XCB_EVENT_MASK_VISIBILITY_CHANGE
| XCB_EVENT_MASK_POINTER_MOTION
| XCB_EVENT_MASK_BUTTON_PRESS
| XCB_EVENT_MASK_BUTTON_RELEASE };
int border_width = 0;
xcb_create_window(c,
XCB_COPY_FROM_PARENT,
win,
screen->root,
0, 0,
launch_width, launch_height,
border_width,
XCB_WINDOW_CLASS_INPUT_OUTPUT,
screen->root_visual,
mask, values);
// map the window on the screen
xcb_map_window(c, win);
xcb_flush(c);
return win;
}
int init_socket () {
// in_addr v4 = { 0 };
sockaddr_in v4 = { 0 };
sockaddr_in6 v6 = { 0 };
ifaddrs* pInterfaces = 0;
getifaddrs(&pInterfaces);
ifaddrs* pInterface = pInterfaces;
while (pInterface) {
if (!(pInterface->ifa_flags & IFF_LOOPBACK)) {
if (pInterface->ifa_addr->sa_family == AF_INET) {
sockaddr_in* ipv4interface = (sockaddr_in*)pInterface->ifa_addr;
in_addr* ipv4 = & ipv4interface->sin_addr;
memcpy(&v4, ipv4interface, sizeof(v4));
// printipv4(ipv4);
char str4[INET_ADDRSTRLEN] = { 0 };
inet_ntop(AF_INET, ipv4, str4, INET_ADDRSTRLEN);
printf("%s IPv4: %s\n", pInterface->ifa_name, str4);
} else if (pInterface->ifa_addr->sa_family == AF_INET6) {
sockaddr_in6* ipv6interface = (sockaddr_in6*)pInterface->ifa_addr;
in6_addr* ipv6 = & ipv6interface->sin6_addr;
int linkLocal = ((unsigned short*)ipv6->s6_addr)[0];
if (linkLocal != 0x80FE) {
memcpy(&v6, ipv6interface, sizeof(v6));
char str6[INET6_ADDRSTRLEN] = { 0 };
inet_ntop(AF_INET6, ipv6, str6, INET6_ADDRSTRLEN);
printf("%s IPv6: %s\n", pInterface->ifa_name, str6);
}
}
}
pInterface = pInterface->ifa_next;
}
freeifaddrs(pInterfaces);
// 1 socket per interface and protocol version
int fdDns = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);
// bind to a random port
// int port = 12345;
// v4.sin_port = htons(port);
int bindOk = bind(fdDns, (sockaddr*)&v4, sizeof(v4));
if (bindOk == -1) {
printf("Failed to bind to a random port\n");//port %d\n", port);
}
socklen_t bytes_our_addr = sizeof(v4);
if (getsockname(fdDns, (struct sockaddr *)&v4, &bytes_our_addr) != -1) {
printf("UDP is listening on port %d\n", ntohs(v4.sin_port));
}
return fdDns;
}
termios orig_term_attr = { 0 };
void restore_terminal () {
tcsetattr(fileno(stdin), TCSANOW, &orig_term_attr);
}
unsigned char bitstream[ 7337 ] = { 0 };
void load_bitstream () {
FILE* file = fopen("./../arachne-pnr/example-384-processed.bin", "rb");
if (!file) {
fprintf(stderr, "Unable to open bitstream file");
return;
}
unsigned long fileLen = 7337;
fread(bitstream, fileLen, 1, file);
fclose(file);
}
int main (int args_array_size, const char** args_array) {
unsigned char char_to_send = '1';
printf("Instant-384 UDP Proxy v1.0\n");
bool should_send = false;
sigset_t mask = { 0 };
sigemptyset(&mask);
sigaddset(&mask, SIGINT);
sigaddset(&mask, SIGQUIT);
// Block signals so that they aren't handled according to their default dispositions
sigprocmask(SIG_BLOCK, &mask, 0);
int sfd = signalfd(-1, &mask, SFD_NONBLOCK);
xcb_connection_t* c = xcb_connect(0, 0);
int window_width = 64;
int window_height = 64;
xcb_drawable_t win = create_xcb_window(c, window_width, window_height);
int xcb_fd = xcb_get_file_descriptor(c);
int event_pump_fd = create_epoll_pump();
int fdDns = init_socket();
make_async(fdDns);
add_listener(event_pump_fd, xcb_fd);
add_listener(event_pump_fd, sfd);
termios new_term_attr;
/* set the terminal to raw mode */
tcgetattr(fileno(stdin), &orig_term_attr);
memcpy(&new_term_attr, &orig_term_attr, sizeof(termios));
new_term_attr.c_lflag &= ~(ECHO|ICANON);
new_term_attr.c_cc[VTIME] = 0;
new_term_attr.c_cc[VMIN] = 0;
tcsetattr(fileno(stdin), TCSANOW, &new_term_attr);
add_listener(event_pump_fd, STDIN_FILENO);
add_listener(event_pump_fd, fdDns, EPOLLOUT);
EGLDisplay egl_display;
EGLConfig egl_config;
EGLContext egl_context;
EGLSurface egl_surface;
setup_egl(
win,
&egl_display,
&egl_config,
&egl_context,
&egl_surface);
for (;;) {
xcb_generic_event_t* e = 0;
while (true) {
epoll_event ready_events[ 1024 ] = { 0 };
int num_fd_ready = -1;
do {
// num_fd_ready = epoll_pwait(event_pump_fd, ready_events, ALEN(ready_events), -1, &mask);
num_fd_ready = epoll_wait(event_pump_fd, ready_events, ALEN(ready_events), -1);
printf("Got an event from the pump\n");
if (num_fd_ready < 0) {
printf("Should we exit?\n");
break;
}
for (int i = 0; i < num_fd_ready; ++i) {
int fdSource = ready_events[i].data.fd;
if (fdSource == xcb_fd) {
printf("Got second XCB fd event from the pump\n");
goto after_pump;
} else if (fdSource == sfd) {
printf("signal\n");
signalfd_siginfo info = { 0 };
int ret = read(sfd, &info, sizeof(info));
if (ret == sizeof(info)) {
if (info.ssi_signo == 2) {
// Ctrl+C
printf("Exit by Ctrl+C\n");
restore_terminal();
return 0;
}
printf("signo = %d\n", info.ssi_signo);
printf("pid = %d\n", info.ssi_pid);
printf("uid = %d\n", info.ssi_uid);
num_fd_ready = 0;
break;
}
} else if (fdSource == fdDns && ready_events[i].events & EPOLLIN) {
unsigned char dnsPacket[ 1500 ] = { 0 };
sockaddr_storage srcAddr = { 0 };
socklen_t bytesSrcAddr = sizeof(srcAddr);
ssize_t bytesRecvd = recvfrom(fdDns, dnsPacket, sizeof(dnsPacket), 0, (sockaddr*)&srcAddr, &bytesSrcAddr);
printf("UDP packet from ");
printipv4(&((sockaddr_in*)&srcAddr)->sin_addr);
int sent = -1;
//for (int a = 0; a < 1; ++a) {
// sent = sendto(fdDns, dnsPacket, bytesValidRequest + sizeof(DnsShortAnswerA), MSG_DONTWAIT, (sockaddr*)&srcAddr, bytesSrcAddr);
//}
// sent = sendto(fdDns, dnsPacket, bytesRecvd, MSG_DONTWAIT, (sockaddr*)&srcAddr, bytesSrcAddr);
if (sent == -1) {
printf("---------- Send failed: %d\n", errno);
}
} else if (fdSource == fdDns && ready_events[i].events & EPOLLOUT) {
printf("UDP socket ready to write %c\n", char_to_send);
if (should_send) {
should_send = false;
//unsigned char udpPacket[ 7334 ] = { 0 };
//udpPacket[ 0 ] = 0xAA;
//udpPacket[ 7333 ] = char_to_send;
sockaddr_in dstAddr = { 0 };
dstAddr.sin_family = AF_INET;
dstAddr.sin_addr.s_addr = inet_addr("192.168.254.54");
int dstPort = 42;
dstAddr.sin_port = htons(dstPort);
load_bitstream();
int sent = sendto(fdDns, bitstream, sizeof(bitstream), MSG_DONTWAIT,
(sockaddr*)&dstAddr, sizeof(dstAddr));
//int sent = sendto(fdDns, udpPacket, sizeof(udpPacket), MSG_DONTWAIT,
// (sockaddr*)&dstAddr, sizeof(dstAddr));
if (sent == -1) {
printf("---------- Send failed: %d\n", errno);
}
}
} else if (STDIN_FILENO == fdSource) {
int byte_result = 0;
read(ready_events[i].data.fd, &byte_result, 1);
if (byte_result == 10) {
// "Enter"
printf("\n");
// } else if (byte_result == 97) {
} else if (byte_result >= ' ' && byte_result <= '~') {
char_to_send = byte_result;
printf("Sending bitstream %c...\n", char_to_send);
//unsigned char udpPacket[ 7334 ] = { 0 };//char_to_send };//, 0 };
//udpPacket[ 0 ] = 0xAA;
//udpPacket[ 7333 ] = char_to_send;
sockaddr_in dstAddr = { 0 };
dstAddr.sin_family = AF_INET;
dstAddr.sin_addr.s_addr = inet_addr("192.168.254.54");
int dstPort = 42;
dstAddr.sin_port = htons(dstPort);
load_bitstream();
int sent = sendto(fdDns, bitstream, sizeof(bitstream), MSG_DONTWAIT,
(sockaddr*)&dstAddr, sizeof(dstAddr));
//int sent = sendto(fdDns, udpPacket, sizeof(udpPacket), MSG_DONTWAIT,
// (sockaddr*)&dstAddr, sizeof(dstAddr));
if (sent == -1) {
printf("---------- Send failed: %d\n", errno);
}
// should_send = true;
} else {
printf("STDIN %d %d\n", num_fd_ready, ready_events[i].data.fd);
printf("STDIN read %d\n", byte_result);
}
} else {
printf("[[[ GOT SOME UNEXPECTED INTERRUPTION OF epoll ]]]\n");
}
}
} while (num_fd_ready > 0);
after_pump:
printf("Events pump done\n");
if ((e = xcb_poll_for_event(c))) {
printf("xcb event\n");
break;
}
}
if (!e) {
printf("Done.\n");
break;
}
switch (e->response_type & ~0x80) {
case XCB_EXPOSE: {
printf("Exposure\n");
runApp(window_width, window_height);
eglSwapBuffers(egl_display, egl_surface);
break;
}
case XCB_KEY_PRESS:
printf("Break on keypress.\n");
goto endloop;
case XCB_RESIZE_REQUEST: {
const xcb_resize_request_event_t* cfgEvent
= (const xcb_resize_request_event_t*)e;
printf("%dx%d\n", cfgEvent->width, cfgEvent->height);
window_width = cfgEvent->width;
window_height = cfgEvent->height;
runApp(window_width, window_height);
eglSwapBuffers(egl_display, egl_surface);
break;
}
case XCB_CONFIGURE_NOTIFY: {
const xcb_configure_notify_event_t* cfgEvent = (const xcb_configure_notify_event_t *)e;
printf("%dx%d\n", cfgEvent->width, cfgEvent->height);
/*
if (((cfgEvent->width != width) || (cfgEvent->height != height))) {
destWidth = cfgEvent->width;
destHeight = cfgEvent->height;
if ((destWidth > 0) && (destHeight > 0))
{
// Swap chain recreation ins done in this function
windowResize();
}
}*/
}
} // switch
printf("XCB %d\n", e->response_type);
free(e);
}
endloop:
restore_terminal();
return 0;
}
Raw
yosys_launch.sh
# Synthesize
./../yosys/yosys -p "read_verilog ./proj/example.v; synth_ice40 -nobram -blif example.blif"
# Place & route
./bin/arachne-pnr -d 384 -P qn32 -p ./proj/ice40lp384.pcf -o example.txt --post-place-blif ./post.blif ./example.blif
# Compiled version of icepack removing deep sleep because we're directly reprogramming over the 5-wire protocol
# CRESET_B, SPI_SCK, SPI_DI, CDONE, SPI_SS_B
./a.out -vvv -n ./example.txt example.bin
# Generate a Verilog with RAM filled with the FPGA image in it (temporary solution)
node ./lattice-conv.js
# reports of what you've made
./../yosys/yosys -q -o ./post.json ./post.blif
./../yosys/yosys -p "read_verilog -sv ./proj/example.v; synth_ice40 -nobram -blif example.blif" && ./bin/arachne-pnr -d 384 -P qn32 -p ./proj/ice40lp384.pcf -o example.txt --post-place-blif ./post.blif ./example.blif && ./a.out -vvv -n -s ./example.txt example-384.bin && node ./gen.js && ./../direct384/build/build.sh # && ./../yosys/yosys -q -o ./post.json ./post.blif
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