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avesus/old-testbench.v

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Working reprogrammer
Raw
old-testbench.v
`timescale 1ns / 1ps
module testbench ();
endmodule
/*
module testbench2 ();
reg GCLK100 = 1'b0;
wire ETH_MDC;
wire ETH_MDIO, ETH_RX_DV;
reg signal_ETH_MDIO_write = 1'bz;
reg signal_ETH_RX_DV_write = 1'bz;
wire signal_ETH_MDIO_read;
wire signal_ETH_RX_DV_read;
assign signal_ETH_MDIO_read = ETH_MDIO;
assign ETH_MDIO = signal_ETH_MDIO_write;
assign signal_ETH_RX_DV_read = ETH_RX_DV;
assign ETH_RX_DV = signal_ETH_RX_DV_write;
reg ETH_REF_CLK = 1'b0;
wire ETH_RSTN;
reg ETH_CRS_DV = 1'b0, ETH_RXD0 = 1'b0, ETH_RXD1 = 1'b0;
wire ETH_TX_EN, ETH_TXD0, ETH_TXD1;
wire LED0_B, LED1_B, LED2_B, LED3_B;
wire LED0_R, LED1_R, LED2_R, LED3_R;
reg DONE = 1'b0;
wire CK_IO26, CK_IO27, CK_IO28, CK_IO29, CK_IO30, CK_IO31, CK_IO32, CK_IO33, CK_IO34;
reg BTN3 = 1'b0, BTN2 = 1'b0, BTN1 = 1'b0, SW3 = 1'b0, SW2 = 1'b0, SW1 = 1'b0, SW0 = 1'b0;
wire CK_IO0, CK_IO1, CK_IO2, CK_IO3, CK_IO4, CK_IO5;
reg CK_RST = 1'b1;
always begin
#5 GCLK100 = ~GCLK100;
end
always begin
#10 ETH_REF_CLK = ~ETH_REF_CLK;
end
top entire_fpga (
.GCLK100 (GCLK100),
.CK_RST (CK_RST),
.BTN0 (BTN0),
.BTN1 (BTN1),
.BTN2 (BTN2),
.BTN3 (BTN3),
.SW0 (SW0),
.SW1 (SW1),
.SW2 (SW2),
.SW3 (SW3),
.LED0_B (LED0_B),
.LED1_B (LED1_B),
.LED2_B (LED2_B),
.LED3_B (LED3_B),
.LED0_R (LED0_R),
.LED1_R (LED1_R),
.LED2_R (LED2_R),
.LED3_R (LED3_R),
/*
.ETH_RXD0 (ETH_RXD0),
.ETH_RXD1 (ETH_RXD1),
.ETH_CRS_DV (ETH_CRS_DV),
.ETH_TXD0 (ETH_TXD0),
.ETH_TXD1 (ETH_TXD1),
.ETH_TX_EN (ETH_TX_EN),
.ETH_MDC (ETH_MDC),
.ETH_MDIO (ETH_MDIO),
.ETH_RX_DV (ETH_RX_DV),
.ETH_REF_CLK (ETH_REF_CLK),
.ETH_RSTN (ETH_RSTN),
* /
// LED strip
/*
.CK_IO37 (CK_IO37),
.CK_IO39 (CK_IO39),
* /
// Lattice Reprogrammer
.CK_IO0 (CK_IO0),
.CK_IO1 (CK_IO1),
.CK_IO2 (CK_IO2),
.CK_IO3 (CK_IO3),
.CK_IO4 (CK_IO4),
.CK_IO5 (CK_IO5),
// Diagnostic outputs
.CK_IO26 (CK_IO26),
.CK_IO27 (CK_IO27),
.CK_IO28 (CK_IO28),
.CK_IO29 (CK_IO29),
.CK_IO30 (CK_IO30),
.CK_IO31 (CK_IO31),
.CK_IO32 (CK_IO32),
.CK_IO33 (CK_IO33),
.CK_IO34 (CK_IO34),
.JD7 (ETH_TXD1), // TX1
.JA1 (ETH_TXD0), // TX0
.JA2 (ETH_RXD1), // RX1
.JA3 (ETH_CRS_DV), // CRS_DV
.JA4 (ETH_MDC), // MDC
.JA7 (ETH_TX_EN), // TX_EN
.JA8 (ETH_RXD0), // RX0
.JA9 (ETH_REF_CLK), // REFCLK
.JA10 (ETH_MDIO) // MDIO
/* .LED4 (LED4),
.LED5 (LED5),
.LED6 (LED6),
.LED7 (LED7) * /
);
/*
CustomDelay #(.CLOCK_FREQUENCY_HZ (100_000_000))
delay_service (
.CLK (GCLK100),
.DELAY_IN_NANOSECONDS (32'd80),
.RESET (REQUEST_DELAY),
.COMPLETE (DELAY_PASSED));
* /
initial begin
#4205 signal_ETH_RX_DV_write = 1'b1;
#1340
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#15
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
// SFD byte
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// ff ff ff ff ff ff c8 d9 d2 78 13 34 08 06 00 01 08 00 06 04 00 01 c8 d9 d2 78 13 34 c0 a8 00 01 00 00 00 00 00 00 c0 a8 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cd f4 59 79
// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
// \xff\xff\xff\xff\xff\xff\xc8\xd9\xd2\x78\x13\x34\x08\x06\x00\x01\x08\x00\x06\x04\x00\x01\xc8\xd9\xd2\x78\x13\x34\xc0\xa8\x00\x01\x00\x00\x00\x00\x00\x00\xc0\xa8\x00\x02\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00
// Another one for 192.168.254.54 and requester .11:
// \xc8\xd9\xd2\x78\x13\x34\x42\x55\x55\x55\x55\x55\x08\x06\x00\x01\x08\x00\x06\x04\x00\x02\x42\x55\x55\x55\x55\x55\xc0\xa8\xfe\x36\xc8\xd9\xd2\x78\x13\x34\xc0\xa8\xfe\x0b\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00
// Byte 0
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 1
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 2
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 3
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 4
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 5
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Bytes 6, 7, 8, 9, 10, 11 - sender's MAC c8 d9 d2 78 13 34
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 12: 0x08
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 13: 0x06
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 14: 0x00
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 15: 0x01
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 16: 0x08
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 17: 0x00
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 18: 0x06
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 19: 0x04
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 20: 0x00
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 21: 0x01
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 22, 23, 24, 25, 26, 27 - sender's MAC c8 d9 d2 78 13 34
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 28, 29, 30, 31 - sender's IP address c0 a8 00 01
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 32, 33, 34, 35, 36, 37 - dest MAC address (unknown)
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 38, 39, 40, 41 - dest IP address to resolve into MAC 36_fe_a8_c0
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#1280
// 58
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
// 59
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
// 60
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// 61
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// 62
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
// Last byte # 63
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
/*
#1345
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#1345
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#1340
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#15
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
// SFD byte
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// ff ff ff ff ff ff c8 d9 d2 78 13 34 08 06 00 01 08 00 06 04 00 01 c8 d9 d2 78 13 34 c0 a8 00 01 00 00 00 00 00 00 c0 a8 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cd f4 59 79
// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
// \xff\xff\xff\xff\xff\xff\xc8\xd9\xd2\x78\x13\x34\x08\x06\x00\x01\x08\x00\x06\x04\x00\x01\xc8\xd9\xd2\x78\x13\x34\xc0\xa8\x00\x01\x00\x00\x00\x00\x00\x00\xc0\xa8\x00\x02\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00
// Byte 0
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 1
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 2
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 3
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 4
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 5
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 6
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// Byte 7
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#4000
// 58
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
// 59
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
// 60
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// 61
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// 62
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
// Last byte # 63
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#1340
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#15
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
// SFD byte
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// ff ff ff ff ff ff c8 d9 d2 78 13 34 08 06 00 01 08 00 06 04 00 01 c8 d9 d2 78 13 34 c0 a8 00 01 00 00 00 00 00 00 c0 a8 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cd f4 59 79
// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
// \xff\xff\xff\xff\xff\xff\xc8\xd9\xd2\x78\x13\x34\x08\x06\x00\x01\x08\x00\x06\x04\x00\x01\xc8\xd9\xd2\x78\x13\x34\xc0\xa8\x00\x01\x00\x00\x00\x00\x00\x00\xc0\xa8\x00\x02\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00
// Bytes 0-5: target MAC 42 55 55 55 55 55
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
// Bytes 6, 7, 8, 9, 10, 11 - sender's MAC c8 d9 d2 78 13 34
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 12: 0x08
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 13: 0x06
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 14: 0x00
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 15: 0x01
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 16: 0x08
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 17: 0x00
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 18: 0x06
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 19: 0x04
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 20: 0x00
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Byte 21: 0x01
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 22, 23, 24, 25, 26, 27 - sender's MAC c8 d9 d2 78 13 34
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 28, 29, 30, 31 - sender's IP address c0 a8 00 01
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 32, 33, 34, 35, 36, 37 - dest MAC address (unknown)
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
// Bytes 38, 39, 40, 41 - dest IP address to resolve into MAC 36_fe_a8_c0
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1;
#20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b0; #20 ETH_RXD0 = 1'b1; ETH_RXD1 = 1'b1; #20 ETH_RXD0 = 1'b0; ETH_RXD1 = 1'b0;
#1280
// 58
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
// 59
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
// 60
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// 61
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
// 62
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
// Last byte # 63
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#1345
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#1345
ETH_CRS_DV = 1'b1;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b1;
ETH_RXD1 = 1'b1;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
#20
ETH_CRS_DV = 1'b0;
ETH_RXD0 = 1'b0;
ETH_RXD1 = 1'b0;
* /
# 4000 CK_RST = 1'b0;
# 4200 CK_RST = 1'b1;
# 1_800_000 CK_RST = 1'b0;
# 4200 CK_RST = 1'b1;
#5000 DONE = 1'b1;
end
endmodule
/*
module testbench2 ();
reg GCLK100, CK_RST, BTN0, BTN1;
wire ETH_REF_CLK;//, CK_IO35, CK_IO38, BTN0;
wire CK_IO37, CK_IO39, LED6, LED7, ETH_MDC, ETH_MDIO, LED1_B;
// wire CK_IO34, CK_IO37, CK_IO36, CK_IO39, LED4, LED5, LED6, LED7;
reg BTN2, SW0;
top t (
.GCLK100 (GCLK100),
.CK_RST (CK_RST),
.BTN0 (BTN0),
.BTN1 (BTN1),
.BTN2 (BTN2),
.SW0 (SW0),
.LED1_B (LED1_B),
.ETH_REF_CLK (ETH_REF_CLK),
.ETH_MDC (ETH_MDC),
.ETH_MDIO (ETH_MDIO),
.CK_IO37 (CK_IO37),
.CK_IO39 (CK_IO39),
.CK_IO0 (CK_IO0),
.CK_IO1 (CK_IO1),
.CK_IO2 (CK_IO2),
.CK_IO3 (CK_IO3),
.CK_IO4 (CK_IO4),
.CK_IO5 (CK_IO5),
.LED4 (LED4),
.LED5 (LED5),
.LED6 (LED6),
.LED7 (LED7)
);
always begin
#5 GCLK100 = ~GCLK100;
end
*/
//always begin
// #20 ETH_REF_CLK = ~ETH_REF_CLK;
//end
/*
reg EVT_EDGE, not_in1, xnor_in1, xnor_in2;
wire EXIT_PULSE, xnor_out, not_out;
EdgeToPulse pulse1 (
.EDGE (EVT_EDGE),
.PULSE (EXIT_PULSE));
LUT4 # (
.INIT (16'b01010101_01010101)
) not1 (
.O (not_out),
.I0 (not_in1),
.I1 (1'b0),
.I2 (1'b0),
.I3 (1'b0)
);
LUT4 # (
.INIT (16'b10011001_10011001)
) xnor1 (
.O (xnor_out),
.I0 (xnor_in1),
.I1 (xnor_in2),
.I2 (1'b0),
.I3 (1'b0)
);
* /
initial begin
//Initialize clock
GCLK100 = 1'b0;
//ETH_REF_CLK = 1'b0;
CK_RST = 1'b1;
BTN0 = 1'b0;
BTN1 = 1'b0;
/*EVT_EDGE = 1'b0;
xnor_in1 = 1'b0;
xnor_in2 = 1'b0;
not_in1 = 1'b0;* /
BTN2 = 1'b0;
SW0 = 1'b0;
#15 CK_RST = 1'b0;
#3_000 CK_RST = 1'b1;
#10 BTN1 = 1'b1;
#10 BTN2 = 1'b1;
#10 BTN2 = 1'b0;
#10 SW0 = 1'b1;
#10 BTN2 = 1'b1;
#10 SW0 = 1'b0;
#10 SW0 = 1'b1;
/*#20 EVT_EDGE = 1'b1;
#20 EVT_EDGE = 1'b0;
#20 EVT_EDGE = 1'b1;
#20 EVT_EDGE = 1'b0;
#20 not_in1 = 1'b1;
#20 not_in1 = 1'b0;
#20 not_in1 = 1'b1;
#20 xnor_in1 = 1'b1;
#20 xnor_in1 = 1'b0;
#20 xnor_in2 = 1'b1;
#20 xnor_in1 = 1'b1;* /
#11_500_000 CK_RST = 1'b0;
#100 CK_RST = 1'b1;
//#185 BTN0 = 1'b1;
//#27 BTN0 = 1'b0;
//End simulation
//#90_000_000
//$finish;
end
endmodule
*/
/*
`define DELAY_IN_NS 2'd0
`define DELAY_IN_US 2'd1
`define DELAY_IN_MS 2'd2
`define DELAY_IN_S 2'd3
module CustomDelay #(
parameter CLOCK_CYCLE_NS = 10
) (
input wire CLK,
input wire [31:0] DELAY_IN_NANOSECONDS,
input wire RESET,
output wire COMPLETE
);
// Statically calculate the number of bits required to represent the counted number
// localparam CLOCK_CYCLE_IN_NS = 32'b1 / CLOCK_FREQUENCY_HZ;
//localparam NUMBER_OF_PULSES_FOR_MAXIMUM_DELAY = 32'h7FFFFFFF / CLOCK_CYCLE_IN_NS;
//localparam MAXIMUM_BITS = $clog2(NUMBER_OF_PULSES_FOR_MAXIMUM_DELAY);
reg [32:0] counter = 0;
reg complete = 1'b0;
reg counting = 1'b0;
always @(posedge CLK) begin
if (RESET)
begin
counter <= DELAY_IN_NANOSECONDS / CLOCK_CYCLE_NS;
complete <= 1'b0;
counting <= 1'b1;
end
if (counting & ~complete & counter == 32'b1 & ~RESET)
begin
complete <= 1'b1;
counting <= 1'b0;
end
if (counting)
begin
counter <= counter - 1;
end
end
assign COMPLETE = complete;
endmodule
*/
// Unused in RMII
//input wire ETH_RXD3,
//input wire ETH_RXD2,
//output wire ETH_TXD2,
//output wire ETH_TXD3,
// input wire ETH_COL, // PHYAD0 not in full-duplex. Always 0 in full-duplex. Not used in RMII
// input wire ETH_RXERR, // MDIX_EN synchronous to RX_CLK if error receiving
// input wire ETH_RX_DV, // MII_MODE asserted high when valid data received
//input wire ETH_TX_CLK, // 25 MHz derived from ETH_REF_CLK
// input wire ETH_RX_CLK, // 25 MHz recovered. Not used in RMII
Raw
old.v
`timescale 1ns / 1ps
`define COUNTER_RESOLUTION_BITS 24
// Can receive Ethernet packets on 100 Mbit/s up to 9200 bytes in size.
// Standard packets are 1500 bytes.
// Receives Ethernet header in dedicated memory to interface with external world:
// The packet structure:
//
module JumboFrameReprogrammer ();
endmodule
module SystemCounter #(
parameter RESOLUTION_BITS = 5
) (
input wire CLOCK,
output reg [RESOLUTION_BITS-1:0] COUNTER = 0
);
always @(posedge CLOCK)
begin
COUNTER <= #4 COUNTER + 1'b1;
end
endmodule
module DelayEngine # (
parameter COUNTER_RESOLUTION_BITS = `COUNTER_RESOLUTION_BITS ) (
input wire CLOCK,
output wire COUNTING,
input wire START,
input wire [COUNTER_RESOLUTION_BITS-1:0] DELAY,
output wire COUNTED
);
// Global supercounter
wire [COUNTER_RESOLUTION_BITS-1:0] SYSTEM_COUNTER;
SystemCounter #(
.RESOLUTION_BITS (COUNTER_RESOLUTION_BITS)
) system_counter (
.CLOCK (CLOCK),
.COUNTER (SYSTEM_COUNTER)
);
// Timers service
reg [COUNTER_RESOLUTION_BITS-1:0] timestamp_started_1 = 0;
reg [COUNTER_RESOLUTION_BITS-1:0] delay_1 = 0;
reg counting = 1'b0;
reg counted = 1'b0;
reg [COUNTER_RESOLUTION_BITS-1:0] time_passed_since_timestamp_1 = 0;
always @(posedge CLOCK)
begin
if (~counting & START)
begin
delay_1 = DELAY;
timestamp_started_1 <= #4 SYSTEM_COUNTER;
counting <= #4 1'b1;
counted <= #4 1'b0;
end
else
// Compute how many ticks have passed
begin
if (counting)
begin
time_passed_since_timestamp_1 <= #4 (SYSTEM_COUNTER - timestamp_started_1);
if (time_passed_since_timestamp_1 >= delay_1)
begin
counting <= #4 1'b0;
counted <= #4 1'b1;
end
end
end
end
assign COUNTING = counting;
assign COUNTED = counted;
endmodule
module top (
input wire GCLK100, // Quartz 100 MHz
input wire CK_RST,
input wire BTN0,
input wire BTN1,
input wire BTN2,
input wire BTN3,
input wire SW0,
input wire SW1,
input wire SW2,
input wire SW3,
output wire CK_IO37, //+
output wire CK_IO39, //+
output wire CK_IO5, //SCK
input wire CK_IO4, // SO
output wire CK_IO3, //SI
output wire CK_IO2, // SS_B
input wire CK_IO1, // CDONE
output wire CK_IO0, // CRESET_B
// ONLY OUTPUTS HERE, DON'T FRY THE BOARD!!!
output wire CK_IO26, // (black)
output wire CK_IO27,
output wire CK_IO28,
output wire CK_IO29,
output wire CK_IO30,
output wire CK_IO31,
output wire CK_IO32,
output wire CK_IO33, // (orange wire)
// A separate wire (the green one) DON'T FRY THE BOARD!
output wire CK_IO34,
// Management interface
/*
output wire ETH_MDC, // Management data clock max 25 MHz
inout wire ETH_MDIO, // Management data I/O
output wire ETH_TX_EN, // Active high
output wire ETH_TXD1,
output wire ETH_TXD0,
input wire ETH_RXD1,
input wire ETH_RXD0,
input wire ETH_CRS_DV, // "Data is ready" CRS_DV/LED_CFG not in full-duplex. Receive medium is not idle (carrier sense)
// Check that these are empty!!! (we're successfully in RMII)
input wire ETH_RXD2,
input wire ETH_RXD3,
// Physical interface
output wire ETH_REF_CLK, // 50 MHz in RMII mode
output wire ETH_RSTN, // Reset active low 1 us power on reset only
// To put into RMII mode only
inout wire ETH_RX_DV, // Put to 1 while resetting to put PHY into the RMII mode then go Z
*/
output wire LED4,
output wire LED5,
output wire LED6,
output wire LED7,
output wire LED0_B,
output wire LED0_R,
output wire LED0_G,
output wire LED1_B,
output wire LED1_R,
output wire LED1_G,
output wire LED2_B,
output wire LED2_R,
output wire LED2_G,
output wire LED3_B,
output wire LED3_R,
output wire LED3_G,
output wire JD7, // TX1
output wire JA1, // TX0
input wire JA2, // RX1
input wire JA3, // CRS_DV
output wire JA4, // MDC
output wire JA7, // TX_EN
input wire JA8, // RX0
input wire JA9, // REFCLK
inout wire JA10, // MDIO
inout wire JD2,
output wire JD3,
output wire JD4,
output wire JD8,
inout wire JD9,
output wire JD10
);
wire SPI_FLASH_SI = JD2; // blue
wire SPI_FLASH_SCK = JD3; // green
wire SPI_FLASH_NOT_HOLD = JD4; // yellow
wire SPI_FLASH_NOT_WP = JD8; // orange
wire SPI_FLASH_SO = JD9; // red
wire SPI_FLASH_NOT_CS = JD10; // brown
assign SPI_FLASH_NOT_CS = ~BTN0;
assign SPI_FLASH_SCK = GCLK100; //1'b0;
assign SPI_FLASH_NOT_WP = 1'b1;
assign SPI_FLASH_NOT_HOLD = 1'b1;
// 9 pins of RMII PHY
wire CRS_DV, RX0, RX1, REFCLK, MDIO;
reg MDC = 1'b0;
/*
reg mdio_signal_write = 1'bz;
wire mdio_signal_read;
assign ETH_MDIO = mdio_signal_write;
assign mdio_signal_read = ETH_MDIO;
*/
reg TX_EN = 1'b0;
reg TX0 = 1'b0;
reg TX1 = 1'b0;
/*
reg MDIO_src = 1'b0;
always @(posedge REFCLK)
begin
if (~MDC)
begin
mdio_signal_write <= #4 1'bz;
MDIO_src <= #4 mdio_signal_read;
end
else
mdio_signal_write <= #4 1'b0;
begin
end
end
*/
// Delay engine for the RMII emulator
wire DELAY_ENGINE_COUNTING, DELAY_ENGINE_COUNTED, DELAY_ENGINE_START;
wire [`COUNTER_RESOLUTION_BITS-1:0] DELAY_ENGINE_DELAY;
assign JA7 = TX_EN;
assign JD7 = TX1;
assign JA1 = TX0;
assign RX0 = JA8;
assign RX1 = JA2;
assign CRS_DV = JA3;
assign JA4 = MDC;
// assign REFCLK = JA9;
BUFG global_clock_50_mhz (
.I (JA9),
.O (REFCLK));
assign MDIO = JA10;
/*
EthernetPhyWrapper ethernet_rmii_chip (
// 9-pin RMII emulation
.MDC (MDC), // Management data clock max 25 MHz
// .MDIO (MDIO), // Management data I/O
.TX_EN (TX_EN), // Active high
.TX1 (TX1),
.TX0 (TX0),
.RX1 (RX1),
.RX0 (RX0),
.CRS_DV (CRS_DV),
.REFCLK (REFCLK),
// Arty interface. Remove in real external RMII PHY.
// Emulates power-on reset because Arty boots the PHY in MII mode
// Transparent wires
// Management interface
.ARTY_ETH_MDC (ETH_MDC), // Management data clock max 25 MHz
// .ARTY_ETH_MDIO (ETH_MDIO), // Management data I/O
.ARTY_ETH_TX_EN (ETH_TX_EN), // Active high
.ARTY_ETH_TXD1 (ETH_TXD1),
.ARTY_ETH_TXD0 (ETH_TXD0),
.ARTY_ETH_RXD1 (ETH_RXD1),
.ARTY_ETH_RXD0 (ETH_RXD0),
.ARTY_ETH_CRS_DV (ETH_CRS_DV), // "Data is ready" CRS_DV/LED_CFG not in full-duplex. Receive medium is not idle (carrier sense)
// Physical interface
.ARTY_ETH_REF_CLK (ETH_REF_CLK), // 50 MHz in RMII mode. Derived from GCLK100
.ARTY_ETH_RSTN (ETH_RSTN), // Reset active low 1 us power on reset only
// To put into RMII mode only
.ARTY_ETH_RX_DV (ETH_RX_DV), // Put to 1 while resetting to put PHY into the RMII mode then go Z
.ARTY_GCLK100 (GCLK100),
.DELAY_ENGINE_COUNTING (DELAY_ENGINE_COUNTING),
.DELAY_ENGINE_COUNTED (DELAY_ENGINE_COUNTED),
.DELAY_ENGINE_START (DELAY_ENGINE_START),
.DELAY_ENGINE_DELAY (DELAY_ENGINE_DELAY)
);
*/
DelayEngine delay_engine (
.CLOCK (REFCLK),
.COUNTING (DELAY_ENGINE_COUNTING),
.START (DELAY_ENGINE_START),
.DELAY (DELAY_ENGINE_DELAY),
.COUNTED (DELAY_ENGINE_COUNTED));
//assign LED3_R = CRS_DV;
reg [7:0] receiving_byte = 8'd0;
reg [7:0] received_byte = 8'd0;
reg byte_is_ready = 1'b0;
reg [1:0] receive_ptr = 2'd0;
reg [13:0] receiving_byte_number = 14'd0;
reg receiving = 1'b0;
reg synchronized_crs_dv_0 = 1'b0;
reg synchronized_crs_dv = 1'b0;
reg sfd_detected = 1'b0;
reg [1:0] no_crs_toggle = 2'd0;
reg [31:0] crc_state = 32'hFFFFFFFF;
reg [7:0] latched_byte_for_crc32 = 8'd0;
(* keep = "true", DONT_TOUCH = "true" *) reg [31:0] fcs_reg = 32'h00000000;
wire [31:0] crc_next_combinational_slow;
(* keep = "true", DONT_TOUCH = "true" *) Lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.LFSR_CONFIG ("GALOIS"),
.STYLE("LOOP")
)
eth_crc_8 (
.data_in(latched_byte_for_crc32), // { RX1, RX0, receiving_byte[5:0] }
.state_in(crc_state),
.state_out(crc_next_combinational_slow)
);
reg byte_for_crc32_is_ready = 1'b0;
reg reset_crc_state = 1'b0;
/*
always @(posedge REFCLK)
begin
if (reset_crc_state)
begin
crc_state <= #4 32'hFFFFFFFF;
end
else
if (byte_for_crc32_is_ready)
begin
crc_state <= #13 crc_next_combinational_slow;
end
fcs_reg <= #4 ~crc_state;
end */
// ARP packet parser.
// We start responding while this packet runs the data.
// Because the response won't complete before a potential new packet can arrive,
// if we detected an ARP packet we're responding to, we will lock the parser until the send finishes.
// This may lead to misses of packets, but these are repeated often by the ARP stack.
reg arp_parser_is_locked = 1'b0;
reg sending_arp_response = 1'b0;
wire [10:0] arp_response_bit_address;
//TX1 <= #4 RX1;
//TX_EN <= #4 1'b1;
//TX0 <= #4 RX0;
//TX1 <= #4 RX1;
reg reset_arp_response_counter = 1'b0;
reg [1:0] skip_first_arp_sending_counter_pulse = 2'b10;
reg maybe_arp_request = 1'b1; // & each condition until the last one on every received byte. Sets to 1 on first packet
reg target_is_broadcast = 1'b1;
reg target_is_direct_mac_address = 1'b1;
assign LED0_R = ~maybe_arp_request;
assign LED1_R = ~target_is_broadcast;
assign LED2_R = ~target_is_direct_mac_address;
wire arp_response_sent;
reg [31:0] requester_ip_address = 32'b0;
reg [47:0] requester_mac_address = 48'b0;
// TODO: fix test
//wire [31:0] const_device_ip_address = 32'h02_00_a8_c0;
wire [31:0] const_device_ip_address = 32'h36_fe_a8_c0;
wire [47:0] const_device_mac_address = 48'h55_55_55_55_55_42;
wire [63:0] const_eth_preamble = 64'hD5_55_55_55_55_55_55_55;
// Offsets
wire [3:0] current_dibit_index_in_byte = receive_ptr * 3'd2;
wire [5:0] mac_index_combinational_slow = (receiving_byte_number - 14'd6) * 14'd8 + current_dibit_index_in_byte;
wire [4:0] ip_address_index_combinational_slow = (receiving_byte_number - 14'd28) * 14'd8 + current_dibit_index_in_byte;
wire [4:0] our_ip_address_index_combinational_slow = (receiving_byte_number - 14'd38) * 14'd8 + current_dibit_index_in_byte;
wire [5:0] our_mac_address_index_combinational_slow = receiving_byte_number * 14'd8 + current_dibit_index_in_byte;
wire [7:0] eth_frame_type_index_combinational_slow = (receiving_byte_number - 14'd12) * 14'd8 + current_dibit_index_in_byte;
wire [79:0] const_eth_frame_type_pattern = 80'h01000406000801000608;
wire [79:0] const_eth_frame_type_reply_pattern = 80'h02000406000801000608;
wire [15:0] const_eth_frame_type_ip_v4 = 16'h0008;
// 512 bytes max address (doesn't support 1500 packets yet)
reg [8:0] crc_encoding_byte_number = 9'b0;
reg maybe_udp_packet = 1'b1;
reg code_red = 1'b0;
assign LED3_R = code_red;
reg [7:0] received_udp_packet = 8'b0;
reg [1:0] bitstream_dibit = 2'b0;
reg bitstream_write_enable = 1'b0;
reg [17:0] bitstream_write_addr = 18'b0;
/*
always @(negedge REFCLK)
begin
if (bitstream_write_enable)
begin
bitstream_write_addr <= #4 bitstream_write_addr + 18'd1;
end
else
begin
bitstream_write_addr <= #4 18'b0;
end
end
*/
// assign bitstream_dibit = { RX1, RX0 };
always @(posedge REFCLK)
begin
if (receiving & sfd_detected)
begin
if (maybe_udp_packet)
begin
// Frame type == IPv4
if (receiving_byte_number >= 14'd12 & receiving_byte_number < 14'd14)
begin
maybe_udp_packet <= #4 const_eth_frame_type_ip_v4[eth_frame_type_index_combinational_slow +: 2] == { RX1, RX0 } ? maybe_udp_packet : 1'b0;
end
else if (receiving_byte_number >= 14'd30 & receiving_byte_number < 14'd34) begin
maybe_udp_packet <= #4 const_device_ip_address[((receiving_byte_number - 14'd30) * 14'd8 + current_dibit_index_in_byte) +: 2] == { RX1, RX0 } ? maybe_udp_packet : 1'b0;
end
/*else if (receiving_byte_number == 14'd14)
begin
code_red <= #4 1'b1;
end*/
else if (receiving_byte_number >= 14'd42 & receiving_byte_number < 14'd7379)
begin
bitstream_write_enable <= #4 1'b1;
bitstream_dibit <= #4 { RX1, RX0 };
// bitstream_dibit <= #4 { 1'b1, 1'b0 };
bitstream_write_addr <= #4 (receiving_byte_number - 14'd42) * 14'd8 + current_dibit_index_in_byte;
//if (receiving_byte_number >= 14'd7375) // 42
//begin
// receiving_byte_number
// current_dibit_index_in_byte
//if (receiving_byte_number == 14'd7375)
if (receiving_byte_number == 14'd7360) //0x1cc0 == 0x99
begin
received_udp_packet[((receiving_byte_number - 14'd7360) * 14'd8 + current_dibit_index_in_byte) +: 2] <= #4 { RX1, RX0 };
code_red <= #4 1'b1;
reset_synchronizer2 <= #4 1'b1;
end
//end
end
else if (receiving_byte_number == 14'd7379)
begin
bitstream_write_enable <= #4 1'b0;
reset_synchronizer2 <= #4 1'b0;
end
end
end
if (receiving & sfd_detected & ~arp_parser_is_locked)
begin
if (maybe_arp_request)
begin
// Testbench only
/*
if (receiving_byte_number >= 14'd6 & receiving_byte_number < 14'd41)
begin
bitstream_write_enable <= #4 1'b1;
bitstream_dibit <= #4 { RX1, RX0 };
bitstream_write_addr <= #4 (receiving_byte_number - 14'd6) * 14'd8 + current_dibit_index_in_byte;
end
else if (receiving_byte_number == 14'd41)
begin
bitstream_write_enable <= #4 1'b0;
end
*/
// Capture receiver's MAC address (might be broadcast our our)
if (receiving_byte_number < 14'd6) begin
target_is_direct_mac_address <= #4 const_device_mac_address[our_mac_address_index_combinational_slow +: 2] == { RX1, RX0 } ? target_is_direct_mac_address : 1'b0;
target_is_broadcast <= #4 target_is_broadcast & RX1 & RX0;
// Previous flag - the last flag will be caught in the byte 6
maybe_arp_request <= #4 (target_is_direct_mac_address | target_is_broadcast);
end
else
// Capture sender's MAC address
if (receiving_byte_number >= 14'd6 & receiving_byte_number < 14'd12) begin
if (receiving_byte_number == 14'd6)
begin
// It's calculated in the end of the cycle
maybe_arp_request <= #4 (target_is_direct_mac_address | target_is_broadcast);
end
requester_mac_address[mac_index_combinational_slow +: 2] <= #4 { RX1, RX0 };
end
else
// Frame type == ARP
if (receiving_byte_number >= 14'd12 & receiving_byte_number < 14'd22) begin
maybe_arp_request <= #4 const_eth_frame_type_pattern[eth_frame_type_index_combinational_slow +: 2] == { RX1, RX0 } ? maybe_arp_request : 1'b0;
end
else
// Capture sender's IP address
if (receiving_byte_number >= 14'd28 & receiving_byte_number < 14'd32) begin
requester_ip_address[ip_address_index_combinational_slow +: 2] <= #4 { RX1, RX0 };
end
else
// Finally compare if they're looking for us, and start sending a response if they do! :-)
if (receiving_byte_number >= 14'd38 & receiving_byte_number < 14'd42) begin
maybe_arp_request <= #4 const_device_ip_address[our_ip_address_index_combinational_slow +: 2] == { RX1, RX0 } ? maybe_arp_request : 1'b0;
end
else
if (receiving_byte_number == 14'd42)
begin
arp_parser_is_locked <= #4 1'b1;
sending_arp_response <= #4 1'b1;
reset_arp_response_counter <= #4 1'b1;
end
end
end
//end
// it's trivial now! :-) Voila!
//always @(posedge REFCLK)
//begin
// Send 72 bytes in di-bits
if (sending_arp_response)
begin
reset_arp_response_counter <= #4 1'b0;
if (~arp_response_sent)
begin
// Silly Xilinx counters don't start counting on "enable" (they are too power efficient LOL)
if (skip_first_arp_sending_counter_pulse > 2'b0)
begin
if (~arp_response_bit_address)
begin
skip_first_arp_sending_counter_pulse <= #4 skip_first_arp_sending_counter_pulse - 2'b1;
// Anyway, set the first two bits of preamble to let them settle
// { TX1, TX0 } <= #4 const_eth_preamble[ arp_response_bit_address +: 2 ];
crc_encoding_byte_number <= #4 14'b0;
//reset_crc_state <= #4 1'b0;
//byte_for_crc32_is_ready <= #4 1'b0;
//latched_byte_for_crc32 <= #4 { RX1, RX0, receiving_byte[5:0] };
//byte_for_crc32_is_ready <= #4 1'b1;
// Reset CRC32
// crc_state <= #4 32'hFFFFFFFF;
end
end
else
begin
// CODE RED!
TX_EN <= #4 1'b1;
// Calculate CRC32 1 byte per clock (it doesn't match to the bit address
// If arp_response_bit_address % 8 is 0 (the beginning of every byte)
// Byte address (arp_response_bit_address gets incremented by 2 so divide it by 2 to increment byte address by 1).
crc_encoding_byte_number <= #4 arp_response_bit_address[10:2];
if (crc_encoding_byte_number < 11'd60)
//if (crc_encoding_byte_number < 11'd58)
begin
if (~arp_response_bit_address[1])
begin
// Capture result of computation of CRC32 (latched_byte_for_crc32 + crc_state) => crc_next_combinational_slow => crc_state
//if (crc_encoding_byte_number < 11'd59)
//begin
crc_state <= #13 crc_next_combinational_slow;
//end
end
else
begin
if (crc_encoding_byte_number == 11'd0)
begin
// Initialize crc_state at the same time when supplying the 0th byte.
crc_state <= #4 32'hFFFFFFFF;
end
if (crc_encoding_byte_number < 11'd6)
begin
latched_byte_for_crc32 <= #4 requester_mac_address[ crc_encoding_byte_number * 11'd8 +: 8 ];
end
else
if (crc_encoding_byte_number >= 11'd6 & crc_encoding_byte_number < 11'd12)
begin
latched_byte_for_crc32 <= #4 const_device_mac_address[ (crc_encoding_byte_number - 11'd6) * 11'd8 +: 8 ];
end
else
if (crc_encoding_byte_number >= 11'd12 & crc_encoding_byte_number < 11'd22)
begin
latched_byte_for_crc32 <= #4 const_eth_frame_type_reply_pattern[ (crc_encoding_byte_number - 11'd12) * 11'd8 +: 8 ];
end
else
if (crc_encoding_byte_number >= 11'd22 & crc_encoding_byte_number < 11'd28)
begin
latched_byte_for_crc32 <= #4 const_device_mac_address[ (crc_encoding_byte_number - 11'd22) * 11'd8 +: 8 ];
end
else
if (crc_encoding_byte_number >= 11'd28 & crc_encoding_byte_number < 11'd32)
begin
latched_byte_for_crc32 <= #4 const_device_ip_address[ (crc_encoding_byte_number - 11'd28) * 11'd8 +: 8 ];
end
else
if (crc_encoding_byte_number >= 11'd32 & crc_encoding_byte_number < 11'd38)
begin
latched_byte_for_crc32 <= #4 requester_mac_address[ (crc_encoding_byte_number - 11'd32) * 11'd8 +: 8 ];
end
else
if (crc_encoding_byte_number >= 11'd38 & crc_encoding_byte_number < 11'd42)
begin
latched_byte_for_crc32 <= #4 requester_ip_address[ (crc_encoding_byte_number - 11'd38) * 11'd8 +: 8 ];
end
else
if (crc_encoding_byte_number >= 11'd42 & crc_encoding_byte_number < 11'd60)
// if (crc_encoding_byte_number >= 11'd42 & crc_encoding_byte_number < 11'd58)
begin
// Zero padding
latched_byte_for_crc32 <= #4 8'b0;
end
end
end
if (arp_response_bit_address < 11'd64)
begin
{ TX1, TX0 } <= #4 const_eth_preamble[ arp_response_bit_address +: 2 ];
end
else
if (arp_response_bit_address >= 11'd64 & arp_response_bit_address < 11'd112)
begin
{ TX1, TX0 } <= #4 requester_mac_address[ arp_response_bit_address - 11'd64 +: 2 ];
end
else
if (arp_response_bit_address >= 11'd112 & arp_response_bit_address < 11'd160)
begin
{ TX1, TX0 } <= #4 const_device_mac_address[ arp_response_bit_address - 11'd112 +: 2 ];
end
else
if (arp_response_bit_address >= 11'd160 & arp_response_bit_address < 11'd240)
begin
{ TX1, TX0 } <= #4 const_eth_frame_type_reply_pattern[ arp_response_bit_address - 11'd160 +: 2 ];
end
else
if (arp_response_bit_address >= 11'd240 & arp_response_bit_address < 11'd288)
begin
{ TX1, TX0 } <= #4 const_device_mac_address[ arp_response_bit_address - 11'd240 +: 2 ];
end
else
if (arp_response_bit_address >= 11'd288 & arp_response_bit_address < 11'd320)
begin
{ TX1, TX0 } <= #4 const_device_ip_address[ arp_response_bit_address - 11'd288 +: 2 ];
end
else
if (arp_response_bit_address >= 11'd320 & arp_response_bit_address < 11'd368)
begin
{ TX1, TX0 } <= #4 requester_mac_address[ arp_response_bit_address - 11'd320 +: 2 ];
end
else
if (arp_response_bit_address >= 11'd368 & arp_response_bit_address < 11'd400)
begin
{ TX1, TX0 } <= #4 requester_ip_address[ arp_response_bit_address - 11'd368 +: 2 ];
end
else
if (arp_response_bit_address >= 11'd400 & arp_response_bit_address < 11'd544)
//if (arp_response_bit_address >= 11'd400 & arp_response_bit_address < 11'd528)
begin
// Zero padding
{ TX1, TX0 } <= #4 2'b0;
end
else
if (arp_response_bit_address >= 11'd544 & arp_response_bit_address < 11'd576)
//if (arp_response_bit_address >= 11'd528 & arp_response_bit_address < 11'd560)
begin
// CRC32
{ TX1, TX0 } <= #4 ~crc_state[ arp_response_bit_address - 11'd544 +: 2 ];
//{ TX1, TX0 } <= #4 ~crc_state[ arp_response_bit_address - 11'd528 +: 2 ];
end
end
end
else
begin
sending_arp_response <= #4 1'b0;
skip_first_arp_sending_counter_pulse <= #4 2'b10;
TX_EN <= #4 1'b0;
{ TX1, TX0 } <= #4 2'b0;
// Unlock the parser so it can receive some ARP packets and collect a different data
// This unlock might happen in the middle of receiving of another packet,
// then unlock must happen after that receive will finishes.
// We don't reset "maybe_arp_request" here, it'll happen in the beginning of another packet,
// if the current packet was receiving, we'll drop it because we're not caching MAC and IP addresses of
// requestors yet (but it's totally doable with a double-buffering).
arp_parser_is_locked <= #4 1'b0;
end
end
//synchronized_crs_dv_0 <= #4 CRS_DV;
//synchronized_crs_dv <= synchronized_crs_dv_0;
//if (~receiving & synchronized_crs_dv & (RX1 | RX0))
if (~receiving & CRS_DV & ~RX1 & RX0 & ~sfd_detected)
begin
receiving <= #4 1'b1;
receiving_byte_number <= 14'd0;
receive_ptr <= #4 1'b0;
end
if (receiving)
begin
if (~sfd_detected)
begin
if (RX1 & RX0)
begin
sfd_detected <= #4 1'b1;
receive_ptr <= #4 1'b0;
// Reset parser because it might be tricked by the previous packet
// If it was sending, we're missing the parsing of the current packet:
// that bug is by design.
if (~arp_parser_is_locked)
begin
maybe_arp_request <= #4 1'b1;
maybe_udp_packet <= #4 1'b1;
target_is_broadcast <= #4 1'b1;
target_is_direct_mac_address <= #4 1'b1;
end
end
end
else
begin
if (receive_ptr == 2'd0)
begin
receiving_byte[1:0] <= #4 { RX1, RX0 };
//byte_for_crc32_is_ready <= #4 1'b0;
//if (receiving_byte_number == 14'b0)
//begin
// reset_crc_state <= #4 1'b1;
//end
end
if (receive_ptr == 2'd1)
begin
receiving_byte[3:2] <= #4 { RX1, RX0 };
//if (receiving_byte_number == 14'd0)
//begin
// reset_crc_state <= #4 1'b0;
//end
end
if (receive_ptr == 2'd2)
begin
receiving_byte[5:4] <= #4 { RX1, RX0 };
end
if (receive_ptr == 2'd3)
begin
receiving_byte[7:6] <= #4 { RX1, RX0 };
receiving_byte_number <= #4 receiving_byte_number + 14'd1;
//if (receiving_byte_number < 14'd60)
//begin
// latched_byte_for_crc32 <= #4 { RX1, RX0, receiving_byte[5:0] };
// byte_for_crc32_is_ready <= #4 1'b1;
//end
// Output it
// received_byte <= #4 { RX1, RX0, receiving_byte[5:0] };
// Or output a specific byte in the packet:
if (receiving_byte_number == {0,0,0,0,0,0,0,0,0,0, SW3, SW2, SW1, SW0 })
//if (receiving_byte_number == {0,0,0,0,0,0,0,0,1'b1,1'b1,1'b1,1'b1, SW1, SW0 }) //14'd6) // 0, 1, 2, 3, 4, 5 - DST MAC
//if (receiving_byte_number == 14'd63) // 0, 1, 2, 3, 4, 5 - DST MAC
//if (receiving_byte_number == 14'd41) // 0, 1, 2, 3, 4, 5 - DST MAC
begin
received_byte <= #4 { RX1, RX0, receiving_byte[5:0] };
byte_is_ready <= #4 1'b1;
end
end
receive_ptr <= #4 receive_ptr + 2'd1;
end
if (~CRS_DV)
begin
if (no_crs_toggle == 2'd3)
begin
receiving <= #4 1'b0;
sfd_detected <= #4 1'b0;
no_crs_toggle <= #4 2'd0;
end
no_crs_toggle <= no_crs_toggle + 1'b1;
end
end
if (CRS_DV)
begin
no_crs_toggle <= #4 2'd0;
end
end
assign LED1_B = sending_arp_response;
COUNTER_TC_MACRO # (
.COUNT_BY (48'h000000000002), // Count by a di-bit
.DEVICE ("7SERIES"),
.DIRECTION ("UP"),
.RESET_UPON_TC ("TRUE"), //Reset counter upon terminal count
.TC_VALUE (10'd576), // Terminal count value, number of bits to send an ARP response
.WIDTH_DATA (11) // Counter output bus width, 1-48
) arp_response_counter_registers (
.Q (arp_response_bit_address), // Counter output bus, width determined by WIDTH_DATA parameter
.TC (arp_response_sent), // 1-bit terminal count output, high = terminal count is reached
.CLK (REFCLK), // 1-bit positive edge clock input
.CE (sending_arp_response), // 1-bit active high clock enable input
.RST (reset_arp_response_counter) // 1-bit active high synchronous reset
);
/*
assign CK_IO26 = crc_state[0];
assign CK_IO27 = crc_state[1];
assign CK_IO28 = crc_state[2];
assign CK_IO29 = crc_state[3];
assign CK_IO30 = crc_state[4];
assign CK_IO31 = crc_state[5];
assign CK_IO32 = crc_state[6];
assign CK_IO33 = crc_state[7];
*/
/*
assign CK_IO26 = ~BTN1 ? received_byte[0] : fcs_reg[0 + 8 * SW0 + 16 * SW1];
assign CK_IO27 = ~BTN1 ? received_byte[1] : fcs_reg[1 + 8 * SW0 + 16 * SW1];
assign CK_IO28 = ~BTN1 ? received_byte[2] : fcs_reg[2 + 8 * SW0 + 16 * SW1];
assign CK_IO29 = ~BTN1 ? received_byte[3] : fcs_reg[3 + 8 * SW0 + 16 * SW1];
assign CK_IO30 = ~BTN1 ? received_byte[4] : fcs_reg[4 + 8 * SW0 + 16 * SW1];
assign CK_IO31 = ~BTN1 ? received_byte[5] : fcs_reg[5 + 8 * SW0 + 16 * SW1];
assign CK_IO32 = ~BTN1 ? received_byte[6] : fcs_reg[6 + 8 * SW0 + 16 * SW1];
assign CK_IO33 = ~BTN1 ? received_byte[7] : fcs_reg[7 + 8 * SW0 + 16 * SW1];
*/
/*
assign CK_IO26 = ~BTN1 ? received_byte[0] : fcs_reg[0 + 8 * SW0 + 16 * SW1];
assign CK_IO27 = ~BTN1 ? received_byte[1] : fcs_reg[1 + 8 * SW0 + 16 * SW1];
assign CK_IO28 = ~BTN1 ? received_byte[2] : fcs_reg[2 + 8 * SW0 + 16 * SW1];
assign CK_IO29 = ~BTN1 ? received_byte[3] : fcs_reg[3 + 8 * SW0 + 16 * SW1];
assign CK_IO30 = ~BTN1 ? received_byte[4] : fcs_reg[4 + 8 * SW0 + 16 * SW1];
assign CK_IO31 = ~BTN1 ? received_byte[5] : fcs_reg[5 + 8 * SW0 + 16 * SW1];
assign CK_IO32 = ~BTN1 ? received_byte[6] : fcs_reg[6 + 8 * SW0 + 16 * SW1];
assign CK_IO33 = ~BTN1 ? received_byte[7] : fcs_reg[7 + 8 * SW0 + 16 * SW1];*/
wire [7:0] fcs_0 = fcs_reg[7:0]; // { fcs_reg[0], fcs_reg[1], fcs_reg[2], fcs_reg[3], fcs_reg[4], fcs_reg[5], fcs_reg[6], fcs_reg[7] };
wire [7:0] fcs_1 = fcs_reg[15:8]; //{ fcs_reg[8], fcs_reg[9], fcs_reg[10], fcs_reg[11], fcs_reg[12], fcs_reg[13], fcs_reg[14], fcs_reg[15] };
wire [7:0] fcs_2 = fcs_reg[23:16]; //{ fcs_reg[16], fcs_reg[17], fcs_reg[18], fcs_reg[19], fcs_reg[20], fcs_reg[21], fcs_reg[22], fcs_reg[23] };
wire [7:0] fcs_3 = fcs_reg[31:24]; //{ fcs_reg[24], fcs_reg[25], fcs_reg[26], fcs_reg[27], fcs_reg[28], fcs_reg[29], fcs_reg[30], fcs_reg[31] };
/*
assign CK_IO26 = ~SW3 ? received_byte[0] : ~SW0 & ~SW1 ? fcs_0[0] : SW0 & ~SW1 ? fcs_1[0] : ~SW0 & SW1 ? fcs_2[0] : fcs_3[0];
assign CK_IO27 = ~SW3 ? received_byte[1] : ~SW0 & ~SW1 ? fcs_0[1] : SW0 & ~SW1 ? fcs_1[1] : ~SW0 & SW1 ? fcs_2[1] : fcs_3[1];
assign CK_IO28 = ~SW3 ? received_byte[2] : ~SW0 & ~SW1 ? fcs_0[2] : SW0 & ~SW1 ? fcs_1[2] : ~SW0 & SW1 ? fcs_2[2] : fcs_3[2];
assign CK_IO29 = ~SW3 ? received_byte[3] : ~SW0 & ~SW1 ? fcs_0[3] : SW0 & ~SW1 ? fcs_1[3] : ~SW0 & SW1 ? fcs_2[3] : fcs_3[3];
assign CK_IO30 = ~SW3 ? received_byte[4] : ~SW0 & ~SW1 ? fcs_0[4] : SW0 & ~SW1 ? fcs_1[4] : ~SW0 & SW1 ? fcs_2[4] : fcs_3[4];
assign CK_IO31 = ~SW3 ? received_byte[5] : ~SW0 & ~SW1 ? fcs_0[5] : SW0 & ~SW1 ? fcs_1[5] : ~SW0 & SW1 ? fcs_2[5] : fcs_3[5];
assign CK_IO32 = ~SW3 ? received_byte[6] : ~SW0 & ~SW1 ? fcs_0[6] : SW0 & ~SW1 ? fcs_1[6] : ~SW0 & SW1 ? fcs_2[6] : fcs_3[6];
assign CK_IO33 = ~SW3 ? received_byte[7] : ~SW0 & ~SW1 ? fcs_0[7] : SW0 & ~SW1 ? fcs_1[7] : ~SW0 & SW1 ? fcs_2[7] : fcs_3[7];
*/
/*
assign CK_IO26 = requester_mac_address[0];
assign CK_IO27 = requester_mac_address[1];
assign CK_IO28 = requester_mac_address[2];
assign CK_IO29 = requester_mac_address[3];
assign CK_IO30 = requester_mac_address[4];
assign CK_IO31 = requester_mac_address[5];
assign CK_IO32 = requester_mac_address[6];
assign CK_IO33 = requester_mac_address[7];
*/
assign CK_IO34 = byte_is_ready;
/*
SW0
SW1
LED0_B
LED1_B
*/
// assign ETH_RSTN = CK_RST;
// assign LED0_R = ETH_CRS_DV;
// assign LED1_R = ETH_RXERR;
// assign LED2_R = ETH_RX_DV;
// assign CK_IO34 = 1'b0;// ETH_MDIO;
//assign LED2_B = ETH_RXD2;
//assign LED3_B = ETH_RXD3;
/*
//assign CK_IO26 = ETH_RXD0;//BTN0;
//assign CK_IO27 = ETH_RXD1;//BTN1;
//assign CK_IO28 = ETH_RXD2;//BTN2;
//assign CK_IO29 = ETH_RXD3;//BTN3;
*/
/*
assign CK_IO26 = BTN0;
assign CK_IO27 = BTN1;
assign CK_IO28 = BTN2;
assign CK_IO29 = BTN3;
assign CK_IO30 = SW0;
assign CK_IO31 = SW1;
assign CK_IO32 = SW2;
assign CK_IO33 = SW3;
*/
assign CK_IO26 = received_udp_packet[0];
assign CK_IO27 = received_udp_packet[1];
assign CK_IO28 = received_udp_packet[2];
assign CK_IO29 = received_udp_packet[3];
assign CK_IO30 = received_udp_packet[4];
assign CK_IO31 = received_udp_packet[5];
assign CK_IO32 = received_udp_packet[6];
assign CK_IO33 = received_udp_packet[7];
// assign LED2_B = ~clk_25;
/*
reg [31:0] cnt_50 = {32'b0};
reg pulse_50;
reg clk_25 = 1'b0;
reg [31:0] cnt_2 = {32'b0};
reg pulse_2;
reg clk_1 = 1'b0;
reg [31:0] cnt_0_062 = {32'b0};
reg pulse_0_062;
reg clk_0_031 = 1'b0;
always @(posedge GCLK100)
begin
if (pulse_50)
begin
clk_25 = ~clk_25;
end
{ pulse_50, cnt_50 } <= cnt_50 + 32'h8000_0000; // 25 MHz
// { pulse_50, cnt_50 } <= cnt_50 + 32'h4000_0000; // 12.5 MHz
if (pulse_2)
begin
clk_1 = ~clk_1;
end
{ pulse_2, cnt_2 } <= cnt_2 + 32'h51eb851; // 1 MHz
if (pulse_0_062)
begin
clk_0_031 = ~clk_0_031;
end
// { pulse_0_062, cnt_0_062 } <= cnt_0_062 + 32'h28f5c2; // 31.250 kHz
{ pulse_0_062, cnt_0_062 } <= cnt_0_062 + 32'h147ae1; // 31.250 kHz
end
*/
//assign CK_IO37 = LED0_G;
assign CK_IO39 = REFCLK;
/*
wire eth_md_mem0;
wire [6:0] counter_read_phy_cnt_addr;
reg counter_read_phy_counted_to_the_end = 1'b0;
wire counter_read_phy_counted_to_the_end_signal;
//assign ETH_REF_CLK = clk_25;
COUNTER_TC_MACRO # (
.COUNT_BY (48'h000000000001), // Count by value
.DEVICE ("7SERIES"), // Target Device: "7SERIES"
.DIRECTION ("UP"), // Counter direction, "UP" or "DOWN"
.RESET_UPON_TC ("FALSE"),//Reset counter upon terminal count, "TRUE" or "FALSE"
.TC_VALUE (7'h2F), // Working to read status
//.TC_VALUE (7'h40), // Writing control value
//.TC_VALUE (7'h0E), // Terminal count value
.WIDTH_DATA (7) // Counter output bus width, 1-48
) counter_read_phy (
.Q (counter_read_phy_cnt_addr), // Counter output bus, width determined by WIDTH_DATA parameter
.TC (counter_read_phy_counted_to_the_end_signal), // 1-bit terminal count output, high = terminal count is reached
.CLK (GCLK100), // 1-bit positive edge clock input
.CE (BTN1 & clk_0_031 & pulse_0_062), // 1-bit active high clock enable input
.RST (~CK_RST) // driven by reset synchronizer, not resetting state!
);
reg reading_from_phy = 1'b0;
//assign ETH_MDC = BTN1 & clk_0_031 & (counter_read_phy_cnt_addr > 6'h0) & ~reading_from_phy;
//assign ETH_MDIO = ~counter_read_phy_counted_to_the_end ? eth_md_mem0 : 1'bz; // To drive the inout net
RAM64X1S #(
//.INIT(64'b00_10000_10000_01_10__1111111_11111111_11111111_11111111_11) // READ 1
.INIT(64'b00_10000_10000_01_10__1111111_11111111_11111111_11111111_11) // READ 1
//.INIT(64'b00_11000_10000_01_10__1111111_11111111_11111111_11111111_11) // READ 3
//.INIT(64'b00010000100_01_00000_10000_10_10__1111111_11111111_11111111_11111111_11) // WRITE
// RRRRR AAAAA WR ST
) RAM64X1S_inst (
.O (eth_md_mem0), // 1-bit data output
.A0 (counter_read_phy_cnt_addr[0]), // Address[0] input bit
.A1 (counter_read_phy_cnt_addr[1]), // Address[1] input bit
.A2 (counter_read_phy_cnt_addr[2]), // Address[2] input bit
.A3 (counter_read_phy_cnt_addr[3]), // Address[3] input bit
.A4 (counter_read_phy_cnt_addr[4]), // Address[4] input bit
.A5 (counter_read_phy_cnt_addr[5]), // Address[5] input bit
.D (1'b0), // 1-bit data input
.WCLK (1'b0), // Write clock input
.WE (1'b0) // Write enable input
);
wire [5:0] phy_reg_value_cnt_addr;
wire phy_reg_value_counted_to_the_end;// = 1'b0;
COUNTER_TC_MACRO # (
.COUNT_BY (48'h000000000001), // Count by value
.DEVICE ("7SERIES"), // Target Device: "7SERIES"
.DIRECTION ("UP"), // Counter direction, "UP" or "DOWN"
.RESET_UPON_TC ("TRUE"),//Reset counter upon terminal count, "TRUE" or "FALSE"
.TC_VALUE (6'h12), // Terminal count value
.WIDTH_DATA (6) // Counter output bus width, 1-48
) counter_read_status (
.Q (phy_reg_value_cnt_addr), // Counter output bus, width determined by WIDTH_DATA parameter
.TC (phy_reg_value_counted_to_the_end), // 1-bit terminal count output, high = terminal count is reached
//.CLK (GCLK100 & ~reading_from_phy | reading_from_phy & BTN3), //clk_0_031), // 1-bit positive edge clock input
.CLK (GCLK100),// & ~reading_from_phy | reading_from_phy & BTN3), //clk_0_031), // 1-bit positive edge clock input
//.CE (counter_read_phy_counted_to_the_end & (clk_25 & pulse_50 & ~reading_from_phy | reading_from_phy)),// & clk_0_031 & pulse_0_062)), //BTN3)), // 1-bit active high clock enable input
.CE (counter_read_phy_counted_to_the_end & (clk_0_031 & pulse_0_062 & ~reading_from_phy | reading_from_phy & clk_0_031 & pulse_0_062)), //BTN3)), // 1-bit active high clock enable input
.RST (~CK_RST) // driven by reset synchronizer, not resetting state!
);
wire write_enable = counter_read_phy_counted_to_the_end & ~reading_from_phy;
RAM64X1S eth_read_status (
.O (LED0_G), // 1-bit data output
.A0 (phy_reg_value_cnt_addr[0]), // Address[0] input bit
.A1 (phy_reg_value_cnt_addr[1]), // Address[1] input bit
.A2 (phy_reg_value_cnt_addr[2]), // Address[2] input bit
.A3 (phy_reg_value_cnt_addr[3]), // Address[3] input bit
.A4 (phy_reg_value_cnt_addr[4]), // Address[4] input bit
.A5 (phy_reg_value_cnt_addr[5]), // Address[5] input bit
.D (ETH_MDIO), // 1-bit data input
.WCLK (ETH_MDC), // Write clock input
.WE (write_enable) // Write enable input
);
// assign LED3_B = ETH_MDIO & counter_read_phy_counted_to_the_end;
always @(posedge clk_25)
begin
if (counter_read_phy_counted_to_the_end_signal)
begin
counter_read_phy_counted_to_the_end = 1'b1;
end
if (phy_reg_value_counted_to_the_end)
begin
reading_from_phy = 1'b1;
end
end
*/
wire SPI_SCK;// = CK_IO5;
wire SPI_SO;// = CK_IO4;
wire SPI_SI;// = CK_IO3;
wire SPI_SS_B;// = CK_IO2;
wire CDONE;// = CK_IO1;
wire CRESET_B;// = CK_IO0;
wire reprogrammer_enable;// = 1'b1;//~CDONE;
IOBUF io_spi_sck (
.O(), // Buffer output: dc
.IO(CK_IO5), // Buffer inout port (connect directly to top-level port)
.I(SPI_SCK), // Buffer input
.T(~reprogrammer_enable) // 3-state enable input, high=input, low=output
);
IOBUF io_spi_si (
.O(), // Buffer output: dc
.IO(CK_IO3), // Buffer inout port (connect directly to top-level port)
.I(SPI_SI), // Buffer input
.T(~reprogrammer_enable) // 3-state enable input, high=input, low=output
);
IOBUF io_spi_ss_b (
.O(), // Buffer output: dc
.IO(CK_IO2), // Buffer inout port (connect directly to top-level port)
.I(SPI_SS_B), // Buffer input
.T(~reprogrammer_enable) // 3-state enable input, high=input, low=output
);
IOBUF io_spi_creset_b (
.O(), // Buffer output: dc
.IO(CK_IO0), // Buffer inout port (connect directly to top-level port)
.I(CRESET_B), // Buffer input
.T(~reprogrammer_enable) // 3-state enable input, high=input, low=output
);
assign LED0_B = reprogrammer_enable;
// Reprogrammer wiring;
//assign CK_IO5 = SPI_SCK;
assign SPI_SO = CK_IO4;
//assign CK_IO3 = SPI_SI;
//assign CK_IO2 = SPI_SS_B;
assign CDONE = CK_IO1;
//assign CK_IO0 = CRESET_B;
reg btn0_synchronizer1;
reg btn0_synchronizer2;
reg reset_synchronizer1;
reg reset_synchronizer2;
reg [31:0] cnt = {32'b0};
// Not used because REFCLK is 50 MHz!
//reg pix_stb;
//reg divided = 1'b0;
wire reset_src_wire = ~CK_RST;
wire reset = reset_synchronizer2;
reg resetting = 1'b0;
reg resetting_wait = 1'b0;
wire resetting_wait_counted_to_the_end;
reg ready = 1'b0;
reg button_pressed = 1'b0;
reg button_released = 1'b0;
reg memory_clear_wait = 1'b0;
wire memory_clear_wait_counted_to_the_end;
reg sending = 1'b0;
reg sent = 1'b0;
// Sending substate machine:
reg sending_skip_first_pulse_wait = 1'b0;
// reg sending_skip_first_pulse_detected = 1'b0;
reg sending_normal_sending_mode = 1'b0;
wire counted_to_the_end;
reg reset_pressed = 1'b0;
reg reset_released = 1'b0;
/*
Fsm s1 (
input wire CLOCK,
input wire FROM_A,
input wire FROM_B,
input wire FROM_C,
input wire EVT_E,
input wire EVT_F,
input wire EVT_G,
output wire TO_ON_E,
output wire TO_ON_F,
output wire TO_ON_G,
output wire ACTIVE,
output wire ENTERED,
output wire EXITED,
);
*/
always @(posedge REFCLK)//GCLK100)
begin
btn0_synchronizer1 <= BTN0;
btn0_synchronizer2 <= btn0_synchronizer1;
reset_synchronizer1 <= reset_src_wire;
//reset_synchronizer2 <= reset_synchronizer1;
// Not used because REFCLK is 50 MHz!
/*
if (pix_stb)
begin
divided = ~divided;
end
*/
// { pix_stb, cnt } <= cnt + 32'ha3cb22; // 1us // divide by 4: (2^32)/4 = 0x4000
// { pix_stb, cnt } <= cnt + 32'ha7c5;
// { pix_stb, cnt } <= cnt + 32'h28f5c28; // 500 kHz
//{ pix_stb, cnt } <= cnt + 32'h51eb851; // 1 MHz
// { pix_stb, cnt } <= cnt + 32'h9999_999a; // 30 MHz
// Not used because REFCLK is 50 MHz!
//{ pix_stb, cnt } <= cnt + 32'hffff_ffff; // 50 MHz
//{ pix_stb, cnt } <= cnt + 32'h8000_0000; // 25 MHz
// { pix_stb, cnt } <= cnt + 32'h7ae1_47ae; // 24 MHz
// { pix_stb, cnt } <= cnt + 32'h4000_0000; // 12.5 MHz
// { pix_stb, cnt } <= cnt + 32'h56;
if (reset & ~reset_pressed)
begin
reset_pressed = 1'b1;
reset_released = 1'b0;
end
if (~reset & reset_pressed)
begin
reset_pressed = 1'b0;
reset_released = 1'b1;
end
if (reset_released)
begin
reset_released = 1'b0;
resetting = 1'b1;
ready = 1'b0;
sending = 1'b0;
sending_skip_first_pulse_wait = 1'b0;
//sending_skip_first_pulse_detected = 1'b0;
sending_normal_sending_mode = 1'b0;
sent = 1'b0;
memory_clear_wait = 1'b0;
resetting_wait = 1'b0;
end
if (resetting & ~reset & ~resetting_wait)
begin
// resetting = 1'b0;
// ready = 1'b1;
resetting_wait = 1'b1;
end
if (resetting_wait & resetting_wait_counted_to_the_end)
begin
resetting_wait = 1'b0;
resetting = 1'b0;
memory_clear_wait = 1'b1;
end
if (memory_clear_wait & memory_clear_wait_counted_to_the_end)
begin
memory_clear_wait = 1'b0;
//ready = 1'b1;
//ready = 1'b0;
sent = 1'b0;
sending = 1'b1;
//button_released = 1'b0;
end
if (btn0_synchronizer2 & ~button_pressed)
begin
button_pressed = 1'b1;
end
if (~btn0_synchronizer2 & button_pressed)
begin
button_pressed = 1'b0;
button_released = 1'b1;
end
else if ((ready | sent) & button_released)
begin
ready = 1'b0;
sent = 1'b0;
sending = 1'b1;
button_released = 1'b0;
end
if (sending & counted_to_the_end)
begin
sending = 1'b0;
sending_skip_first_pulse_wait = 1'b0;
// sending_skip_first_pulse_detected = 1'b0;
sending_normal_sending_mode = 1'b0;
sent = 1'b1;
end
/* if (sending_skip_first_pulse_detected) // & ~divided) // the pulse is over: transition into normal send mode
begin
sending_skip_first_pulse_detected = 1'b0;
sending_normal_sending_mode = 1'b1;
end */
if (sending_skip_first_pulse_wait) // & divided) // became positive (first pulse)
begin
sending_skip_first_pulse_wait = 1'b0;
//sending_skip_first_pulse_detected = 1'b1;
sending_normal_sending_mode = 1'b1;
end
// First ender the sending substate
// if (sending & ~sending_skip_first_pulse_wait & ~sending_skip_first_pulse_detected & ~sending_normal_sending_mode)
if (sending & ~sending_skip_first_pulse_wait & ~sending_normal_sending_mode)
begin
sending_skip_first_pulse_wait = 1'b1;
end
end
wire [3:0] resetting_wait_cnt_addr;
COUNTER_TC_MACRO # (
.COUNT_BY (48'h000000000001), // Count by value
.DEVICE ("7SERIES"), // Target Device: "7SERIES"
.DIRECTION ("UP"), // Counter direction, "UP" or "DOWN"
.RESET_UPON_TC ("FALSE"),//Reset counter upon terminal count, "TRUE" or "FALSE"
//.TC_VALUE (3'h2), // Terminal count value
//.TC_VALUE (3'h4), // Terminal count value
.TC_VALUE (4'h9), // Terminal count value
.WIDTH_DATA (4) // Counter output bus width, 1-48
) counter_200_ns (
.Q (resetting_wait_cnt_addr), // Counter output bus, width determined by WIDTH_DATA parameter
.TC (resetting_wait_counted_to_the_end), // 1-bit terminal count output, high = terminal count is reached
// .CLK (GCLK100), // 1-bit positive edge clock input
.CLK (REFCLK), // 1-bit positive edge clock input
//.CE (pix_stb & divided & resetting_wait), // 1-bit active high clock enable input
.CE (resetting_wait), // 1-bit active high clock enable input
.RST (reset) // driven by reset synchronizer, not resetting state!
);
wire [15:0] memory_clear_wait_cnt_addr;
COUNTER_TC_MACRO # (
.COUNT_BY (48'h000000000001), // Count by value
.DEVICE ("7SERIES"), // Target Device: "7SERIES"
.DIRECTION ("UP"), // Counter direction, "UP" or "DOWN"
.RESET_UPON_TC ("FALSE"),//Reset counter upon terminal count, "TRUE" or "FALSE"
//.TC_VALUE (16'h9c40), // Terminal count value 800 us at 50 MHz
.TC_VALUE (16'h7530), // Terminal count value 600 us at 50 MHz
//.TC_VALUE (16'h4e20), // Terminal count value
.WIDTH_DATA (16) // Counter output bus width, 1-48
) counter_800_us (
.Q (memory_clear_wait_cnt_addr), // Counter output bus, width determined by WIDTH_DATA parameter
.TC (memory_clear_wait_counted_to_the_end), // 1-bit terminal count output, high = terminal count is reached
//.CLK (GCLK100), // 1-bit positive edge clock input
.CLK (REFCLK),
//.CE (pix_stb & divided & memory_clear_wait), // 1-bit active high clock enable input
.CE (memory_clear_wait), // 1-bit active high clock enable input
.RST (resetting) // 1-bit active high synchronous reset
);
wire [17:0] addr;
COUNTER_TC_MACRO # (
.COUNT_BY (48'h000000000001), // Count by value
.DEVICE ("7SERIES"), // Target Device: "7SERIES"
.DIRECTION ("UP"), // Counter direction, "UP" or "DOWN"
.RESET_UPON_TC ("TRUE"),//Reset counter upon terminal count, "TRUE" or "FALSE"
//.TC_VALUE (18'h3eef8), // Terminal count value
// .TC_VALUE (18'h3eff8), // Terminal count value
//.TC_VALUE (18'h2edf8), // Terminal count value for iCE40HX1K
.TC_VALUE (18'he579), // Terminal count value for iCE40LP384
.WIDTH_DATA (18) // Counter output bus width, 1-48
) counter1 (
.Q (addr), // Counter output bus, width determined by WIDTH_DATA parameter
.TC (counted_to_the_end), // 1-bit terminal count output, high = terminal count is reached
.CLK (~REFCLK), // 1-bit positive edge clock input
// .CE (pix_stb & divided & sending), // 1-bit active high clock enable input
.CE (sending), // 1-bit active high clock enable input
.RST (resetting) // 1-bit active high synchronous reset
);
assign reprogrammer_enable = ~counted_to_the_end;
// TODO: wait 49 SPI_SCK cycles after receiving the CDONE signal
wire output_data;
wire output_clock = sending & sending_normal_sending_mode & REFCLK & (addr != 18'b0); // divided;
// RamSource ram_source (.i_clock (GCLK100), .i_reset (resetting), .i_enable (sending_normal_sending_mode), .i_address (addr), .o_data (output_data));
/*
reg output_data_reg = 1'b0;
always @(posedge REFCLK)
begin
output_data_reg <= #4 output_data;
end
*/
// RamSource ram_source (.i_clock (GCLK100), .i_reset (1'b0), .i_enable (sending_normal_sending_mode), .i_address (addr), .o_data (output_data)); // was working recently
RamSource ram_source (.i_clock (~REFCLK), .i_reset (1'b0), .i_enable (sending_normal_sending_mode | bitstream_write_enable),
.i_address (bitstream_write_enable ? bitstream_write_addr : addr),
.o_data (output_data),
.i_data (bitstream_dibit),
.i_we (bitstream_write_enable)
);
/*
wire [7:0] block;
RamFile #(
.INIT_00 (256'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000),
.INIT_01 (256'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111),
.INIT_02 (256'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111),
.INIT_03 (256'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111),
) f0 (.i_clock (GCLK100), .i_reset (resetting), .i_enable (sending_normal_sending_mode), .i_address (addr[14:0]), .o_data (block[0]));
wire [2:0] block_address = addr[17:15];
assign output_data = block[ block_address ]; */
assign LED7 = output_data;
assign LED6 = output_clock;
assign LED5 = CDONE;
assign SPI_SS_B = sent; //~(reset | resetting | ready | sending | memory_clear_wait);
assign LED4 = SPI_SS_B & SPI_SO;
assign CRESET_B = ~resetting;
assign SPI_SCK = output_clock;
assign SPI_SI = output_data;
//assign SPI_SI = output_data_reg;
endmodule
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