Lattice iCEstick + ILI9225 display

readme.md

links and commands

Pinout: https://docs.google.com/spreadsheets/d/1QEWxRQcYXZ_-n6hW59Y_82jv4_ZzkEXvRMxwPaldgFA/edit?usp=sharing

icestick.pcf

# full iCEstick pinout:
# http://www.pighixxx.com/test/portfolio-items/icestick/

set_io CLK_pad 21

set_io FT2232H_GPIOL2_pad 1
set_io FT2232H_GPIOL1_pad 2
set_io FT2232H_GPIOL0_pad 3
set_io FT2232H_TMS_CS_pad 4
set_io FT2232H_TDO_DI_pad 7
set_io FT2232H_TDI_DO_pad 8
set_io FT2232H_TCK_SK_pad 9

set_io D1_pad 99
set_io D2_pad 98
set_io D3_pad 97
set_io D4_pad 96
set_io D5_pad 95

set_io RXD_pad 106
set_io TXD_pad 105
set_io SD_pad 107

set_io J3_3_pad 62
set_io J3_4_pad 61

#set_io PMOD1_pad 78
#set_io PMOD2_pad 79
#set_io PMOD3_pad 80
#set_io PMOD4_pad 81
#set_io PMOD7_pad 87
#set_io PMOD8_pad 88
#set_io PMOD9_pad 90
#set_io PMOD10_pad 91

#set_io J1_3_pad 112
#set_io J1_4_pad 113
#set_io J1_5_pad 114
#set_io J1_6_pad 115
#set_io J1_7_pad 116
#set_io J1_8_pad 117
#set_io J1_9_pad 118
#set_io J1_10_pad 119

#set_io J3_5_pad 60
#set_io J3_6_pad 56
#set_io J3_7_pad 48
#set_io J3_8_pad 47
#set_io J3_9_pad 45
#set_io J3_10_pad 44

#set_io SPI_SDO_pad 67
#set_io SPI_SDI_pad 68
#set_io SPI_SCK_pad 70
#set_io SPI_SS_B_pad 71

top.v

	/*
	SB_HFOSC # (
		.CLKHF_DIV (2'b00)
	) osc_inst_0(
		.CLKHFEN (ENCLKHF),
		.CLKHFPU (CLKHF_POWERUP),
		.CLKHF (CLKHF)
	)  /* synthesis ROUTE_THROUGH_FABRIC=0 * /;

	
	SB_GB_IO # (
		.PIN_TYPE (6'b011000),
		.PULLUP (1'b1)

	) io_cell_13_9__1 (
		.PACKAGE_PIN (io_13_9__1_led4), // User’s Pin signal name
		.LATCH_INPUT_VALUE (latch_input_value), // Latches/holds the Input value
		.CLOCK_ENABLE (clock_enable), // Clock Enable common to input and output clock
		.INPUT_CLK (input_clk), // Clock for the input registers
		.OUTPUT_CLK (output_clk), // Clock for the output registers
		.OUTPUT_ENABLE (output_enable), // Output Pin Tristate/Enable control
		.D_OUT_0 (to_led), // Data 0 – out to Pin/Rising clk edge
		.D_OUT_1 (d_out_1), // Data 1 - out to Pin/Falling clk edge
		.D_IN_0 (d_in_0), // Data 0 - Pin input/Rising clk edge
		.D_IN_1 (d_in_1) // Data 1 – Pin input/Falling clk edge
		.GLOBAL_BUFFER_OUTPUT (Global_Buffered_User_Clock) // Example use – clock buffer
								//driven from the input pin
	);

	SB_LUT4 # (
		.LUT_INIT (16'b00000000_11110010)
	) rs1 (
		.O (Q), // output
		.I0 (Q), // data input 0
		.I1 (R), // data input 1
		.I2 (S), // data input 2
		.I3 (1'b0) // data input 3
	);

	SB_CARRY my_carry_inst (
		.CO (CO),
		.I0 (I0),
		.I1 (I1),
		.CI (CI));

	SB_DFFER ff1(
       	       .D (BTN),
       	       .C (CLK),
       	       .E (1'b1),
       	       .R (1'b0),
       	       .Q (line1));
*/


/*

Instantiation template:

	PIOPair # (
		.PIN_TYPE_0 (6'b000001),
		.PIN_TYPE_1 (6'b000001))
		
	io_pair_1 (

		.CLK_EN (), // Clock Enable common to input and output clock
		.OUT_CLK (),   // Clock for the output registers
		.IN_CLK (),    // Clock for the input registers

		.PAD_0 (),
		.PAD_1 (),

		// Output Pin Tristate/Enable control
		.OUT_EN_0 (),
		.OUT_EN_1 (),

		.LATCH_INPUT_VALUE_0 (),
		.LATCH_INPUT_VALUE_1 (),

		.D_OUT_0 (),
		.D_OUT_1 (),
		.D_OUT_DDR_0 (),
		.D_OUT_DDR_1 (),

		.D_IN_0 (),
		.D_IN_1 (),
		.D_IN_DDR_0 (),
		.D_IN_DDR_1 ()
	);

*/


module PIOPair # (
		parameter PIN_TYPE_0 = 6'b000001,
		parameter PIN_TYPE_1 = 6'b000001,
		parameter PULLUP_0 = 1'b0, // By default, the IO will have NO pull up. This parameter is used only on bank 0, 1, and 2. Ignored when it is placed at bank 3
		parameter PULLUP_1 = 1'b0 // By default, the IO will have NO pull up. This parameter is used only on bank 0, 1, and 2. Ignored when it is placed at bank 3
	) (
		input wire CLK_EN, // Clock Enable common to input and output clock
		input wire OUT_CLK,   // Clock for the output registers
		input wire IN_CLK,    // Clock for the input registers

		inout wire PAD_0,
		inout wire PAD_1,

		// Output Pin Tristate/Enable control
		input wire OUT_EN_0,
		input wire OUT_EN_1,

		input wire D_OUT_0,
		input wire D_OUT_1,
		input wire D_OUT_DDR_0,
		input wire D_OUT_DDR_1,

		output wire D_IN_0,
		output wire D_IN_1,
		output wire D_IN_DDR_0,
		output wire D_IN_DDR_1
	);

	SB_IO # (
		.PIN_TYPE (PIN_TYPE_0),
		.PULLUP (PULLUP_0),
		.NEG_TRIGGER (1'b0),
		.IO_STANDARD ("SB_LVCMOS")	// Other IO standards are supported in bank 3
						// only: SB_SSTL2_CLASS_2, SB_SSTL2_CLASS_1,
						// SB_SSTL18_FULL, SB_SSTL18_HALF, SB_MDDR10,
						// SB_MDDR8, SB_MDDR4, SB_MDDR2 etc.
	) io_0 (
		.PACKAGE_PIN (PAD_0),
		.LATCH_INPUT_VALUE (),
		.CLOCK_ENABLE (CLK_EN),
		.INPUT_CLK (IN_CLK),
		.OUTPUT_CLK (OUT_CLK),

		.OUTPUT_ENABLE (OUT_EN_0),
		.D_OUT_0 (D_OUT_0),
		.D_OUT_1 (D_OUT_DDR_0),
		.D_IN_0 (D_IN_0),
		.D_IN_1 (D_IN_DDR_0)
	);

	SB_IO # (
		.PIN_TYPE (PIN_TYPE_1),
		.PULLUP (PULLUP_1),
		.NEG_TRIGGER (1'b0),
		.IO_STANDARD ("SB_LVCMOS")
	) io_1 (
		.PACKAGE_PIN (PAD_1),
		.LATCH_INPUT_VALUE (),
		.CLOCK_ENABLE (CLK_EN),
		.INPUT_CLK (IN_CLK),
		.OUTPUT_CLK (OUT_CLK),

		.OUTPUT_ENABLE (OUT_EN_1),
		.D_OUT_0 (D_OUT_1),
		.D_OUT_1 (D_OUT_DDR_1),
		.D_IN_0 (D_IN_1),
		.D_IN_1 (D_IN_DDR_1)
	);
endmodule

module ArrowHead # (
		parameter INITIAL = 1'b0
	) (
		input wire IN,
		input wire CASC_STATE,
		output wire CASC_RESET,
		output wire STATE_OUT,
		input wire RESET_IN,
		output wire TX_HAPPENED,
		input wire CLOCK
	);

	reg state = INITIAL;
	reg TX_HAPPENED = 1'b0;
	always @(posedge CLOCK)
	begin
		state <= IN | (state & ~RESET_IN);
		TX_HAPPENED <= IN;
	end
	assign STATE_OUT = state | CASC_STATE;
	assign CASC_RESET = RESET_IN;

	//assign CASC_STATE = 1'b0;
	//assign CASC_RESET_TAIL = 1'b0;
endmodule

module ArrowTail (
		input wire STATE_IN,
		output wire RESET_OUT,
		input wire CASC_RESET_TAIL,
		output wire CASC_STATE_TAIL,
		output wire OUT,
		input wire EVENT
	);

	assign OUT = EVENT & ~CASC_RESET_TAIL & STATE_IN;
	assign CASC_STATE_TAIL = STATE_IN;
	assign RESET_OUT = OUT | CASC_RESET_TAIL;
endmodule

// State with only 1 output and 0 inputs is always initial
module State_1_Output (
		input wire EVENT_0,
		output wire S_OUT_0,
		input wire CLOCK
	);
	wire head_STATE_OUT;
	wire head_RESET_IN;
	ArrowHead # (.INITIAL (1'b1)) head (
		.CASC_STATE (1'b0),
		.STATE_OUT (head_STATE_OUT),
		.RESET_IN (head_RESET_IN),
		.IN (1'b0),
		.CLOCK (CLOCK));

	ArrowTail tail (
		.EVENT (EVENT_0),
		.OUT (S_OUT_0),
		.STATE_IN (head_STATE_OUT),
		.RESET_OUT (head_RESET_IN),
		.CASC_RESET_TAIL (1'b0));
endmodule

module State_3_Inputs_2_Outputs (
		// From source states
		input wire S_IN_0,
		input wire S_IN_1,
		input wire S_IN_2,
		// Generated events when enters state
		output wire ON_IN_0,
		output wire ON_IN_1,
		output wire ON_IN_2,
		// Events to drive one of the outputs
		input wire EVENT_0,
		input wire EVENT_1,
		// To destination states
		output wire S_OUT_0,
		output wire S_OUT_1,
		input wire CLOCK
	);

	wire 	head_0_STATE_OUT,
		head_0_RESET_IN,
		head_1_STATE_OUT,
		head_1_RESET_IN,
		head_2_STATE_OUT,
		head_2_RESET_IN,
		tail_0_CASC_STATE_TAIL,
		tail_0_CASC_RESET_TAIL;

	ArrowHead head_0 (
		.IN (S_IN_0),
		.TX_HAPPENED (ON_IN_0),
		.CASC_STATE (1'b0),
		.STATE_OUT (head_0_STATE_OUT),
		.RESET_IN (head_0_RESET_IN),
		.CLOCK (CLOCK));
	ArrowHead head_1 (
		.IN (S_IN_1),
		.TX_HAPPENED (ON_IN_1),
		.STATE_OUT (head_1_STATE_OUT),
		.RESET_IN (head_1_RESET_IN),
		.CASC_STATE (head_0_STATE_OUT),
		.CASC_RESET (head_0_RESET_IN),
		.CLOCK (CLOCK));
	ArrowHead head_2 (
		.IN (S_IN_2),
		.TX_HAPPENED (ON_IN_2),
		.STATE_OUT (head_2_STATE_OUT),
		.RESET_IN (head_2_RESET_IN),
		.CASC_STATE (head_1_STATE_OUT),
		.CASC_RESET (head_1_RESET_IN),
		.CLOCK (CLOCK));

	ArrowTail tail_0 (
		.EVENT (EVENT_0),
		.OUT (S_OUT_0),
		.CASC_STATE_TAIL (tail_0_CASC_STATE_TAIL),
		.CASC_RESET_TAIL (tail_0_CASC_RESET_TAIL),
		.STATE_IN (head_2_STATE_OUT),
		.RESET_OUT (head_2_RESET_IN));

	ArrowTail tail_1 (
		.EVENT (EVENT_1),
		.OUT (S_OUT_1),
		.STATE_IN (tail_0_CASC_STATE_TAIL),
		.RESET_OUT (tail_0_CASC_RESET_TAIL),
		.CASC_RESET_TAIL (1'b0));
endmodule


module State_1_Input_1_Output (
		// From source states
		input wire S_IN_0,
		// Generated events when enters state
		output wire ON_IN_0,
		// Events to drive one of the outputs
		input wire EVENT_0,
		// To destination states
		output wire S_OUT_0,
		input wire CLOCK
	);

	wire head_0_STATE_OUT, head_0_RESET_IN;

	ArrowHead head_0 (
		.IN (S_IN_0),
		.TX_HAPPENED (ON_IN_0),
		.STATE_OUT (head_0_STATE_OUT),
		.RESET_IN (head_0_RESET_IN),
		.CASC_STATE (1'b0),
		.CLOCK (CLOCK));

	ArrowTail tail_0 (
		.EVENT (EVENT_0),
		.OUT (S_OUT_0),
		.STATE_IN (head_0_STATE_OUT),
		.RESET_OUT (head_0_RESET_IN),
		.CASC_RESET_TAIL (1'b0));
endmodule


module top (
		inout CLK_pad,

		inout wire FT2232H_GPIOL2_pad,
		inout wire FT2232H_GPIOL1_pad,
		inout wire FT2232H_GPIOL0_pad,
		inout wire FT2232H_TMS_CS_pad,
		inout wire FT2232H_TDO_DI_pad,
		inout wire FT2232H_TDI_DO_pad,
		inout wire FT2232H_TCK_SK_pad,

		inout wire D1_pad,
		inout wire D2_pad,
		inout wire D3_pad,
		inout wire D4_pad,
		inout wire D5_pad,

		inout wire RXD_pad,
		inout wire TXD_pad,
		inout wire SD_pad,

		inout wire J3_3_pad,
		inout wire J3_4_pad
/*
		inout wire PMOD1_pad,
		inout wire PMOD2_pad,
		inout wire PMOD3_pad,
		inout wire PMOD4_pad,
		inout wire PMOD7_pad,
		inout wire PMOD8_pad,
		inout wire PMOD9_pad,
		inout wire PMOD10_pad,

		inout wire J1_3_pad,
		inout wire J1_4_pad,
		inout wire J1_5_pad,
		inout wire J1_6_pad,
		inout wire J1_7_pad,
		inout wire J1_8_pad,
		inout wire J1_9_pad,
		inout wire J1_10_pad,

		inout wire J3_5_pad,
		inout wire J3_6_pad,
		inout wire J3_7_pad,
		inout wire J3_8_pad,
		inout wire J3_9_pad,
		inout wire J3_10_pad,

		inout wire SPI_SDO_pad,
		inout wire SPI_SDI_pad,
		inout wire SPI_SCK_pad,
		inout wire SPI_SS_B_pad */
	);

	wire GBUF6;

	SB_GB_IO # (
		.PIN_TYPE (6'b000011),
		.PULLUP (1'b0),
		.NEG_TRIGGER (1'b0),
		.IO_STANDARD ("SB_LVCMOS")
	) io_00_08_1 (

		.CLOCK_ENABLE (),
		.INPUT_CLK (), // Clock for the input registers
		.OUTPUT_CLK (), // Clock for the output registers

		.PACKAGE_PIN (CLK_pad),

		.LATCH_INPUT_VALUE (1'b1),
		.OUTPUT_ENABLE (),

		.D_OUT_0 (), .D_OUT_1 (),
		.D_IN_0 (), .D_IN_1 (),

		.GLOBAL_BUFFER_OUTPUT (GBUF6)
	);

	// 18 full IO pairs with individual
	// CLOCK_ENABLE, OUTPUT_CLK, and INPUT_CLK signals
	// 8 half-pairs using SB_GB_IO and SB_IO

	// FT2232H MPSSE mode uses 7 wires connected to 4 IO tiles:
	//   3 inouts GPIOL2, GPIOL1, GPIOL0
	//   3 inputs TMS_CS, TDI_DO, TCK_SK,
	//   1 output TDO_DI,

	wire FT2232H_GPIOL2_in, FT2232H_GPIOL1_in, FT2232H_GPIOL0_in;
	wire FT2232H_GPIOL2_in_ddr, FT2232H_GPIOL1_in_ddr, FT2232H_GPIOL0_in_ddr;

	wire FT2232H_GPIOL2_OUT_EN, FT2232H_GPIOL1_OUT_EN, FT2232H_GPIOL0_OUT_EN;
	wire FT2232H_GPIOL2_out, FT2232H_GPIOL1_out, FT2232H_GPIOL0_out;
	wire FT2232H_GPIOL2_out_ddr, FT2232H_GPIOL1_out_ddr, FT2232H_GPIOL0_out_ddr;

	wire FT2232H_TMS_CS_in, FT2232H_TDI_DO_in, FT2232H_TCK_SK_in;
	wire FT2232H_TMS_CS_in_ddr, FT2232H_TDI_DO_in_ddr, FT2232H_TCK_SK_in_ddr;

	wire FT2232H_TDO_DI_OUT_EN;
	wire FT2232H_TDO_DI_out;
	wire FT2232H_TDO_DI_out_ddr;

	wire FT2232H_CLK_EN;

	// Full IO
	PIOPair # (
		.PIN_TYPE_0 (6'b110000),
		.PIN_TYPE_1 (6'b110000)
	) pio_0_14 (
		.CLK_EN (FT2232H_CLK_EN), // Clock Enable common to input and output clock
		.OUT_CLK (GBUF6),   // Clock for the output registers
		.IN_CLK (GBUF6),    // Clock for the input registers

		.PAD_0 (FT2232H_GPIOL1_pad),
		.PAD_1 (FT2232H_GPIOL2_pad),

		// Output Pin Tristate/Enable control
		.OUT_EN_0 (FT2232H_GPIOL1_OUT_EN),
		.OUT_EN_1 (FT2232H_GPIOL2_OUT_EN),

		.D_OUT_0 (FT2232H_GPIOL1_out),
		.D_OUT_1 (FT2232H_GPIOL2_out),
		.D_OUT_DDR_0 (FT2232H_GPIOL1_out_ddr),
		.D_OUT_DDR_1 (FT2232H_GPIOL1_out_ddr),

		.D_IN_0 (FT2232H_GPIOL1_in),
		.D_IN_1 (FT2232H_GPIOL2_in),
		.D_IN_DDR_0 (FT2232H_GPIOL1_in_ddr),
		.D_IN_DDR_1 (FT2232H_GPIOL2_in_ddr)
	);

	// A half pair is full IO, a half pair is input only
	PIOPair # (
		.PIN_TYPE_0 (6'b000000),
		.PIN_TYPE_1 (6'b110000)
	) pio_0_13 (
		.CLK_EN (FT2232H_CLK_EN), // Clock Enable common to input and output clock
		.OUT_CLK (GBUF6),   // Clock for the output registers
		.IN_CLK (GBUF6),    // Clock for the input registers

		.PAD_0 (FT2232H_TMS_CS_pad),
		.PAD_1 (FT2232H_GPIOL0_pad),

		// Output Pin Tristate/Enable control
		.OUT_EN_0 (1'b0),
		.OUT_EN_1 (FT2232H_GPIOL0_OUT_EN),

		.D_OUT_0 (),
		.D_OUT_1 (FT2232H_GPIOL0_out),
		.D_OUT_DDR_0 (),
		.D_OUT_DDR_1 (FT2232H_GPIOL0_out_ddr),

		.D_IN_0 (FT2232H_TMS_CS_in),
		.D_IN_1 (FT2232H_GPIOL0_in),
		.D_IN_DDR_0 (FT2232H_TMS_CS_in_ddr),
		.D_IN_DDR_1 (FT2232H_GPIOL0_in_ddr)
	);


	// 1 input 1 output tile
	PIOPair # (
		.PIN_TYPE_0 (6'b000000),
		.PIN_TYPE_1 (6'b110000)
	) pio_0_12 (
		.CLK_EN (FT2232H_CLK_EN), // Clock Enable common to input and output clock
		.OUT_CLK (GBUF6),   // Clock for the output registers
		.IN_CLK (GBUF6),    // Clock for the input registers

		.PAD_0 (FT2232H_TDI_DO_pad),
		.PAD_1 (FT2232H_TDO_DI_pad),

		// Output Pin Tristate/Enable control
		.OUT_EN_0 (1'b0),
		.OUT_EN_1 (FT2232H_TDO_DI_OUT_EN),

		.D_OUT_0 (),
		.D_OUT_1 (FT2232H_TDO_DI_out),
		.D_OUT_DDR_0 (),
		.D_OUT_DDR_1 (FT2232H_TDO_DI_out_ddr),

		.D_IN_0 (FT2232H_TDI_DO_in),
		.D_IN_1 (),
		.D_IN_DDR_0 (FT2232H_TDI_DO_in_ddr),
		.D_IN_DDR_1 ()
	);

	// Input only
	SB_IO # (
		.PIN_TYPE (6'b000000), // no out, in DDR
		.PULLUP (1'b0),
		.NEG_TRIGGER (1'b0),
		.IO_STANDARD ("SB_LVCMOS")
	) io_00_11_1 (

		.CLOCK_ENABLE (FT2232H_CLK_EN),
		.INPUT_CLK (GBUF6), // Clock for the input registers
		.OUTPUT_CLK (), // Clock for the output registers

		.PACKAGE_PIN (FT2232H_TCK_SK_pad),

		.LATCH_INPUT_VALUE (),
		.OUTPUT_ENABLE (),
		.D_OUT_0 (), .D_OUT_1 (),

		.D_IN_0 (FT2232H_TCK_SK_in),
		.D_IN_1 (FT2232H_TCK_SK_in_ddr)
	);


	wire D1_OUT_EN;
	wire D2_OUT_EN;
	wire D3_OUT_EN;
	wire D4_OUT_EN;
	wire D5_OUT_EN;

	wire D1_top_red;
	wire D2_right_red;
	wire D3_bottom_red;
	wire D4_left_red;
	wire D5_center_green;

	wire LED_CLK_EN;

	// 2 outputs tile
	PIOPair # (
		.PIN_TYPE_0 (6'b110111),
		.PIN_TYPE_1 (6'b110111)
	) pio_13_11 (
		.CLK_EN (LED_CLK_EN),
		.OUT_CLK (GBUF6),
		.IN_CLK (),

		.PAD_0 (D4_pad),
		.PAD_1 (D3_pad),

		// Output Pin Tristate/Enable control
		.OUT_EN_0 (D4_OUT_EN),
		.OUT_EN_1 (D3_OUT_EN),

		.D_OUT_0 (D4_left_red),
		.D_OUT_1 (D3_bottom_red),
		.D_OUT_DDR_0 (), .D_OUT_DDR_1 (), .D_IN_0 (), .D_IN_1 (), .D_IN_DDR_0 (), .D_IN_DDR_1 ()
	);

	// 2 outputs tile
	PIOPair # (
		.PIN_TYPE_0 (6'b110111),
		.PIN_TYPE_1 (6'b110111)
	) pio_13_12 (
		.CLK_EN (LED_CLK_EN),
		.OUT_CLK (GBUF6),
		.IN_CLK (),

		.PAD_0 (D2_pad),
		.PAD_1 (D1_pad),

		// Output Pin Tristate/Enable control
		.OUT_EN_0 (D2_OUT_EN),
		.OUT_EN_1 (D1_OUT_EN),

		.D_OUT_0 (D2_right_red),
		.D_OUT_1 (D1_top_red),
		.D_OUT_DDR_0 (), .D_OUT_DDR_1 (), .D_IN_0 (), .D_IN_1 (), .D_IN_DDR_0 (), .D_IN_DDR_1 ()
	);

	// Output only
	SB_IO # (
		.PIN_TYPE (6'b110111), // output reg, en reg; input latch
		.PULLUP (1'b0),
		.NEG_TRIGGER (1'b0),
		.IO_STANDARD ("SB_LVCMOS")
	) io_13_09_1 (

		.CLOCK_ENABLE (LED_CLK_EN),
		.INPUT_CLK (), // Clock for the input registers
		.OUTPUT_CLK (GBUF6), // Clock for the output registers

		.PACKAGE_PIN (D5_pad),

		.LATCH_INPUT_VALUE (1'b1),
		.OUTPUT_ENABLE (D5_OUT_EN),
		.D_OUT_0 (D5_center_green),
		.D_OUT_1 (), .D_IN_0 (), .D_IN_1 ()
	);

	// reg en_led = 1'b1;
	assign LED_CLK_EN = 1'b1; //en_led;

	//reg green_led_out_en = 1'b1;
	//assign D5_OUT_EN = green_led_out_en;

	//reg green_led = 1'b1;
	//assign D5_center_green = green_led;


	wire RXD_in;
	wire RXD_in_ddr;

	wire TXD_out;
	wire TXD_out_ddr;
	wire TXD_OUT_EN;

	wire SD_out;
	wire SD_OUT_EN;

	wire IR_CLK_EN;

	// 1 input 1 output tile
	PIOPair # (
		.PIN_TYPE_0 (6'b000000),
		.PIN_TYPE_1 (6'b110111)
	) pio_13_15 (
		.CLK_EN (IR_CLK_EN), // Clock Enable common to input and output clock
		.OUT_CLK (GBUF6),   // Clock for the output registers
		.IN_CLK (GBUF6),    // Clock for the input registers

		.PAD_0 (RXD_pad),
		.PAD_1 (SD_pad),

		// Output Pin Tristate/Enable control
		.OUT_EN_0 (1'b0),
		.OUT_EN_1 (SD_OUT_EN),

		.D_OUT_0 (),
		.D_OUT_1 (SD_out),
		.D_OUT_DDR_0 (), .D_OUT_DDR_1 (),

		.D_IN_0 (RXD_in),
		.D_IN_1 (),
		.D_IN_DDR_0 (RXD_in_ddr),
		.D_IN_DDR_1 ()
	);

	// 1 output tile
	SB_IO # (
		.PIN_TYPE (6'b110000),
		.PULLUP (1'b0),
		.NEG_TRIGGER (1'b0),
		.IO_STANDARD ("SB_LVCMOS")
	) io_13_14_1 (

		.CLOCK_ENABLE (IR_CLK_EN),
		.INPUT_CLK (), // Clock for the input registers
		.OUTPUT_CLK (GBUF6), // Clock for the output registers

		.PACKAGE_PIN (TXD_pad),

		.LATCH_INPUT_VALUE (1'b1),
		.OUTPUT_ENABLE (TXD_OUT_EN),
		.D_OUT_0 (TXD_out),
		.D_OUT_1 (TXD_out_ddr),
		.D_IN_0 (), .D_IN_1 ()
	);

	assign IR_CLK_EN = 1'b1;
	assign SD_OUT_EN = 1'b1;
	assign TXD_OUT_EN = 1'b1;

	// Enable receiving mode
	assign SD_out = 1'b0;
	assign TXD_out = 1'b0;


	//assign D4_left_red = ~RXD_in;
	// assign D3_bottom_red = ~RXD_in_ddr;

	assign D1_OUT_EN = 1'b1;
	assign D2_OUT_EN = 1'b1;
	assign D3_OUT_EN = 1'b1;
	assign D4_OUT_EN = 1'b1;
	assign D5_OUT_EN = 1'b1;

	// assign D1_top_red = RXD_in ^ RXD_in_ddr;

	wire EVENT_E;//, EVENT_D;

	wire D1_top_red;
	wire D2_right_red;
	reg D3_bottom_red = 1'b0;
	reg D4_left_red = 1'b0;
	wire D5_center_green;

	assign EVENT_E = RXD_in ^ RXD_in_ddr;
	// assign EVENT_D = ;

	/*
	wire	state_i_S_OUT_0,
		state_b_S_OUT_0,
		state_c_S_OUT_0,
		state_c2_S_OUT_0,
		state_c3_S_OUT_0,
		state_b_S_IN_0,
		state_c_S_IN_0,
		state_c2_S_IN_0,
		state_c3_S_IN_0;

	State_1_Output state_i (
		.EVENT_0 (EVENT_E),
		.S_OUT_0 (state_i_S_OUT_0),
		.CLOCK (GBUF6));

	State_1_Input_1_Output state_b (
		.ON_IN_0 (D4_left_red),
		.EVENT_0 (EVENT_E),
		.S_IN_0 (state_b_S_IN_0),
		.S_OUT_0 (state_b_S_OUT_0),
		.CLOCK (GBUF6));

	wire entered_c, entered_c2;
	State_1_Input_1_Output state_c (
		.ON_IN_0 (entered_c),
		.EVENT_0 (EVENT_E),
		.S_IN_0 (state_c_S_IN_0),
		.S_OUT_0 (state_c_S_OUT_0),
		.CLOCK (GBUF6));
	State_1_Input_1_Output state_c2 (
		.ON_IN_0 (entered_c2),
		.EVENT_0 (EVENT_E),
		.S_IN_0 (state_c_S_OUT_0),
		.S_OUT_0 (state_c2_S_OUT_0),
		.CLOCK (GBUF6));
	State_1_Input_1_Output state_c3 (
		.ON_IN_0 (D5_center_green),
		.EVENT_0 (EVENT_E),
		.S_IN_0 (state_c2_S_OUT_0),
		.S_OUT_0 (state_c3_S_OUT_0),
		.CLOCK (GBUF6));

	State_3_Inputs_2_Outputs state_a (
		.S_IN_0 (state_b_S_OUT_0),
		.S_IN_1 (state_i_S_OUT_0),
		.S_IN_2 (state_c3_S_OUT_0),

		.ON_IN_0 (EVENT_D),
		.ON_IN_1 (D2_right_red),
		.ON_IN_2 (D3_bottom_red),

		.EVENT_0 (EVENT_E),
		.EVENT_1 (EVENT_D),

		.S_OUT_0 (state_b_S_IN_0),
		.S_OUT_1 (state_c_S_IN_0),
		.CLOCK (GBUF6));
	*/
        reg state_i = 1'b1, state_a = 1'b0, state_b = 1'b0, state_c = 1'b0, state_c2 = 1'b0, state_c3 = 1'b0;

        reg EVENT_D = 1'b0; // generated event on entering "a" from "b" on event "E"

        always @(posedge GBUF6)
	begin
		if (state_i & EVENT_E) begin
			state_i <= 1'b0; // ~state_i;
			state_a <= 1'b1; // state_i;
		end

		if (state_a & EVENT_E) begin
			state_a <= 1'b0; // ~state_a;
			state_b <= 1'b1; // state_a;
			// on enter: generated event
			D4_left_red <= 1'b1; // ~D4_left_red;
		end

		if (state_a & EVENT_D) begin
			state_a <= 1'b0; // ~state_a;
			state_c <= 1'b1; // state_a;
		end

		if (state_c & EVENT_E) begin
			state_c <= 1'b0; // ~state_c;
			state_c2 <= 1'b1; // state_c;
		end

		if (state_c2 & EVENT_E) begin
			state_c2 <= 1'b0; // ~state_c2;
			state_c3 <= 1'b1; // state_c2;
		end

		if (state_c3 & EVENT_E) begin
			state_c3 <= 1'b0; // ~state_c3;
			state_a <= 1'b1; // state_c3;
			D3_bottom_red <= 1'b1; // ~D3_bottom_red;
		end

		if (state_b & EVENT_E) begin
			state_b <= 1'b0; // ~state_b;
			state_a <= 1'b1; // state_b;
			EVENT_D <= 1'b1;
		end

		// reset all generated events so they last only one clock cycle

		if (D4_left_red) D4_left_red <= 1'b0; // ~D4_left_red;
		if (EVENT_D) EVENT_D <= 1'b0; // ~EVENT_D;
		if (D3_bottom_red) D3_bottom_red <= 1'b0; // ~D3_bottom_red;
	end

	reg top_circle = 1'b0;
	reg bottom_circle = 1'b0;
	always @(posedge GBUF6)
	begin
		if (D4_left_red || EVENT_D)
		begin
			top_circle <= 1'b1;
			bottom_circle <= 1'b0;
		end
		// else if (entered_c || entered_c2 || D5_center_green || D3_bottom_red)
		else if (state_c || state_c2 || state_c3 || D3_bottom_red)
		begin
			top_circle <= 1'b0;
			bottom_circle <= 1'b1;
		end
	end
	assign D1_top_red = top_circle;


	//assign STATE_IN = STATE_OUT;
	//assign RESET_IN = RESET_OUT;
	//assign IN = OUT;
	//assign EVENT = D1_top_red;
	//assign D3_bottom_red = TX_HAPPENED;

	wire LCD_RST_OUT_EN = 1'b1;
	wire LCD_LED_OUT_EN = 1'b1;

	reg LCD_RST = 1'b1;
	// reg LCD_LED = 1'b0;
	wire LCD_LED = ~bottom_circle;

	// 2 outputs tile: RST & LED
	PIOPair # (
		.PIN_TYPE_0 (6'b110111),
		.PIN_TYPE_1 (6'b110111)
	) pio_09_00 (
		.CLK_EN (LED_CLK_EN),
		.OUT_CLK (GBUF6),
		.IN_CLK (),

		.PAD_0 (J3_4_pad),
		.PAD_1 (J3_3_pad),

		// Output Pin Tristate/Enable control
		.OUT_EN_0 (LCD_RST_OUT_EN),
		.OUT_EN_1 (LCD_LED_OUT_EN),

		.D_OUT_0 (LCD_RST),
		.D_OUT_1 (LCD_LED),
		.D_OUT_DDR_0 (), .D_OUT_DDR_1 (), .D_IN_0 (), .D_IN_1 (), .D_IN_DDR_0 (), .D_IN_DDR_1 ()
	);



	// Eventful statechart formalism for reactive computing of Boolean logic functions
	wire C_T, C_S, A_T, A_S, B_T, B_S;
	reg [2:0] state = 0;
	reg M_S = 0;
	reg M_T = 0;
	always @(posedge GBUF6) begin
		if (state == 0) begin
			if (C_S | A_S | B_S) M_S <= 1;
			if (A_T) begin state[1] <= 1; M_S <= 1; end
			if (B_T) begin state[2] <= 1; M_T <= 
	end

/*
	inout wire PMOD1;
	inout wire PMOD2;
	inout wire PMOD3;
	inout wire PMOD4;
	inout wire PMOD7;
	inout wire PMOD8;
	inout wire PMOD9;
	inout wire PMOD10;


	inout wire J1_3;
	inout wire J1_4;
	inout wire J1_5;
	inout wire J1_6;
	inout wire J1_7;
	inout wire J1_8;
	inout wire J1_9;
	inout wire J1_10;

	inout wire J3_5;
	inout wire J3_6;
	inout wire J3_7;
	inout wire J3_8;
	inout wire J3_9;
	inout wire J3_10;

	inout wire SPI_SDO;
	inout wire SPI_SDI;
	inout wire SPI_SCK;
	inout wire SPI_SS_B;
*/

endmodule