lab4 - seven segment decoder -- almost passed of...

lab4_seven_seg.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:21:01 01/29/2014 
-- Design Name: 
-- Module Name:    SevenSeg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity seven_segment_display is
	 
	 generic(
		COUNTER_BITS : natural := 16
	 );
    
	 Port ( 
			clk : in  STD_LOGIC;
			data_in : in std_logic_vector(15 downto 0);
			dp_in, blank : in std_logic_vector(3 downto 0);
			seg : out std_logic_vector(6 downto 0);
			dp : out std_logic;
			an : out std_logic_vector(3 downto 0)
	 );
	 
end seven_segment_display;

architecture Behavioral of seven_segment_display is

--signal r_next, r_reg : std_logic_vector(3 downto 0);
signal q_next, q_reg : unsigned(COUNTER_BITS-1 downto 0) := to_unsigned(0,COUNTER_BITS);
signal anode_select : std_logic_vector(1 downto 0);
signal an_intermediate : std_logic_vector(3 downto 0);

--signal data_mux_out : std_logic_vector(3 downto 0); --input into decoder

signal decoder_input : std_logic_vector(3 downto 0) := (others => '0');
signal dp_temp : std_logic;

begin

process(clk)
begin
	if clk'event and clk='1' then
		q_reg<=q_next;
	end if;
end process;

--next state logic
q_next <= q_reg + 1;


--which anode to assert?
anode_select <= 	std_logic_vector( q_reg(COUNTER_BITS-1 downto COUNTER_BITS-2) );
	

an_intermediate <= 	"1110" when anode_select = "00" else --anode 0 asserted for valus 00000000 thru 00111111
							"1101" when anode_select = "01" else				  
							"1011" when anode_select = "10" else
							"0111";	
--or with blank because when blank is high anode should NOT be asserted.							
an <= an_intermediate or blank(3 downto 0); --when blank is high, anode shouldn't be asserted.


--data_mux_out is wired into the seven_seg_decoder
with anode_select select decoder_input <=
	data_in(3 downto 0) when "00",
	data_in(7 downto 4) when "01",
	data_in(11 downto 8) when "10",
	data_in(15 downto 12) when others;


--assign segment output when decoder input.
with decoder_input select seg <=
	 "1000000" when "0000",
	 "1111001" when "0001", --the digit '1', note 0 means that the cathode is asserted high.
	 "0100100" when "0010",
	 "0110000" when "0011",
	 "0011001" when "0100",
	 "0010010" when "0101",
	 "0000010" when "0110",
	 "1111000" when "0111",
	 "0000000" when "1000",
	 "0010000" when "1001",
	 "0001000" when "1010",
	 "0000011" when "1011",
	 "1000110" when "1100",
	 "0100001" when "1101",
	 "0000110" when "1110",
	 "0001110" when others;

	 --"" when "",
	 
 


--dp multiplexer
with anode_select select dp <=
	not ( dp_in(0) ) when "00",
	not ( dp_in(1) ) when "01",
	not ( dp_in(2) ) when "10",
	not ( dp_in(3) ) when others;




end Behavioral;