hw4 ECEn 320

hw.vhd

--
-- Lecture 9 Problem #1
-- 8.3
-- 	Alex Spencer.
--

library IEEE;
use IEEE.numeric_std.all;
use ieee.std_logic_1164.all;

entity eight_3 is 

port(
	j, k, clk, reset : in std_logic;
	q : out std_logic
);


end eight_3;

architecture eight_3_arch of eight_3 is
	signal q_next,q_reg : std_logic;
begin

	process(clk,reset)
	begin
	
		if(reset = '1') then
			q_reg <= '0';
		elsif(clk'event and clk='1') then
			q_reg <= q_next;
		end if;
	
	end process;

	--logic..
	q_next <=   q_reg when (j='0' and k='0') else
				'0' when (j='0' and k='1') else
				'1' when (j='1' and k='0') else
				not(q_reg);
	
	q <= q_reg; -- output is reg signal.

end eight_3_arch;



--
-- Lecture 9 problem #2
-- 	Alex Spencer.
--

library IEEE;
use IEEE.numeric_std.all;
use ieee.std_logic_1164.all;

entity eight_3 is 

port(
	j, k, clk, reset : in std_logic;
	q : out std_logic
);


end eight_3;

architecture eight_3_arch of eight_3 is
	signal q_next,q_reg : std_logic;
begin

	process(clk,reset)
	begin
	
		if(clk'event and reset='1' and clk='0') then --synchronous reset.
			q_reg <= '0';
		elsif(clk'event and clk='0') then --negative edge triggered.
			q_reg <= q_next;
		end if;
	
	end process;

	q_next <=   q_reg when (t='0') else
				not(q_reg);
	
	q <= q_reg; 

end eight_3_arch;




--
-- Lecture 10 problem #1
-- Book problem 8.5
-- Alex Spencer
--

library ieee;
use ieee.std_logic_1164.all;

entity eight_5 is
	port(
		clk, reset : in std_logic;
		ctrl : in std_logic_vector(2 downto 0);
		d : in std_logic_vector(3 downto 0);
		q : out std_logic_vector(3 downto 0)
	);
end eight_5;

architecture behav_eight_5 of eight_5 is
	signal r_reg, r_next : std_logic_vector(3 downto 0);
begin
	process(clk,reset)
	begin
		if(reset = '1') then
			r_reg <= (others=>'0');
		elsif(clk'event and clk='1') then
			r_reg <= r_next;
		end if;
		
	end process;

	--next state

	with ctrl select 
		r_next <= 
			r_reg when "000",
			r_reg(2 downto 0)&d(0) when "001",
			d(3)&r_reg(3 downto 1) when "010",
			r_reg(2 downto 0)&r_reg(3) when "011",
			r_reg(0)&r_reg(3 downto 1) when "100",
			d when others;
	
	q <= q_reg;
	
end behav_eight_5;






--
-- Lecture 10 problem #2
-- Book problem 8.7
-- Alex Spencer
--

library ieee;
use ieee.std_logic_1164.all;

entity eight_7 is
	port(
		clk, reset : in std_logic;
		ctrl : in std_logic_vector(2 downto 0);
		q : out std_logic_vector(3 downto 0);
		decode_out : out std_logic_vector(2 downto 0)
	);
end eight_7;

architecture behav of eight_7 is
	signal q_reg, q_next : unsigned(3 downto 0);
begin
	process(clk,reset)
	begin
		if(reset = '1') then
			q_reg <= (others=>'0');
		elsif(clk'event and clk='1') then
			q_reg <= q_next;
		end if;
		
	end process;

	--next state

	with q_reg select 
		q_next <= 
			"0011" when "0000" or "0001" or "0010" or "1100" or "1101" or "1110" or "1111",
			q_reg +1 when others;
	q <= q_reg;
	
end eight_7;


--
-- Lecture 10 problem #3
-- Book problem 8.8
-- Alex Spencer
--

library ieee;
use ieee.std_logic_1164.all;

entity eight_8 is
	port(
		clk, reset : in std_logic;
		ctrl : in std_logic_vector(2 downto 0);
		q : out std_logic_vector(3 downto 0)
	);
end eight_8;

architecture behav of eight_8 is
	signal q_reg, q_next : unsigned(3 downto 0);
begin

	--reg with mod 5 counter.
	process(clk,reset)
	begin
		if(reset = '1') then
			q_reg <= (others=>'0');
		elsif(clk'event and clk='1' and q_reg < 4) then
			q_reg <= q_reg+1;
		elseif(clk'event and clk='1' and q_reg = 4) then
			q_reg = (others=>'0'); --reset mod 4 counter.
		end if;
		
	end process;

	--decoder
	with q select 
		decode_out <= 
			"000" when "000",
			"011" when "001",
			"110" when "010",
			"101" when "011",
			"111" when others; --100
	
	q <= q_reg;
	
end eight_8;



--
-- Lecture 10 problem #4
-- Book problem 8.10
-- Alex Spencer
--

library ieee;
use ieee.std_logic_1164.all;

entity eight_10 is
	port(
		clk, reset : in std_logic;
		ctrl : in std_logic_vector(2 downto 0);
		q : out std_logic_vector --1Hz signal with 50% duty cycle.
	);
end eight_10;

architecture behav of eight_10 is
	signal q_reg : unsigned(3 downto 0);
	signal one_hz_reg : std_logic;
begin

	--reg with mod 5 counter.
	process(clk,reset)
	begin
		if(reset = '1') then
			q_reg <= (others=>'0');
		elsif(clk'event and clk='1' and q_reg < 500000) then
			q_reg <= q_reg+1; --increment counter.
		elsif(clk'event and clk='1' and q_reg >= 500000) then
			q_reg = (others=>'0'); --1MHZ counter.
			if(one_hz_reg = 1) then --1Hz oscillating signal.
				one_hz_reg = '0'
			else
				one_hz_reg = '1';
			end if;
		end if;
		
	end process;

	q <= one_hz_reg;
	
end eight_10;