LAB5 - EE320 - passing test bench, holy hell.

gistfile1.vhdl

----------------------------------------------------------------------------------
-- Company: BYU
-- Engineer: ALEX SPENCER
-- Create Date:    14:29:00 02/04/2014 
-- Module Name:    vga_timing - Behavioral 
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity vga_timing is
	generic (
		COUNTER_BITS: natural := 15
	);
	port(
		clk 			: in std_logic;
		rst 			: in std_logic;
		HS				: out std_logic;
		VS				: out std_logic;
		pixel_x		: out std_logic_vector(9 downto 0);
		pixel_y		: out std_logic_vector(9 downto 0);
		last_column	: out std_logic;
		last_row		: out std_logic;
		blank			: out std_logic
	);
end vga_timing;

architecture arch_vga of vga_timing is

	signal r_reg			: std_logic:='0';
	signal r_next			: std_logic:='0';

	signal pixel_h_reg	: unsigned(9 downto 0):=(others=>'0');
	signal pixel_v_reg	: unsigned(9 downto 0):=(others=>'0');
	signal pixel_h_next	: unsigned(9 downto 0):=(others=>'0');
	signal pixel_v_next	: unsigned(9 downto 0):=(others=>'0');

	signal VS_reg, VS_next : std_logic :='0';
	signal HS_reg, HS_next : std_logic :='0';
	
	signal h_end			: std_logic:='0';
	signal v_end			: std_logic:='0';
	signal pixel_en 		: std_logic:='0';
	
begin

	process(clk,rst)
	begin
		if (rst='1') then
			r_reg <= '0';
			pixel_h_reg <= (others => '0');
			pixel_v_reg <= (others => '0');
			VS_reg <= '0';
			HS_reg <= '0';
		elsif (clk='1' and clk'event) then
			r_reg <= r_next;
			pixel_h_reg <= pixel_h_next;
			pixel_v_reg <= pixel_v_next;
--			VS_reg <= VS_next;
--			HS_reg <= HS_next;
		end if;
	end process;
	-- Horizontal Counter
	process(pixel_en, pixel_h_reg, h_end)
		begin
			if ( pixel_en = '1') then
				if ( h_end = '1') then
					pixel_h_next <= (others=>'0');
				else
					pixel_h_next <= pixel_h_reg + 1;
				end if;
			else
				pixel_h_next <= pixel_h_reg;
			end if;
	end process;
	
	-- Vertical Counter
	process(pixel_en, pixel_v_reg, h_end, v_end)
		begin
			if ( pixel_en = '1') AND (h_end='1') then
				if ( v_end = '1') then
					pixel_v_next <= (others=>'0');
				else
					pixel_v_next <= pixel_v_reg + 1;
				end if;
			else
				pixel_v_next <= pixel_v_reg;
			end if;
	end process;
		--25Mhz tick creation.
	r_next <= not r_reg; --50Mhz
	pixel_en <= '1' when (r_reg='1') else '0';
	
--	h_end 	<= '1' when pixel_h_reg = (639) else '0';
--	v_end 	<= '1' when pixel_v_reg = (479) and pixel_h_reg = (639) else '0';
	
	h_end 	<= '1' when pixel_h_reg = (799) else '0';
--	v_end 	<= '1' when pixel_v_reg = (479) and pixel_h_reg = (799) else '0';
	v_end 	<= '1' when pixel_v_reg = (520) else '0';
	
	last_row <= '1' when pixel_h_reg = (639) and pixel_h_reg = (799) else '0';
	last_column <= '1' when pixel_h_reg = (639) else '0';

--	HS_next <= '0' when (pixel_h_reg)< 799 else '1'; 
--	VS_next <= '0' when (pixel_v_reg)< 520 else '1'; 
	
--HS <= '0' when pixel_h_reg >= 656 and pixel_h_reg <
	
--	HS_next <= '1' when pixel_h_reg < 656 else
--					'0' when pixel_h_reg < 752 else
--					'1';
	HS <=  '0' when pixel_h_reg < 752 and pixel_h_reg >=656  else
					'1';
	
--	VS <= '1' when pixel_v_reg < 490 and pixel_h_reg = 799 else
--					'0' when pixel_v_reg < 492 and pixel_h_reg = 799 else
--					'1';
	VS <= '0' when pixel_v_reg >= 490 and pixel_v_reg < 492 else '1';
--	VS <= '0' when pixel_v_reg >= 508 and pixel_v_reg < 510 else '1';
--	VS <= '0' when pixel_v_reg >= 509 and pixel_v_reg < 511 else '1';
	
--	HS <= HS_reg;
--	VS <= VS_reg;
	
	blank <= '0' when (pixel_h_reg < 640) and (pixel_v_reg < 480) else '1';

	pixel_x <= std_logic_vector(pixel_h_reg);
	pixel_y <= std_logic_vector(pixel_v_reg);

end arch_vga;