Lab5 - VGA controller ECEn 320 -- top level, not working.

hello.vhd

----------------------------------------------------------------------------------
-- Company: BREGHM YENG UNEVERSETY
-- 
-- Create Date:    11:55:25 02/05/2014 
-- Design Name: 
-- Module Name:    TopLevelVGA - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TopLevelVGA is
	port(
	
		--mapped to component.
		clk 			: in std_logic;
--		rst 			: in std_logic;
		
		--hardware inputs
		sw : in std_logic_vector(7 downto 0);
		btn : in std_logic_vector(3 downto 0);
		
--		pixel_x		: in std_logic_vector(9 downto 0);
--		pixel_y		: in std_logic_vector(9 downto 0);
--		last_column	: in std_logic;
--		last_row		: in std_logic;
--		blank			: in std_logic;
		--outputs
		vgaRed	: out std_logic_vector(2 downto 0);
		vgaGreen	: out std_logic_vector(2 downto 0);
		vgaBlue	: out std_logic_vector(1 downto 0);
		signal Hsync : out std_logic;
		signal Vsync : out std_logic
	);
end TopLevelVGA;

architecture Behavioral of TopLevelVGA is
	--top level I/O
		signal red_wire	:  std_logic_vector(2 downto 0);
		signal green_wire	:  std_logic_vector(2 downto 0);
		signal blue_wire	:  std_logic_vector(1 downto 0);

		signal current_color : std_logic_vector(7 downto 0); --top three bits are red, next three are green, bottom 2 are blue.
		
		signal red_reg :  std_logic_vector(2 downto 0);
		signal green_reg :  std_logic_vector(2 downto 0);
		signal blue_reg :  std_logic_vector(1 downto 0);
		signal HS_reg : std_logic;
		signal VS_reg : std_logic;
		
	--vga I/O
		--inputs
		signal top_pixel_x		:  std_logic_vector(9 downto 0);
		signal top_pixel_y		:  std_logic_vector(9 downto 0);
		signal top_last_column	:  std_logic;
		signal top_last_row		:  std_logic;
		signal top_blank			:  std_logic; 
		signal top_rst				:	std_logic;
		--outputs	
		signal	top_HS					: std_logic;
		signal	top_VS					: std_logic;

--const's:
		constant BLACK		:	std_logic_vector(7 downto 0) := "11111111";
		constant BLUE		:	std_logic_vector(7 downto 0) := "11111111";
		constant GREEN		:	std_logic_vector(7 downto 0) := "11111111";
		constant CYAN		:	std_logic_vector(7 downto 0) := "11111111";
		constant RED		:	std_logic_vector(7 downto 0) := "11111111";
		constant MAGENTA	:	std_logic_vector(7 downto 0) := "11111111";
		constant YELLOW	:	std_logic_vector(7 downto 0) := "11111111";
		constant WHITE		:	std_logic_vector(7 downto 0) := "11111111";

	component vga_timing
		port(
			clk 			: in std_logic;
			rst 			: in std_logic;
			HS				: out std_logic;
			VS				: out std_logic;
			pixel_x		: out std_logic_vector(9 downto 0);
			pixel_y		: out std_logic_vector(9 downto 0);
			last_column	: out std_logic;
			last_row		: out std_logic;
			blank			: out std_logic
		);
	end component;

begin

--left is component, right is top level.
my_vga : vga_timing port map(
										clk=>clk,rst=>top_rst,HS=>top_HS,VS=>top_VS, 
										pixel_x=>top_pixel_x, pixel_y=>top_pixel_y,
										last_column=>top_last_column, last_row=>top_last_row,
										blank=>top_blank
									);

--reset with button 3
with btn select top_rst <=
		'0' when "0001", --btn0 pressed.
		'0' when "0010",
		'0' when "0100", --black display
		'1' when "1000",
		top_rst when others;
		
--red
with btn select red_wire <=
		current_color(7 downto 5) 		when "0001", --btn0 pressed. -> color bar.
		sw(7 downto 5) 					when "0010", --switches determine color
		"111" 								when "0100", --black display
		"XXX" 										when "1000",
		red_wire 							when others;
--green
with btn select green_wire <=
		current_color(4 downto 2) 		when "0001", --btn0 pressed.
		sw(4 downto 2) 					when "0010", --switches determine color
		"111" 								when "0100", --black display
		"XXX" 										when "1000",
		green_wire 							when others;
--blue
with btn select blue_wire <=
		current_color(1 downto 0)		when "0001", --btn0 pressed.
		sw(1 downto 0) 					when "0010", --switches determine color
		"11" 									when "0100",
		"XX" 										when "1000",
		blue_wire 							when others;

--choose color
current_color <= BLUE;
--with top_pixel_y select current_color <=
--		current_color <= 
--								BLACK			when top_pixel_y < 60*1 else
--								BLUE			when top_pixel_y< 60*2 else
--								GREEN			when top_pixel_y< 60*3 else
--								CYAN			when top_pixel_y< 60*4 else
--								RED			when top_pixel_y< 60*5 else
--								MAGENTA		when top_pixel_y< 60*6 else
--								YELLOW		when top_pixel_y< 60*7 else
--								WHITE			when top_pixel_y< 60*8 else
--								BLACK	;

--registers..
		
		--REGS.
		process(clk)
		begin 
			if(clk'event and clk='1') then
				 if(top_blank = '1') then --CLEAR IF BLANK.
					red_reg <= "000";
					green_reg <= "000";
					blue_reg <= "00";
					--HS_reg <= '0';
					--VS_reg <= '0';
				 else
					red_reg <= red_wire;
					green_reg <= green_wire;
					blue_reg <= blue_wire;
					HS_reg <= top_HS;
					VS_reg <= top_VS;
				 end if;
			end if;
		end process;
		
		
--assign registers to output.
	vgaRed <= red_reg;
	vgaGreen <= green_reg;
	vgaBlue <= blue_reg;
	Hsync <= HS_reg;
	Vsync <= VS_reg;
	
end Behavioral;