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@ayufan
Created January 3, 2017 13:41
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Pine A64 boot0 parameters
const boot0_file_head_t BT0_head =
{
{
/* jump_instruction */
( 0xEA000000 | ( ( ( sizeof( boot0_file_head_t ) + sizeof(uboot_hash_value) + sizeof( int ) - 1 ) / sizeof( int ) - 2 ) & 0x00FFFFFF ) ),
BOOT0_MAGIC,
STAMP_VALUE,
#ifdef ALIGN_SIZE_8K
0x2000,
#else
0x4000,
#endif
sizeof( boot_file_head_t ),
BOOT_PUB_HEAD_VERSION,
CONFIG_BOOT0_RET_ADDR,
CONFIG_BOOT0_RUN_ADDR,
0,
{
0, 0, '4','.','0','.','0',0
},
},
{
//__u32 prvt_head_size;
0,
//char prvt_head_vsn[4];
1,
//unsigned int dram_para[32] ;
{
0x02a0, 0x03,
0x3b3bbb, 0x1, 0x10e410e4, 0x1000,
0x1840, 0x40, 0x18, 0x02,
0x4a2195, 0x02424190, 0x08b060, 0x04b005dc,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x8808, 0x20250000,
0x0, 0x04000800, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0
},
//__s32 uart_port;
0,
//normal_gpio_cfg uart_ctrl[2];
{
{ 2, 8, 4, 1, -1, -1, {0}},//PB8: 4--RX
{ 2, 9, 4, 1, -1, -1, {0}},//PB9: 4--TX
},
//__s32 enable_jtag;
0,
//normal_gpio_cfg jtag_gpio[5];
{{0},{0},{0},{0},{0}},
//normal_gpio_cfg storage_gpio[32];
{
{ 6, 2, 2, 1, 2, -1, {0}},
{ 6, 3, 2, 1, 2, -1, {0}},
{ 6, 1, 2, 1, 2, -1, {0}},
{ 6, 0, 2, 1, 2, -1, {0}},
{ 6, 5, 2, 1, 2, -1, {0}},
{ 6, 4, 2, 1, 2, -1, {0}},
{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},
{ 3, 5, 3, 1, 3, -1, {0}},
{ 3, 6, 3, 1, 3, -1, {0}},
{ 3, 8, 3, 1, 3, -1, {0}},
{ 3, 9, 3, 1, 3, -1, {0}},
{ 3,10, 3, 1, 3, -1, {0}},
{ 3,11, 3, 1, 3, -1, {0}},
{ 3,12, 3, 1, 3, -1, {0}},
{ 3,13, 3, 1, 3, -1, {0}},
{ 3,14, 3, 1, 3, -1, {0}},
{ 3,15, 3, 1, 3, -1, {0}},
},
//char storage_data[512 - sizeof(normal_gpio_cfg) * 32];
{
0,0,0,0, 0,0,0,0,
0,0,0,0, -1,-1,-1,-1, 2,0,0,0, -1,-1,-1,-1,
1,0,0,0, 0,0,0,0, 1,0,0,0, 0,0,0,0,
4,0,0,0, 0,0,0,0, 8,0,0,0, 0,0,0,0,
}
}
};
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