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September 5, 2017 08:49
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rock64-speteck-4gb.patch
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| From 71b77f7f6a331cba94f4c92c2671f116994403ea Mon Sep 17 00:00:00 2001 | |
| From: tug <tug@skyth-tek.com> | |
| Date: Mon, 4 Sep 2017 15:40:02 +0800 | |
| Subject: [PATCH 13/13] for speteck 4G ddr | |
| Signed-off-by: tug <tug@skyth-tek.com> | |
| --- | |
| .../boot/dts/rk322xh-dram-default-timing.dtsi | 4 ++-- | |
| 1 file changed, 2 insertions(+), 2 deletions(-) | |
| diff --git a/arch/arm64/boot/dts/rk322xh-dram-default-timing.dtsi b/arch/arm64/boot/dts/rk322xh-dram-default-timing.dtsi | |
| index 6f3c843..36d4296 100644 | |
| --- a/arch/arm64/boot/dts/rk322xh-dram-default-timing.dtsi | |
| +++ b/arch/arm64/boot/dts/rk322xh-dram-default-timing.dtsi | |
| @@ -70,8 +70,8 @@ | |
| lpddr3_odt_dis_freq = <666>; | |
| phy_lpddr3_odt_dis_freq = <666>; | |
| - lpddr3_drv = <LP3_DS_40ohm>; | |
| - lpddr3_odt = <LP3_ODT_240ohm>; | |
| + lpddr3_drv = <LP3_DS_34ohm>; | |
| + lpddr3_odt = <LP3_ODT_DIS>; | |
| phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>; | |
| phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>; | |
| phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>; | |
| -- | |
| 1.7.9.5 | |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| From 71b77f7f6a331cba94f4c92c2671f116994403ea Mon Sep 17 00:00:00 2001 | |
| From: tug <tug@skyth-tek.com> | |
| Date: Mon, 4 Sep 2017 15:40:02 +0800 | |
| Subject: [PATCH 13/13] for speteck 4G ddr | |
| Signed-off-by: tug <tug@skyth-tek.com> | |
| --- | |
| .../boot/dts/rk322xh-dram-default-timing.dtsi | 4 ++-- | |
| 1 file changed, 2 insertions(+), 2 deletions(-) | |
| diff --git a/arch/arm64/boot/dts/rk322xh-dram-default-timing.dtsi b/arch/arm64/boot/dts/rk322xh-dram-default-timing.dtsi | |
| index 6f3c843..36d4296 100644 | |
| --- a/arch/arm64/boot/dts/rk322xh-dram-default-timing.dtsi | |
| +++ b/arch/arm64/boot/dts/rk322xh-dram-default-timing.dtsi | |
| @@ -70,8 +70,8 @@ | |
| lpddr3_odt_dis_freq = <666>; | |
| phy_lpddr3_odt_dis_freq = <666>; | |
| - lpddr3_drv = <LP3_DS_40ohm>; | |
| - lpddr3_odt = <LP3_ODT_240ohm>; | |
| + lpddr3_drv = <LP3_DS_34ohm>; | |
| + lpddr3_odt = <LP3_ODT_DIS>; | |
| phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>; | |
| phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>; | |
| phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>; | |
| -- | |
| 1.7.9.5 | |
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