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Release notes for Chisel3 Release 3.5.0-RC1

Feature

• DataView is a mechanism for "viewing" Scala objects as a subtype of Data. Often, this is useful for viewing one subtype of Data, as another. One can think about a DataView as a cross between a customizable cast and an untagged union. (#1955)
• Instance/Definition introduces a new experimental API for module instantiation that disentagles elaborating the definition (or implementation) from instantiation of a given module. This solves Chisel's longstanding reliance on "Deduplication" for generating Verilog with multiple instances of the same module. (#2045)
• ExtModule now has support for 3 methods of providing the underlying verilog implementations: in-line string, scala/java resource (best for use in libraries), and via a file path name. (#1154)
• Naming improvements
  • When prefixing with a data, eagerly get local name (#1614)
• Use Data refs for name prefixing with aggregate elements (#1616)

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Introduction

Hello! Hopefully you saw this linked to in a deprecation warning and want to migrate your code. Great! We want to make it as easy as possible, so if you liked this, please feel free to say so on the chisel-users mailing list :)

What are Forms?

Forms were a way to describe, in the FIRRTL compiler, the state of the circuit regarding which IR nodes exist within the circuit. As a circuit is transformed to eventually emit Verilog (or another backend), more complex IR nodes are rewritten to simpler IR nodes.

While useful, we made a bad decision to require custom transformations to use these forms as the mechanism by which the compiler schedules transformations. These forms were too clunky and lacked the fine-grain necessary to properly describe the dependency relationship between transformations.

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The Chisel project admins request that You sign a Contributor License Agreement ("CLA")
regarding any software code and/or documentation You desire to contribute to 
the Chisel Project ("Contribution").  

If you are submitting your Contribution to the Chisel Project on behalf of the Regents
of the University of California, You hearby agree to license your Contribution under
the 3-Clause BSD License, and to include the appropriate copyright notice required by
the license.

If you are submitting your Contribution to the Chisel Project on behalf of yourself or

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object RemoveNonInst {
  def run(c: Circuit): Circuit = c map onModule
  def onModule(m: DefModule): DefModule = m map onStmt map firrtl.Utils.squashEmpty
  def onStmt(s: Statement): Statement = s map onStmt match {
    case d: WDefInstance => d
    case d: DefInstance => d
    case b: Block => b
    case c: Conditionally => Block(Seq(c.conseq, c.alt))
    case other => EmptyStmt
  }