Hello! Hopefully you saw this linked to in a deprecation warning and want to migrate your code. Great! We want to make it as easy as possible, so if you liked this, please feel free to say so on the chisel-users mailing list :)
Forms were a way to describe, in the FIRRTL compiler, the state of the circuit regarding which IR nodes exist within the circuit. As a circuit is transformed to eventually emit Verilog (or another backend), more complex IR nodes are rewritten to simpler IR nodes.
While useful, we made a bad decision to require custom transformations to use these forms as the mechanism by which the compiler schedules transformations. These forms were too clunky and lacked the fine-grain necessary to properly describe the dependency relationship between transformations.