axi2mm.py

class AAXIS2MM:
    def __init__(self, block):
        self._core=block.S_AXIL
        self.read = self._core.read
        self.mmio=self._core.mmio
        self.write=self._core.write
    
    @property
    def CMD_CONTROL(self):
        reg = self.read(0)
        names = ('r_busy', 'r_err', 'r_complete', 'r_continuous', 'r_increment_n',
                 'r_tlast_syncd_n', 'decode_error', 'slave_error', 'overflow_error',
                 'aborting', 'fifo_len', 'abort')
        bits = (31, 30, 29, 28, 27, 26, 25, 24, 23, 22, (20,16), (15,8))
        
        def cvrt(x, bits):
            if isinstance(bits, int):
                return bool(1&(reg>>bits))
            else:
                return (reg>>bits[1])& (2**(bits[0]-bits[1]+1)-1)

        return {k:cvrt(reg, v) for k,v in zip(names, bits)}
        
    @property
    def addr(self):
        """5 bytes"""
        return self.read(0x10) | ((self.read(0x14)&0xffff)<<32)
        
    @addr.setter
    def addr(self,x):
#         x&=(2**35-1)
#         self.write(0x10, x&0xffffffff)
#         self.write(0x14, (x>>32)&0xffffffff)
        self.write(0x10, x.to_bytes(8,'little'))
    
    @property
    def len(self):
        return self.read(0x18)

    @len.setter
    def len(self, x):
        self.write(0x18, x)
    
    def abort(self):
        self.write(0, (self.read(0)^0xff00)|0x2600)
        
    def setup(self):
        x = self.read(0)
        clear = 2**32-1
        clear^=(1<<28)|(1<27)|0xff00  #no continuous, increment, clear abort
        x&=clear
        self.write(0,x)